US10879402B2 - Thin film transistor and display unit - Google Patents

Thin film transistor and display unit Download PDF

Info

Publication number
US10879402B2
US10879402B2 US16/150,278 US201816150278A US10879402B2 US 10879402 B2 US10879402 B2 US 10879402B2 US 201816150278 A US201816150278 A US 201816150278A US 10879402 B2 US10879402 B2 US 10879402B2
Authority
US
United States
Prior art keywords
insulating film
gate insulating
semiconductor layer
thin film
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US16/150,278
Other versions
US20190259878A1 (en
Inventor
Naoki Asano
Tokuaki Kuniyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Magnolia Blue Corp
Original Assignee
Joled Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Joled Inc filed Critical Joled Inc
Assigned to JOLED INC. reassignment JOLED INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ASANO, NAOKI, KUNIYOSHI, TOKUAKI
Publication of US20190259878A1 publication Critical patent/US20190259878A1/en
Application granted granted Critical
Publication of US10879402B2 publication Critical patent/US10879402B2/en
Assigned to INCJ, LTD. reassignment INCJ, LTD. SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Joled, Inc.
Assigned to Joled, Inc. reassignment Joled, Inc. CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Assignors: Joled, Inc.
Assigned to JDI DESIGN AND DEVELOPMENT G.K. reassignment JDI DESIGN AND DEVELOPMENT G.K. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Joled, Inc.
Assigned to MAGNOLIA BLUE CORPORATION reassignment MAGNOLIA BLUE CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JDI DESIGN AND DEVELOPMENT G.K.
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H01L29/7869—
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H01L29/41733—
    • H01L29/42384—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H01L27/1225—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the technology relates to a thin film transistor (TFT) including a semiconductor layer and a gate electrode that are provided on a substrate and to a display unit including such a TFT.
  • TFT thin film transistor
  • a thin transistor film has found its application in a variety of electronic apparatuses, such as a display apparatus.
  • a thin film transistor includes a semiconductor layer, a gate insulating film, a gate electrode, and any other component, on a substrate. Reference is made to International Publication No. WO2007/032128, for example.
  • a thin film transistor has been desired which is capable of suppressing characteristic degradation in mobility and S value, for example.
  • a thin film transistor includes: a substrate; a semiconductor layer provided in a selective region of the substrate; a first gate insulating film provided in the selective region of the substrate and covering a surface of the semiconductor layer; a second gate insulating film extending across opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the semiconductor layer; and a gate electrode facing the semiconductor layer across the second gate insulating film.
  • a display unit is provided with a display element and a thin film transistor configured to drive the display element.
  • the thin film transistor includes: a substrate; a semiconductor layer provided in a selective region of the substrate; a first gate insulating film provided in the selective region of the substrate and covering a surface of a semiconductor layer; a second gate insulating film extending across opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the semiconductor layer; and a gate electrode facing the semiconductor layer across the second gate insulating film.
  • FIG. 1 is a schematic cross-sectional view, taken along a channel width direction, of a thin film transistor having an example configuration according to one embodiment of the technology.
  • FIG. 2 is a schematic cross-sectional view, taken along a channel length direction, of the thin film transistor illustrated in FIG. 1 .
  • FIG. 3 is a schematic plan view of the thin film transistor illustrated in FIGS. 1 and 2 .
  • FIG. 4A is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1 , for illustrating an example process of a manufacturing method of the thin film transistor according to one embodiment of the technology.
  • FIG. 4B is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1 , for illustrating an example process following the process of FIG. 4A .
  • FIG. 4C is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1 , for illustrating an example process following the process of FIG. 4B .
  • FIG. 4D is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1 , for illustrating an example process following the process of FIG. 4C .
  • FIG. 5 is a schematic cross-sectional view, taken along the channel width direction, of a thin film transistor of a comparative example.
  • FIG. 6 is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 5 , for illustrating an example process of a manufacturing method of the thin film transistor according to one embodiment of the technology.
  • FIG. 7A is a graph illustrating example mobility of each of the thin film transistors illustrated in FIGS. 1 and 5 .
  • FIG. 7B is a graph illustrating an example S value of each of the thin film transistors illustrated in FIGS. 1 and 5 .
  • FIG. 8 is a block diagram of an example display unit to which a thin film transistor according to one embodiment of the technology is applied.
  • FIG. 9 is a block diagram of an example imaging unit to which a thin film transistor according to one embodiment of the technology is applied.
  • FIG. 10 is a block diagram of an electronic unit having an example configuration according to one embodiment of the technology.
  • FIGS. 1 to 3 each schematically illustrate a thin film transistor 1 having an example configuration according to an embodiment of the technology.
  • FIG. 1 is a cross-sectional view of the thin film transistor 1 taken along a Y-Z plane extending in a channel width direction.
  • FIG. 2 is a cross-sectional view of the thin film transistor 1 taken along an X-Z plane in a channel length direction.
  • FIG. 3 is a plan view of the thin film transistor 1 on an X-Y plane.
  • FIG. 1 illustrates a cross-sectional configuration of the thin film transistor 1 taken along the line I-I′ in FIG. 3
  • FIG. 2 illustrates a cross-sectional configuration of the thin film transistor 1 taken along the line II-II′ in FIG. 3 .
  • the thin film transistor 1 may be provided in a driving circuit for a display unit (e.g., a display unit 2 A illustrated in FIG. 8 described below) or an imaging unit (e.g., an imaging unit 2 B illustrated in FIG. 9 described below), for example.
  • the driving circuit may include, for example, a storage capacitor, as well as the thin film transistor 1 .
  • the thin film transistor 1 may be a top-gate transistor, for example.
  • the thin film transistor 1 includes, in this order from a substrate 11 , an under coat (UC) film 12 , an insulating film 13 , a semiconductor layer 14 , a gate insulating film 15 , and a gate electrode 16 .
  • the thin film transistor 1 may further include an interlayer insulating film 17 and source-drain electrodes 18 provided in this order on the semiconductor layer 14 .
  • the substrate 11 may include glass, quartz, or silicon, for example.
  • the substrate 11 may include a resin material, such as polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), or polyethylene naphthalate (PEN).
  • PET polyethylene terephthalate
  • PI polyimide
  • PC polycarbonate
  • PEN polyethylene naphthalate
  • the substrate 11 may include a plate of metal, such as a stainless-steel (SUS), on which an insulating material film is provided.
  • SUS stainless-steel
  • the UC film 12 suppresses or prevents movement of sodium ions and other substances from the substrate 11 to an upper layer.
  • the UC film 12 may include an insulating material, such as silicon nitride (SiN) or silicon oxide (SiO).
  • the UC film 12 may be a laminate including, in this order from the substrate 11 , a silicon nitride (SiN) film and a silicon oxide (SiO) film.
  • the UC film 12 may extend over the entire top surface of the substrate 11 .
  • the insulating film 13 on the UC film 12 may extend over the entire top surface of the substrate 11 , for example.
  • the insulating film 13 may be an inorganic insulating film, such as a silicon oxide (SiO) film, a silicon nitride (SiN) film, a silicon oxide nitride (SiON) film, or an aluminum oxide (AlO) film.
  • the insulating film 13 may be provided between the paired electrodes of the storage capacitor.
  • the semiconductor layer 14 is provided in a selective region of the substrate 11 .
  • the insulating film 13 and the UC film 12 may be provided between the semiconductor layer 14 and the substrate 11 .
  • the semiconductor layer 14 may have a length L 14 along an X axis extending in a channel length direction, and a width W 14 along a Y axis extending in a channel width direction.
  • the semiconductor layer 14 may include an oxide semiconductor that contains, as a main component, an oxide of one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), or niobium (Nb), for example.
  • Specific but non-limiting examples of the oxide included in the semiconductor layer 14 may include indium-tin-zinc oxide (ITZO), indium-gallium-zinc oxide (IGZO: InGaZnO), zinc oxide (ZnO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), and indium oxide (InO).
  • the semiconductor layer 14 may include a semiconductor material, such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or other organic semiconductors.
  • the semiconductor layer 14 may have a thickness in a range from 10 nm to 300 nm, for example. In an embodiment of the technology, the semiconductor layer 14 may have a thickness of 60 nm or less. As the thickness of the semiconductor layer 14 is reduced, an absolute number of defects included in the semiconductor layer 14 is reduced, which suppresses a negative shift of a threshold voltage. This enables achievement of an excellent characteristic, such as a high on/off ratio, of the thin film transistor 1 . Further, this reduces formation time of the semiconductor layer 14 . This results in an improvement in productivity.
  • the semiconductor layer 14 may include a channel region and low-resistive regions.
  • the channel region of the semiconductor layer 14 may face the gate electrode 16 .
  • the low-resistive regions of the semiconductor layer 14 may each have an electric resistance lower than that of the channel region.
  • the low-resistive regions of the semiconductor layer 14 may be respectively provided on two sides of the channel region along the channel length direction.
  • the source-drain electrodes 18 may be respectively coupled to the low-resistive regions, as illustrated in FIG. 2 .
  • a surface S 14 , facing the gate electrode 16 , of the semiconductor layer 14 and end faces of the semiconductor layer 14 are covered with the gate insulating film 15 .
  • the semiconductor layer 14 may be electrically separated from the gate electrode 16 .
  • the gate insulating film 15 provided between the semiconductor layer 14 and the gate electrode 16 includes a first gate insulating film 15 A and a second gate insulating film 15 B.
  • the first gate insulating film 15 A is provided in contact with the surface S 14 of the semiconductor layer 14 .
  • the second gate insulating film 15 B covers the first gate insulating film 15 A covering the semiconductor layer 14 .
  • the first gate insulating film 15 A provided on the semiconductor layer 14 is provided in the selective region of the substrate 11 .
  • the first gate insulating film 15 A may be formed in the same process as the semiconductor layer 14 , with a resist film (e.g., a resist film R illustrated in FIG. 4C , as described below) used for formation of the semiconductor layer 14 .
  • the first gate insulating film 15 A covers and protects the surface S 14 of the semiconductor layer 14 , during the manufacturing processing.
  • the first gate insulating film 15 A may have a planer shape substantially the same as that of the semiconductor layer 14 .
  • the first gate insulating film 15 A may have end faces respectively aligned with the end faces of the semiconductor layer 14 in plan view of the X-Y plane, as illustrated in FIGS. 1 to 3 .
  • the first gate insulating film 15 A may have a width W 15A equal to a width W 14 of the semiconductor layer 14 , along the channel width direction, as illustrated in FIGS. 1 to 3 .
  • the first gate insulating film 15 A may extend over a smaller region than the semiconductor layer 14 in a plan view, as a result of processing, for example. In such a case, the first gate insulating film 15 A may be provided in a region inward from the selective region of the substrate 11 in which the semiconductor layer 14 is provided.
  • the second gate insulating film 15 B provided between the first gate insulating film 15 A and the gate electrode 16 may have a width W 15B along the channel width direction.
  • the width W 15B of the second gate insulating film 15 B along the channel width direction may be greater than the width W 15A of the first gate insulating film 15 A along the channel width direction.
  • the second gate insulating film 15 B may extend over opposite sides of the first gate insulating film 15 A along the channel width direction. In other words, the second gate insulating film 15 B may cover part of the end faces, oriented in the channel width direction, of the semiconductor layer 14 .
  • the second gate insulating film 15 B provided between each of the end faces of the semiconductor layer 14 and the gate electrode 16 suppresses occurrence of a short circuit between the gate electrode 16 and each of the end faces of the semiconductor layer 14 .
  • the second gate insulating film 15 B may have a planar shape substantially the same as that of the gate electrode 16 , as illustrated in FIG. 3 , and the thin film transistor 1 may have a self-aligned structure.
  • the first gate insulating film 15 A may have a thickness TA different from the thickness TB of the second gate insulating film 15 B, along the Z axis.
  • the total of the thickness TA of the first gate insulating film 15 A and the thickness TB of the second gate insulating film 15 B may be in a range from 50 to 300 nm, for example.
  • the thickness TA of the first gate insulating film 15 A may be greater than the thickness TB of the second gate insulating film 15 B.
  • the thickness TB of the second gate insulating film 15 B may be greater than the thickness TA of the first gate insulating film 15 A. Such a configuration suppresses occurrence of a short circuit between the gate electrode 16 and the semiconductor layer 14 .
  • the first gate insulating film 15 A and the second gate insulating film 15 B may include the same insulating material. This simplifies the manufacturing processing.
  • Specific but non-limiting examples of the insulating material of the first gate insulating film 15 A and the second gate insulating film 15 B may include an inorganic insulating material, such as silicon oxide (SiO), silicon nitride (SiN), silicon nitride oxide (SiON), and aluminum oxide (AlO).
  • the first gate insulating film 15 A may include a different material from the second gate insulating film 15 B.
  • the gate electrode 16 faces the semiconductor layer 14 across the second gate insulating film 15 B.
  • the gate electrode 16 may control a carrier density in the channel region of the semiconductor layer 14 with a gate voltage (Vg) applied thereto, and serve as a wiring line to supply a potential.
  • the gate electrode 16 may have a width W 16 equal to the width W 15B of the second gate insulating film 15 B, along the channel width direction, for example.
  • the gate electrode 16 may have end faces respectively aligned with end faces of the second gate insulating film 15 B in plan view, as illustrated in FIGS. 1 to 3 .
  • the gate electrode 16 may include a metal containing one of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), or copper (Cu), or a metal alloy thereof, for example.
  • the gate electrode 16 may include a compound containing at least one of these elements or a multilayer film including two or more of these elements.
  • the gate electrode 16 may be a transparent electrically-conductive film, such as an ITO film.
  • the interlayer insulating film 17 may extend over the entire top surface of the substrate substrate 11 , for example.
  • the interlayer insulating film 17 may include an inorganic insulating material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxide nitride (SiON), or aluminum oxide (Al 2 O 3 ).
  • the interlayer insulating film 17 may include an organic insulating material, such as polyimide resin, novolak resin, or acrylic resin.
  • the interlayer insulating film 17 may be a laminate of an inorganic insulating film and an organic insulating film. Note that illustration of the interlayer insulating film 17 is omitted in FIG. 1 .
  • Each of the source-drain electrode 18 provided on the interlayer insulating film 17 may serve as a source or drain of the thin film transistor 1 .
  • the source-drain electrodes 18 may be respectively coupled to the low-resistive regions of the semiconductor layer 14 through respective contact holes of the interlayer insulating film 17 and the first gate insulating film 15 A.
  • the source-drain electrodes 18 may include the same material as the gate electrode 16 .
  • Specific but non-limiting examples of the material of the source-drain electrodes 18 may include the same ones as those described above for the gate electrode 16 .
  • the source-drain electrodes 18 may include a material having high electrical conductivity.
  • the thin film transistor 1 may be manufactured through the following processes illustrated in FIG. 4A to FIG. 4D .
  • the UC film 12 and the insulating film 13 may be formed in this order on the substrate 11 .
  • a semiconductor-material film 14 M and an insulating-material film 15 AM may be formed sequentially in this order on the insulating film 13 .
  • the semiconductor-material film 14 M may be formed into the semiconductor layer 14
  • the insulating-material film 15 AM may be formed into the first gate insulating film 15 A.
  • the semiconductor-material film 14 M and the insulating-material film 15 AM may be sequentially formed. This protects the surface S 14 of the semiconductor layer 14 during the manufacturing processing.
  • the semiconductor-material film 14 M and the insulating-material film 15 AM may be patterned in the same process using a resist film R having a predetermined shape, as illustrated in FIG. 4C .
  • the insulating-material film 15 AM may be subjected to dry-etching using the resist film R, and thereafter the semiconductor-material film 14 M may be subjected to wet-etching using the resist film R. Thereafter, the resist film R may be removed, and annealing may be performed.
  • the semiconductor layer 14 and the first gate insulating film 15 A that have planar shapes identical to each other may be formed in the same process.
  • the surface S 14 of the semiconductor layer 14 may be covered by the first gate insulating film 15 A. This suppresses adhesion of residual substances of the resist film R to the surface S 14 of the semiconductor layer 14 and occurrence of a defect on the surface S 14 of the semiconductor layer 14 due to the annealing, for example.
  • an insulating-material film 15 BM and an electrically-conductive-material film 16 M may be formed in this order so as to extend over the entire top surface of the substrate 11 and cover the semiconductor layer 14 and the first gate insulating film 15 A, as illustrated in FIG. 4D .
  • the insulating-material film 15 BM may cover a top surface and end faces of the first gate insulating film 15 A and end faces of the semiconductor layer 14 .
  • the insulating-material film 15 BM and the electrically-conductive-material film 16 M may be processed into the second gate insulating film 15 B and the gate electrode 16 , respectively.
  • the insulating-material film 15 BM and the electrically-conductive-material film 16 M may be patterned in sequence. For example, a resist film having a predetermined shape may be formed on the electrically-conductive-material film 16 M, and thereafter the electrically-conductive-material film 16 M and the insulating-material film 15 BM may be etched in this order using the resist film.
  • the gate electrode 16 and the second gate insulating film 15 B may be formed that have planar shapes identical to each other.
  • the interlayer insulating film 17 may be formed so as to extend over the entire top surface of the substrate 11 .
  • the source-drain electrodes 18 may be formed on the interlayer insulating film 17 to produce the thin film transistor 1 illustrated in FIGS. 1 to 3 .
  • the channel region of the semiconductor layer 14 may be activated in response to application of a voltage exceeding a threshold to the gate electrode 16 . This causes a current to flow between the paired source-drain electrodes 18 .
  • the first gate insulating film 15 A and the second gate insulating film 15 B may be provided between the semiconductor layer 14 and the gate electrode 16 .
  • the first gate insulating film 15 A and the semiconductor layer 14 may be formed in the same process.
  • the first gate insulating film 15 A may cover the surface S 14 of the semiconductor layer 14 . Accordingly, the surface S 14 of the semiconductor layer 14 may be protected by the first gate insulating film 15 A immediately after the formation of the semiconductor layer 14 .
  • FIG. 5 is a schematic cross-sectional view of a thin film transistor 100 of a comparative example, taken along the Y-Z plane extending in the channel width direction.
  • the thin film transistor 100 includes only the second gate insulating film 15 B between the semiconductor layer 14 and the gate electrode 16 .
  • the second gate insulating film 15 B is in contact with the surface S 14 of the semiconductor layer 14 .
  • the thin film transistor 100 is manufactured through the following processes, for example.
  • the UC film 12 and the insulating film 13 are formed on the substrate 11 , as in the thin film transistor 1 .
  • the semiconductor layer 14 is formed on the UC film 12 , using the resist film R having a predetermined shape.
  • the resist film R is removed, and annealing is performed.
  • the second gate insulating film 15 B and the gate electrode 16 are formed, as in the thin film transistor 1 .
  • the semiconductor layer 14 is patterned while the surface S 14 of the semiconductor layer 14 is not covered with the first gate insulating film 15 A of FIG. 4C .
  • This may possibly cause adhesion of residual substances of the resist film R to the surface S 14 of the semiconductor layer 14 or a defect on the surface S 14 of the semiconductor layer 14 due to the annealing.
  • the defect on the surface S 14 of the semiconductor layer 14 may possibly cause characteristic degradation in, for example, mobility and an S value, of the thin film transistor 100 .
  • the semiconductor layer 14 may be patterned while the surface S 14 of the semiconductor layer 14 (i.e., the semiconductor-material film 14 M) is coved with the first gate insulating film 15 A (i.e., the insulating-material film 15 AM).
  • the first gate insulating film 15 A i.e., the insulating-material film 15 AM.
  • FIGS. 7A and 7B illustrate characteristics of the thin film transistors 1 and 100 in correlation with variation in the thickness TA of the first gate insulating film 15 A.
  • FIG. 7A illustrates mobility of each of the thin film transistors 1 and 100 .
  • FIG. 7B illustrates an S value of each of the thin film transistors 1 and 100 .
  • the total of the thickness TA of the first gate insulating film 15 A and the thickness TB of the second gate insulating film 15 B is 200 nm.
  • the thickness TA of the first gate insulating film 15 A is 0 nm, that is, only the second gate insulating film 15 B is provided.
  • the thin film transistor 1 including the first gate insulating film 15 A has an improved S value, compared with the thin film transistor 100 without the first gate insulating film 15 A. Further, the characteristic of the thin film transistor 1 is improved as the thickness TA of the first gate insulating film 15 A becomes greater than the thickness TB of the second gate insulating film 15 B: for example, the thickness TA may be set to 150 nm, and the thickness TB to 50 nm.
  • the first gate insulating film 15 A and the second gate insulating film 15 B are provided between the semiconductor layer 14 and the gate electrode 16 in any embodiment of the technology. This suppresses occurrence of a defect on the surface S 14 of the semiconductor layer 14 during the manufacturing processing. Accordingly, it is possible to suppress characteristic degradation in, for example, mobility and the S value, of the thin film transistor 1 .
  • the end faces of the semiconductor layer 14 that are uncovered with the first gate insulating film 15 A are covered with the second gate insulating film 15 B in any embodiment of the technology. Accordingly, it is possible to suppress occurrence of a short circuit between each of the end faces of the semiconductor layer 14 and the gate electrode 16 .
  • the thin film transistor 1 may be applicable to a driving circuit in a display unit (e.g., a display unit 2 A of FIG. 8 described below) or an imaging unit (e.g., an imaging unit 2 B of FIG. 9 described below), for example.
  • a display unit e.g., a display unit 2 A of FIG. 8 described below
  • an imaging unit e.g., an imaging unit 2 B of FIG. 9 described below
  • FIG. 8 is a block diagram of the display unit 2 A having an example configuration according to an embodiment of the technology.
  • the display unit 2 A may display images based on external or internal image signals.
  • the display unit 2 A may be applied to a liquid crystal display as well as the organic EL display described above.
  • the display unit 2 A may include, for example, a timing controller 31 , a signal processor 32 , a driver 33 , and a display pixel section 34 .
  • the timing controller 31 may include a timing generator that generates various timing signals or control signals, and control driving of the signal processor 32 on the basis of these timing signals, for example.
  • the signal processor 32 may perform a predetermined correction on a digital image signal received from an external device, and output the corrected image signal to the driver 33 .
  • the driver 33 may include a scanning-line driving circuit and a signal-line driving circuit, for example.
  • the driver 33 may drive pixels in the display pixel section 34 through respective control lines.
  • the display pixel section 34 may include display elements, such as organic EL elements or liquid crystal display elements, and circuitry that drives the display elements for each pixel, for example.
  • the thin film transistor 1 according to any embodiment of the technology may be used in any circuitry in the driver 33 or the display pixel section 34 , for example.
  • FIG. 9 is a block diagram of the imaging unit 2 B having an example configuration according to an embodiment of the technology.
  • the imaging unit 2 B may be a solid-state imaging unit that acquires images in the form of electric signals, for example.
  • the imaging unit 2 B may include a charge-coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) image sensor.
  • the imaging unit 2 B may include a timing controller 35 , a driver 36 , an image pixel section 37 , and a signal processor 38 .
  • the timing controller 35 may include a timing generator that generates various timing signals or control signals, and control driving of the driver 36 on the basis of these timing signals.
  • the driver 36 may include a row-selection circuit, an AD conversion circuit, and a horizontal transfer scanning circuit, for example.
  • the driver 36 may read a signal from any pixel in the image pixel section 37 through corresponding one of control lines.
  • the image pixel section 37 may include imaging elements such as photodiodes (e.g., photoelectric conversion elements) and a pixel circuit to read signals, for example.
  • the signal processor 38 may perform various signal processing on the signal received from the image pixel section 37 .
  • the thin film transistor 1 according to any embodiment of the technology may be applied to circuitry in the driver 36 or the image pixel section 37 , for example.
  • FIG. 10 is a block diagram of an electronic apparatus 3 having an example configuration according to an embodiment of the technology.
  • Specific but non-limiting examples of the electronic apparatus 3 include television sets, personal computers (PCs), smartphones, tablet PCs, mobile phones, digital still cameras, and digital video cameras.
  • the electronic apparatus 3 may include, for example, the display unit 2 A or the imaging unit 2 B of any embodiment of the technology, and an interface section 40 .
  • the interface section 40 may be an input section that receives various external signals and external electric power.
  • the interface section 40 may include, for example, a user interface section such as a touch panel, a keyboard, or operation buttons.
  • the technology has been described with reference to at least one embodiment, the technology is not limited thereto, but may be modified in a wide variety of ways.
  • factors such as a material and a thickness of each layer exemplified in any foregoing embodiment, etc. are illustrative and non-limiting. Any other material and any other thickness may be adopted besides those described above.
  • a thin film transistor including:
  • the first gate insulating film and the second gate insulating film are provided between the semiconductor layer and the gate electrode. This configuration allows the semiconductor layer and the first gate insulating film to be formed in the same process, and the surface of the semiconductor layer to be protected by the first gate insulating film immediately after the formation of the semiconductor layer.
  • the first gate insulating film and the second gate insulating film are provided between the semiconductor layer and the gate electrode. This configuration suppresses occurrence of a defect on a surface of the semiconductor layer during the manufacturing processing. Accordingly, it is possible to suppress characteristic degradation in, for example, mobility and an S value, of the thin film transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A thin film transistor includes a substrate, a semiconductor layer, a first gate insulating film, a second gate insulating film, and a gate electrode. The semiconductor layer is provided in a selective region of the substrate. The first gate insulating film is provided in the selective region of the substrate and covers a surface of the semiconductor layer. The second gate insulating film extends across opposite sides of the first gate insulating film along a channel width direction and covers the first gate insulating film that covers the semiconductor layer. The gate electrode faces the semiconductor layer across the second gate insulating film.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Japanese Priority Patent Application No. 2018-025959 filed on Feb. 16, 2018, the entire contents of which are incorporated herein by reference.
BACKGROUND
The technology relates to a thin film transistor (TFT) including a semiconductor layer and a gate electrode that are provided on a substrate and to a display unit including such a TFT.
A thin transistor film has found its application in a variety of electronic apparatuses, such as a display apparatus. A thin film transistor includes a semiconductor layer, a gate insulating film, a gate electrode, and any other component, on a substrate. Reference is made to International Publication No. WO2007/032128, for example.
SUMMARY
A thin film transistor has been desired which is capable of suppressing characteristic degradation in mobility and S value, for example.
It is desirable to provide a thin film transistor that is able to suppress characteristic degradation and a display unit that includes such a thin film transistor.
A thin film transistor according to one embodiment of the technology includes: a substrate; a semiconductor layer provided in a selective region of the substrate; a first gate insulating film provided in the selective region of the substrate and covering a surface of the semiconductor layer; a second gate insulating film extending across opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the semiconductor layer; and a gate electrode facing the semiconductor layer across the second gate insulating film.
A display unit according to one embodiment of the technology is provided with a display element and a thin film transistor configured to drive the display element. The thin film transistor includes: a substrate; a semiconductor layer provided in a selective region of the substrate; a first gate insulating film provided in the selective region of the substrate and covering a surface of a semiconductor layer; a second gate insulating film extending across opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the semiconductor layer; and a gate electrode facing the semiconductor layer across the second gate insulating film.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the technology and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments and, together with the specification, serve to explain the principles of the technology.
FIG. 1 is a schematic cross-sectional view, taken along a channel width direction, of a thin film transistor having an example configuration according to one embodiment of the technology.
FIG. 2 is a schematic cross-sectional view, taken along a channel length direction, of the thin film transistor illustrated in FIG. 1.
FIG. 3 is a schematic plan view of the thin film transistor illustrated in FIGS. 1 and 2.
FIG. 4A is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1, for illustrating an example process of a manufacturing method of the thin film transistor according to one embodiment of the technology.
FIG. 4B is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1, for illustrating an example process following the process of FIG. 4A.
FIG. 4C is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1, for illustrating an example process following the process of FIG. 4B.
FIG. 4D is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 1, for illustrating an example process following the process of FIG. 4C.
FIG. 5 is a schematic cross-sectional view, taken along the channel width direction, of a thin film transistor of a comparative example.
FIG. 6 is a schematic cross-sectional view of the thin film transistor illustrated in FIG. 5, for illustrating an example process of a manufacturing method of the thin film transistor according to one embodiment of the technology.
FIG. 7A is a graph illustrating example mobility of each of the thin film transistors illustrated in FIGS. 1 and 5.
FIG. 7B is a graph illustrating an example S value of each of the thin film transistors illustrated in FIGS. 1 and 5.
FIG. 8 is a block diagram of an example display unit to which a thin film transistor according to one embodiment of the technology is applied.
FIG. 9 is a block diagram of an example imaging unit to which a thin film transistor according to one embodiment of the technology is applied.
FIG. 10 is a block diagram of an electronic unit having an example configuration according to one embodiment of the technology.
 DETAILED DESCRIPTION
In the following, some preferred but non-limiting embodiments of the disclosure are described in detail with reference to the accompanying drawings. Note that sizes, materials, specific values, and any other factors illustrated in respective embodiments are illustrative for easier understanding of the technology, and are not intended to limit the scope of the technology unless otherwise specifically stated. Further, elements in the following example implementations which are not recited in a most-generic independent claim of the disclosure are optional and may be provided on an as-needed basis. Throughout the present specification and the drawings, elements having substantially the same function and configuration are denoted with the same reference numerals to avoid any redundant description. Further, elements that are not directly related to the technology are unillustrated in the drawings. The drawings are schematic and are not intended to be drawn to scale.
Embodiments
[Configuration]
FIGS. 1 to 3 each schematically illustrate a thin film transistor 1 having an example configuration according to an embodiment of the technology. FIG. 1 is a cross-sectional view of the thin film transistor 1 taken along a Y-Z plane extending in a channel width direction. FIG. 2 is a cross-sectional view of the thin film transistor 1 taken along an X-Z plane in a channel length direction. FIG. 3 is a plan view of the thin film transistor 1 on an X-Y plane. FIG. 1 illustrates a cross-sectional configuration of the thin film transistor 1 taken along the line I-I′ in FIG. 3, and FIG. 2 illustrates a cross-sectional configuration of the thin film transistor 1 taken along the line II-II′ in FIG. 3. The thin film transistor 1 may be provided in a driving circuit for a display unit (e.g., a display unit 2A illustrated in FIG. 8 described below) or an imaging unit (e.g., an imaging unit 2B illustrated in FIG. 9 described below), for example. The driving circuit may include, for example, a storage capacitor, as well as the thin film transistor 1.
The thin film transistor 1 may be a top-gate transistor, for example. With reference to FIG. 1, the thin film transistor 1 includes, in this order from a substrate 11, an under coat (UC) film 12, an insulating film 13, a semiconductor layer 14, a gate insulating film 15, and a gate electrode 16. With reference to FIG. 2, the thin film transistor 1 may further include an interlayer insulating film 17 and source-drain electrodes 18 provided in this order on the semiconductor layer 14.
The substrate 11 may include glass, quartz, or silicon, for example. Alternatively, the substrate 11 may include a resin material, such as polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), or polyethylene naphthalate (PEN). Instead of these materials, the substrate 11 may include a plate of metal, such as a stainless-steel (SUS), on which an insulating material film is provided.
The UC film 12 suppresses or prevents movement of sodium ions and other substances from the substrate 11 to an upper layer. The UC film 12 may include an insulating material, such as silicon nitride (SiN) or silicon oxide (SiO). For example, the UC film 12 may be a laminate including, in this order from the substrate 11, a silicon nitride (SiN) film and a silicon oxide (SiO) film. The UC film 12 may extend over the entire top surface of the substrate 11.
The insulating film 13 on the UC film 12 may extend over the entire top surface of the substrate 11, for example. The insulating film 13 may be an inorganic insulating film, such as a silicon oxide (SiO) film, a silicon nitride (SiN) film, a silicon oxide nitride (SiON) film, or an aluminum oxide (AlO) film. The insulating film 13 may be provided between the paired electrodes of the storage capacitor.
The semiconductor layer 14 is provided in a selective region of the substrate 11. The insulating film 13 and the UC film 12 may be provided between the semiconductor layer 14 and the substrate 11. The semiconductor layer 14 may have a length L14 along an X axis extending in a channel length direction, and a width W14 along a Y axis extending in a channel width direction.
The semiconductor layer 14 may include an oxide semiconductor that contains, as a main component, an oxide of one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), or niobium (Nb), for example. Specific but non-limiting examples of the oxide included in the semiconductor layer 14 may include indium-tin-zinc oxide (ITZO), indium-gallium-zinc oxide (IGZO: InGaZnO), zinc oxide (ZnO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), and indium oxide (InO). Alternatively, the semiconductor layer 14 may include a semiconductor material, such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or other organic semiconductors. The semiconductor layer 14 may have a thickness in a range from 10 nm to 300 nm, for example. In an embodiment of the technology, the semiconductor layer 14 may have a thickness of 60 nm or less. As the thickness of the semiconductor layer 14 is reduced, an absolute number of defects included in the semiconductor layer 14 is reduced, which suppresses a negative shift of a threshold voltage. This enables achievement of an excellent characteristic, such as a high on/off ratio, of the thin film transistor 1. Further, this reduces formation time of the semiconductor layer 14. This results in an improvement in productivity.
The semiconductor layer 14 may include a channel region and low-resistive regions. The channel region of the semiconductor layer 14 may face the gate electrode 16. The low-resistive regions of the semiconductor layer 14 may each have an electric resistance lower than that of the channel region. The low-resistive regions of the semiconductor layer 14 may be respectively provided on two sides of the channel region along the channel length direction. The source-drain electrodes 18 may be respectively coupled to the low-resistive regions, as illustrated in FIG. 2. A surface S14, facing the gate electrode 16, of the semiconductor layer 14 and end faces of the semiconductor layer 14 are covered with the gate insulating film 15. The semiconductor layer 14 may be electrically separated from the gate electrode 16.
In an embodiment of the technology, the gate insulating film 15 provided between the semiconductor layer 14 and the gate electrode 16 includes a first gate insulating film 15A and a second gate insulating film 15B. The first gate insulating film 15A is provided in contact with the surface S14 of the semiconductor layer 14. The second gate insulating film 15B covers the first gate insulating film 15A covering the semiconductor layer 14. Such a structure suppresses occurrence of a defect on the surface S14 of the semiconductor layer 14 during the manufacturing processing, as described in detail below.
The first gate insulating film 15A provided on the semiconductor layer 14 is provided in the selective region of the substrate 11. The first gate insulating film 15A may be formed in the same process as the semiconductor layer 14, with a resist film (e.g., a resist film R illustrated in FIG. 4C, as described below) used for formation of the semiconductor layer 14. The first gate insulating film 15A covers and protects the surface S14 of the semiconductor layer 14, during the manufacturing processing.
In an embodiment of the technology, the first gate insulating film 15A may have a planer shape substantially the same as that of the semiconductor layer 14. The first gate insulating film 15A may have end faces respectively aligned with the end faces of the semiconductor layer 14 in plan view of the X-Y plane, as illustrated in FIGS. 1 to 3. The first gate insulating film 15A may have a width W15A equal to a width W14 of the semiconductor layer 14, along the channel width direction, as illustrated in FIGS. 1 to 3. In another embodiment of the technology, the first gate insulating film 15A may extend over a smaller region than the semiconductor layer 14 in a plan view, as a result of processing, for example. In such a case, the first gate insulating film 15A may be provided in a region inward from the selective region of the substrate 11 in which the semiconductor layer 14 is provided.
The second gate insulating film 15B provided between the first gate insulating film 15A and the gate electrode 16 may have a width W15B along the channel width direction. The width W15B of the second gate insulating film 15B along the channel width direction may be greater than the width W15A of the first gate insulating film 15A along the channel width direction. The second gate insulating film 15B may extend over opposite sides of the first gate insulating film 15A along the channel width direction. In other words, the second gate insulating film 15B may cover part of the end faces, oriented in the channel width direction, of the semiconductor layer 14. The second gate insulating film 15B provided between each of the end faces of the semiconductor layer 14 and the gate electrode 16 suppresses occurrence of a short circuit between the gate electrode 16 and each of the end faces of the semiconductor layer 14. In an embodiment of the technology, the second gate insulating film 15B may have a planar shape substantially the same as that of the gate electrode 16, as illustrated in FIG. 3, and the thin film transistor 1 may have a self-aligned structure.
In an embodiment of the technology, the first gate insulating film 15A may have a thickness TA different from the thickness TB of the second gate insulating film 15B, along the Z axis. The total of the thickness TA of the first gate insulating film 15A and the thickness TB of the second gate insulating film 15B may be in a range from 50 to 300 nm, for example. For example, the thickness TA of the first gate insulating film 15A may be greater than the thickness TB of the second gate insulating film 15B. Such a configuration protects the surface S14 of the semiconductor layer 14 more securely and suppresses characteristic degradation of the thin film transistor 1 more effectively. Alternatively, the thickness TB of the second gate insulating film 15B may be greater than the thickness TA of the first gate insulating film 15A. Such a configuration suppresses occurrence of a short circuit between the gate electrode 16 and the semiconductor layer 14.
In an embodiment of the technology, the first gate insulating film 15A and the second gate insulating film 15B may include the same insulating material. This simplifies the manufacturing processing. Specific but non-limiting examples of the insulating material of the first gate insulating film 15A and the second gate insulating film 15B may include an inorganic insulating material, such as silicon oxide (SiO), silicon nitride (SiN), silicon nitride oxide (SiON), and aluminum oxide (AlO). In another embodiment of the technology, the first gate insulating film 15A may include a different material from the second gate insulating film 15B.
The gate electrode 16 faces the semiconductor layer 14 across the second gate insulating film 15B. The gate electrode 16 may control a carrier density in the channel region of the semiconductor layer 14 with a gate voltage (Vg) applied thereto, and serve as a wiring line to supply a potential. The gate electrode 16 may have a width W16 equal to the width W15B of the second gate insulating film 15B, along the channel width direction, for example. The gate electrode 16 may have end faces respectively aligned with end faces of the second gate insulating film 15B in plan view, as illustrated in FIGS. 1 to 3.
The gate electrode 16 may include a metal containing one of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), or copper (Cu), or a metal alloy thereof, for example. Alternatively, the gate electrode 16 may include a compound containing at least one of these elements or a multilayer film including two or more of these elements. The gate electrode 16 may be a transparent electrically-conductive film, such as an ITO film.
The interlayer insulating film 17 may extend over the entire top surface of the substrate substrate 11, for example. For example, the interlayer insulating film 17 may include an inorganic insulating material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxide nitride (SiON), or aluminum oxide (Al2O3). Alternatively, the interlayer insulating film 17 may include an organic insulating material, such as polyimide resin, novolak resin, or acrylic resin. Still alternatively, the interlayer insulating film 17 may be a laminate of an inorganic insulating film and an organic insulating film. Note that illustration of the interlayer insulating film 17 is omitted in FIG. 1.
Each of the source-drain electrode 18 provided on the interlayer insulating film 17 may serve as a source or drain of the thin film transistor 1. For example, the source-drain electrodes 18 may be respectively coupled to the low-resistive regions of the semiconductor layer 14 through respective contact holes of the interlayer insulating film 17 and the first gate insulating film 15A. For example, the source-drain electrodes 18 may include the same material as the gate electrode 16. Specific but non-limiting examples of the material of the source-drain electrodes 18 may include the same ones as those described above for the gate electrode 16. In an embodiment of the technology, the source-drain electrodes 18 may include a material having high electrical conductivity.
[Manufacturing Method]
The thin film transistor 1 according to any embodiment of the technology may be manufactured through the following processes illustrated in FIG. 4A to FIG. 4D.
First, with reference to FIG. 4A, the UC film 12 and the insulating film 13 may be formed in this order on the substrate 11. Thereafter, with reference to FIG. 4B, a semiconductor-material film 14M and an insulating-material film 15AM may be formed sequentially in this order on the insulating film 13. In a subsequent process, the semiconductor-material film 14M may be formed into the semiconductor layer 14, and the insulating-material film 15AM may be formed into the first gate insulating film 15A. In this embodiment of the technology, the semiconductor-material film 14M and the insulating-material film 15AM may be sequentially formed. This protects the surface S14 of the semiconductor layer 14 during the manufacturing processing.
After the formation of the semiconductor-material film 14M and the insulating-material film 15AM, the semiconductor-material film 14M and the insulating-material film 15AM may be patterned in the same process using a resist film R having a predetermined shape, as illustrated in FIG. 4C. For example, the insulating-material film 15AM may be subjected to dry-etching using the resist film R, and thereafter the semiconductor-material film 14M may be subjected to wet-etching using the resist film R. Thereafter, the resist film R may be removed, and annealing may be performed. Through these processes, the semiconductor layer 14 and the first gate insulating film 15A that have planar shapes identical to each other may be formed in the same process. In this embodiment of the technology, the surface S14 of the semiconductor layer 14 may be covered by the first gate insulating film 15A. This suppresses adhesion of residual substances of the resist film R to the surface S14 of the semiconductor layer 14 and occurrence of a defect on the surface S14 of the semiconductor layer 14 due to the annealing, for example.
After the formation of the semiconductor layer 14 and the first gate insulating film 15A in the same process, an insulating-material film 15BM and an electrically-conductive-material film 16M may be formed in this order so as to extend over the entire top surface of the substrate 11 and cover the semiconductor layer 14 and the first gate insulating film 15A, as illustrated in FIG. 4D. The insulating-material film 15BM may cover a top surface and end faces of the first gate insulating film 15A and end faces of the semiconductor layer 14. In a subsequent process, the insulating-material film 15BM and the electrically-conductive-material film 16M may be processed into the second gate insulating film 15B and the gate electrode 16, respectively.
After the formation of the insulating-material film 15BM and the electrically-conductive-material film 16M, the insulating-material film 15BM and the electrically-conductive-material film 16M may be patterned in sequence. For example, a resist film having a predetermined shape may be formed on the electrically-conductive-material film 16M, and thereafter the electrically-conductive-material film 16M and the insulating-material film 15BM may be etched in this order using the resist film. Through these processes, the gate electrode 16 and the second gate insulating film 15B may be formed that have planar shapes identical to each other.
Thereafter, the interlayer insulating film 17 may be formed so as to extend over the entire top surface of the substrate 11. At the end of the manufacturing processing, the source-drain electrodes 18 may be formed on the interlayer insulating film 17 to produce the thin film transistor 1 illustrated in FIGS. 1 to 3.
[Workings and Effects]
In the thin film transistor 1 according to any embodiment of the technology, the channel region of the semiconductor layer 14 may be activated in response to application of a voltage exceeding a threshold to the gate electrode 16. This causes a current to flow between the paired source-drain electrodes 18.
In the thin film transistor 1, the first gate insulating film 15A and the second gate insulating film 15B may be provided between the semiconductor layer 14 and the gate electrode 16. The first gate insulating film 15A and the semiconductor layer 14 may be formed in the same process. The first gate insulating film 15A may cover the surface S14 of the semiconductor layer 14. Accordingly, the surface S14 of the semiconductor layer 14 may be protected by the first gate insulating film 15A immediately after the formation of the semiconductor layer 14. Some workings and effects of the technology will now be described with reference to a comparative example.
FIG. 5 is a schematic cross-sectional view of a thin film transistor 100 of a comparative example, taken along the Y-Z plane extending in the channel width direction. The thin film transistor 100 includes only the second gate insulating film 15B between the semiconductor layer 14 and the gate electrode 16. In other words, in the thin film transistor 100, the second gate insulating film 15B is in contact with the surface S14 of the semiconductor layer 14.
The thin film transistor 100 is manufactured through the following processes, for example.
First, with reference to FIG. 4A, the UC film 12 and the insulating film 13 are formed on the substrate 11, as in the thin film transistor 1. Thereafter, with reference to FIG. 6, the semiconductor layer 14 is formed on the UC film 12, using the resist film R having a predetermined shape. Thereafter, the resist film R is removed, and annealing is performed. Thereafter, the second gate insulating film 15B and the gate electrode 16 are formed, as in the thin film transistor 1.
As described above, in the manufacturing method of the thin film transistor 100 according to the comparative example, the semiconductor layer 14 is patterned while the surface S14 of the semiconductor layer 14 is not covered with the first gate insulating film 15A of FIG. 4C. This may possibly cause adhesion of residual substances of the resist film R to the surface S14 of the semiconductor layer 14 or a defect on the surface S14 of the semiconductor layer 14 due to the annealing. The defect on the surface S14 of the semiconductor layer 14 may possibly cause characteristic degradation in, for example, mobility and an S value, of the thin film transistor 100.
In contrast, in the manufacturing method of the thin film transistor 1 according to any embodiment of the technology, the semiconductor layer 14 may be patterned while the surface S14 of the semiconductor layer 14 (i.e., the semiconductor-material film 14M) is coved with the first gate insulating film 15A (i.e., the insulating-material film 15AM). This suppresses adhesion of residual substances of the resist film R to the surface S14 of the semiconductor layer 14 and occurrence of a defect on the surface S14 of the semiconductor layer 14 due to the annealing, for example.
FIGS. 7A and 7B illustrate characteristics of the thin film transistors 1 and 100 in correlation with variation in the thickness TA of the first gate insulating film 15A. FIG. 7A illustrates mobility of each of the thin film transistors 1 and 100. FIG. 7B illustrates an S value of each of the thin film transistors 1 and 100. In FIGS. 7A and 7B, the total of the thickness TA of the first gate insulating film 15A and the thickness TB of the second gate insulating film 15B is 200 nm. For the thin film transistor 100, the thickness TA of the first gate insulating film 15A is 0 nm, that is, only the second gate insulating film 15B is provided.
As illustrated in FIGS. 7A and 7B, the thin film transistor 1 including the first gate insulating film 15A has an improved S value, compared with the thin film transistor 100 without the first gate insulating film 15A. Further, the characteristic of the thin film transistor 1 is improved as the thickness TA of the first gate insulating film 15A becomes greater than the thickness TB of the second gate insulating film 15B: for example, the thickness TA may be set to 150 nm, and the thickness TB to 50 nm.
As described above, the first gate insulating film 15A and the second gate insulating film 15B are provided between the semiconductor layer 14 and the gate electrode 16 in any embodiment of the technology. This suppresses occurrence of a defect on the surface S14 of the semiconductor layer 14 during the manufacturing processing. Accordingly, it is possible to suppress characteristic degradation in, for example, mobility and the S value, of the thin film transistor 1.
Additionally, the end faces of the semiconductor layer 14 that are uncovered with the first gate insulating film 15A are covered with the second gate insulating film 15B in any embodiment of the technology. Accordingly, it is possible to suppress occurrence of a short circuit between each of the end faces of the semiconductor layer 14 and the gate electrode 16.
Application Examples
The thin film transistor 1 according to any embodiment of the technology may be applicable to a driving circuit in a display unit (e.g., a display unit 2A of FIG. 8 described below) or an imaging unit (e.g., an imaging unit 2B of FIG. 9 described below), for example.
FIG. 8 is a block diagram of the display unit 2A having an example configuration according to an embodiment of the technology. The display unit 2A may display images based on external or internal image signals. For example, the display unit 2A may be applied to a liquid crystal display as well as the organic EL display described above. The display unit 2A may include, for example, a timing controller 31, a signal processor 32, a driver 33, and a display pixel section 34.
The timing controller 31 may include a timing generator that generates various timing signals or control signals, and control driving of the signal processor 32 on the basis of these timing signals, for example. The signal processor 32 may perform a predetermined correction on a digital image signal received from an external device, and output the corrected image signal to the driver 33. The driver 33 may include a scanning-line driving circuit and a signal-line driving circuit, for example. The driver 33 may drive pixels in the display pixel section 34 through respective control lines. The display pixel section 34 may include display elements, such as organic EL elements or liquid crystal display elements, and circuitry that drives the display elements for each pixel, for example. The thin film transistor 1 according to any embodiment of the technology may be used in any circuitry in the driver 33 or the display pixel section 34, for example.
FIG. 9 is a block diagram of the imaging unit 2B having an example configuration according to an embodiment of the technology. The imaging unit 2B may be a solid-state imaging unit that acquires images in the form of electric signals, for example. The imaging unit 2B may include a charge-coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) image sensor. The imaging unit 2B may include a timing controller 35, a driver 36, an image pixel section 37, and a signal processor 38.
The timing controller 35 may include a timing generator that generates various timing signals or control signals, and control driving of the driver 36 on the basis of these timing signals. The driver 36 may include a row-selection circuit, an AD conversion circuit, and a horizontal transfer scanning circuit, for example. The driver 36 may read a signal from any pixel in the image pixel section 37 through corresponding one of control lines. The image pixel section 37 may include imaging elements such as photodiodes (e.g., photoelectric conversion elements) and a pixel circuit to read signals, for example. The signal processor 38 may perform various signal processing on the signal received from the image pixel section 37. The thin film transistor 1 according to any embodiment of the technology may be applied to circuitry in the driver 36 or the image pixel section 37, for example.
[Example Electronic Apparatuses]
The display unit 2A or the imaging unit 2B according to any embodiment of the technology may be applied to a variety of electronic apparatuses. FIG. 10 is a block diagram of an electronic apparatus 3 having an example configuration according to an embodiment of the technology. Specific but non-limiting examples of the electronic apparatus 3 include television sets, personal computers (PCs), smartphones, tablet PCs, mobile phones, digital still cameras, and digital video cameras.
The electronic apparatus 3 may include, for example, the display unit 2A or the imaging unit 2B of any embodiment of the technology, and an interface section 40. The interface section 40 may be an input section that receives various external signals and external electric power. Optionally, the interface section 40 may include, for example, a user interface section such as a touch panel, a keyboard, or operation buttons.
Although the technology has been described with reference to at least one embodiment, the technology is not limited thereto, but may be modified in a wide variety of ways. For example, factors such as a material and a thickness of each layer exemplified in any foregoing embodiment, etc. are illustrative and non-limiting. Any other material and any other thickness may be adopted besides those described above.
It should be appreciated that the effects described herein are mere examples. Effects of an embodiment of the technology are not limited to those described herein. The technology may further include any effect other than those described herein.
It is possible to achieve at least the following configurations from the above-described example embodiments of the technology.
(1) A thin film transistor including:
    • a substrate;
    • a semiconductor layer provided in a selective region of the substrate;
    • a first gate insulating film provided in the selective region of the substrate and covering a surface of the semiconductor layer;
    • a second gate insulating film extending across opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the semiconductor layer; and
    • a gate electrode facing the semiconductor layer across the second gate insulating film.
      (2) The thin film transistor according to (1), in which the first gate insulating film has a planar shape a same as a planar shape of the semiconductor layer.
      (3) The thin film transistor according to (1) or (2), in which the second gate insulating film has a width greater than a width of the semiconductor layer, along the channel width direction.
      (4) The thin film transistor according to any one of (1) to (3), in which the second gate insulating film is provided between each of end faces of the semiconductor layer and the gate electrode, the end faces of the semiconductor layer being oriented in the channel width direction.
      (5) The thin film transistor according to any one of (1) to (4), in which the second gate insulating film has a planar shape a same as a planar shape of the gate electrode.
      (6) The thin film transistor according to any one of (1) to (5), in which the second gate insulating film includes an insulating material a same as a material of the first gate insulating film.
      (7) The thin film transistor according to any one of (1) to (6), in which the second gate insulating film has a thickness different from a thickness of the first gate insulating film.
      (8) The thin film transistor according to any one of (1) to (7), in which the second gate insulating film has a thickness greater than a thickness of the first gate insulating film.
      (9) The thin film transistor according to any one of (1) to (7), in which the first gate insulating film has a thickness greater than a thickness of the second gate insulating film.
      (10) The thin film transistor according to any one of (1) to (9), in which the semiconductor layer includes an oxide semiconductor material.
      (11) A display unit provided with a display element and a thin film transistor configured to drive the display element, the thin film transistor including:
    • a substrate;
    • a semiconductor layer provided in a selective region of the substrate;
    • a first gate insulating film provided in the selective region of the substrate and covering a surface of the semiconductor layer;
    • a second gate insulating film extending across opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the semiconductor layer; and
    • a gate electrode facing the semiconductor layer across the second gate insulating film.
In the thin film transistor and the display unit according to any embodiment of the technology, the first gate insulating film and the second gate insulating film are provided between the semiconductor layer and the gate electrode. This configuration allows the semiconductor layer and the first gate insulating film to be formed in the same process, and the surface of the semiconductor layer to be protected by the first gate insulating film immediately after the formation of the semiconductor layer.
In the thin film transistor and the display unit according to any embodiment of the technology, the first gate insulating film and the second gate insulating film are provided between the semiconductor layer and the gate electrode. This configuration suppresses occurrence of a defect on a surface of the semiconductor layer during the manufacturing processing. Accordingly, it is possible to suppress characteristic degradation in, for example, mobility and an S value, of the thin film transistor.
Note that effects of the technology are not limited to those described hereinabove, and may be any effect described herein.
Although the technology has been described in terms of example embodiments, it is not limited thereto. It should be appreciated that variations may be made in the described embodiments by persons skilled in the art without departing from the scope of the technology as defined by the following claims. The limitations in the claims are to be interpreted broadly based on the language employed in the claims and not limited to examples described in this specification or during the prosecution of the application, and the examples are to be construed as non-exclusive. For example, in this technology, the use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another. Moreover, no element or component in this technology is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.

Claims (17)

What is claimed is:
1. A thin film transistor comprising:
a substrate;
a semiconductor layer provided in a selective region of the substrate;
a first gate insulating film provided in the selective region of the substrate and covering a surface of the semiconductor layer;
a second gate insulating film extending continuously beyond opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the surface of the semiconductor layer; and
a gate electrode facing the semiconductor layer across the second gate insulating film.
2. The thin film transistor according to claim 1, wherein the first gate insulating film has a planar shape a same as a planar shape of the semiconductor layer.
3. The thin film transistor according to claim 1, wherein the second gate insulating film has a width greater than a width of the semiconductor layer, along the channel width direction.
4. The thin film transistor according to claim 1, wherein the second gate insulating film is provided between a first end face of the semiconductor layer and the gate electrode, and between a second end face of the semiconductor layer and the gate electrode, the first and second end faces of the semiconductor layer being oriented in the channel width direction.
5. The thin film transistor according to claim 1, wherein the second gate insulating film has a planar shape a same as a planar shape of the gate electrode.
6. The thin film transistor according to claim 1, wherein the second gate insulating film includes an insulating material a same as a material of the first gate insulating film.
7. The thin film transistor according to claim 1, wherein the second gate insulating film has a thickness different from a thickness of the first gate insulating film.
8. The thin film transistor according to claim 1, wherein the second gate insulating film has a thickness greater than a thickness of the first gate insulating film.
9. The thin film transistor according to claim 1, wherein the first gate insulating film has a thickness greater than a thickness of the second gate insulating film.
10. The thin film transistor according to claim 1, wherein the semiconductor layer includes an oxide semiconductor material.
11. The thin film transistor according to claim 1, wherein the first gate insulating film is between the semiconductor layer and the second gate insulating film.
12. The thin film transistor according to claim 1, wherein
the first gate insulating film includes
one face facing the semiconductor layer,
another face opposite to the one face and facing the second gate insulating film, and
two side faces opposite to each other in the channel width direction, each of the two side faces connecting the one face and the another face, and
the second gate insulating film covers the another face and the two side faces of the first gate insulating film.
13. The thin film transistor according to claim 12, wherein
the semiconductor layer includes
a first end face facing a direction same as one of the two side faces of the first gate insulating film, and
a second end face facing a direction same as the other of the two side faces of the first gate insulating film, and
the second gate insulating film covers the first end face and the second end face of the semiconductor layer.
14. A display unit provided with a display element and a thin film transistor configured to drive the display element, the thin film transistor comprising:
a substrate;
a semiconductor layer provided in a selective region of the substrate;
a first gate insulating film provided in the selective region of the substrate and covering a surface of the semiconductor layer;
a second gate insulating film extending continuously beyond opposite sides of the first gate insulating film along a channel width direction and covering the first gate insulating film that covers the surface of the semiconductor layer; and
a gate electrode facing the semiconductor layer across the second gate insulating film.
15. The thin film transistor according to claim 14, wherein the first gate insulating film is between the semiconductor layer and the second gate insulating film.
16. The thin film transistor according to claim 14, wherein
the first gate insulating film includes
one face facing the semiconductor layer,
another face opposite to the one face and facing the second gate insulating film, and
two side faces opposite to each other in the channel width direction, each of the two side faces connecting the one face and the another face, and
the second gate insulating film covers the another face and the two side faces of the first gate insulating film.
17. The thin film transistor according to claim 16, wherein
the semiconductor layer includes
a first end face facing a direction same as one of the two side faces of the first gate insulating film, and
a second end face facing a direction same as the other of the two side faces of the first gate insulating film, and
the second gate insulating film covers the first end face and the second end face of the semiconductor layer.
US16/150,278 2018-02-16 2018-10-03 Thin film transistor and display unit Active 2038-12-24 US10879402B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018025959A JP2019145562A (en) 2018-02-16 2018-02-16 Thin film transistor and display device
JP2018-025959 2018-02-16

Publications (2)

Publication Number Publication Date
US20190259878A1 US20190259878A1 (en) 2019-08-22
US10879402B2 true US10879402B2 (en) 2020-12-29

Family

ID=67618168

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/150,278 Active 2038-12-24 US10879402B2 (en) 2018-02-16 2018-10-03 Thin film transistor and display unit

Country Status (2)

Country Link
US (1) US10879402B2 (en)
JP (1) JP2019145562A (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1020337A (en) 1996-07-02 1998-01-23 Hitachi Ltd Method for manufacturing semiconductor device
WO2007032128A1 (en) 2005-09-16 2007-03-22 Sharp Kabushiki Kaisha Thin film transistor
JP2009200528A (en) 2009-06-03 2009-09-03 Sharp Corp Thin film transistor device, and manufacturing method thereof
US20130320328A1 (en) 2012-06-04 2013-12-05 Samsung Display Co., Ltd. Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof
US20160247928A1 (en) 2015-02-20 2016-08-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US9455349B2 (en) * 2013-10-22 2016-09-27 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor thin film transistor with reduced impurity diffusion
US20170117374A1 (en) 2015-10-27 2017-04-27 Nlt Technologies, Ltd. Thin film transistor, display device, and method for manufacturing thin film transistor
JP2017085079A (en) 2015-10-27 2017-05-18 Ｎｌｔテクノロジー株式会社 THIN FILM TRANSISTOR, DISPLAY DEVICE, AND METHOD FOR PRODUCING THIN FILM TRANSISTOR

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1020337A (en) 1996-07-02 1998-01-23 Hitachi Ltd Method for manufacturing semiconductor device
WO2007032128A1 (en) 2005-09-16 2007-03-22 Sharp Kabushiki Kaisha Thin film transistor
US20090261355A1 (en) 2005-09-16 2009-10-22 Hiroshi Matsukizono Thin film transistor
JP2009200528A (en) 2009-06-03 2009-09-03 Sharp Corp Thin film transistor device, and manufacturing method thereof
US20130320328A1 (en) 2012-06-04 2013-12-05 Samsung Display Co., Ltd. Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof
JP2013251526A (en) 2012-06-04 2013-12-12 Samsung Display Co Ltd Thin film transistor, thin film transistor display board equipped with the same and manufacturing method of the same
US9455349B2 (en) * 2013-10-22 2016-09-27 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor thin film transistor with reduced impurity diffusion
US20160247928A1 (en) 2015-02-20 2016-08-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
JP2016157938A (en) 2015-02-20 2016-09-01 株式会社半導体エネルギー研究所 Semiconductor device and method for producing semiconductor device
US20170117374A1 (en) 2015-10-27 2017-04-27 Nlt Technologies, Ltd. Thin film transistor, display device, and method for manufacturing thin film transistor
JP2017085079A (en) 2015-10-27 2017-05-18 Ｎｌｔテクノロジー株式会社 THIN FILM TRANSISTOR, DISPLAY DEVICE, AND METHOD FOR PRODUCING THIN FILM TRANSISTOR

Also Published As

Publication number Publication date
JP2019145562A (en) 2019-08-29
US20190259878A1 (en) 2019-08-22

Similar Documents

Publication Publication Date Title
US10811445B2 (en) Semiconductor device, method of manufacturing semiconductor device, and display unit
US10886411B2 (en) Semiconductor device and display unit
US11189735B2 (en) Semiconductor device and display apparatus
US10319883B2 (en) Semiconductor device and display unit
US20170053947A1 (en) Thin-film transistor, semiconductor unit, and electronic apparatus
US10879402B2 (en) Thin film transistor and display unit
US10431603B2 (en) Semiconductor device
US11081591B2 (en) Semiconductor device and display unit
US20180108861A1 (en) Display unit and electronic apparatus
US11239371B2 (en) Thin-film transistor including source-drain electrodes connected to a semiconducting film and extending through a semiconductor auxiliary film
US11127762B2 (en) Semiconductor device and display including wiring line having protective metal film
US10825882B2 (en) Semiconductor device and display unit
JP2021197416A (en) Manufacturing method of semiconductor device and semiconductor device
US10607834B2 (en) Method of manufacturing semiconductor device by etching and washing
JP2020136506A (en) Semiconductor device, display device, and manufacturing method of the semiconductor device
JP7598749B2 (en) Semiconductor Device
JP6811096B2 (en) Semiconductor devices, display devices and electronic devices
JP2018170319A (en) Semiconductor device, method for manufacturing the same, and display device
JP6732829B2 (en) Semiconductor device and display device
JP6732713B2 (en) Semiconductor device and display device
JP6781051B2 (en) Semiconductor devices, display devices and electronic devices
JP2018195630A (en) Transistor and display device

Legal Events

Date Code Title Description
AS Assignment

Owner name: JOLED INC., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ASANO, NAOKI;KUNIYOSHI, TOKUAKI;REEL/FRAME:047060/0771

Effective date: 20180822

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: INCJ, LTD., JAPAN

Free format text: SECURITY INTEREST;ASSIGNOR:JOLED, INC.;REEL/FRAME:063396/0671

Effective date: 20230112

AS Assignment

Owner name: JOLED, INC., JAPAN

Free format text: CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671;ASSIGNOR:JOLED, INC.;REEL/FRAME:064067/0723

Effective date: 20230425

AS Assignment

Owner name: JDI DESIGN AND DEVELOPMENT G.K., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JOLED, INC.;REEL/FRAME:066382/0619

Effective date: 20230714

Owner name: JDI DESIGN AND DEVELOPMENT G.K., JAPAN

Free format text: ASSIGNMENT OF ASSIGNOR'S INTEREST;ASSIGNOR:JOLED, INC.;REEL/FRAME:066382/0619

Effective date: 20230714

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

AS Assignment

Owner name: MAGNOLIA BLUE CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JDI DESIGN AND DEVELOPMENT G.K.;REEL/FRAME:072039/0656

Effective date: 20250625

Owner name: MAGNOLIA BLUE CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNOR'S INTEREST;ASSIGNOR:JDI DESIGN AND DEVELOPMENT G.K.;REEL/FRAME:072039/0656

Effective date: 20250625