US10840376B2 - Gate structure and method with enhanced gate contact and threshold voltage - Google Patents

Gate structure and method with enhanced gate contact and threshold voltage Download PDF

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US10840376B2
US10840376B2 US15/884,614 US201815884614A US10840376B2 US 10840376 B2 US10840376 B2 US 10840376B2 US 201815884614 A US201815884614 A US 201815884614A US 10840376 B2 US10840376 B2 US 10840376B2
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region
gate stack
fins
nitride layer
segment
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US20190165173A1 (en
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Max Liu
Yen-Ming Peng
Wei-Shuo HO
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US15/884,614 priority Critical patent/US10840376B2/en
Priority to DE102018104004.0A priority patent/DE102018104004B4/en
Priority to KR1020180045040A priority patent/KR102112117B1/en
Priority to TW107124485A priority patent/TWI713220B/en
Priority to CN201810790528.1A priority patent/CN109841569B/en
Publication of US20190165173A1 publication Critical patent/US20190165173A1/en
Priority to US16/729,415 priority patent/US11107922B2/en
Publication of US10840376B2 publication Critical patent/US10840376B2/en
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Priority to US17/410,769 priority patent/US11804547B2/en
Priority to US18/355,997 priority patent/US12119403B2/en
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02518—Deposited layers
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/823821—
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6215—Fin field-effect transistors [FinFET] having multiple independently-addressable gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P14/2905—
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    • H10W10/181—

Definitions

  • An integrated circuit is formed on a semiconductor substrate and includes various devices, such as transistors, diodes, and/or resistors, configured and connected together to a functional circuit.
  • the integrated circuit further includes field-effect transistors, such as metal-oxide-semiconductor FETs (MOSFETs) or complimentary MOSFETs, wherein each includes a gate electrode to control the channel region of the corresponding FET.
  • MOSFETs metal-oxide-semiconductor FETs
  • MOSFETs metal-oxide-semiconductor FETs
  • nMOS n-type MOS
  • pMOS p-type MOS
  • FIG. 1A is a top view of a semiconductor device structure constructed according to various aspects of the present disclosure in one embodiment.
  • FIGS. 1B and 1C are sectional views of the semiconductor structure of FIG. 1A taken along the dashed lines AA′ and BB′ respectively, in accordance with some embodiments.
  • FIGS. 4 and 5 are sectional views of the semiconductor structure of FIG. 1A taken along the dashed line DD′, in accordance with various embodiments.
  • FIGS. 6 and 7 are sectional views of the semiconductor structure of FIG. 1A taken along the dashed line FF′, in accordance with various embodiments.
  • FIG. 8 is a flowchart of a method fabricating the semiconductor structure, in accordance with some embodiments.
  • FIG. 9 is a flowchart of a method fabricating metal gate stacks of the semiconductor structure, in accordance with some embodiments.
  • FIG. 10A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
  • FIG. 10B is a sectional view of the semiconductor structure of FIG. 10A taken along the dashed line AA′ constructed according to various aspects of the present disclosure.
  • FIG. 11A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
  • FIG. 11B is a sectional view of the semiconductor structure of FIG. 11A taken along the dashed line AA′ constructed according to various aspects of the present disclosure.
  • FIGS. 12A, 13A and 14A are top views of the semiconductor structure at various fabrication stages constructed according to various aspects of the present disclosure.
  • FIGS. 12B, 13B and 14B are sectional views of the semiconductor structure taken along the dashed line AA′ at various fabrication stages, respectively, constructed according to various aspects of the present disclosure.
  • FIGS. 12C, 13C and 14C are sectional views of the semiconductor structure taken along the dashed line BB′ at various fabrication stages, respectively, constructed according to various aspects of the present disclosure.
  • FIG. 15A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
  • FIGS. 15B and 15C are sectional views of the semiconductor structure of FIG. 15A taken along the dashed lines AA′ and BB′, respectively, in accordance with some embodiments.
  • FIG. 16A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
  • FIGS. 16B, 16C, 16D and 16E are sectional views of the semiconductor structure of FIG. 16A taken along the dashed lines AA′, BB′, CC′ and DD′, respectively, in accordance with some embodiments.
  • FIG. 17A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
  • FIGS. 17B and 17C are sectional views of the semiconductor structure of FIG. 17A taken along the dashed lines AA′ and BB′, respectively, in accordance with some embodiments.
  • FIG. 18A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
  • FIGS. 18B and 18C are sectional views of the semiconductor structure of FIG. 18A taken along the dashed lines AA′ and BB′, respectively, in accordance with some embodiments.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.
  • FIG. 1A is a sectional view of a semiconductor structure (or a work piece) 100 constructed according to various aspects of the present disclosure in one embodiment.
  • FIG. 1B is a sectional view of the semiconductor structure 100 , in portion, along the dashed lines AA′ in accordance with some embodiments.
  • FIG. 1C is a sectional view of the semiconductor structure 100 , in portion, along the dashed lines BB′ in accordance with some embodiments.
  • the semiconductor structure 100 and the method making the same are collectively described with reference to FIGS. 1A through 1C and other figures.
  • the semiconductor structure 100 is formed on fin active regions and includes fin field-effect transistors (FinFETs).
  • FinFETs fin field-effect transistors
  • the semiconductor structure 100 is formed on flat fin active regions and includes plain field-effect transistors (FETs).
  • the semiconductor structure 100 includes a dual gate dielectric FET that may be n-type, p-type, a complementary MOSFET having both an n-type FET (nFET) and a p-type FET (pFET).
  • nFET n-type FET
  • pFET p-type FET
  • the dual gate dielectric FET is an nFET.
  • the active regions are those regions with semiconductor surface wherein various doped features are formed and configured to one or more device, such as a diode, a transistor, and/or other suitable devices.
  • the active regions may include a semiconductor material similar to that (such as silicon) of the bulk semiconductor material of the substrate 102 or different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (such as alternatively silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth, for performance enhancement, such as strain effect to increase carrier mobility.
  • the first active regions 106 and the second active regions 108 each have an elongated shape oriented in the X direction.
  • the X direction is orthogonal to the Y direction, both X and Y directions defining the top surface of the substrate 102 .
  • the top surface has a normal direction along the Z direction, which is orthogonal to both X and Y directions.
  • the active regions 106 and 108 are three dimensional, such as fin active regions extruded above the substrate 102 .
  • the fin active regions are extruded from the substrate 102 and provide three-dimensional profiling for more effective coupling between the channel region (or simply referred to as channel) and the gate electrode.
  • the fin active regions may be formed by selective etching to recessing the isolation features 104 , or selective epitaxial growth to grow active regions with a semiconductor same or different from that of the substrate 102 , or a combination thereof.
  • the first fin active regions 106 and the second fin active regions 108 are also simply referred to as first fins 106 and second fins 108 , respectively.
  • the first fins 106 are disposed in the first region 102 A and are adjacent with isolation feature with large dimensions.
  • the first region 102 A is further divided into two sub-regions: an inter-fin region 102 C and an isolation region 102 D.
  • the inter-fin region 102 C and the isolation region 102 D substantially differ in pattern density and therefore in fabrication behavior.
  • the first fins 106 are configured densely with small gaps between the adjacent fins. Even though the isolation features 104 are still present in the fin gaps of the inter-fin region, the dimensions (such as d 1 in FIG. 1A ) of those gaps along the Y direction are substantially less than the dimension d 2 of the isolation feature 104 in the isolation region 102 D.
  • the second region 102 B is also divided into two sub-regions: an inter-fin region 102 E and an isolation region 102 F.
  • the inter-fin region 102 E and the isolation region 102 F substantially differ in pattern density in a way similar to those of the first region 102 A.
  • the second fins 108 are configured densely with small gaps between the adjacent fins. The dimensions of those gaps along the Y direction are substantially less than the dimension of the isolation feature 104 in the isolation region 102 F, such as the ratio of those two dimensions being greater than 5, or greater than 10 according to various examples.
  • the number of the second fins 108 is greater than 5 according to some embodiments.
  • the semiconductor substrate 102 further includes various doped features, such as n-type doped wells, p-type doped wells, source and drain, other doped features, or a combination thereof configured to form various devices or components of the devices.
  • the semiconductor substrate 102 includes a doped well 110 of a first-type in the first region 102 A.
  • the doped well 110 is doped with a p-type dopant (therefore referred to as p-well).
  • the p-well 110 is formed in the first fins 106 .
  • the dopant (such as boron) in the p-well 110 may be introduced to the first fins 106 by ion implantation or other suitable technology.
  • the semiconductor substrate 102 may include a second-type doped well 111 in the second region 102 B, wherein the second-type is opposite to the first-type in conductivity.
  • the doped well 111 is doped with an n-type dopant (therefore referred to as n-well).
  • the n-well 111 is formed in the second fins 108 .
  • the dopant (such as phosphorous) in the n-well 111 may be introduced to the second fins 108 by ion implantation or other suitable technology.
  • the semiconductor structure 100 further includes a first gate stack 112 disposed in the first region 102 A and having an elongated shape oriented in the Y direction.
  • the first gate stack 112 is disposed on the first fins 106 in the inter-fin region 102 C and continuously extends from the inter-fin region 102 C to the isolation region 102 D.
  • the first gate stack 112 includes a gate dielectric layer and a gate electrode formed thereon.
  • the first gate stack 112 has different structures in the inter-fin region 102 C and the isolation region 102 D, which is further described in details later.
  • Gate spacer 116 may be further formed on the sidewalls of the first gate stack 112 .
  • the gate spacer 116 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric material or a combination thereof.
  • the gate spacer 116 may have a multilayer structure and may be formed by depositing dielectric material and then anisotropic etching, such as plasma etching.
  • the semiconductor structure 100 further includes a second gate stack 114 disposed in the second region 102 B and having an elongated shape oriented in the Y direction.
  • the second gate stack 114 is disposed on the second fins 108 in the inter-fin region 102 E and continuously extends from the inter-fin region 102 E to the isolation region 102 F.
  • the second gate stack 114 includes a gate dielectric layer and a gate electrode formed thereon.
  • the second gate stack 114 is different from the first gate stack 112 .
  • the second gate stack 114 has different structures in the inter-fin region 102 E and the isolation region 102 F.
  • the gate spacer 116 may be further formed on the sidewalls of the second gate stack 114 .
  • the first gate stack 112 and the second gate stack 114 are formed in a gate-last process, in which dummy gate stacks are formed first and then replaced by metal gate stacks by a procedure that includes etching, deposition and polishing.
  • FIGS. 2-7 are sectional views of the semiconductor structure 100 , in portion, constructed according to various aspects of the present disclosure.
  • FIG. 2 is a sectional view of the first gate stack 112 in the isolation region 102 D taken along the dashed line CC′
  • FIG. 3 is a sectional view of the second gate stack 114 in the isolation region 102 F taken along the dashed line EE′
  • FIGS. 4 and 5 are sectional views of the first gate stack 112 in the inter-fin region 102 C taken along the dashed line DD′ in the gap between the adjacent fins according to various embodiments
  • FIG. 6 and 7 are sectional views of the second gate stack 114 in the inter-fin region 102 E taken along the dashed line FF′ in the gap between the adjacent fins according to various embodiments.
  • the first gate stack 112 and the second gate stack 114 are described below in parallel for comparison.
  • the first gate stack 112 includes a first segment in the isolation region 102 D and a second segment in the inter-fin region 102 C.
  • the first segment of the first gate stack 112 in the isolation region 102 D is illustrated in FIG. 2 .
  • the first gate stack 112 in the first segment includes a gate dielectric layer 202 and a gate electrode.
  • the gate dielectric layer 202 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material.
  • the gate dielectric layers a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride.
  • the high k dielectric material layer includes metal oxide: ZrO2, Al2O3, and HfO2, formed by a suitable method, such as metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE).
  • MOCVD metal organic chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • MBE molecular beam epitaxy
  • the gate dielectric layer 202 is formed in a high-k-last process, so the gate dielectric layer is U-shaped and surrounding the gate electrode from bottom surface and sidewalls.
  • the gate dielectric layer 202 may further include an interfacial layer interposed between the semiconductor substrate 102 and the high k dielectric material.
  • the interfacial layer includes silicon oxide formed by ALD, thermal oxidation or ultraviolet-Ozone Oxidation, according to some examples.
  • the gate electrode of the first gate stack 112 in the first segment includes a first tantalum titanium nitride layer 206 , a titanium aluminum nitride layer 208 , and a second tantalum titanium nitride layer 210 , and a low resistance metal (LRM) layer 212 stacked in sequence.
  • the first tantalum titanium nitride layer 206 , the titanium aluminum nitride layer 208 , and the second tantalum titanium nitride layer 210 are all U-shaped and are wrapped around the LRM layer 212 .
  • the LRM layer 212 includes one low resistance metal, such as tungsten, copper, aluminum, aluminum copper alloy or other suitable metal/metal alloy with low resistivity.
  • the second gate stack 114 also includes a first segment in the isolation region 102 F and a second segment in the inter-fin region 102 E.
  • the first segment of the second gate stack 114 in the isolation region 102 E is illustrated in FIG. 3 .
  • the second gate stack 114 in the first segment includes a gate dielectric layer 202 and a gate electrode.
  • the gate dielectric layer 202 is similar to that of the first gate stack 112 .
  • the gate dielectric layer 202 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material.
  • the gate dielectric layers a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride, formed by a suitable method, such as MOCVD, PVD, ALD, or MBE.
  • the gate dielectric layer 202 may further include an interfacial layer interposed between the semiconductor substrate 102 and the high k dielectric material.
  • the gate electrode of the second gate stack 114 in the first segment includes a first tantalum titanium nitride layer 206 and a titanium aluminum nitride layer 208 .
  • the second gate stack 114 is free of LRM and is further free of the second tantalum titanium nitride layer 210 .
  • the first tantalum titanium nitride layer 206 is U-shaped and being surrounded by the gate dielectric layer 202 that is also U-shaped in the present embodiment.
  • the titanium aluminum nitride layer 208 is shaped with a void (also referred to as air gap) 310 defined therein.
  • First gate stack 112 and the second gate stack 114 are different from each other while comparing the respective first segment within the isolation region, as described above.
  • the first and second gate stacks in the corresponding inter-fin regions have different structures as well and are described below with reference to FIGS. 4 and 5 .
  • the corresponding structure is illustrated in FIG. 4 when the number n of the first fins 106 within the inter-fin region 102 C is greater than 5; and is illustrated in FIG. 5 when the number n of the first fins 106 within the inter-fin region 102 C is equal to 2.
  • the second segment of the first gate stack 112 in the inter-fin region 102 C is different from the first segment.
  • the second segment of the first gate stack 112 in the inter-fin region 102 C includes the gate dielectric layer 202 similar to that of the first segment.
  • the gate dielectric layer 202 includes a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride.
  • the gate electrode of the first gate stack 112 in the second segment includes the first tantalum titanium nitride layer 206 , the titanium aluminum nitride layer 208 , and the second tantalum titanium nitride layer 210 .
  • the gate electrode of the first gate stack 112 in the second segment encloses one or more void, such as voids 402 and 404 .
  • the second segment is free of the LRM.
  • the second segment has narrow wrist in the X direction while the first segment has substantially vertical sidewalls. All above are related to the method of making the gate stack and the loading effect associated with.
  • the second segment of the first gate stack 112 within the inter-fin region 102 C spans different dimensions along the X direction at different level. Particularly, the second segment spans a first dimension a 1 at the top surface of the first gate stack 112 ; a second dimension a 2 as the narrowest (or minimum dimension) at a certain level; a third dimension a 3 at the middle of the first gate stack 112 ; and a fourth dimension a 4 at the bottom surface of the first gate stack 112 .
  • the minimum dimension a 2 is at the level substantially coincident with or substantially close to the top surface of the first fins 106 . It is noted that the top surface of the first fins 106 is above the top surface of the isolation features 104 , where the vertical height difference is referred to as fin height H, as illustrated in FIG. 1B .
  • a 4 >a 3 >a 1 >a 2 a first ratio of a 1 /a 2 is greater than 1.1; a second ratio of a 3 /a 2 is greater than 1.2; and a third ratio of a 4 /a 2 is greater than 1.4.
  • the first segment of the first gate stack 112 within the inter-fin region 102 C is some differences, as illustrated in FIG. 5 .
  • the gate electrode of the first gate stack 112 in the second segment still has a similar narrow wrist and includes the first tantalum titanium nitride layer 206 , the titanium aluminum nitride layer 208 , the second tantalum titanium nitride layer 210 , and also the LRM layer 212 .
  • the LRM layer 212 is only disposed above the void 502 and caps the void 502 .
  • the second segment of the second gate stack 114 in the inter-fin region 102 E is described with reference to FIG. 6 when the number m of fins in the inter-fin region 102 E is equal to 2 and with reference to FIG. 7 when the number m of fins in the inter-fin region 102 E is greater than 5.
  • the second segment of the second gate stack 114 in the inter-fin region 102 E includes the gate dielectric layer 202 similar to that of the first segment.
  • the gate dielectric layer 202 includes a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride.
  • the gate electrode of the second gate stack 114 in the second segment includes the first tantalum titanium nitride layer 206 and the titanium aluminum nitride layer 208 ; is free of the second tantalum titanium nitride layer 210 and the LRM layer 212 ; and encloses one or more void, such as a void 702 , which has a size greater than the void 310 .
  • the void 602 is less than the void 702 but greater than the void 310 in size.
  • the second segment of the second gate stack 114 in the inter-fin region 102 E has a narrow wrist (as illustrated in FIGS. 6 and 7 ) in the X direction while the first segment has substantially vertical sidewalls in a way similar to that of the first gate stack 112 .
  • the semiconductor structure 100 includes a channel region 124 defined on the first fins 106 and underlying the first gate stack 112 .
  • the channel 124 may be tuned for proper threshold voltage or other parameters by ion implantation.
  • the channel 124 has a same type of dopant (p-type) to that of the p-well 110 but with a greater doping concentration, depending on the application and device specification.
  • the semiconductor structure 100 includes source/drain (S/D) features (or simply referred to as source and drain) 126 formed on the first fins 106 on opposite sides of the first gate stack 112 .
  • the S/D features 126 are doped with n-type dopant (such as phosphorous).
  • the S/D features 126 may be formed by ion implantation and/or diffusion. Other processing steps may be further included to form the S/D features. For example, a rapid thermal annealing (RTA) process may be used to activate the implanted dopant.
  • RTA rapid thermal annealing
  • the S/D features may have different doping profiles formed by multi-step implantation. For example, additional doping features such as light doped drain (LDD) or double diffused drain (DDD) may be included.
  • LDD light doped drain
  • DDD double diffused drain
  • the S/D features 126 may have different structures, such as raised, recessed, or strained.
  • the formation of the S/D features may include an etching to recess the source and drain regions; epitaxial growth to form epitaxial S/D features with in-situ doping; and an annealing for activation.
  • the channel 124 is interposed between the S/D features 126 .
  • the semiconductor structure 100 includes a channel region 132 defined on the second fins 108 and underlying the second gate stack 114 .
  • the channel 132 may be tuned for proper threshold voltage or other parameters by ion implantation.
  • the channel 132 has a same type of dopant (n-type) to that of the n-well 111 but with a greater doping concentration, depending on the application and device specification.
  • the semiconductor structure 100 includes S/D features 134 formed on the second fins 108 on opposite sides of the second gate stack 114 .
  • the S/D features 134 are doped with p-type dopant (such as boron).
  • the S/D features 134 may be formed by ion implantation and/or diffusion. Other processing steps, such RTA, may be further included to form the S/D features.
  • the S/D features may have different doping profiles formed by multi-step implantation, such as LDD or DDD.
  • the S/D features 134 may have different structures, such as raised, recessed, or strained by a similar procedure to form the S/D features 126 .
  • the channel 132 is interposed between the S/D features 134 .
  • the S/D features are epitaxial source and drain.
  • the epitaxial S/D features may be formed by selective epitaxial growth for straining effect with enhanced carrier mobility and device performance.
  • the S/D features are formed by one or more epitaxial growth (epitaxial process), whereby silicon (Si) features, silicon germanium (SiGe) features, silicon carbide (SiC) features, and/or other suitable semiconductor features are grown in a crystalline state on the fins within the source and drain regions (such as defined by a patterned hard mask).
  • the semiconductor structure 100 may further include other features, such as an interconnection structure that further includes metal lines from multiple metal layers to provide horizontal electrical connections; contacts to provide vertical connections from the substrate to the metal lines; and vias to provide vertical connections between metal lines in adjacent metal layers.
  • the contacts include contacts to source and drain and gate contact to gate electrode.
  • the gate contact to the first gate stack 112 is configured to land on the first segment of the first gate stack 112 within the isolation region 102 D.
  • the channel 124 , the S/D features 126 and the first gate stack 112 are configured to form an nFET in the first region 102 A.
  • the channel 132 , the S/D features 134 and the second gate stack 114 are configured to form a pFET in the second region 102 B. Due to the structures of the nFET and pFET, each gate has a work function tuned with respective gate electrode and a threshold voltage reduced for enhanced device performance.
  • the first gate stack 112 as the gate stack of the nFET, includes the first segment within the isolation region 102 D with different structure from the second segment within the inter-fin region 102 C. The first segment includes the LRM while the second segment is free of the LRM.
  • the contact resistance between the gate electrode and the gate contact is substantially reduced.
  • the second segment of the first gate stack 112 is disposed on the first fins 106 and is overlying the channel region of the corresponding nFET, the work function of the gate electrode will have impact to the threshold voltage of the corresponding nFET. Without the LRM in the second segment, the threshold voltage of the corresponding nFET is reduced. For example, when tungsten is used in the LRM as the filling metal, it is also have fluorine incorporated in. Fluorine will increase the threshold voltage. Threshold voltage is reduced when tungsten or generally LRM is eliminated from the second segment.
  • the first gate stack 112 for nFET with respective structures for the first segment with LRM in the isolation region 102 D and the second segment without LRM in the inter-fin region 102 C, both the threshold voltage and gate contact resistance are reduced, leading to the enhancement of the device performance.
  • the second gate stack 114 for pFET is also designed with enhanced device performance.
  • FIG. 8 is a flowchart of the method 800 for making the semiconductor structure 100 having an nFET with the first gate stack 112 and a pFET with the second gate stack 114 of respective structures in the isolation regions and the inter-fin regions.
  • the method 800 is described with reference to FIG. 8 and other figures. As some detailed description is provided with FIGS. 1A-1C and 2-7 , those languages will not be repeated below.
  • the method 800 includes an operation to form isolation features 104 in the semiconductor substrate 102 , thereby defining a first active region 1002 in the first region 102 A and a second active region 1004 in the second region 102 B.
  • FIG. 10A is a top view of the semiconductor structure 100 ; and FIG. 10B is a sectional view of the semiconductor structure 100 taken along the dashed line AA′.
  • the first active regions 1002 are configured within an inter-fin region 102 C with an adjacent isolation region 102 D.
  • the second active regions 1004 are configured within an inter-fin region 102 E with an adjacent isolation region 102 F.
  • the formation of the isolation features may include forming a patterned mask by lithography; etching the substrate 102 through the openings of the patterned mask to form trenches; filling the trench with one or more dielectric material; and performing a CMP process.
  • the patterned mask includes openings to define the regions for the isolation features 104 .
  • the patterned mask layer may be a soft mask (such as a photoresist layer), or a hard mask (such as silicon oxide, silicon nitride or a combination thereof).
  • the formation of the patterned hard mask may include depositing a hard mask layer, forming a patterned resist layer by a lithography process that further includes spin-on coating a resist layer, performing an exposure process, developing the exposed resist layer, etching the hard mask through the openings of the patterned resist layer, and removing the patterned resist layer by wet stripping or plasma ashing.
  • the method 800 further includes an operation to form first fin active regions (simply referred to as first fins) 106 and second fin active regions (simply referred to as second fins) 108 extruded above the isolation features 104 .
  • FIG. 11A is a top view of the semiconductor structure 100 ; and
  • FIG. 11B is a sectional view of the semiconductor structure 100 taken along the dashed line AA′.
  • Those fin active regions also collectively referred to as a fin structure.
  • the fin structure may be formed by selective etching to recess the isolation features 104 .
  • the fin structure may be formed by selective epitaxial growth to the active regions with one or more semiconductor material.
  • the fin structure may be formed by a hybrid procedure having both selective etching to recess and selective epitaxial growth.
  • the fin structure may have elongated shape oriented along the X direction.
  • the epitaxial grown semiconductor material may include silicon, germanium, silicon germanium, silicon carbide or other suitable semiconductor material.
  • the selective etching process may include wet etching, dry etching, other suitable etching or a combination thereof.
  • the method 800 may include an operation to form doped wells, such as a doped well 110 on the first fins 106 within the first region 102 A and the a doped well 111 on the second fins 108 within the second region 102 B.
  • doped wells such as a doped well 110 on the first fins 106 within the first region 102 A and the a doped well 111 on the second fins 108 within the second region 102 B.
  • the doped well 110 is a p-type doped well (p-well) where p-type dopant (such as boron) is introduced into the first fins 106 by a suitable technology, such ion implantation; and the doped well 111 is an n-type doped well (n-well) where n-type dopant (such as phosphorous) is introduced into the second fins 108 by a suitable technology.
  • p-well p-type doped well
  • n-type dopant such as boron
  • FIG. 12A is a top view of the semiconductor structure 100 ;
  • FIG. 12B is a sectional view of the semiconductor structure 100 in portion taken along the dashed line AA′; and
  • FIG. 12C is a sectional view of the semiconductor structure 100 in portion taken along the dashed line BB′, constructed in accordance with some aspects of the present disclosure.
  • the dummy gate stacks 1202 and 1204 may include a gate dielectric layer, such as silicon oxide, high-k dielectric material, other suitable dielectric material, or a combination thereof.
  • the dummy gate stacks 1202 and 1204 also include gate electrode of any suitable conductive material, such as doped poly-silicon.
  • the dummy gate stacks 1202 and 1204 are formed by depositions and patterning process, which further includes lithography process and etching.
  • the procedure to form the dummy gate stacks includes forming a thermal oxide layer on the fins by thermal oxidation; depositing a poly-silicon layer by CVD; forming a patterned mask layer 1206 by photolithography process; and performing an etching process to the deposited dummy gate materials.
  • the patterned mask layer includes openings to define the regions for the first and second dummy gate stacks.
  • the patterned mask layer 1206 may be a soft mask (such as a photoresist layer), or a hard mask (such as silicon oxide, silicon nitride or a combination thereof) formed with a similar processes to form the hard mask for the isolation features 104 during the operation 802 .
  • gate spacer 116 is also formed on sidewalls of the dummy gate stacks ( 1202 and 1204 ).
  • the gate spacer 116 includes one or more dielectric material, such as silicon oxide or silicon nitride.
  • the formation of the gate spacer 116 may include depositing one or more dielectric material layer on the dummy gate stacks; and performing an anisotropic etching process to the dielectric material layer.
  • the anisotropic etching process includes dry etching using a suitable etchant.
  • the method 800 includes an operation to form various S/D features, such as S/D features 126 in the first region 102 A and S/D features 134 in the second region 102 B.
  • FIG. 13A is a top view of the semiconductor structure 100 ;
  • FIG. 13B is a sectional view of the semiconductor structure 100 in portion taken along the dashed line AA′;
  • FIG. 13C is a sectional view of the semiconductor structure 100 in portion taken along the dashed line BB′, constructed in accordance with some aspects of the present disclosure.
  • the S/D features 126 are interposed by the channel 124 underlying the gate stack 1202 .
  • the S/D features 126 are doped with an n-type dopant, such as phosphorous.
  • the channel 124 is doped with a p-type dopant, such as boron.
  • the S/D features 134 are interposed by the channel 132 underlying the gate stack 1204 .
  • the S/D features 134 are doped with a p-type dopant, such as boron.
  • the channel 132 is doped with an n-type dopant, such as phosphorous.
  • the S/D features are formed by multiple steps and two types of source and drain features are formed separately.
  • the source and drain are epitaxial source and drain.
  • the epitaxial source and drain may be formed by selective epitaxial growth for straining effect with enhanced carrier mobility and device performance.
  • the source and drain are formed by one or more epitaxial growth (epitaxial process), whereby silicon (Si) features, silicon germanium (SiGe) features, silicon carbide (SiC) features, and/or other suitable semiconductor features are grown in a crystalline state on the first active region within the source and drain regions (such as defined by a patterned hard mask).
  • an etching process is applied to recess portions of the first active region 106 within the source and drain regions before the epitaxy growth.
  • the etching process may also remove any dielectric material disposed on the source/drain regions, such as during the formation of the gate sidewall features.
  • Suitable epitaxy processes include CVD deposition technologies (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy, and/or other suitable processes.
  • the source and drain features may be in-situ doped during the epitaxy process by introducing doping species, such as n-type dopants (e.g., phosphorus or arsenic) for the S/D features 126 , or p-type dopants (e.g., boron or BF 2 ) for the S/D features 134 .
  • doping species such as n-type dopants (e.g., phosphorus or arsenic) for the S/D features 126 , or p-type dopants (e.g., boron or BF 2
  • the source and drain are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to introduce the corresponding dopant into the source and drain.
  • the raised source and drain are formed by epitaxial growth with more than one semiconductor material layers. For example, a silicon germanium layer is epitaxially grown on the first fins 106 to form the S/D features 126 ; and a silicon layer or a silicon carbide is epitaxially grown on the second fins 108 to form the S/D features 134 .
  • the method 800 includes an operation to form an inter-layer dielectric (ILD) layer 136 on the semiconductor structure 100 .
  • the ILD layer 136 includes one or more dielectric material to provide isolation functions to various device components.
  • the ILD layer 136 includes a dielectric material, such as silicon oxide, a low-k dielectric material, other suitable dielectric material, or a combination thereof.
  • the low-k dielectric material includes fluorinated silica glass (FSG), carbon doped silicon oxide, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable dielectric materials with dielectric constant substantially less than that of the thermal silicon oxide.
  • the formation of the ILD layer 136 includes deposition and CMP, for examples.
  • the deposition may include spin-on coating, CVD, other suitable deposition technology or a combination thereof.
  • the CMP process may stop on the hard mask 1206 using the hard mask as polishing stop layer and then the hard mask is removed by etching. Alternatively, the hard mask 1206 is removed by CMP as well. After the CMP, the dummy gate stacks are uncovered by the ILD layer 136 .
  • the method 800 includes an operation to form metal gate stacks 112 and 114 to replace the dummy gate stacks 1202 and 1204 , respectively.
  • FIG. 14A is a top view of the semiconductor structure 100 ;
  • FIG. 14B is a sectional view of the semiconductor structure 100 in portion taken along the dashed line AA′; and
  • FIG. 14C is a sectional view of the semiconductor structure 100 in portion taken along the dashed line BB′, constructed in accordance with some aspects of the present disclosure.
  • the formation of the metal gate stacks includes etching, deposition and CMP. More detailed descriptions are provided with reference to FIG. 9 as a flowchart of the method 814 .
  • FIG. 15A is a top view of the semiconductor structure 100 ;
  • FIG. 15B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region along the dashed line AA′; and
  • FIG. 15C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region along the dashed line BB′, constructed in accordance with some aspects of the present disclosure.
  • the segment of the dummy gate stack 1202 in the inter-fin region 102 C due to the high uneven profile in the inter-fin region 102 C, the corresponding portion of the gate trench 1502 in the inter-fin region 102 C has an uneven profile and a narrow wrist, as illustrated in FIG. 15C , while the portion of the gate trench 1502 in the isolation region 102 D has a substantially vertical profile, as illustrated in FIG. 15B .
  • the gate trench(s) 1504 also includes two portions in the isolation region 102 F and the inter-fin region 102 E, respectively, with similar structures.
  • FIG. 16A is a top view of the semiconductor structure 100 ;
  • FIG. 16B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102 D along the dashed line AA′;
  • FIG. 16C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102 C along the dashed line BB′,
  • FIG. 16D is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102 F along the dashed line CC′; and
  • FIG. 16A is a top view of the semiconductor structure 100 ;
  • FIG. 16B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102 D along the dashed line AA′;
  • FIG. 16C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102 C along the dashed line BB′,
  • FIG. 16D is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102 F along
  • the gate dielectric layer 202 may include a high-k dielectric layer or may additionally include an interfacial layer, such as a silicon oxide layer.
  • the gate dielectric layer 202 may be formed by a suitable technology including ALD, MOCVD, PVD, MBE, other suitable technology, or a combination thereof.
  • the gate dielectric layer 202 is formed in a high-k-last process, and the gate dielectric layer 202 is U-shaped in the gate trenches 1502 and 1504 , respectively.
  • the method 814 proceeds to an operation to deposit a first tantalum titanium nitride layer 206 in the gate trenches 1502 and 1504 by a suitable method, such as PVD or other suitable deposition technology.
  • a suitable method such as PVD or other suitable deposition technology.
  • the method 814 proceeds to an operation to deposit the titanium aluminum nitride layer 208 in the gate trenches 1502 and 1504 by a suitable method, such as PVD or other suitable deposition technology.
  • the operation 906 is designed to substantially fill the trenches 1502 and 1504 . It is noted that various material layers may be deposited on the ILD layer 136 even though FIGS. 16B-16E do not show.
  • the intermediate gate stack 1602 is formed in the first region 102 A and the gate stack 114 is formed in the second region 102 B.
  • the intermediate gate stack 1602 includes an air gap defined in the titanium aluminum nitride layer 208 , such as the air gap 402 in the inter-fin region 102 C, which is caused by the narrow wrist profile and the deposition closes up before completely filling the gate trench.
  • the second gate stack 114 also includes an air gap 310 in the isolation region 102 F and may further include an air gap 602 in the inter-fin region 102 E.
  • FIG. 17A is a top view of the semiconductor structure 100 ;
  • FIG. 17B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102 D along the dashed line AA′;
  • FIG. 17C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102 C along the dashed line BB′, constructed in accordance with some aspects of the present disclosure.
  • the patterned mask layer 1702 may be a soft mask, such as a patterned resist layer formed by a lithography process; or a patterned hard mask layer, such as a patterned silicon nitride layer formed by lithography process and etching.
  • the method 814 proceeds to an operation to perform a second etching process to the semiconductor structure in the first region 102 A while the second region 102 B is protected by the patterned mask layer 1702 .
  • the second etching process may include wet etching, dry etching or other suitable etching technology with proper etchant to partially remove the titanium aluminum nitride layer 208 of the intermediate gate stack 1602 in the first region 102 A, resulting in a trench 1704 in the isolation region 102 D and a trench 1706 in the inter-fin region 102 C.
  • the patterned mask 1702 may be removed after the second etching process or may be removed at a later fabrication stage since the subsequent depositions will not impact the second gate stack 114 as it is already filled.
  • FIG. 18A is a top view of the semiconductor structure 100 ;
  • FIG. 18B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102 D along the dashed line AA′;
  • FIG. 18C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102 C along the dashed line BB′, constructed in accordance with some aspects of the present disclosure.
  • the method 814 proceeds to an operation to deposit a LRM layer 212 in the first region 102 A by a suitable method, such as PVD or other suitable deposition technology.
  • the LRM layer 212 includes tungsten, copper, aluminum, aluminum copper alloy, a combination thereof.
  • the second tantalum titanium nitride layer 210 and the LRM layer 212 completely fill in the segment of the first gate stack 112 in the isolation region 102 D and substantially fill in the segment of the first gate stack 112 in the inter-fin region 102 C, which may leave a void 404 on the top portion.
  • the method 814 proceeds to an operation to perform a CMP process to remove the excessive portions of the deposited materials and planarize the top surface of the semiconductor structure 100 .
  • the CMP process completely removes the deposited materials on the ILD layer 136 .
  • the patterned mask layer 1702 may be additionally removed by the CMP process or be alternatively removed by another etching process if the patterned mask layer 1702 is not removed previously.
  • the first metal gate stack 112 and the second metal gate stack 114 are both formed with respective structures as described above.
  • the method 800 may additionally include other operations before, during or after the operations described above.
  • the method 800 may include an operation 816 to form an interconnection structure to couple various features of the nFET, pFET and various other devices into an integrated circuit.
  • the interconnection structure includes multiple metal layers with metal lines for horizontal connection and further includes via features for vertical connection between adjacent metal layers.
  • the interconnection structure further includes dielectric material(s), such ILD to provide isolation functions to various conductive features embedded therein.
  • the interconnection structure may be formed by a suitable technology, such as single damascene process, dual damascene process or other suitable process.
  • Various conductive features may include copper, aluminum, tungsten, silicide, other suitable conductive material or combinations thereof.
  • the ILD may include silicon oxide, low-k dielectric material, other suitable dielectric material or a combination thereof.
  • the ILD may include multiple layers, each further including an etch stop layer (such as silicon nitride) to provide etch selectivity.
  • Various conductive features may further include lining layers, such as titanium nitride and titanium, to provide barrier to prevent inter-diffusion, adhesion or other material integration effects.
  • the present disclosure provides a semiconductor structure having nFET and pFET with respective gate structure and a method making the same.
  • the gate stack for the nFETs has a first segment in the isolation region and a second segment in the inter-fin region, wherein the first segment includes a LRM while the second segment is free of the LRM.
  • the gate contact is disposed and is landing on the first segment of the nFET gate, the contact resistance between the gate electrode and the gate contact is substantially reduced.
  • the second segment of the nFET gate is disposed on the fins and is overlying the channel region of the corresponding nFET, the work function of the metal compositions of the gate electrode will have impact to the threshold voltage of the corresponding nFET.
  • the threshold voltage of the corresponding nFET is reduced.
  • Those structures of the nFET gate reduce both the threshold voltage and the contact resistance, therefore enhancing the device performance.
  • the disclosed structure and method are compatible with advanced technologies with smaller feature sizes, such as the advanced technology of 7 nm.
  • the semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region.
  • the second segment of the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) layer stacked in sequence.
  • the first segment of the first gate stack within the first region is free of the LRM layer.
  • the present disclosure provides a semiconductor structure in accordance with some other embodiments.
  • the semiconductor structure includes a semiconductor substrate having a first region and a second region; first fins disposed on the semiconductor substrate within the first region and second fins disposed on the semiconductor substrate within the second region; a first gate stack disposed directly on the first fins, wherein the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) in sequence; and a second gate stack disposed directly on the second fins, wherein the second gate stack is free of the LRM and includes the first tantalum titanium nitride layer and the titanium aluminum nitride layer, wherein the LRM includes at least one of tungsten, copper, aluminum, and copper aluminum alloy.
  • LRM low resistance metal
  • the present disclosure provides a method in accordance with some embodiments.
  • the method includes forming isolation features in a semiconductor substrate, defining first fins in a first region and second fins in a second region; forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins; depositing an inter-layer dielectric (ILD) layer on the substrate; removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer; depositing a first tantalum titanium nitride layer in the first and second gate trenches; depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench; forming a patterned mask to cover the second region and uncover the first region; performing an etching process to the titanium aluminum nitride layer in the first gate trench; depositing a second tantalum titanium nitride layer in the first gate

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Abstract

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

Description

PRIORITY DATA
This application claims priority to U.S. Provisional Patent Application Ser. No. 62/591,895 filed Nov. 29, 2017, the entire disclosure of which is hereby incorporated herein by reference.
BACKGROUND
An integrated circuit is formed on a semiconductor substrate and includes various devices, such as transistors, diodes, and/or resistors, configured and connected together to a functional circuit. Especially, the integrated circuit further includes field-effect transistors, such as metal-oxide-semiconductor FETs (MOSFETs) or complimentary MOSFETs, wherein each includes a gate electrode to control the channel region of the corresponding FET. When a semiconductor device such as a MOSFET is scaled down through various technology nodes, high k dielectric material and metal are adopted to form a gate stack. However, in a method to form metal gate stacks for n-type MOS (nMOS) transistors and p-type MOS (pMOS) transistors, various issues may arise when integrating the processes and materials for this purpose. For example, when a filling metal is used to form metal gate, it may inadvertently increase the threshold voltage of the transistor. Furthermore, the non-uniformity of the metal gate causes device performance variation. Thus, to fabricate various devices in a same substrate, the manufacturing cost, material integration, and device performance (such as transistor threshold voltage and contact resistance) are all factors to be considered. Therefore, it is therefore desired to have a new device structure and the method making the same to address the above concerns with enhanced circuit performance.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1A is a top view of a semiconductor device structure constructed according to various aspects of the present disclosure in one embodiment.
FIGS. 1B and 1C are sectional views of the semiconductor structure of FIG. 1A taken along the dashed lines AA′ and BB′ respectively, in accordance with some embodiments.
FIGS. 2 and 3 are sectional views of the semiconductor structure of FIG. 1A taken along the dashed lines CC′ and EE′ respectively, in accordance with some embodiments.
FIGS. 4 and 5 are sectional views of the semiconductor structure of FIG. 1A taken along the dashed line DD′, in accordance with various embodiments.
FIGS. 6 and 7 are sectional views of the semiconductor structure of FIG. 1A taken along the dashed line FF′, in accordance with various embodiments.
FIG. 8 is a flowchart of a method fabricating the semiconductor structure, in accordance with some embodiments.
FIG. 9 is a flowchart of a method fabricating metal gate stacks of the semiconductor structure, in accordance with some embodiments.
FIG. 10A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
FIG. 10B is a sectional view of the semiconductor structure of FIG. 10A taken along the dashed line AA′ constructed according to various aspects of the present disclosure.
FIG. 11A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
FIG. 11B is a sectional view of the semiconductor structure of FIG. 11A taken along the dashed line AA′ constructed according to various aspects of the present disclosure.
FIGS. 12A, 13A and 14A are top views of the semiconductor structure at various fabrication stages constructed according to various aspects of the present disclosure.
FIGS. 12B, 13B and 14B are sectional views of the semiconductor structure taken along the dashed line AA′ at various fabrication stages, respectively, constructed according to various aspects of the present disclosure.
FIGS. 12C, 13C and 14C are sectional views of the semiconductor structure taken along the dashed line BB′ at various fabrication stages, respectively, constructed according to various aspects of the present disclosure.
FIG. 15A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
FIGS. 15B and 15C are sectional views of the semiconductor structure of FIG. 15A taken along the dashed lines AA′ and BB′, respectively, in accordance with some embodiments.
FIG. 16A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
FIGS. 16B, 16C, 16D and 16E are sectional views of the semiconductor structure of FIG. 16A taken along the dashed lines AA′, BB′, CC′ and DD′, respectively, in accordance with some embodiments.
FIG. 17A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
FIGS. 17B and 17C are sectional views of the semiconductor structure of FIG. 17A taken along the dashed lines AA′ and BB′, respectively, in accordance with some embodiments.
FIG. 18A is a top view of the semiconductor structure at a fabrication stage constructed according to various aspects of the present disclosure.
FIGS. 18B and 18C are sectional views of the semiconductor structure of FIG. 18A taken along the dashed lines AA′ and BB′, respectively, in accordance with some embodiments.
 DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
FIG. 1A is a sectional view of a semiconductor structure (or a work piece) 100 constructed according to various aspects of the present disclosure in one embodiment. FIG. 1B is a sectional view of the semiconductor structure 100, in portion, along the dashed lines AA′ in accordance with some embodiments. FIG. 1C is a sectional view of the semiconductor structure 100, in portion, along the dashed lines BB′ in accordance with some embodiments. The semiconductor structure 100 and the method making the same are collectively described with reference to FIGS. 1A through 1C and other figures. In some embodiments, the semiconductor structure 100 is formed on fin active regions and includes fin field-effect transistors (FinFETs). In some embodiments, the semiconductor structure 100 is formed on flat fin active regions and includes plain field-effect transistors (FETs). The semiconductor structure 100 includes a dual gate dielectric FET that may be n-type, p-type, a complementary MOSFET having both an n-type FET (nFET) and a p-type FET (pFET). As an example for illustration only but not limiting, the dual gate dielectric FET is an nFET.
The semiconductor structure 100 includes a substrate 102. The substrate 102 includes a bulk silicon substrate. Alternatively, the substrate 102 may include an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. Possible substrates 102 also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.
The substrate 102 also includes various isolation features, such as isolation features 104 formed on the substrate 102 and defining various active regions on the substrate 102, such as first active regions 106 in a first region 102A and second active regions 108 in a second region 102B. In the present embodiment, the first active regions 106 are designed for various nFETs to be formed thereon; and the second active regions 108 are designed for various pFETs to be formed thereon. The isolation feature 104 utilizes isolation technology, such as local oxidation of silicon (LOCOS) and/or shallow trench isolation (STI), to define and electrically isolate the various active regions. The isolation feature 104 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The isolation feature 104 is formed by any suitable process. As one example, forming STI features includes a lithography process to expose a portion of the substrate, etching a trench in the exposed portion of the substrate (for example, by using a dry etching and/or wet etching), filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials, and planarizing the substrate and removing excessive portions of the dielectric material(s) by a polishing process, such as a chemical mechanical polishing (CMP) process. In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer and filling layer(s) of silicon nitride or silicon oxide.
The active regions (such as 106 and 108) are those regions with semiconductor surface wherein various doped features are formed and configured to one or more device, such as a diode, a transistor, and/or other suitable devices. The active regions may include a semiconductor material similar to that (such as silicon) of the bulk semiconductor material of the substrate 102 or different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (such as alternatively silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth, for performance enhancement, such as strain effect to increase carrier mobility. The first active regions 106 and the second active regions 108 each have an elongated shape oriented in the X direction. The X direction is orthogonal to the Y direction, both X and Y directions defining the top surface of the substrate 102. The top surface has a normal direction along the Z direction, which is orthogonal to both X and Y directions.
In the present embodiment, the active regions 106 and 108 are three dimensional, such as fin active regions extruded above the substrate 102. The fin active regions are extruded from the substrate 102 and provide three-dimensional profiling for more effective coupling between the channel region (or simply referred to as channel) and the gate electrode. The fin active regions may be formed by selective etching to recessing the isolation features 104, or selective epitaxial growth to grow active regions with a semiconductor same or different from that of the substrate 102, or a combination thereof. The first fin active regions 106 and the second fin active regions 108 are also simply referred to as first fins 106 and second fins 108, respectively.
The first fins 106 are disposed in the first region 102A and are adjacent with isolation feature with large dimensions. Thus the first region 102A is further divided into two sub-regions: an inter-fin region 102C and an isolation region 102D. The inter-fin region 102C and the isolation region 102D substantially differ in pattern density and therefore in fabrication behavior. In the inter-fin region 102C, the first fins 106 are configured densely with small gaps between the adjacent fins. Even though the isolation features 104 are still present in the fin gaps of the inter-fin region, the dimensions (such as d1 in FIG. 1A) of those gaps along the Y direction are substantially less than the dimension d2 of the isolation feature 104 in the isolation region 102D. In some examples, the ratio d2/d1 is greater than 5. In some examples, the ratio d2/d1 is greater than 10. In the inter-fin region 102C, the number of the first fins 106 is greater than 5 according to some embodiments.
Similarly, the second region 102B is also divided into two sub-regions: an inter-fin region 102E and an isolation region 102F. The inter-fin region 102E and the isolation region 102F substantially differ in pattern density in a way similar to those of the first region 102A. Particularly, in the inter-fin region 102E, the second fins 108 are configured densely with small gaps between the adjacent fins. The dimensions of those gaps along the Y direction are substantially less than the dimension of the isolation feature 104 in the isolation region 102F, such as the ratio of those two dimensions being greater than 5, or greater than 10 according to various examples. In the inter-fin region 102E, the number of the second fins 108 is greater than 5 according to some embodiments.
The semiconductor substrate 102 further includes various doped features, such as n-type doped wells, p-type doped wells, source and drain, other doped features, or a combination thereof configured to form various devices or components of the devices. In the present embodiment, the semiconductor substrate 102 includes a doped well 110 of a first-type in the first region 102A. The doped well 110 is doped with a p-type dopant (therefore referred to as p-well). The p-well 110 is formed in the first fins 106. The dopant (such as boron) in the p-well 110 may be introduced to the first fins 106 by ion implantation or other suitable technology. For example, the p-well 110 may be formed by a procedure that includes forming a patterned mask with an opening on the substrate 102 wherein the opening defines the region for the p-well 110; and performing an ion implantation to introduce a p-type dopant (such as boron) into the first fins 106 using the patterned mask as an implantation mask. The patterned mask may be a patterned resist layer formed by lithography or a pattern hard mask formed by deposition, lithography process and etching.
Similarly, the semiconductor substrate 102 may include a second-type doped well 111 in the second region 102B, wherein the second-type is opposite to the first-type in conductivity. In the present example, the doped well 111 is doped with an n-type dopant (therefore referred to as n-well). The n-well 111 is formed in the second fins 108. The dopant (such as phosphorous) in the n-well 111 may be introduced to the second fins 108 by ion implantation or other suitable technology.
The semiconductor structure 100 further includes a first gate stack 112 disposed in the first region 102A and having an elongated shape oriented in the Y direction. The first gate stack 112 is disposed on the first fins 106 in the inter-fin region 102C and continuously extends from the inter-fin region 102C to the isolation region 102D. The first gate stack 112 includes a gate dielectric layer and a gate electrode formed thereon. Furthermore, the first gate stack 112 has different structures in the inter-fin region 102C and the isolation region 102D, which is further described in details later. Gate spacer 116 may be further formed on the sidewalls of the first gate stack 112. In some examples, the gate spacer 116 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric material or a combination thereof. The gate spacer 116 may have a multilayer structure and may be formed by depositing dielectric material and then anisotropic etching, such as plasma etching.
The semiconductor structure 100 further includes a second gate stack 114 disposed in the second region 102B and having an elongated shape oriented in the Y direction. The second gate stack 114 is disposed on the second fins 108 in the inter-fin region 102E and continuously extends from the inter-fin region 102E to the isolation region 102F. The second gate stack 114 includes a gate dielectric layer and a gate electrode formed thereon. The second gate stack 114 is different from the first gate stack 112. Furthermore, the second gate stack 114 has different structures in the inter-fin region 102E and the isolation region 102F. The gate spacer 116 may be further formed on the sidewalls of the second gate stack 114. The first gate stack 112 and the second gate stack 114 are formed in a gate-last process, in which dummy gate stacks are formed first and then replaced by metal gate stacks by a procedure that includes etching, deposition and polishing.
The first gate stack 112 and the second gate stack 114 are further described in details with reference to FIGS. 2-7, which are sectional views of the semiconductor structure 100, in portion, constructed according to various aspects of the present disclosure. Specifically, FIG. 2 is a sectional view of the first gate stack 112 in the isolation region 102D taken along the dashed line CC′; FIG. 3 is a sectional view of the second gate stack 114 in the isolation region 102F taken along the dashed line EE′; FIGS. 4 and 5 are sectional views of the first gate stack 112 in the inter-fin region 102C taken along the dashed line DD′ in the gap between the adjacent fins according to various embodiments; and FIGS. 6 and 7 are sectional views of the second gate stack 114 in the inter-fin region 102E taken along the dashed line FF′ in the gap between the adjacent fins according to various embodiments. The first gate stack 112 and the second gate stack 114 are described below in parallel for comparison.
The first gate stack 112 includes a first segment in the isolation region 102D and a second segment in the inter-fin region 102C. The first segment of the first gate stack 112 in the isolation region 102D is illustrated in FIG. 2. The first gate stack 112 in the first segment includes a gate dielectric layer 202 and a gate electrode. The gate dielectric layer 202 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material. In the present embodiment, the gate dielectric layers a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride. In various examples, the high k dielectric material layer includes metal oxide: ZrO2, Al2O3, and HfO2, formed by a suitable method, such as metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). In some embodiments, the gate dielectric layer 202 is formed in a high-k-last process, so the gate dielectric layer is U-shaped and surrounding the gate electrode from bottom surface and sidewalls. The gate dielectric layer 202 may further include an interfacial layer interposed between the semiconductor substrate 102 and the high k dielectric material. The interfacial layer includes silicon oxide formed by ALD, thermal oxidation or ultraviolet-Ozone Oxidation, according to some examples.
Still referring to FIG. 2, the gate electrode of the first gate stack 112 in the first segment includes a first tantalum titanium nitride layer 206, a titanium aluminum nitride layer 208, and a second tantalum titanium nitride layer 210, and a low resistance metal (LRM) layer 212 stacked in sequence. The first tantalum titanium nitride layer 206, the titanium aluminum nitride layer 208, and the second tantalum titanium nitride layer 210 are all U-shaped and are wrapped around the LRM layer 212. The LRM layer 212 includes one low resistance metal, such as tungsten, copper, aluminum, aluminum copper alloy or other suitable metal/metal alloy with low resistivity.
The second gate stack 114 also includes a first segment in the isolation region 102F and a second segment in the inter-fin region 102E. The first segment of the second gate stack 114 in the isolation region 102E is illustrated in FIG. 3. The second gate stack 114 in the first segment includes a gate dielectric layer 202 and a gate electrode. The gate dielectric layer 202 is similar to that of the first gate stack 112. For example, the gate dielectric layer 202 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material. In the present embodiment, the gate dielectric layers a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride, formed by a suitable method, such as MOCVD, PVD, ALD, or MBE. In some embodiments, the gate dielectric layer 202 may further include an interfacial layer interposed between the semiconductor substrate 102 and the high k dielectric material.
Still referring to FIG. 3, the gate electrode of the second gate stack 114 in the first segment includes a first tantalum titanium nitride layer 206 and a titanium aluminum nitride layer 208. However, the second gate stack 114 is free of LRM and is further free of the second tantalum titanium nitride layer 210. The first tantalum titanium nitride layer 206 is U-shaped and being surrounded by the gate dielectric layer 202 that is also U-shaped in the present embodiment. Furthermore, the titanium aluminum nitride layer 208 is shaped with a void (also referred to as air gap) 310 defined therein. First gate stack 112 and the second gate stack 114 are different from each other while comparing the respective first segment within the isolation region, as described above.
The first and second gate stacks in the corresponding inter-fin regions have different structures as well and are described below with reference to FIGS. 4 and 5. The corresponding structure is illustrated in FIG. 4 when the number n of the first fins 106 within the inter-fin region 102C is greater than 5; and is illustrated in FIG. 5 when the number n of the first fins 106 within the inter-fin region 102C is equal to 2. The second segment of the first gate stack 112 in the inter-fin region 102C is different from the first segment.
Referring to FIG. 4, the second segment of the first gate stack 112 in the inter-fin region 102C includes the gate dielectric layer 202 similar to that of the first segment. For example, the gate dielectric layer 202 includes a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride. The gate electrode of the first gate stack 112 in the second segment includes the first tantalum titanium nitride layer 206, the titanium aluminum nitride layer 208, and the second tantalum titanium nitride layer 210. However, the gate electrode of the first gate stack 112 in the second segment encloses one or more void, such as voids 402 and 404. When the number of fins in the inter-fin region 102C is greater than 5, the second segment is free of the LRM.
The second segment has narrow wrist in the X direction while the first segment has substantially vertical sidewalls. All above are related to the method of making the gate stack and the loading effect associated with. The second segment of the first gate stack 112 within the inter-fin region 102C spans different dimensions along the X direction at different level. Particularly, the second segment spans a first dimension a1 at the top surface of the first gate stack 112; a second dimension a2 as the narrowest (or minimum dimension) at a certain level; a third dimension a3 at the middle of the first gate stack 112; and a fourth dimension a4 at the bottom surface of the first gate stack 112. The minimum dimension a2 is at the level substantially coincident with or substantially close to the top surface of the first fins 106. It is noted that the top surface of the first fins 106 is above the top surface of the isolation features 104, where the vertical height difference is referred to as fin height H, as illustrated in FIG. 1B. Among the above dimensions, a4>a3>a1>a2. In some embodiments, a first ratio of a1/a2 is greater than 1.1; a second ratio of a3/a2 is greater than 1.2; and a third ratio of a4/a2 is greater than 1.4.
When the number of the first fins 106 is equal to 2, the first segment of the first gate stack 112 within the inter-fin region 102C is some differences, as illustrated in FIG. 5. The gate electrode of the first gate stack 112 in the second segment still has a similar narrow wrist and includes the first tantalum titanium nitride layer 206, the titanium aluminum nitride layer 208, the second tantalum titanium nitride layer 210, and also the LRM layer 212. However, as void 502 is formed inside the second tantalum titanium nitride layer 210, the LRM layer 212 is only disposed above the void 502 and caps the void 502.
The second segment of the second gate stack 114 in the inter-fin region 102E is described with reference to FIG. 6 when the number m of fins in the inter-fin region 102E is equal to 2 and with reference to FIG. 7 when the number m of fins in the inter-fin region 102E is greater than 5. Referring to FIG. 7, the second segment of the second gate stack 114 in the inter-fin region 102E includes the gate dielectric layer 202 similar to that of the first segment. For example, the gate dielectric layer 202 includes a high-k dielectric material layer, such as metal oxide, metal nitride or metal oxynitride. The gate electrode of the second gate stack 114 in the second segment includes the first tantalum titanium nitride layer 206 and the titanium aluminum nitride layer 208; is free of the second tantalum titanium nitride layer 210 and the LRM layer 212; and encloses one or more void, such as a void 702, which has a size greater than the void 310.
When the number of fins in the inter-fin region 102E is equal to 2, the void 602 is less than the void 702 but greater than the void 310 in size. However, the second segment of the second gate stack 114 in the inter-fin region 102E has a narrow wrist (as illustrated in FIGS. 6 and 7) in the X direction while the first segment has substantially vertical sidewalls in a way similar to that of the first gate stack 112.
Referring back to FIGS. 1A-1C, the semiconductor structure 100 includes a channel region 124 defined on the first fins 106 and underlying the first gate stack 112. The channel 124 may be tuned for proper threshold voltage or other parameters by ion implantation. The channel 124 has a same type of dopant (p-type) to that of the p-well 110 but with a greater doping concentration, depending on the application and device specification.
The semiconductor structure 100 includes source/drain (S/D) features (or simply referred to as source and drain) 126 formed on the first fins 106 on opposite sides of the first gate stack 112. The S/D features 126 are doped with n-type dopant (such as phosphorous). The S/D features 126 may be formed by ion implantation and/or diffusion. Other processing steps may be further included to form the S/D features. For example, a rapid thermal annealing (RTA) process may be used to activate the implanted dopant. The S/D features may have different doping profiles formed by multi-step implantation. For example, additional doping features such as light doped drain (LDD) or double diffused drain (DDD) may be included. Also, the S/D features 126 may have different structures, such as raised, recessed, or strained. For example, the formation of the S/D features may include an etching to recess the source and drain regions; epitaxial growth to form epitaxial S/D features with in-situ doping; and an annealing for activation. The channel 124 is interposed between the S/D features 126.
The semiconductor structure 100 includes a channel region 132 defined on the second fins 108 and underlying the second gate stack 114. The channel 132 may be tuned for proper threshold voltage or other parameters by ion implantation. The channel 132 has a same type of dopant (n-type) to that of the n-well 111 but with a greater doping concentration, depending on the application and device specification.
The semiconductor structure 100 includes S/D features 134 formed on the second fins 108 on opposite sides of the second gate stack 114. The S/D features 134 are doped with p-type dopant (such as boron). The S/D features 134 may be formed by ion implantation and/or diffusion. Other processing steps, such RTA, may be further included to form the S/D features. The S/D features may have different doping profiles formed by multi-step implantation, such as LDD or DDD. Also, the S/D features 134 may have different structures, such as raised, recessed, or strained by a similar procedure to form the S/D features 126. The channel 132 is interposed between the S/D features 134.
In the present embodiment, the S/D features are epitaxial source and drain. The epitaxial S/D features may be formed by selective epitaxial growth for straining effect with enhanced carrier mobility and device performance. The S/D features are formed by one or more epitaxial growth (epitaxial process), whereby silicon (Si) features, silicon germanium (SiGe) features, silicon carbide (SiC) features, and/or other suitable semiconductor features are grown in a crystalline state on the fins within the source and drain regions (such as defined by a patterned hard mask).
The semiconductor structure 100 may further include other features, such as an interconnection structure that further includes metal lines from multiple metal layers to provide horizontal electrical connections; contacts to provide vertical connections from the substrate to the metal lines; and vias to provide vertical connections between metal lines in adjacent metal layers. The contacts include contacts to source and drain and gate contact to gate electrode. Particularly, the gate contact to the first gate stack 112 is configured to land on the first segment of the first gate stack 112 within the isolation region 102D.
The channel 124, the S/D features 126 and the first gate stack 112 are configured to form an nFET in the first region 102A. The channel 132, the S/D features 134 and the second gate stack 114 are configured to form a pFET in the second region 102B. Due to the structures of the nFET and pFET, each gate has a work function tuned with respective gate electrode and a threshold voltage reduced for enhanced device performance. Furthermore, the first gate stack 112, as the gate stack of the nFET, includes the first segment within the isolation region 102D with different structure from the second segment within the inter-fin region 102C. The first segment includes the LRM while the second segment is free of the LRM. As the gate contact is disposed and is landing on the first segment of the first gate stack 112 in the isolation region 102D, the contact resistance between the gate electrode and the gate contact is substantially reduced. The second segment of the first gate stack 112 is disposed on the first fins 106 and is overlying the channel region of the corresponding nFET, the work function of the gate electrode will have impact to the threshold voltage of the corresponding nFET. Without the LRM in the second segment, the threshold voltage of the corresponding nFET is reduced. For example, when tungsten is used in the LRM as the filling metal, it is also have fluorine incorporated in. Fluorine will increase the threshold voltage. Threshold voltage is reduced when tungsten or generally LRM is eliminated from the second segment. Therefore, the first gate stack 112 for nFET with respective structures for the first segment with LRM in the isolation region 102D and the second segment without LRM in the inter-fin region 102C, both the threshold voltage and gate contact resistance are reduced, leading to the enhancement of the device performance. Similarly, the second gate stack 114 for pFET is also designed with enhanced device performance.
FIG. 8 is a flowchart of the method 800 for making the semiconductor structure 100 having an nFET with the first gate stack 112 and a pFET with the second gate stack 114 of respective structures in the isolation regions and the inter-fin regions. The method 800 is described with reference to FIG. 8 and other figures. As some detailed description is provided with FIGS. 1A-1C and 2-7, those languages will not be repeated below.
Referring to block 802 of FIG. 8 and FIGS. 10A-10B, the method 800 includes an operation to form isolation features 104 in the semiconductor substrate 102, thereby defining a first active region 1002 in the first region 102A and a second active region 1004 in the second region 102B. FIG. 10A is a top view of the semiconductor structure 100; and FIG. 10B is a sectional view of the semiconductor structure 100 taken along the dashed line AA′. In the first region 102A, the first active regions 1002 are configured within an inter-fin region 102C with an adjacent isolation region 102D. Similarly, in the second region 102B, the second active regions 1004 are configured within an inter-fin region 102E with an adjacent isolation region 102F. The formation of the isolation features may include forming a patterned mask by lithography; etching the substrate 102 through the openings of the patterned mask to form trenches; filling the trench with one or more dielectric material; and performing a CMP process. The patterned mask includes openings to define the regions for the isolation features 104. The patterned mask layer may be a soft mask (such as a photoresist layer), or a hard mask (such as silicon oxide, silicon nitride or a combination thereof). The formation of the patterned hard mask may include depositing a hard mask layer, forming a patterned resist layer by a lithography process that further includes spin-on coating a resist layer, performing an exposure process, developing the exposed resist layer, etching the hard mask through the openings of the patterned resist layer, and removing the patterned resist layer by wet stripping or plasma ashing.
Referring to block 804 of FIG. 8 and FIGS. 11A-11B, the method 800 further includes an operation to form first fin active regions (simply referred to as first fins) 106 and second fin active regions (simply referred to as second fins) 108 extruded above the isolation features 104. FIG. 11A is a top view of the semiconductor structure 100; and FIG. 11B is a sectional view of the semiconductor structure 100 taken along the dashed line AA′. Those fin active regions also collectively referred to as a fin structure. In some embodiments, the fin structure may be formed by selective etching to recess the isolation features 104. In some embodiments, the fin structure may be formed by selective epitaxial growth to the active regions with one or more semiconductor material. In yet some embodiments, the fin structure may be formed by a hybrid procedure having both selective etching to recess and selective epitaxial growth. The fin structure may have elongated shape oriented along the X direction. The epitaxial grown semiconductor material may include silicon, germanium, silicon germanium, silicon carbide or other suitable semiconductor material. The selective etching process may include wet etching, dry etching, other suitable etching or a combination thereof.
Referring to block 806 of FIG. 8 and FIGS. 11A-11B, the method 800 may include an operation to form doped wells, such as a doped well 110 on the first fins 106 within the first region 102A and the a doped well 111 on the second fins 108 within the second region 102B. In the present embodiment, the doped well 110 is a p-type doped well (p-well) where p-type dopant (such as boron) is introduced into the first fins 106 by a suitable technology, such ion implantation; and the doped well 111 is an n-type doped well (n-well) where n-type dopant (such as phosphorous) is introduced into the second fins 108 by a suitable technology.
Referring to block 808 of FIG. 8 and FIGS. 12A-12C, the method 800 proceeds to an operation to form dummy gate stack on the substrate 102, such as first dummy gate stack(s) 1202 in the first region 102A and second dummy gate stack(s) 1204 in the second region 102B. FIG. 12A is a top view of the semiconductor structure 100; FIG. 12B is a sectional view of the semiconductor structure 100 in portion taken along the dashed line AA′; and FIG. 12C is a sectional view of the semiconductor structure 100 in portion taken along the dashed line BB′, constructed in accordance with some aspects of the present disclosure. The dummy gate stacks 1202 and 1204 may include a gate dielectric layer, such as silicon oxide, high-k dielectric material, other suitable dielectric material, or a combination thereof. The dummy gate stacks 1202 and 1204 also include gate electrode of any suitable conductive material, such as doped poly-silicon. The dummy gate stacks 1202 and 1204 are formed by depositions and patterning process, which further includes lithography process and etching. In the present embodiment, the procedure to form the dummy gate stacks includes forming a thermal oxide layer on the fins by thermal oxidation; depositing a poly-silicon layer by CVD; forming a patterned mask layer 1206 by photolithography process; and performing an etching process to the deposited dummy gate materials. The patterned mask layer includes openings to define the regions for the first and second dummy gate stacks. The patterned mask layer 1206 may be a soft mask (such as a photoresist layer), or a hard mask (such as silicon oxide, silicon nitride or a combination thereof) formed with a similar processes to form the hard mask for the isolation features 104 during the operation 802.
During the operation 808, gate spacer 116 is also formed on sidewalls of the dummy gate stacks (1202 and 1204). The gate spacer 116 includes one or more dielectric material, such as silicon oxide or silicon nitride. The formation of the gate spacer 116 may include depositing one or more dielectric material layer on the dummy gate stacks; and performing an anisotropic etching process to the dielectric material layer. In some examples, the anisotropic etching process includes dry etching using a suitable etchant.
Referring to block 810 of FIG. 8 and FIGS. 13A-13C, the method 800 includes an operation to form various S/D features, such as S/D features 126 in the first region 102A and S/D features 134 in the second region 102B. FIG. 13A is a top view of the semiconductor structure 100; FIG. 13B is a sectional view of the semiconductor structure 100 in portion taken along the dashed line AA′; and FIG. 13C is a sectional view of the semiconductor structure 100 in portion taken along the dashed line BB′, constructed in accordance with some aspects of the present disclosure. The S/D features 126 are interposed by the channel 124 underlying the gate stack 1202. The S/D features 126 are doped with an n-type dopant, such as phosphorous. The channel 124 is doped with a p-type dopant, such as boron. Similarly, the S/D features 134 are interposed by the channel 132 underlying the gate stack 1204. The S/D features 134 are doped with a p-type dopant, such as boron. The channel 132 is doped with an n-type dopant, such as phosphorous. The S/D features are formed by multiple steps and two types of source and drain features are formed separately.
In some embodiments, the source and drain are epitaxial source and drain. The epitaxial source and drain may be formed by selective epitaxial growth for straining effect with enhanced carrier mobility and device performance. The source and drain are formed by one or more epitaxial growth (epitaxial process), whereby silicon (Si) features, silicon germanium (SiGe) features, silicon carbide (SiC) features, and/or other suitable semiconductor features are grown in a crystalline state on the first active region within the source and drain regions (such as defined by a patterned hard mask). In an alternative embodiment, an etching process is applied to recess portions of the first active region 106 within the source and drain regions before the epitaxy growth. The etching process may also remove any dielectric material disposed on the source/drain regions, such as during the formation of the gate sidewall features. Suitable epitaxy processes include CVD deposition technologies (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy, and/or other suitable processes. The source and drain features may be in-situ doped during the epitaxy process by introducing doping species, such as n-type dopants (e.g., phosphorus or arsenic) for the S/D features 126, or p-type dopants (e.g., boron or BF2) for the S/D features 134. If the source and drain are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to introduce the corresponding dopant into the source and drain. In some other embodiments, the raised source and drain are formed by epitaxial growth with more than one semiconductor material layers. For example, a silicon germanium layer is epitaxially grown on the first fins 106 to form the S/D features 126; and a silicon layer or a silicon carbide is epitaxially grown on the second fins 108 to form the S/D features 134.
Referring to block 812 of FIG. 8 and FIGS. 13A-13C, the method 800 includes an operation to form an inter-layer dielectric (ILD) layer 136 on the semiconductor structure 100. The ILD layer 136 includes one or more dielectric material to provide isolation functions to various device components. The ILD layer 136 includes a dielectric material, such as silicon oxide, a low-k dielectric material, other suitable dielectric material, or a combination thereof. In some examples, the low-k dielectric material includes fluorinated silica glass (FSG), carbon doped silicon oxide, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable dielectric materials with dielectric constant substantially less than that of the thermal silicon oxide. The formation of the ILD layer 136 includes deposition and CMP, for examples. The deposition may include spin-on coating, CVD, other suitable deposition technology or a combination thereof. The CMP process may stop on the hard mask 1206 using the hard mask as polishing stop layer and then the hard mask is removed by etching. Alternatively, the hard mask 1206 is removed by CMP as well. After the CMP, the dummy gate stacks are uncovered by the ILD layer 136.
Referring to block 814 of FIG. 8 and FIGS. 14A-14C, the method 800 includes an operation to form metal gate stacks 112 and 114 to replace the dummy gate stacks 1202 and 1204, respectively. FIG. 14A is a top view of the semiconductor structure 100; FIG. 14B is a sectional view of the semiconductor structure 100 in portion taken along the dashed line AA′; and FIG. 14C is a sectional view of the semiconductor structure 100 in portion taken along the dashed line BB′, constructed in accordance with some aspects of the present disclosure. The formation of the metal gate stacks includes etching, deposition and CMP. More detailed descriptions are provided with reference to FIG. 9 as a flowchart of the method 814.
Referring to block 902 of FIG. 9 and FIGS. 15A-15C, the method 814 begins with an operation to perform a first etching process to remove the dummy gate stacks 1202 and 1204, resulting in gate trenches 1502 and 1504. FIG. 15A is a top view of the semiconductor structure 100; FIG. 15B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region along the dashed line AA′; and FIG. 15C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region along the dashed line BB′, constructed in accordance with some aspects of the present disclosure. The first etching process includes one or more etching steps with suitable etchant and may include dry etching, wet etching or a combination thereof. For example, the wet etching may use hydrofluoric acid, or an ammonia-hydrogen peroxide-water mixture that is a solution including NH4OH, H2O2 and H2O. With etching loading effect, the segments of a dummy gate stack in the corresponding isolation region and inter-fin region have different etching characteristics. Taking the first dummy gate stack 1202 as an example, the segment of the dummy gate stack 1202 in the inter-fin region 102C, due to the high uneven profile in the inter-fin region 102C, the corresponding portion of the gate trench 1502 in the inter-fin region 102C has an uneven profile and a narrow wrist, as illustrated in FIG. 15C, while the portion of the gate trench 1502 in the isolation region 102D has a substantially vertical profile, as illustrated in FIG. 15B. In the second region 102B, the gate trench(s) 1504 also includes two portions in the isolation region 102F and the inter-fin region 102E, respectively, with similar structures.
After the formation of the gate trenches 1502 and 1504, a gate dielectric layer 202 may be formed in the gate trenches by deposition, as illustrated in FIGS. 16A-16E. FIG. 16A is a top view of the semiconductor structure 100; FIG. 16B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102D along the dashed line AA′; FIG. 16C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102C along the dashed line BB′, FIG. 16D is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102F along the dashed line CC′; and FIG. 16E is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102E along the dashed line DD′, constructed in accordance with some aspects of the present disclosure. The gate dielectric layer 202 may include a high-k dielectric layer or may additionally include an interfacial layer, such as a silicon oxide layer. The gate dielectric layer 202 may be formed by a suitable technology including ALD, MOCVD, PVD, MBE, other suitable technology, or a combination thereof. In the present embodiment, the gate dielectric layer 202 is formed in a high-k-last process, and the gate dielectric layer 202 is U-shaped in the gate trenches 1502 and 1504, respectively.
Referring to block 904 of FIG. 9 and FIGS. 16A-16C, the method 814 proceeds to an operation to deposit a first tantalum titanium nitride layer 206 in the gate trenches 1502 and 1504 by a suitable method, such as PVD or other suitable deposition technology.
Referring to block 906 of FIG. 9 and FIGS. 16A-16E, the method 814 proceeds to an operation to deposit the titanium aluminum nitride layer 208 in the gate trenches 1502 and 1504 by a suitable method, such as PVD or other suitable deposition technology. The operation 906 is designed to substantially fill the trenches 1502 and 1504. It is noted that various material layers may be deposited on the ILD layer 136 even though FIGS. 16B-16E do not show. After the operation 906, the intermediate gate stack 1602 is formed in the first region 102A and the gate stack 114 is formed in the second region 102B. In the present embodiment, the intermediate gate stack 1602 includes an air gap defined in the titanium aluminum nitride layer 208, such as the air gap 402 in the inter-fin region 102C, which is caused by the narrow wrist profile and the deposition closes up before completely filling the gate trench. Similarly, the second gate stack 114 also includes an air gap 310 in the isolation region 102F and may further include an air gap 602 in the inter-fin region 102E.
Referring to block 908 of FIG. 9 and FIGS. 17A-17C, the method 814 proceeds to an operation to form a patterned mask layer 1702 that covers the second region 102B and expose the first region 102A. FIG. 17A is a top view of the semiconductor structure 100; FIG. 17B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102D along the dashed line AA′; and FIG. 17C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102C along the dashed line BB′, constructed in accordance with some aspects of the present disclosure. The patterned mask layer 1702 may be a soft mask, such as a patterned resist layer formed by a lithography process; or a patterned hard mask layer, such as a patterned silicon nitride layer formed by lithography process and etching.
Referring to block 910 of FIG. 9 and FIGS. 17A-17C, the method 814 proceeds to an operation to perform a second etching process to the semiconductor structure in the first region 102A while the second region 102B is protected by the patterned mask layer 1702. The second etching process may include wet etching, dry etching or other suitable etching technology with proper etchant to partially remove the titanium aluminum nitride layer 208 of the intermediate gate stack 1602 in the first region 102A, resulting in a trench 1704 in the isolation region 102D and a trench 1706 in the inter-fin region 102C. The patterned mask 1702 may be removed after the second etching process or may be removed at a later fabrication stage since the subsequent depositions will not impact the second gate stack 114 as it is already filled.
Referring to block 912 of FIG. 9 and FIGS. 18A-18C, the method 814 proceeds to an operation to deposit a second tantalum titanium nitride layer 210 in the trenches 1704 and 1706 by a suitable method, such as PVD or other suitable deposition technology. FIG. 18A is a top view of the semiconductor structure 100; FIG. 18B is a sectional view of the semiconductor structure 100 in portion taken in the isolation region 102D along the dashed line AA′; and FIG. 18C is a sectional view of the semiconductor structure 100 in portion taken in the inter-fin region 102C along the dashed line BB′, constructed in accordance with some aspects of the present disclosure.
Referring to block 914 of FIG. 9 and FIGS. 18A-18C, the method 814 proceeds to an operation to deposit a LRM layer 212 in the first region 102A by a suitable method, such as PVD or other suitable deposition technology. In some embodiments, the LRM layer 212 includes tungsten, copper, aluminum, aluminum copper alloy, a combination thereof. The second tantalum titanium nitride layer 210 and the LRM layer 212 completely fill in the segment of the first gate stack 112 in the isolation region 102D and substantially fill in the segment of the first gate stack 112 in the inter-fin region 102C, which may leave a void 404 on the top portion.
Referring to block 916 of FIG. 9 and FIGS. 18A-18C, the method 814 proceeds to an operation to perform a CMP process to remove the excessive portions of the deposited materials and planarize the top surface of the semiconductor structure 100. The CMP process completely removes the deposited materials on the ILD layer 136. The patterned mask layer 1702 may be additionally removed by the CMP process or be alternatively removed by another etching process if the patterned mask layer 1702 is not removed previously. Thus, the first metal gate stack 112 and the second metal gate stack 114 are both formed with respective structures as described above.
Now referring back to FIG. 8, the method 800 may additionally include other operations before, during or after the operations described above. For example, the method 800 may include an operation 816 to form an interconnection structure to couple various features of the nFET, pFET and various other devices into an integrated circuit. The interconnection structure includes multiple metal layers with metal lines for horizontal connection and further includes via features for vertical connection between adjacent metal layers. The interconnection structure further includes dielectric material(s), such ILD to provide isolation functions to various conductive features embedded therein. In the present example for illustration, the interconnection structure may be formed by a suitable technology, such as single damascene process, dual damascene process or other suitable process. Various conductive features (contact features, via features and metal lines) may include copper, aluminum, tungsten, silicide, other suitable conductive material or combinations thereof. The ILD may include silicon oxide, low-k dielectric material, other suitable dielectric material or a combination thereof. The ILD may include multiple layers, each further including an etch stop layer (such as silicon nitride) to provide etch selectivity. Various conductive features may further include lining layers, such as titanium nitride and titanium, to provide barrier to prevent inter-diffusion, adhesion or other material integration effects.
The present disclosure provides a semiconductor structure having nFET and pFET with respective gate structure and a method making the same. Especially, the gate stack for the nFETs has a first segment in the isolation region and a second segment in the inter-fin region, wherein the first segment includes a LRM while the second segment is free of the LRM. As the gate contact is disposed and is landing on the first segment of the nFET gate, the contact resistance between the gate electrode and the gate contact is substantially reduced. The second segment of the nFET gate is disposed on the fins and is overlying the channel region of the corresponding nFET, the work function of the metal compositions of the gate electrode will have impact to the threshold voltage of the corresponding nFET. Without the LRM in the second segment, the threshold voltage of the corresponding nFET is reduced. Those structures of the nFET gate reduce both the threshold voltage and the contact resistance, therefore enhancing the device performance. Furthermore, the disclosed structure and method are compatible with advanced technologies with smaller feature sizes, such as the advanced technology of 7 nm.
Thus, the present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
The present disclosure provides a semiconductor structure in accordance with some other embodiments. The semiconductor structure includes a semiconductor substrate having a first region and a second region; first fins disposed on the semiconductor substrate within the first region and second fins disposed on the semiconductor substrate within the second region; a first gate stack disposed directly on the first fins, wherein the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) in sequence; and a second gate stack disposed directly on the second fins, wherein the second gate stack is free of the LRM and includes the first tantalum titanium nitride layer and the titanium aluminum nitride layer, wherein the LRM includes at least one of tungsten, copper, aluminum, and copper aluminum alloy.
The present disclosure provides a method in accordance with some embodiments. The method includes forming isolation features in a semiconductor substrate, defining first fins in a first region and second fins in a second region; forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins; depositing an inter-layer dielectric (ILD) layer on the substrate; removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer; depositing a first tantalum titanium nitride layer in the first and second gate trenches; depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench; forming a patterned mask to cover the second region and uncover the first region; performing an etching process to the titanium aluminum nitride layer in the first gate trench; depositing a second tantalum titanium nitride layer in the first gate trench; and filling a low resistance metal in the first gate trench.
The foregoing has outlined features of several embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

What is claimed is:
1. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region being adjacent to the first region;
first fins formed on the semiconductor substrate within the first region, wherein the first fins are oriented along a first direction and disposed with a spacing d1 along a second direction being orthogonal to the first direction, and wherein a number of the first fins is greater than 5;
a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region, wherein the STI feature continuously extends to fill up the second region and spans a dimension d2 along the second direction, wherein a ratio d2/d1 is greater than 5; and
a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending along the second direction to the first STI feature within the second region, wherein the second segment of the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) layer stacked in sequence, wherein the first segment of the first gate stack within the first region is free of the LRM layer.
2. The semiconductor structure of claim 1, wherein
each of the first fins has an elongated shape oriented in the first direction and spans a width w along the second direction;
the first gate stack has another elongated shape oriented in the second direction; and
the dimension d2 is substantially greater than the width w.
3. The semiconductor structure of claim 2, wherein
the first segment of the first gate stack includes the first tantalum titanium nitride layer and the titanium aluminum nitride layer; and
the first segment of the first gate stack within the first region further defines a void surrounded by the titanium aluminum nitride layer.
4. The semiconductor structure of claim 1, wherein the first segment of the first gate stack has a first length L1 at a top surface, a second length L2 at a middle and a third length L3 at a bottom surface, wherein L2 is greater L1 and L3 is greater than L2, wherein L1, L2 and L3 are dimensions along the first direction.
5. The semiconductor structure of claim 4, wherein the first segment of the first gate stack has a fourth length L4 above the middle, L4 being less than L1.
6. The semiconductor structure of claim 5, wherein a first ratio of L1/L4 is greater than 1.1; a second ratio of L2/L4 is greater than 1.2; and a third ratio of L3/L4 is greater than 1.4.
7. The semiconductor structure of claim 1, wherein the LRM layer includes at least one of tungsten, copper, aluminum, and copper aluminum alloy.
8. The semiconductor structure of claim 1, wherein each of one of the first fins further includes an n-type channel region doped of a p-type dopant and underlying the first gate stack.
9. The semiconductor structure of claim 8, further comprising:
second fins formed on the semiconductor substrate within a third region;
a second STI feature disposed on the semiconductor substrate within a fourth region; and
a second gate stack disposed directly on the second fins, wherein the second gate stack is free of the LRM layer and the second tantalum titanium nitride layer.
10. The semiconductor structure of claim 9, wherein the tantalum aluminum nitride layer of the second gate stack is shaped with a void defined therein.
11. The semiconductor structure of claim 9, further comprising a p-type channel region doped of an n-type dopant formed in the second fins, wherein the p-type channel region is underlying the second gate stack.
12. The semiconductor structure of claim 11, wherein
first source and drain features formed on the first fins, interposed by the n-type channel region, wherein the first gate stack, the first source and drain features, and the n-type channel are configured to an n-type field-effect transistor (nFET); and
second source and drain features formed on the second fins, interposed by the p-type channel region, wherein the second gate stack, the second source and drain features, and the p-type channel are configured to a p-type field-effect transistor (pFET).
13. The semiconductor structure of claim 1, wherein
the first tantalum titanium nitride layer in the second segment of the first gate stack is shaped to surround the titanium aluminum nitride layer from bottom and sidewalls;
the titanium aluminum nitride layer in the second segment of the first gate stack is shaped to surround the second tantalum titanium nitride layer from bottom and sidewalls; and
the second tantalum titanium nitride layer in the second segment of the first gate stack is shaped to surround the LRM layer from bottom and sidewalls.
14. The semiconductor structure of claim 1, wherein
the first gate stack further includes a first gate dielectric layer of a high-k dielectric material; and
the second gate stack further includes a second gate dielectric layer of the high-k dielectric material.
15. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region;
first fins disposed on the semiconductor substrate within the first region and second fins disposed on the semiconductor substrate within the second region;
a first gate stack disposed directly on the first fins, wherein the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) in sequence, wherein the first gate stack includes a first elongate shape oriented along a first direction, and wherein a first number of the first fins is 2; and
a second gate stack disposed directly on the second fins, wherein the second gate stack is free of the LRM and includes the first tantalum titanium nitride layer and the titanium aluminum nitride layer, wherein the LRM includes at least one of tungsten, copper, aluminum, and copper aluminum alloy, wherein the second gate stack includes a second elongate shape oriented along the first direction, wherein the first and second gate stacks are distanced away in a second direction that is orthogonal to the first direction, and wherein a second number of the second fins is greater than 5.
16. The semiconductor structure of claim 15, further comprising:
an n-type channel region formed on the first fins, wherein the n-type channel region is doped with a p-type dopant and is underlying the first gate stack;
a p-type channel region formed on the second fins, wherein the p-type channel region is doped with an n-type dopant and is underlying the second gate stack;
first source and drain features formed on the first fins, interposed by the n-type channel region, wherein the first gate stack, the first source and drain features, and the n-type channel are configured to an n-type field-effect transistor (nFET); and
second source and drain features formed on the second fins, interposed by the p-type channel region, wherein the second gate stack, the second source and drain features, and the p-type channel are configured to a p-type field-effect transistor (pFET).
17. The semiconductor structure of claim 16, wherein each of the first fins has an elongated shape oriented in a first direction;
the first gate stack has a first length L1 at a top surface, a second length L2 at a middle and a third length L3 at a bottom surface, wherein L2 is greater L1 and L3 is greater than L2, wherein L1, L2 and L3 are dimensions along the first direction.
18. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region being adjacent to the first region;
first fins formed on the semiconductor substrate within the first region, wherein the first fins are oriented in a first direction and disposed with a spacing d1 along a second direction being orthogonal to the first direction, and wherein a number of the first fins is greater than 5;
a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region, wherein the STI feature continuously extends to fill up the second region and spans a dimension d2 along the second direction, wherein a ratio d2/d1 is greater than 5; and
a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region, wherein
the second segment of the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) layer stacked in sequence,
the first segment of the first gate stack includes the first tantalum titanium nitride layer and the titanium aluminum nitride layer, and
the first segment of the first gate stack within the first region is free of the LRM layer and further defines a void surrounded by the titanium aluminum nitride layer.
19. The semiconductor structure of claim 18, wherein
the first segment of the first gate stack has a first length L1 at a top surface, a second length L2 at a middle and a third length L3 at a bottom surface,
the first segment of the first gate stack has a fourth length L4 above the middle, L4 being less than L1, and
L2 is greater L1, L3 is greater than L2, and L4 is less than L1.
20. The semiconductor structure of claim 15, wherein
first source and drain features formed on the first fins, interposed by the n-type channel region, wherein the first gate stack, the first source and drain features, and the n-type channel are configured to an n-type field-effect transistor (nFET); and
second source and drain features formed on the second fins, interposed by the p-type channel region, wherein the second gate stack, the second source and drain features, and the p-type channel are configured to a p-type field-effect transistor (pFET).
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