US10658380B2 - Formation of termination structures in stacked memory arrays - Google Patents
Formation of termination structures in stacked memory arrays Download PDFInfo
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- US10658380B2 US10658380B2 US16/160,146 US201816160146A US10658380B2 US 10658380 B2 US10658380 B2 US 10658380B2 US 201816160146 A US201816160146 A US 201816160146A US 10658380 B2 US10658380 B2 US 10658380B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H01L27/11582—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L27/11524—
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- H01L27/1157—
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- H01L27/11573—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Definitions
- RAM random-access memory
- ROM read only memory
- DRAM dynamic random access memory
- SDRAM synchronous dynamic random access memory
- RRAM resistive memory
- Flash memory among others.
- Memory devices can be utilized as volatile and non-volatile data storage for a wide range of electronic applications. Volatile memory may require power to maintain its data, whereas non-volatile memory may provide persistent data by retaining stored data when not powered. Flash memory, which is just one type of non-volatile memory, can use a one-transistor memory cells that allow for high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices.
- SSDs solid state drives
- the formation of stacked memory arrays can include a replacement gate process.
- a replacement gate process can be used to remove dielectrics from the stack at levels at which memory cells are to be formed adjacent to the semiconductor structures and to form conductive access lines (e.g., metal access lines) in place of the removed dielectrics.
- conductive access lines e.g., metal access lines
- an opening e.g., a slot or slit
- an opening can be formed through the stack to provide access to the various levels in the stack in order to remove selected dielectric material layers (e.g., via an etchant) and replace them with levels of conductive material (e.g., a metal) that can serve as the access lines.
- FIG. 1 is a top view at a particular processing stage associated with forming a stacked memory array, according to the background art.
- FIGS. 2A to 2S are various views corresponding to particular stages of processing associated with forming a stacked memory array in accordance with a number of embodiments of the present disclosure.
- FIGS. 4A to 4D are various views corresponding to particular stages of processing associated with forming a stacked memory array in accordance with a number of embodiments of the present disclosure.
- FIGS. 5A to 5D are various views corresponding to particular stages of processing associated with forming a stacked memory array in accordance with a number of embodiments of the present disclosure.
- FIGS. 6A to 6D are various views corresponding to particular stages of processing associated with forming a stacked memory array in accordance with a number of embodiments of the present disclosure.
- FIG. 8 is a block diagram of an apparatus in accordance a number of embodiments of the present disclosure.
- a termination structure and contacts can be formed concurrently through a stack of alternating first and second dielectrics.
- the first dielectrics can be at levels in the stack at which memory cells are to be formed adjacent to semiconductor structures passing through the stack.
- An additional dielectric can be formed over an upper surface of the stack and an upper surface of the termination structure.
- the termination structure can include a dielectric liner around a conductor.
- An opening can be formed through the additional dielectric and the stack between groups of the semiconductor structures so that the first opening exposes an upper surface of the conductor. For example, the opening can provide access to the stack during subsequent processing that can occur during a replacement gate process.
- the conductor can be removed from the termination structure to form an additional opening lined with the dielectric liner.
- the openings (e.g., slots) used to access the alternating dielectrics can be formed (e.g., concurrently) by a single etch through the dielectric stack in a first direction and in a second (e.g., transverse) direction, which facilitates electrical isolation of blocks of memory cells from each other after the openings are filled with a dielectric.
- the transverse etch through the stack forms T-intersections that can be difficult to form and that can have various drawbacks.
- Various embodiments of the present disclosure can utilize termination structures that can help isolate the blocks of memory cells from each other without forming T-intersections, thereby avoiding the difficulties and drawbacks associated therewith.
- termination structures can be specifically tailored to help isolate the blocks of memory cells from each other.
- termination structures can have tabs, such as tabs having rectangular or triangular profiles, or prongs, such as tapered prongs or prongs having rectangular profiles.
- FIG. 1 is a top view at a particular processing stage associated with forming a stacked memory array, according to the background art.
- a stack 101 of alternating dielectrics such as nitride alternating with oxide, includes sets 106 - 1 to 106 - 6 of contacts 104 passing through stack 101 and groups 118 - 1 and 118 - 2 of semiconductor structures 105 passing through stack 101 .
- Contacts 104 can be formed after semiconductor structures 105 are formed.
- memory cells can be partially formed adjacent to semiconductor structures 105 (e.g., at levels in stack 101 containing the nitride) before contacts 104 are formed.
- the partially formed memory cells can be completed by accessing the memory cells through opening 108 .
- a conductor such as metal (e.g. tungsten) can be supplied though opening 108 to form lines, such as access lines that can be coupled to the memory cells and that can extend into the regions including sets 106 - 1 and 106 - 2 of contacts 104 so that the contacts 104 of sets 106 - 1 and 106 - 2 pass through oxide alternating with metal, for example.
- access lines corresponding to group 118 - 1 can extend into the region including set 106 - 1
- access lines corresponding to group 118 - 2 can extend into the region including set 106 - 2 .
- formation of opening 108 , removal of the nitride, completing the memory cells, and forming the access lines can be formed as part of a replacement gate process.
- opening 108 can be formed during a single process step (e.g., during a single etch) that can form the segments 110 - 1 to 110 - 3 and segments 112 - 1 and 112 - 2 concurrently.
- the T-intersections can be formed by performing a first etch through the stack 101 to form segments 110 - 1 to 110 - 3 and a second etch through the stack 101 to form segments 112 - 1 and 112 - 2 . Forming such T-intersections can be difficult and can have various drawbacks. For instance, forming segments 112 - 1 and 112 - 2 can result in over etching or under etching, which can result in inadequate separation of the groups 118 - 1 and 118 - 2 or can prevent adequate electrical isolation.
- Segment 112 - 1 can form a continuous space (e.g., discontinuity) in stack 101 that can decouple the region having sets 106 - 5 and 106 - 6 from the ends of groups 118 - 1 and 118 - 2 .
- Segment 112 - 2 can form a continuous space in stack 101 that can decouple the region having sets 106 - 3 and 106 - 4 from the ends of sets 106 - 1 and 106 - 2 .
- stress in stack 101 that can occur as a result of processing prior to the formation of opening 108 can be released during the formation of opening 108 , especially as a result of the formation segments 112 - 1 and 112 - 2 .
- semiconductor structures 105 can move after opening 108 is formed due to the stress release, especially in a direction parallel to segments 110 in the regions adjacent to segments 112 - 1 and 112 - 2 , as a result of the discontinuities caused by segments 112 - 1 and 112 - 2 .
- the discontinuities can result in additional movement during the removal of the nitride and/or during the formation of the access lines.
- the movement can make it difficult to align data line contacts with semiconductor structures 105 , such as to couple data lines to the semiconductor structures 105 .
- the movement of semiconductor structures 105 can be relatively large at and near the ends of the ends of groups 118 - 1 and 118 - 2 and relatively little away from the ends.
- the memory cells adjacent to the semiconductor structures 105 at and near the ends of groups 118 - 1 and 118 - 2 can be “dummy” memory cells. However, this can reduce the total number of memory cells available for data storage.
- FIG. 2A is a top view corresponding to a particular stage of processing associated with forming a stacked memory array in accordance with a number of embodiments of the present disclosure.
- the array can be a three-dimensional NAND memory array.
- FIG. 2B is a cross-section viewed along line B-B in FIG. 2A during the processing stage corresponding to FIG. 2A in accordance with a number of embodiments of the present disclosure.
- FIG. 2C is a cross-section viewed along line C-C in FIG. 2A during the processing stage corresponding to FIG. 2A in accordance with a number of embodiments of the present disclosure.
- FIG. 2D is a cross-section viewed along line D-D in FIG. 2A during the processing stage corresponding to FIG.
- FIGS. 2A to 2D can correspond to a processing stage that can occur after a number of processing stages have occurred.
- a processing stage can include a number of steps that can have a number of sub-steps.
- Stack 201 can be formed over a semiconductor 223 .
- conductive plugs such as metal plugs (e.g., tungsten plugs) can be formed in portions of semiconductor 223 , as shown in FIGS. 2B to 2D for a metal plug 222 .
- semiconductor 223 can be formed over a metal silicide 224 , such as tungsten silicide.
- Semiconductor structures 205 - 1 to 205 - 3 and semiconductor 223 can be polysilicon, silicon conductively doped to have a p-type conductivity (e.g., single crystal p ⁇ silicon), or the like.
- Dielectrics 220 can be oxide, and dielectrics 221 can be nitride.
- memory cells 225 can be partially formed adjacent to each semiconductor structure 205 at levels of stack 201 having dielectrics 221 .
- a tunnel dielectric 227 e.g., tunnel oxide
- a charge storage structure 228 e.g., a charge trap, floating gate, etc.
- a blocking dielectric 230 e.g., oxide
- a respective dielectric 221 can be adjacent to a respective blocking dielectric 230 .
- tunnel dielectric 227 , charge storage structure 228 , and blocking dielectric 230 can wrap completely around (e.g., completely surround) the corresponding semiconductor structure 205 .
- a select transistor 232 can be partially formed adjacent to each semiconductor structure 205 at a level of stack 201 having an uppermost dielectric 221
- a select transistor 234 can be partially formed adjacent to each semiconductor structure 205 at a level of stack 201 having a lowermost dielectric 221
- a gate dielectric 236 e.g., gate oxide
- select transistors 232 and 234 can be formed adjacent to each semiconductor structure 205 .
- Respective dielectrics 221 can be adjacent to the respective gate dielectrics 236 .
- gate dielectric 236 can wrap completely around the corresponding semiconductor structure 225 .
- semiconductor structures 205 can be formed prior to the processing stage depicted in FIGS. 2A to 2D
- select transistors 232 and 234 and memory cells 225 can be partially formed prior to the processing stage depicted in FIGS. 2A to 2D .
- sets of openings 238 - 1 to 238 - 3 are formed (e.g., etched) through stack 201 in a region 213 , such as a contact region, of stack 201 , stopping at an upper surface of a dielectric plug 222 .
- Openings 240 e.g., openings 240 - 1 and 240 - 2 ), such as termination openings, are formed (e.g., etched) through stack 201 concurrently with forming openings 238 - 1 to 238 - 3 , stopping at an upper surface of a dielectric plug 222 .
- openings 240 - 1 and 214 - 2 can be formed through stack 201 in a region 214 of stack 201 adjacent to region 202 .
- Region 214 can be referred to as a non-memory-cell region, for example, in that memory cells might not be formed there.
- FIG. 2E is a top view corresponding to a stage of processing following the stage of processing corresponding to FIG. 2A in accordance with a number of embodiments of the present disclosure.
- FIG. 2F is a cross-section viewed along line F-F in FIG. 2E during the processing stage corresponding to FIG. 2E in accordance with a number of embodiments of the present disclosure.
- FIG. 2G is a cross-section viewed along line G-G in FIG. 2E during the processing stage corresponding to FIG. 2E in accordance with a number of embodiments of the present disclosure.
- forming contacts 204 and termination structures 247 can include concurrently forming dielectric liners 248 , such as oxide liners, in openings 238 , as shown in FIGS. 2E and 2G , and dielectric liners 249 , such as oxide liners, in openings 240 , as shown in FIGS. 2E and 2F .
- a conductive structure such as a metal structure 250 (e.g., of tungsten), is formed in each of the openings 238 lined with the dielectric liners 248 adjacent to dielectric liners 248 , so that the dielectric liners 248 surround the metal structures 250 .
- metal structures 250 can be formed in the openings 238 lined with dielectric liners 248 concurrently with forming metal structures 252 in the openings 240 lined with dielectric liners 249 .
- Each contact 204 can include a metal structure 250 surrounded by a dielectric liner 248
- each termination structure 247 can include a metal structure 252 surrounded by a dielectric liner 249 .
- a dielectric 251 that can be oxide can be formed over an upper surface of stack 201 , over upper surfaces of contacts 204 , and over upper surfaces of termination structures 247 , and shown in FIGS. 2E to 2G .
- the processing stage depicted in FIGS. 2P-2S can form a memory array 260 , for example.
- the openings 254 provide access to the spaces 258 to complete the formation of memory cells 225 and select transistors 232 and 234 .
- formation of memory cells 225 and select transistors 232 and 234 can be completed as part of a replacement gate process.
- a dielectric 261 can be supplied through openings 254 to form dielectric 261 in the spaces 258 adjacent to gate dielectrics 236 and blocking dielectrics 230 , as shown in FIG. 2S .
- dielectric 261 can be high-dielectric-constant (high-K) dielectric, such as alumina (Al 2Q3 ), hafnia (HfO 2 ), zirconia (ZrO 2 ), praeseodymium oxide (Pr 2Q3 ), hafnium tantalum oxynitride (HfTaON), hafnium silicon oxynitride (HfSiON), or the like.
- high-K dielectric such as alumina (Al 2Q3 ), hafnia (HfO 2 ), zirconia (ZrO 2 ), praeseodymium oxide (Pr 2Q3 ), hafnium tantalum oxynitride (HfTaON), hafnium
- a conductor such as metal 263 (e.g., tungsten), can be supplied through openings 254 to form metal 263 in the spaces 258 adjacent to interface metallic 262 , as shown in FIG. 2S .
- metal 263 can form lines, such as access lines that can include control gates of memory cells 225 and control lines that can include gates of select transistors 232 and 234 .
- levels of metal 263 can be formed in the spaces 258 as part of a replacement gate process.
- dielectric 261 , interface metallic 262 , and metal 263 can wrap completely around the corresponding semiconductor structures 205 .
- FIG. 3C is a cross-section corresponding to a processing stage following the processing stage of FIG. 3B in accordance with a number of embodiments of the present disclosure.
- FIG. 3C can correspond to the cross-section of FIG. 2N viewed along line N-N in FIG. 2M .
- the cross-section in FIG. 3C can be below the dielectric 351 and below the upper ends dielectric liner 349 .
- dielectrics in stack 401 can be removed by accessing those dielectrics through opening 454 , such as during a replacement gate process, to form spaces in place of the removed dielectrics.
- the removal of the dielectrics can form a structure similar to the structure in FIG. 2O .
- the termination of opening 454 at V-shaped surface 474 as shown in FIG.
- FIG. 5C is a cross-section corresponding to a processing stage following the processing stage of FIG. 5B in accordance with a number of embodiments of the present disclosure.
- FIG. 5C can correspond to the cross-section of FIG. 2N viewed along line N-N in FIG. 2M .
- the cross-section in FIG. 5C can be below the dielectric 551 and below the upper ends dielectric liner 549 .
- portions of opening 554 can terminate at prongs 573 while another portion can extend into a recess between prongs 573 and terminate at a recessed surface 574 of dielectric liner 549 , such as the surface of sidewall 553 , between prongs 573 .
- recessed surface 574 can be recessed from the ends of prongs 572 .
- dielectrics in stack 501 can be removed by accessing those dielectrics through opening 554 , such as during a replacement gate process, to form spaces in place of the removed dielectrics.
- the removal of the dielectrics can form a structure similar to the structure in FIG. 2O .
- FIG. 5D is a cross-section corresponding to a processing stage following the processing stage of FIG. 5C in accordance with a number of embodiments of the present disclosure.
- FIG. 5D can correspond to the cross-section of FIG. 2R viewed along line R-R in FIG. 2Q .
- the cross-section in FIG. 5D can be below the dielectric 551 and below the upper ends dielectric liner 549 .
- FIG. 6A is a top view corresponding to a particular stage of processing associated with forming a stacked memory array in accordance with a number of embodiments of the present disclosure.
- An opening having a perimeter 641 can be formed through a stack 601 of alternating dielectrics in a manner similar to forming openings 240 , as previously described in conjunction with FIGS. 2A and 2B .
- stack 601 can be stack 201 .
- the opening can replace an opening 240 and can be formed in the region 214 of stack 201 concurrently with forming contact openings 238 .
- a conductive structure such as a metal structure 652 (e.g., of tungsten), can be formed in the lined opening adjacent to liner 649 to form a termination structure 647 that includes dielectric liner 649 surrounding metal structure 652 .
- a metal structure 652 e.g., of tungsten
- each of the termination structures 247 - 1 and 247 - 2 in FIGS. 2E and 2F can be replaced by a respective termination structure 647 .
- Metal structure 652 can be formed concurrently with the metal structures 260 in FIGS. 2E and 2G , for example.
- termination structure 647 can be formed concurrently with contacts, such as contacts 204 in FIGS. 2E and 2G .
- FIG. 6B is a top-down view of a processing stage following the processing stage corresponding to FIG. 6A in accordance with a number of embodiments of the present disclosure.
- a dielectric 651 such as oxide, can be formed over stack 601 and an upper surface of termination structure 647 .
- dielectric 651 can be formed over an upper surface 672 of metal structure 652 .
- opening 654 can be formed through dielectric 651 and stack 601 .
- opening 654 can be an opening 264 in FIGS. 2H to 2K and can be formed between groups of semiconductor structures, such as between the groups 218 - 1 and 218 - 2 of semiconductor structures, so that the opening exposes at least a portion of the upper surface 672 of metal structure 652 .
- a portion of opening 654 can extend over a portion of metal structure 652 and terminate there.
- a remaining portion of opening 654 can terminate at sidewall 653 below upper surface 672 and below dielectric 651 in a manner similar to opening 264 terminating at sidewall 253 in FIGS. 2I and 2J .
- portions of opening 654 can terminate at an inverted V-shaped surface 674 of sidewall 653 .
- dielectric liner 649 can have an inverted V-shaped recess, bounded inverted V-shaped surface 674 , in which opening 654 can terminate.
- the inverted V-shaped recess can include a portion of stack 601 and can be between prongs 672 .
- sidewall 669 can be transverse to opening 654 .
- dielectrics in stack 601 can be removed by accessing those dielectrics through opening 654 , such as during a replacement gate process, to form spaces in place of the removed dielectrics.
- the removal of the dielectrics can form a structure similar to the structure in FIG. 2O .
- the termination of opening 654 at prongs 573 and at inverted V-shaped surface 674 as shown in FIG.
- opening 6C can prevent removal material in opening 654 from flowing around dielectric liner 649 and forming a path for extraneous metal could cause an electrical short between access lines formed from the metal on either side of opening 654 , such as between access lines corresponding to group 218 - 1 and access lines corresponding to group 218 - 2 in FIG. 2L .
- FIG. 6D is a cross-section corresponding to a processing stage following the processing stage of FIG. 6C in accordance with a number of embodiments of the present disclosure.
- FIG. 6D can correspond to the cross-section of FIG. 2R viewed along line R-R in FIG. 2Q .
- the cross-section in FIG. 6D can be below the dielectric 661 and below the upper ends dielectric liner 649 .
- opening 654 and the opening 656 lined with dielectric liner 649 can be lined with a dielectric liner 664 , such as an oxide liner.
- dielectric liner 664 can be formed adjacent to dielectric liner 649 in opening 656 .
- Dielectric liner 649 can wrap completely around dielectric liner 664 below the upper ends of the dielectric liner 649 and below dielectric 651 .
- a semiconductor structure 666 (e.g., of polysilicon), is formed in the opening 654 lined with liner 664 by forming semiconductor structure 666 adjacent to that liner 664 .
- a semiconductor structure 667 (e.g., of polysilicon) is formed in the opening 656 lined with liner 664 by forming semiconductor structure 667 adjacent to that liner 664 .
- Dielectric liner 664 can wrap completely around semiconductor structure 667 below the upper ends of the dielectric liner 664 and below dielectric 661 .
- the structure including a dielectric liner 664 wrapped around semiconductor structure 667 and dielectric liner 649 wrapped around dielectric liner 664 can be a termination structure 671 .
- semiconductor structure 666 and the dielectric liner 664 on either side of semiconductor structure 666 can terminate at the inverted V-shaped surface 674 of sidewall 653 .
- sidewall 669 can be transverse to semiconductor structure 666 and the dielectric liner 664 on either side of semiconductor structure 666 .
- a structure with a semiconductor structure 666 adjacent to dielectric liner 664 can pass through a stack of dielectrics alternating with layers of metal, such as stack dielectrics 220 alternating with layers of metal 263 ( FIG. 2S ), between blocks of memory cells, such as between blocks 268 - 1 and 268 - 1 and between blocks 268 - 2 and 268 - 3 ( FIG. 2P ).
- semiconductor structures 705 , dielectrics 720 , semiconductor 723 , and metal 763 can be as previously described for respective semiconductor structures 205 , dielectrics 220 , semiconductor 223 , and metal 263 shown in FIGS. 2A to 2S .
- the uppermost and lowermost levels of metal 763 can be control lines that form or are coupled to control gates of select transistors 732 and 734 , respectively.
- the levels of metal 763 between the uppermost and lowermost levels of metal 763 can be access lines that form or are coupled to control gates of memory cells 725 .
- Stair-step structure 775 includes steps 776 that can each include a respective level of metal 763 over an adjacent dielectric 720 .
- a respective contact 778 is coupled to the level of metal 763 of each respective step 776 .
- Respective contacts 778 are coupled to activation (e.g., access) circuitry by respective lines 779 .
- Data lines 780 are coupled to semiconductor structures 705 by data line contacts 782 .
- Openings 754 are formed through the stack. Openings 754 can be as previously described for openings 254 . Openings 754 can terminate at termination structures, such as dielectric liners 249 , 349 , 449 , 559 , or 649 , in a manner similar to (e.g., the same as) as previously described for openings 254 , 354 , 454 , 554 , or 654 .
- FIG. 8 is a block diagram of an apparatus in accordance a number of embodiments of the present disclosure.
- the apparatus can be an electronic system, such as a computing system 890 .
- Computing system 890 can include a memory system 892 that can be a solid-state drive (SSD), for instance.
- Memory system 892 can include a host interface 894 , a controller 895 , such as a processor and/or other control circuitry, and a number of memory devices 896 , such as NAND flash devices, that provide a storage volume for the memory system 892 .
- a memory device 896 can have a number of memory arrays 860 , such as memory array 260 shown in FIG. 2P or memory array 760 shown in FIG. 7 .
- semiconductor can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure.
- semiconductor is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art.
- SOS silicon-on-sapphire
- SOI silicon-on-insulator
- TFT thin film transistor
- doped and undoped semiconductors epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art.
- previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.
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