US10546745B2 - Semiconductor processing method - Google Patents

Semiconductor processing method Download PDF

Info

Publication number
US10546745B2
US10546745B2 US15/844,905 US201715844905A US10546745B2 US 10546745 B2 US10546745 B2 US 10546745B2 US 201715844905 A US201715844905 A US 201715844905A US 10546745 B2 US10546745 B2 US 10546745B2
Authority
US
United States
Prior art keywords
semiconductor material
organosulfur
solution
cap layer
sulfur
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US15/844,905
Other versions
US20190189434A1 (en
Inventor
Yun Seog Lee
Joel Pereira de Souza
Devendra K. Sadana
Marinus Hopstaken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US15/844,905 priority Critical patent/US10546745B2/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOPSTAKEN, MARINUS, SADANA, DEVENDRA K., DE SOUZA, JOEL PEREIRA, LEE, YUN SEOG
Publication of US20190189434A1 publication Critical patent/US20190189434A1/en
Application granted granted Critical
Publication of US10546745B2 publication Critical patent/US10546745B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H10P14/668—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H10D64/011—
    • H10P14/6326—
    • H10P14/662—
    • H10P14/69215—
    • H10P14/69391—
    • H10P14/69392—
    • H10P32/14—
    • H10P32/174—
    • H10P50/00—
    • H10P50/283—

Definitions

  • the present application relates to methods of manufacturing semiconductor devices, such as, for example, transistors, in III-V semiconductor substrates. Further aspects of the present application relate to surface passivation of semiconductor substrates and to sulfur-doping of III-V semiconductor substrates with nanoscale dimensional control.
  • Passivation of semiconductor materials during a manufacturing process may allow greater control over electrical properties of an integrated circuit generated by the manufacturing process. Passivation allows a manufacturer to protect surfaces of a semiconductor material or a semiconductor film stack to avoid the formation of oxides or to prevent the adhesion of contaminants to a semiconductor stack or material. Some passivation may protect semiconductor materials such as an intrinsic semiconductor (e.g., silicon) or compound semiconductors (e.g., III-V semiconductors such as, for example, GaAs) from reacting with atmospheric oxygen to form a native oxide layer on the top/exposed surface of the material. Native oxide layers may be removed from a semiconductor material with additional processing steps with concomitant increases in contaminants and/or defects. Undetected native oxide may modify an electrical characteristic of an integrated circuit, such as increasing contact resistance, reducing clock speed, or decreasing I on for a transistor in an integrated circuit.
  • semiconductor materials such as an intrinsic semiconductor (e.g., silicon) or compound semiconductors (e.g., III-V semiconductors such as, for example, GaAs) from
  • Semiconductor materials may be passivated by exposure of the semiconductor material to a sulfur source, wherein the sulfur interacts with the top/exposed surface of the semiconductor material to form a protective sulfur layer on the top/exposed surface of the semiconductor material.
  • Sulfur deposition may be performed by applying a solution of ammonium sulfide (NH 4 ) 2 S to the semiconductor material.
  • NH 4 ammonium sulfide
  • use of ammonium sulfide has significant drawbacks. For example, at temperatures over 15° C., ammonium sulfide decomposes into ammonia and hydrogen sulfide, which are toxic to breathe or ingest.
  • ammonium sulfide uses costly exhaust systems to protect employees and facilities from exposure to toxic decomposition byproducts, and incurs higher waste disposal costs. Further, because ammonium sulfide solutions must be maintained at low temperatures to avoid decomposition into hydrogen sulfide, ammonium sulfide processing exhibits low rates of surface sulfurization (low rates of surface coverage, and thin sulfur film formation). Improvement to semiconductor passivation with sulfur (sulfurization) can improve protection against native oxide formation.
  • Doping of semiconductor materials to modify conductivity of a semiconductor material, or to modify a band gap of a semiconductor material may be performed by implanting dopants into the semiconductor material.
  • Implanting may involve accelerating a dopant atom to a high velocity and directing the accelerated dopant atom into a semiconductor material.
  • An accelerated dopant atom may penetrate to a depth below the surface of the semiconductor material according to the mass of the dopant and the acceleration applied to the dopant atom before the dopant atom strikes the semiconductor surface.
  • the penetration of the implanted dopant atoms may disrupt the crystal lattice of the semiconductor material, which disruption may be healed by an annealing operation performed after implanting of dopant atoms.
  • Implantation into intrinsic semiconductor e.g., silicon
  • annealing of implanted intrinsic semiconductor may restore crystal structure to near-original condition.
  • compound semiconductors such as III-V semiconductors may undergo irreparable damage following implanting and annealing. Localized stoichiometry may be disrupted after implant and annealing, resulting in small regions with deviations from the average stoichiometry of the bulk semiconductor material. Such deviations may result in lowered dopant activation, or higher junction leakage or leakage currents.
  • Sulfur may be used as a dopant for III-V semiconductors because sulfur atoms may be thermally diffused into III-V semiconductors without disrupting the crystal lattice, and without interrupting the uniform distribution of group III and group V atoms within the semiconductor material. Dimensions of a junction formed by thermal diffusion of sulfur may be regulated according to the annealing conditions used to thermally diffuse sulfur atoms into the semiconductor material. Sulfur-doping of III-V semiconductor substrates with nanoscale dimensional control may be improved with improvement in control and coverage amounts of sulfur on a semiconductor material.
  • aspects of the present application relate to a method of processing a semiconductor material which may include applying an organosulfur solution to a top surface of the semiconductor material. Some aspects of the present application relate to an organosulfur solution having at least one organosulfur compound with at least one sulfur atom double bonded to a carbon atom, and a pH of not less than 8.
  • FIG. 1 is a flowchart of a method of passivating a semiconductor surface, according to some embodiments of the present application.
  • FIG. 2 is a flowchart of a method of doping a semiconductor material with sulfur, according to some embodiments of the present application.
  • FIGS. 3A-3F are cross-sectional diagrams of a semiconductor device at stages of a manufacturing process, according to some embodiments of the present application.
  • a semiconductor material whether an intrinsic semiconductor (e.g., silicon) or a compound semiconductor (e.g., SiGe, or a III-V semiconductor, such as GaAs), may be improved over traditional ammonium sulfide [(NH 4 ) 2 S] by using solutions containing an organosulfur compound, such as a thiourea compound, in a strong base.
  • a compound semiconductor may be doped to include a third semiconductor material, such as GaAs being doped with indium to produce the compound semiconductor material InGaAs.
  • Other embodiments of doped compound semiconductor materials are also envisioned in the present disclosure.
  • Thiourea compounds have the general chemical formula (R 1 R 2 N)(R 3 R 4 N)C ⁇ S, where a sulfur atom is double-bonded to a central carbon atom, and the central carbon is singly-bonded to two nitrogen atoms, where each nitrogen atom has two substituents: the first nitrogen has substituents R 1 and R 2 , and the second nitrogen has two substituents R 3 and R 4 .
  • the thiourea substituents R 1 —R 4 may be hydrogen, or aliphatic substituents.
  • An aliphatic substituents may be a saturated alkane such as a methyl group, an ethyl group, a propyl group, or an isopropyl group (i.e., 1—methyl—ethane), although other aliphatic substituents, both saturated and unsaturated, are also envisioned in the present application.
  • Other kinds of organosulfur compounds that may serve as sulfur sources for sulfur-based passivation or doping of semiconductor materials may also include thioamides (R 1 R 2 N)(R 3 )C ⁇ S or other organosulfur compounds where a sulfur atom is double bonded to a carbon atom.
  • the thioamide substituents R 1 —R 3 may be hydrogen, or aliphatic substituents as described above with regard to thiourea compound substituents.
  • Aliphatic substituents for thioamides may include saturated alkanes such as a methyl group, an ethyl group, a propyl group, or an isopropyl group (i.e., 1—methyl—ethane), although other aliphatic substituents are also envisioned.
  • an organosulfur compound has a plurality of sulfur atoms double bonded to carbon atoms.
  • An organosulfur compound may undergo a chemical reaction in strongly basic solution (e.g., a solution having a pH of at least 8) in order to liberate a double-bonded sulfur to form a sulfide S 2 ⁇ ion in solution.
  • strongly basic solution e.g., a solution having a pH of at least 8
  • thiourea (NH 2 )(NH 2 )C ⁇ S reacts with strong base (e.g., a group I base such as NaOH or KOH, or a group II base such as Mg(OH) 2 , or an inorganic base such as ammonium hydroxide or TMAH (tetramethylammoniumhydroxide), to produce sulfide ion in solution.
  • strong base e.g., a group I base such as NaOH or KOH, or a group II base such as Mg(OH) 2
  • an inorganic base such as ammonium hydroxide or TMAH (tetramethylammoniumhydr
  • bases may be used to form sulfide ion in solution, so long as the base is capable of deprotonation of the organosulfur molecule to release sulfide ion, or capable of electrophilic substitution-type interactions with the carbonyl carbon to release sulfide ion from the organosulfur molecule.
  • a base may be sufficiently strong to form sulfide ion when the base can deprotonate an organosulfur compound and trigger or promote sulfur liberation from the organosulfur molecule.
  • a base may also promote sulfur liberation from organosulfur molecules when the base can react with a carbon atom that is double bonded to a sulfur atom, promoting formation of, e.g., a C—O single bond, and resulting in a C ⁇ S double bond becoming a C—S single bond.
  • Sulfide ion may form weak chemical bonds with other sulfur atoms, and adhere to semiconductor materials using Wan der Waals forces, to form protective films of sulfur on semiconductor materials.
  • a rate of sulfurization/sulfur deposition of a semiconductor material may increase by increasing the temperature of the organosulfur solution.
  • a thickness of a sulfur film on the semiconductor material may be increased by extending the time a sulfurization solution is maintained on an exposes surface of a semiconductor material, and by increasing the temperature of the solution to increase chemical reaction rates.
  • a concentration of organosulfur compound in an organosulfur solution may be to saturation, or may be less than saturation, and still perform a sulfurization process on an exposed surface of semiconductor material.
  • Ammonium sulfide, in solid or in solutions can decompose (i.e., form hydrogen sulfide) at temperatures above 15° C.
  • Organosulfur compounds, or solutions thereof do not undergo decomposition like ammonium sulfide.
  • An organosulfur solution may be an aqueous solution, an alcohol-based solution, or have a mixture of water and an alcohol, containing organosulfur molecules.
  • Organosulfur compounds may be applied to a semiconductor substrate at temperatures ranging from just above the freezing point of a solvent for an organosulfur solution (e.g., 0° C. for water, or below 0° C. for simple alcohols such as methanol or ethanol, up to almost the boiling point of a solvent (64° C. for methanol, 78° C. for ethanol, or 100° C. for water), without decomposition.
  • a solvent for an organosulfur solution e.g., 0° C. for water, or below 0° C. for simple alcohols such as methanol or ethanol, up to almost the boiling point of a solvent (64° C. for methanol, 78° C. for ethanol, or 100° C. for water).
  • FIG. 1 is a flow diagram depicting operations in a method 100 of treating semiconductor materials, according to some embodiments of the present application.
  • the method begins in operation 101 .
  • Method 100 includes an optional cleaning operation 110 , wherein a top surface of a semiconductor substrate is treated to remove particles and/or residues form the top surface. Particles and residues may interfere with subsequent processing steps, including film deposition, patterning, and/or etching.
  • Method 100 also includes an optional masking operation 120 , wherein a mask is formed on the top surface of the semiconductor substrate.
  • a mask may be formed by depositing a mask layer on atop surface of the semiconductor substrate, and the mask layer may be patterned using photolithography techniques.
  • a mask layer may be a layer of photoresist and a pattern in the mask layer may be formed by exposing the layer of photoresist with patterned light or radiation, and a portion of the layer photoresist removed by developing the layer of photoresist in a solvent.
  • Method 100 may include an etching operation 130 , wherein a native oxide on the top surface of the semiconductor material may be removed from an exposed portion of the top surface of the semiconductor material. (See FIG.
  • Native oxide may be removed from a semiconductor material by etching using an aqueous etching solution such as hydrofluoric acid (HF), or by a plasma etching process, using a gas mixture such as argon and HF.
  • Method 100 may further include a sulfur-deposition operation (or, a passivation operation) 140 , wherein an organosulfur solution is applied to the top surface of the semiconductor material.
  • the organosulfur solution may be heated, prior to application, to a temperature between 15° C.
  • An organosulfur solution may include a thiourea compound or a thioamide compound, or a mixture thereof, according to some embodiments of the present application. Some embodiments of the present application may apply a plurality of organosulfur solutions to a top surface of the semiconductor material. In some embodiments of the present application, the semiconductor material may be rinsed between applications of organosulfur solutions to the semiconductor material. The method 100 ends with operation 199 .
  • FIG. 2 is a flow diagram depicting operations in a method 200 of treating semiconductor materials, according to some embodiments of the present application.
  • Method 200 begins with operation 201 .
  • Method 200 contains operations 210 , 220 , 230 , and 240 that are be analogous to operations 110 , 120 , 130 , and 140 , respectively, of method 100 .
  • operation 230 (applying a mask layer) may be repeated following a first performance of operation 240 (forming a sulfur layer), and operation 240 may be repeated a second time following the second performance of operation 230 .
  • a thickness of the sulfur layer may be increased.
  • a sulfur layer may be formed with a first thickness in the area that was exposed during the first performance of operation 240 , and subsequently masked by the second performance of operation 230 , while the sulfur may have a second thickness in the area that was exposed (i.e., not masked) during both the first and second performances of operation 240 .
  • Method 200 includes operation 250 , wherein a cap layer is deposited onto a sulfur layer formed during sulfur-deposition operation 240 .
  • a cap layer may serve to trap sulfur below the cap layer and against the top surface of the semiconductor material. In areas where a mask layer may be deposited, a cap layer may trap the deposited sulfur below the cap layer and against a top surface of the mask layer material.
  • a cap layer may include one or more dielectric layers. When a single dielectric material is used as the dielectric layer/cap layer, the dielectric material may include one of silicon dioxide (SiO 2 ), TEOS, spin-on glass, silicon nitride, silicon oxy-nitride, aluminum oxide (Al 2 O 3 ), or hafnium dioxide (HfO 2 ).
  • the plurality of layers may include two or more of silicon dioxide (SiO 2 ), TEOS, spin-on glass, silicon nitride, silicon oxy-nitride, aluminum oxide (Al 2 O 3 ), or hafnium dioxide (HfO 2 ), or some other inorganic oxide or metal oxide.
  • each dielectric layer has an individual dielectric material thickness, which individual thickness may be the same as, or different from, the thickness of another dielectric layer in the cap layer.
  • the cap layer may have a thickness raging from 5 nm to 20 nm, although greater and lesser cap layer thicknesses are also envisioned.
  • Method 200 includes an anneal operation 260 , wherein the semiconductor stack, including the semiconductor material, the sulfur layer, and the cap layer, are annealed in order to drive the atoms of the sulfur layer (formed during operation 240 ) into the lattice of the semiconductor.
  • Anneal operation 260 may include heating the semiconductor stack to temperatures ranging from 250° C. to 400° C., although anneal temperatures greater and lesser than the recited range are also envisioned in the present application.
  • Anneal operation 260 may also include heating the semiconductor stack for an anneal time ranging from 20 minutes to 40 minutes, although times greater than and lesser than the recited range are also envisioned by the present application.
  • an anneal operation may be performed by heating a semiconductor stack to an anneal temperature of 250° C. for an anneal period of 20 minutes, although anneal times greater than 20 minutes are also envisioned. In some embodiments of the present application, an anneal operation may be performed by heating a semiconductor stack to an anneal temperature of 400° C. for an anneal period of 30 minutes, although anneal periods longer or shorter than 30 minutes are also envisioned.
  • Annealing may take place in an RTP (rapid thermal annealing) furnace, or by laser annealing, or by some other process of heating the wafer near the exposed portion of the top surface of the semiconductor material to drive the atoms of the sulfur layer (formed during operation 240 ) into the lattice of the semiconductor. Rapid annealing may take place with material heating up to 700° C. if the anneal period is in the millisecond range.
  • RTP rapid thermal annealing
  • Method 200 includes a removing operation 270 , wherein the top surface of the semiconductor material is exposed after annealing has taken place.
  • Removing operation 270 may include a plasma etching step, and/or an aqueous etching step, or other surface removal processes configured to remove materials above the top surface of the semiconductor material in preparation for deposition of subsequent layers of an semiconductor device, such as gate dielectric materials, interlayer dielectric (ILD) materials, spacer materials, and/or further semiconductor materials.
  • removal operation 270 includes multiple etching and/or removing steps to expose the top surface of the semiconductor material.
  • some parts of the removal operation are blanket (i.e., unselective) removal steps, and some parts of the removal operation selectively remove certain materials while preserving other materials present on the surface of the semiconductor material.
  • FIGS. 3A-3F depict cross-sectional diagrams of semiconductor devices at several stages of a manufacturing process for making integrated circuits, according to some embodiments of the present application.
  • FIG. 3A depicts a first device 300 at a first stage of a manufacturing process similar to method 200 .
  • First device includes a substrate 302 with a semiconductor material 304 deposited thereon.
  • a native oxide 306 is against a top surface of the semiconductor material 304 .
  • FIG. 3B depicts a second device 310 at a second stage of a manufacturing process similar to method 200 , following performance of an etching operation to remove a native oxide such as layer 306 , from the top of the semiconductor material.
  • FIG. 3A depicts a first device 300 at a first stage of a manufacturing process similar to method 200 .
  • First device includes a substrate 302 with a semiconductor material 304 deposited thereon.
  • a native oxide 306 is against a top surface of the semiconductor material 304 .
  • FIG. 3B depicts a
  • sulfur layer 3C depicts a third device 320 at a third stage of a manufacturing process, after a sulfur layer 322 has been grown on the top surface of semiconductor material 304 , such as after operation 240 of method 200 .
  • sulfur layer 322 may be grown from a basic organosulfur solution containing a thiourea compound, thioamide compound, or another sulfur-containing compound wherein at least one sulfur atom is double-bonded to a carbon atom.
  • FIG. 3D depicts a fourth device 330 following deposition of a cap layer 332 over sulfur layer 322 .
  • Cap layer 332 may be a dielectric material, such as silicon dioxide (SiO 2 ), silicon nitride, or silicon oxy-nitride, or a metal oxide such as aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO 2 ), or some other metal oxide, configured to completely cover sulfur layer 322 during an annealing operation.
  • FIG. 3E depicts a fifth device 340 following performance of an annealing operation, such as operation 260 .
  • junction region 345 may have a thickness ranging from 2 nm to 10 nm, although thicknesses smaller or greater than this range are also envisioned by the present application. In a preferred embodiment, the thin junction may extend to a depth of 5 nm below the top surface of the doped semiconductor material.
  • FIG. 3F depicts a sixth device 350 following a removing operation such as operation 270 , wherein cap layer 332 and sulfur layer 322 have been removed from the top surface of semiconductor material 304 (e.g., from the top of junction region 345 ).
  • a cap layer may be removed by chemical etching, or by plasma etching processes, according to embodiments of the present application.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.

Description

BACKGROUND
The present application relates to methods of manufacturing semiconductor devices, such as, for example, transistors, in III-V semiconductor substrates. Further aspects of the present application relate to surface passivation of semiconductor substrates and to sulfur-doping of III-V semiconductor substrates with nanoscale dimensional control.
Passivation of semiconductor materials during a manufacturing process may allow greater control over electrical properties of an integrated circuit generated by the manufacturing process. Passivation allows a manufacturer to protect surfaces of a semiconductor material or a semiconductor film stack to avoid the formation of oxides or to prevent the adhesion of contaminants to a semiconductor stack or material. Some passivation may protect semiconductor materials such as an intrinsic semiconductor (e.g., silicon) or compound semiconductors (e.g., III-V semiconductors such as, for example, GaAs) from reacting with atmospheric oxygen to form a native oxide layer on the top/exposed surface of the material. Native oxide layers may be removed from a semiconductor material with additional processing steps with concomitant increases in contaminants and/or defects. Undetected native oxide may modify an electrical characteristic of an integrated circuit, such as increasing contact resistance, reducing clock speed, or decreasing Ion for a transistor in an integrated circuit.
Semiconductor materials may be passivated by exposure of the semiconductor material to a sulfur source, wherein the sulfur interacts with the top/exposed surface of the semiconductor material to form a protective sulfur layer on the top/exposed surface of the semiconductor material. Sulfur deposition may be performed by applying a solution of ammonium sulfide (NH4)2S to the semiconductor material. However, use of ammonium sulfide has significant drawbacks. For example, at temperatures over 15° C., ammonium sulfide decomposes into ammonia and hydrogen sulfide, which are toxic to breathe or ingest. Manufacturing with ammonium sulfide uses costly exhaust systems to protect employees and facilities from exposure to toxic decomposition byproducts, and incurs higher waste disposal costs. Further, because ammonium sulfide solutions must be maintained at low temperatures to avoid decomposition into hydrogen sulfide, ammonium sulfide processing exhibits low rates of surface sulfurization (low rates of surface coverage, and thin sulfur film formation). Improvement to semiconductor passivation with sulfur (sulfurization) can improve protection against native oxide formation.
Doping of semiconductor materials to modify conductivity of a semiconductor material, or to modify a band gap of a semiconductor material, may be performed by implanting dopants into the semiconductor material. Implanting may involve accelerating a dopant atom to a high velocity and directing the accelerated dopant atom into a semiconductor material. An accelerated dopant atom may penetrate to a depth below the surface of the semiconductor material according to the mass of the dopant and the acceleration applied to the dopant atom before the dopant atom strikes the semiconductor surface. The penetration of the implanted dopant atoms may disrupt the crystal lattice of the semiconductor material, which disruption may be healed by an annealing operation performed after implanting of dopant atoms. Implantation into intrinsic semiconductor (e.g., silicon) and annealing of implanted intrinsic semiconductor may restore crystal structure to near-original condition. However, compound semiconductors such as III-V semiconductors may undergo irreparable damage following implanting and annealing. Localized stoichiometry may be disrupted after implant and annealing, resulting in small regions with deviations from the average stoichiometry of the bulk semiconductor material. Such deviations may result in lowered dopant activation, or higher junction leakage or leakage currents.
Sulfur may be used as a dopant for III-V semiconductors because sulfur atoms may be thermally diffused into III-V semiconductors without disrupting the crystal lattice, and without interrupting the uniform distribution of group III and group V atoms within the semiconductor material. Dimensions of a junction formed by thermal diffusion of sulfur may be regulated according to the annealing conditions used to thermally diffuse sulfur atoms into the semiconductor material. Sulfur-doping of III-V semiconductor substrates with nanoscale dimensional control may be improved with improvement in control and coverage amounts of sulfur on a semiconductor material.
SUMMARY
Aspects of the present application relate to a method of processing a semiconductor material which may include applying an organosulfur solution to a top surface of the semiconductor material. Some aspects of the present application relate to an organosulfur solution having at least one organosulfur compound with at least one sulfur atom double bonded to a carbon atom, and a pH of not less than 8.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
FIG. 1 is a flowchart of a method of passivating a semiconductor surface, according to some embodiments of the present application.
FIG. 2 is a flowchart of a method of doping a semiconductor material with sulfur, according to some embodiments of the present application.
FIGS. 3A-3F are cross-sectional diagrams of a semiconductor device at stages of a manufacturing process, according to some embodiments of the present application.
 DETAILED DESCRIPTION
The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
Sulfur deposition onto a semiconductor material, whether an intrinsic semiconductor (e.g., silicon) or a compound semiconductor (e.g., SiGe, or a III-V semiconductor, such as GaAs), may be improved over traditional ammonium sulfide [(NH4)2S] by using solutions containing an organosulfur compound, such as a thiourea compound, in a strong base. In some embodiments, a compound semiconductor may be doped to include a third semiconductor material, such as GaAs being doped with indium to produce the compound semiconductor material InGaAs. Other embodiments of doped compound semiconductor materials are also envisioned in the present disclosure. Thiourea compounds have the general chemical formula (R1R2N)(R3R4N)C═S, where a sulfur atom is double-bonded to a central carbon atom, and the central carbon is singly-bonded to two nitrogen atoms, where each nitrogen atom has two substituents: the first nitrogen has substituents R1 and R2, and the second nitrogen has two substituents R3 and R4. The thiourea substituents R1—R4 may be hydrogen, or aliphatic substituents. An aliphatic substituents may be a saturated alkane such as a methyl group, an ethyl group, a propyl group, or an isopropyl group (i.e., 1—methyl—ethane), although other aliphatic substituents, both saturated and unsaturated, are also envisioned in the present application. Other kinds of organosulfur compounds that may serve as sulfur sources for sulfur-based passivation or doping of semiconductor materials may also include thioamides (R1R2N)(R3)C═S or other organosulfur compounds where a sulfur atom is double bonded to a carbon atom. The thioamide substituents R1—R3 may be hydrogen, or aliphatic substituents as described above with regard to thiourea compound substituents. Aliphatic substituents for thioamides may include saturated alkanes such as a methyl group, an ethyl group, a propyl group, or an isopropyl group (i.e., 1—methyl—ethane), although other aliphatic substituents are also envisioned. In some embodiments of the present application, an organosulfur compound has a plurality of sulfur atoms double bonded to carbon atoms.
An organosulfur compound may undergo a chemical reaction in strongly basic solution (e.g., a solution having a pH of at least 8) in order to liberate a double-bonded sulfur to form a sulfide S2− ion in solution. For example, thiourea (NH2)(NH2)C═S reacts with strong base (e.g., a group I base such as NaOH or KOH, or a group II base such as Mg(OH)2, or an inorganic base such as ammonium hydroxide or TMAH (tetramethylammoniumhydroxide), to produce sulfide ion in solution. Other bases may be used to form sulfide ion in solution, so long as the base is capable of deprotonation of the organosulfur molecule to release sulfide ion, or capable of electrophilic substitution-type interactions with the carbonyl carbon to release sulfide ion from the organosulfur molecule. A base may be sufficiently strong to form sulfide ion when the base can deprotonate an organosulfur compound and trigger or promote sulfur liberation from the organosulfur molecule. A base may also promote sulfur liberation from organosulfur molecules when the base can react with a carbon atom that is double bonded to a sulfur atom, promoting formation of, e.g., a C—O single bond, and resulting in a C═S double bond becoming a C—S single bond.
Sulfide ion may form weak chemical bonds with other sulfur atoms, and adhere to semiconductor materials using Wan der Waals forces, to form protective films of sulfur on semiconductor materials. A rate of sulfurization/sulfur deposition of a semiconductor material may increase by increasing the temperature of the organosulfur solution. A thickness of a sulfur film on the semiconductor material may be increased by extending the time a sulfurization solution is maintained on an exposes surface of a semiconductor material, and by increasing the temperature of the solution to increase chemical reaction rates.
A concentration of organosulfur compound in an organosulfur solution may be to saturation, or may be less than saturation, and still perform a sulfurization process on an exposed surface of semiconductor material. Ammonium sulfide, in solid or in solutions, can decompose (i.e., form hydrogen sulfide) at temperatures above 15° C. Organosulfur compounds, or solutions thereof, do not undergo decomposition like ammonium sulfide. An organosulfur solution may be an aqueous solution, an alcohol-based solution, or have a mixture of water and an alcohol, containing organosulfur molecules. Organosulfur compounds may be applied to a semiconductor substrate at temperatures ranging from just above the freezing point of a solvent for an organosulfur solution (e.g., 0° C. for water, or below 0° C. for simple alcohols such as methanol or ethanol, up to almost the boiling point of a solvent (64° C. for methanol, 78° C. for ethanol, or 100° C. for water), without decomposition.
An organosulfur solution may generate a passivating layer of sulfur atoms on a semiconductor material such as a III-V semiconductor, to protect the semiconductor from contamination or native oxide formation. FIG. 1 is a flow diagram depicting operations in a method 100 of treating semiconductor materials, according to some embodiments of the present application. The method begins in operation 101. Method 100 includes an optional cleaning operation 110, wherein a top surface of a semiconductor substrate is treated to remove particles and/or residues form the top surface. Particles and residues may interfere with subsequent processing steps, including film deposition, patterning, and/or etching. Method 100 also includes an optional masking operation 120, wherein a mask is formed on the top surface of the semiconductor substrate. A mask may be formed by depositing a mask layer on atop surface of the semiconductor substrate, and the mask layer may be patterned using photolithography techniques. In some embodiments, a mask layer may be a layer of photoresist and a pattern in the mask layer may be formed by exposing the layer of photoresist with patterned light or radiation, and a portion of the layer photoresist removed by developing the layer of photoresist in a solvent. Method 100 may include an etching operation 130, wherein a native oxide on the top surface of the semiconductor material may be removed from an exposed portion of the top surface of the semiconductor material. (See FIG. 3A, having a native oxide (element 306), and 3B, wherein native oxide has been removed form a top surface of a semiconductor material (element 304).) Native oxide may be removed from a semiconductor material by etching using an aqueous etching solution such as hydrofluoric acid (HF), or by a plasma etching process, using a gas mixture such as argon and HF. Method 100 may further include a sulfur-deposition operation (or, a passivation operation) 140, wherein an organosulfur solution is applied to the top surface of the semiconductor material. According to some embodiments of the present application, the organosulfur solution may be heated, prior to application, to a temperature between 15° C. and 90° C., although greater and lesser temperatures may also be used. An organosulfur solution may include a thiourea compound or a thioamide compound, or a mixture thereof, according to some embodiments of the present application. Some embodiments of the present application may apply a plurality of organosulfur solutions to a top surface of the semiconductor material. In some embodiments of the present application, the semiconductor material may be rinsed between applications of organosulfur solutions to the semiconductor material. The method 100 ends with operation 199.
An organosulfur solution may be used to deposit a sulfur layer (see FIG. 3C, element 322) that can form ultrathin junctions of a semiconductor device source and drain regions, according to some embodiments of the present application. FIG. 2 is a flow diagram depicting operations in a method 200 of treating semiconductor materials, according to some embodiments of the present application. Method 200 begins with operation 201. Method 200 contains operations 210, 220, 230, and 240 that are be analogous to operations 110, 120, 130, and 140, respectively, of method 100. In some embodiments of the present application, operation 230 (applying a mask layer) may be repeated following a first performance of operation 240 (forming a sulfur layer), and operation 240 may be repeated a second time following the second performance of operation 230. Thus, by applying a first organosulfur solution and a second organosulfur solution, a thickness of the sulfur layer may be increased. By so doing, a sulfur layer may be formed with a first thickness in the area that was exposed during the first performance of operation 240, and subsequently masked by the second performance of operation 230, while the sulfur may have a second thickness in the area that was exposed (i.e., not masked) during both the first and second performances of operation 240.
Method 200 includes operation 250, wherein a cap layer is deposited onto a sulfur layer formed during sulfur-deposition operation 240. A cap layer may serve to trap sulfur below the cap layer and against the top surface of the semiconductor material. In areas where a mask layer may be deposited, a cap layer may trap the deposited sulfur below the cap layer and against a top surface of the mask layer material. A cap layer may include one or more dielectric layers. When a single dielectric material is used as the dielectric layer/cap layer, the dielectric material may include one of silicon dioxide (SiO2), TEOS, spin-on glass, silicon nitride, silicon oxy-nitride, aluminum oxide (Al2O3), or hafnium dioxide (HfO2). When a plurality of dielectric layers are deposited to form the cap layer, the plurality of layers may include two or more of silicon dioxide (SiO2), TEOS, spin-on glass, silicon nitride, silicon oxy-nitride, aluminum oxide (Al2O3), or hafnium dioxide (HfO2), or some other inorganic oxide or metal oxide. In embodiments of the cap layer having a plurality of dielectric layers, each dielectric layer has an individual dielectric material thickness, which individual thickness may be the same as, or different from, the thickness of another dielectric layer in the cap layer. According to some embodiments of the present application, the cap layer may have a thickness raging from 5 nm to 20 nm, although greater and lesser cap layer thicknesses are also envisioned.
Method 200 includes an anneal operation 260, wherein the semiconductor stack, including the semiconductor material, the sulfur layer, and the cap layer, are annealed in order to drive the atoms of the sulfur layer (formed during operation 240) into the lattice of the semiconductor. Anneal operation 260 may include heating the semiconductor stack to temperatures ranging from 250° C. to 400° C., although anneal temperatures greater and lesser than the recited range are also envisioned in the present application. Anneal operation 260 may also include heating the semiconductor stack for an anneal time ranging from 20 minutes to 40 minutes, although times greater than and lesser than the recited range are also envisioned by the present application. In some embodiments of the present application, an anneal operation may be performed by heating a semiconductor stack to an anneal temperature of 250° C. for an anneal period of 20 minutes, although anneal times greater than 20 minutes are also envisioned. In some embodiments of the present application, an anneal operation may be performed by heating a semiconductor stack to an anneal temperature of 400° C. for an anneal period of 30 minutes, although anneal periods longer or shorter than 30 minutes are also envisioned. Annealing may take place in an RTP (rapid thermal annealing) furnace, or by laser annealing, or by some other process of heating the wafer near the exposed portion of the top surface of the semiconductor material to drive the atoms of the sulfur layer (formed during operation 240) into the lattice of the semiconductor. Rapid annealing may take place with material heating up to 700° C. if the anneal period is in the millisecond range. Sulfur diffuses into the surface region of the semiconductor material, especially III-V semiconductor materials, upon thermal stimulation, whether of short duration (e.g., milliseconds (ms) to seconds (s) range, as with laser annealing) or long duration (e.g., greater than 1 second, as with RTP annealing) thermal stimulation. Method 200 includes a removing operation 270, wherein the top surface of the semiconductor material is exposed after annealing has taken place. Removing operation 270 may include a plasma etching step, and/or an aqueous etching step, or other surface removal processes configured to remove materials above the top surface of the semiconductor material in preparation for deposition of subsequent layers of an semiconductor device, such as gate dielectric materials, interlayer dielectric (ILD) materials, spacer materials, and/or further semiconductor materials. In some embodiments, removal operation 270 includes multiple etching and/or removing steps to expose the top surface of the semiconductor material. In some embodiments of the present application, some parts of the removal operation are blanket (i.e., unselective) removal steps, and some parts of the removal operation selectively remove certain materials while preserving other materials present on the surface of the semiconductor material.
FIGS. 3A-3F depict cross-sectional diagrams of semiconductor devices at several stages of a manufacturing process for making integrated circuits, according to some embodiments of the present application. FIG. 3A depicts a first device 300 at a first stage of a manufacturing process similar to method 200. First device includes a substrate 302 with a semiconductor material 304 deposited thereon. A native oxide 306 is against a top surface of the semiconductor material 304. FIG. 3B depicts a second device 310 at a second stage of a manufacturing process similar to method 200, following performance of an etching operation to remove a native oxide such as layer 306, from the top of the semiconductor material. FIG. 3C depicts a third device 320 at a third stage of a manufacturing process, after a sulfur layer 322 has been grown on the top surface of semiconductor material 304, such as after operation 240 of method 200. According to embodiments of the present application, sulfur layer 322 may be grown from a basic organosulfur solution containing a thiourea compound, thioamide compound, or another sulfur-containing compound wherein at least one sulfur atom is double-bonded to a carbon atom.
FIG. 3D depicts a fourth device 330 following deposition of a cap layer 332 over sulfur layer 322. Cap layer 332 may be a dielectric material, such as silicon dioxide (SiO2), silicon nitride, or silicon oxy-nitride, or a metal oxide such as aluminum oxide (Al2O3), hafnium dioxide (HfO2), or some other metal oxide, configured to completely cover sulfur layer 322 during an annealing operation. FIG. 3E depicts a fifth device 340 following performance of an annealing operation, such as operation 260. A portion of sulfur layer 322 has been incorporated into the layer of semiconductor material 304 to form a junction region 345 at an interface between sulfur layer 322 and the layer of semiconductor material 304. Junction region 345 may have a thickness ranging from 2 nm to 10 nm, although thicknesses smaller or greater than this range are also envisioned by the present application. In a preferred embodiment, the thin junction may extend to a depth of 5 nm below the top surface of the doped semiconductor material. FIG. 3F depicts a sixth device 350 following a removing operation such as operation 270, wherein cap layer 332 and sulfur layer 322 have been removed from the top surface of semiconductor material 304 (e.g., from the top of junction region 345). A cap layer may be removed by chemical etching, or by plasma etching processes, according to embodiments of the present application.
While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims (17)

What is claimed is:
1. A method of processing a semiconductor material, the method comprising:
applying a first organosulfur solution to a top surface of the semiconductor material, the organosulfur solution having at least one organosulfur compound wherein at least one sulfur atom is double bonded to a carbon atom, the organosulfur solution having a pH of not less than 8;
depositing a cap layer onto the semiconductor material after applying the first organosulfur solution; and
performing an annealing operation to diffuse sulfur located between the cap layer and the semiconductor material into the semiconductor material, wherein the annealing operation is performed at a temperature of at least 250° C. for at least 20 minutes.
2. The method of claim 1, further comprising cleaning the top surface of the semiconductor material prior to applying the first organosulfur solution to the top surface of the semiconductor material.
3. The method of claim 1, further comprising removing a native oxide from the top surface of the semiconductor material prior to applying the first organosulfur solution to the top surface of the semiconductor material.
4. The method of claim 1, wherein the semiconductor material comprises either a III-V compound or a Si—Ge semiconductor material.
5. The method of claim 4, wherein the semiconductor material comprises at least indium gallium arsenide (InGaAs).
6. The method of claim 1, wherein the cap layer comprises a dielectric material.
7. The method of claim 1, wherein the cap layer comprises a metal oxide.
8. The method of claim 1, wherein depositing the cap layer further comprises depositing a plurality of dielectric layers, the plurality of dielectric layers comprising at least two of aluminum oxide (Al2O3), hafnium dioxide (HfO2), and silicon dioxide (SiO2).
9. The method of claim 1, further comprising removing the cap layer from the semiconductor material.
10. The method of claim 9, wherein removing the cap layer from the semiconductor material further comprises performing an etching operation.
11. The method of claim 9, wherein removing the cap layer from the semiconductor material further comprises performing a chemical etching operation.
12. The method of claim 1, wherein the organosulfur solution contains a thiourea compound (R1R2N)(R3R4N)C═S wherein each of R1-R4 is selected from the group consisting of hydrogen and a saturated alkane.
13. The method of claim 12, wherein each of R1-R4 is hydrogen.
14. The method of claim 1, wherein the organosulfur solution contains a thioamide compound (R1R2N)(R3)C═S, wherein R1 and R2 are selected from the group consisting of hydrogen and saturated alkanes, and wherein R1 is an aliphatic substituent.
15. The method of claim 14, wherein the thioamide compound substituents R1-R3 are as follows: R1=hydrogen, and R2=hydrogen, and R3=a methyl group.
16. The method of claim 1, further comprising applying a second organosulfur solution to the top surface of the semiconductor material, wherein the second organosulfur solution is applied after the first organosulfur solution.
17. A method of processing a semiconductor material, the method comprising:
applying a first organosulfur solution to a top surface of the semiconductor material, the organosulfur solution having at least one organosulfur compound wherein at least one sulfur atom is double bonded to a carbon atom, the organosulfur solution having a pH of not less than 8;
depositing a cap layer onto the semiconductor material after applying the first organosulfur solution;
performing an annealing operation to diffuse sulfur located between the cap layer and the semiconductor material into the semiconductor material; and
removing the cap layer from the semiconductor material.
US15/844,905 2017-12-18 2017-12-18 Semiconductor processing method Expired - Fee Related US10546745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/844,905 US10546745B2 (en) 2017-12-18 2017-12-18 Semiconductor processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/844,905 US10546745B2 (en) 2017-12-18 2017-12-18 Semiconductor processing method

Publications (2)

Publication Number Publication Date
US20190189434A1 US20190189434A1 (en) 2019-06-20
US10546745B2 true US10546745B2 (en) 2020-01-28

Family

ID=66816346

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/844,905 Expired - Fee Related US10546745B2 (en) 2017-12-18 2017-12-18 Semiconductor processing method

Country Status (1)

Country Link
US (1) US10546745B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140027884A1 (en) * 2012-07-27 2014-01-30 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface
US20150318431A1 (en) * 2012-06-29 2015-11-05 Kyocera Corporation Method for manufacturing photoelectric conversion device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150318431A1 (en) * 2012-06-29 2015-11-05 Kyocera Corporation Method for manufacturing photoelectric conversion device
US20140027884A1 (en) * 2012-07-27 2014-01-30 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface

Also Published As

Publication number Publication date
US20190189434A1 (en) 2019-06-20

Similar Documents

Publication Publication Date Title
US7968440B2 (en) Preparation of ultra-shallow semiconductor junctions using intermediate temperature ramp rates and solid interfaces for defect engineering
US7417248B2 (en) Transistor with shallow germanium implantation region in channel
WO2009104554A1 (en) Semiconductor device fabrication method
TW201438064A (en) Method of forming a molecular dopant monolayer on a substrate
Hsieh et al. Characteristics of low‐temperature and low‐energy plasma‐enhanced chemical vapor deposited SiO2
US20210234035A1 (en) Transistor manufacturing method and gate-all-around device structure
FR2980637A1 (en) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A SELECTIVE REMOVAL STEP FROM A SILICON GERMANIUM LAYER
US20170309484A1 (en) Carbon Vacancy Defect Reduction Method for SiC
US20070089761A1 (en) Non-plasma method of removing photoresist from a substrate
US10541131B2 (en) Indium gallium arsenide surface passivation by sulfur vapor treatment
US10546745B2 (en) Semiconductor processing method
Romero et al. Impact of $\hbox {N} _ {2} $ Plasma Power Discharge on AlGaN/GaN HEMT Performance
JP2010232568A (en) Semiconductor device and manufacturing method thereof
JP7056532B2 (en) Method for manufacturing p-type III nitride semiconductor
US20110001197A1 (en) Method for manufacturing semiconductor device and semiconductor device
US7842587B2 (en) III-V MOSFET fabrication and device
US5674777A (en) Method for forming silicon-boron binary compound layer as boron diffusion source in silicon electronic device
CN104716189A (en) Gallium-antimonide-based semiconductor device provided with interface passivation layer and preparation method thereof
JPWO2007116470A1 (en) Semiconductor device and manufacturing method thereof
US8728930B2 (en) Methods of forming metal silicide-comprising material and methods of forming metal silicide-comprising contacts
RU2227344C2 (en) Process of manufacture of high-power shf field-effect transistors with schottky barrier
CN110429028A (en) A transistor device enhanced and depleted gate integrated manufacturing method and device
CN116053314B (en) A two-dimensional gallium oxide ferroelectric gate enhancement field-effect transistor and its fabrication method
KR940006710B1 (en) Manufacturing method of MES FET
JP2792948B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, YUN SEOG;DE SOUZA, JOEL PEREIRA;SADANA, DEVENDRA K.;AND OTHERS;SIGNING DATES FROM 20171213 TO 20171214;REEL/FRAME:044420/0165

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, YUN SEOG;DE SOUZA, JOEL PEREIRA;SADANA, DEVENDRA K.;AND OTHERS;SIGNING DATES FROM 20171213 TO 20171214;REEL/FRAME:044420/0165

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20240128