TWM625063U - Integrated circuit chip packaging device - Google Patents

Abstract

The present creation provides an integrated circuit chip packaging device. The IC chip package device includes a high-power IC chip, a lead frame, and a package. The lead frame includes a wafer stage and a plurality of pins; at least two adjacent pins on the same side of the plurality of pins and the space between the pins are connected together and widened to form widened pins, which are the same as the widened pins. At least one pin adjacent to the same side of the pin is vacant, and the widened pin is connected to the wafer stage to form a heat dissipation channel between the high-power integrated circuit chip and the external environment; The plane where the feet are located is a recessed plane for carrying a high-power integrated circuit chip, and at least a part of the sinking portion of the stage is exposed to the outside of the package body. Compared with similar structures, the integrated circuit chip package device according to the embodiment of the present invention has better heat dissipation performance and lower manufacturing cost.

Description

Integrated circuit chip packaging device

The present invention relates to the field of semiconductors, and more particularly to an integrated circuit chip packaging device.

The manufacturing process of the IC chip mainly includes the following stages: the design stage of the IC chip, the fabrication stage of the IC chip, the packaging stage of the IC chip, and the test stage of the IC chip. After the integrated circuit chip is fabricated, there are usually a plurality of bonding pads on the integrated circuit chip. In the packaging stage of the integrated circuit chip, these bonding pads on the integrated circuit chip and the corresponding lead frames are usually electrically connected to each other. The integrated circuit chip is usually connected to the lead frame by adhesive (conductive or insulating type) or solder paste, wire, or by means of ball bonding, so that the pads of the integrated circuit chip are connected to the lead frame. The contacts are electrically connected, thereby realizing the electrical connection inside the package structure of the integrated circuit chip.

With the increasing use of power-based ICs, how to realize the packaging of high-power ICs with high heat dissipation performance has become a common concern in the semiconductor industry.

The present invention provides a novel integrated circuit chip package device and a lead frame applied in the package device.

According to an embodiment of the present invention, an integrated circuit chip packaging device is provided, including a high-power integrated circuit chip, a lead frame, and a package body. Wherein, the lead frame includes a wafer stage and a plurality of pins; at least two adjacent pins on the same side of the plurality of pins and the space between the pins are connected together and widened to form the widened pins, and At least one pin adjacent to the same side of the widened pin is vacant, and the widened pin is connected to the wafer stage to form a heat dissipation channel between the high-power integrated circuit chip and the external environment; The plane where the pins are located is a concave and sunken plane, which is used to carry high-power integrated circuit chips, and at least a part of the sunken part of the wafer stage are exposed to the outside of the package.

In one embodiment, the plurality of pins includes at least twelve pins, and one group of at least six pins and the other group of at least six pins of the at least twelve pins are respectively disposed on the wafer stage on both sides.

In one embodiment, the spacing between some or all of the adjacent pins in the plurality of pins is greater than 0.85 mm.

In one embodiment, the distance of the widened pin across the at least one vacant pin to the same side adjacent unvacant pin is greater than 1 mm.

In one embodiment, four adjacent pins and pin spacing spaces on the same side of the plurality of pins are connected together and widened to form widened pins.

In one embodiment, the area of the sunken portion of the stage exposed to the surface of the package body accounts for more than 30% of the surface area of the same side of the package body.

In one embodiment, the integrated circuit chip package device is configured in a chip or dual in-line configuration.

In one embodiment, the high power integrated circuit chip is a power management chip.

According to an embodiment of the present invention, there is also provided a lead frame including a wafer stage and a plurality of pins. Wherein, the wafer stage has a concave and sunken plane relative to the plane where the plurality of pins are located, for carrying high-power integrated circuit chips; and at least two adjacent pins and pins on the same side among the plurality of pins The spacing spaces are connected together and widened to form widened pins, at least one pin adjacent to the same side as the widened pins is left vacant, and the widened pins are connected to the stage to form a high power product The heat dissipation channel between the bulk circuit chip and the external environment.

Compared with similar structures, the integrated circuit chip packaging device according to the inventive embodiment has better heat dissipation performance and lower manufacturing cost, so it can be used for the design, packaging, large-scale manufacturing and application of high-power integrated circuit chips .

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12: pins

2A: Lead frame

2A-1: Slide stage

4-1: High power integrated circuit chip

4-2: Control IC chip

4-3: Slide stage

a1: Length of stage with exposed backside

b1: Width of the backside exposed stage

A: The A-A section line of the cross-sectional view of FIG. 1B is a schematic diagram of the position of the plan view of FIG. 1A

AUX: auxiliary power pin

B: The B-B section line of the cross-sectional view of FIG. 2B is a schematic diagram of the position of the plan view of FIG. 2A

C: The position of the C-C section line of the cross-sectional view of FIG. 3B is indicated in the plan view of FIG. 3A

CS: Power power MOS field effect transistor current detection

DRAIN: drain pin

FB: loop compensation pin

GND: Chip ground pin

HV: High voltage startup pin

L1: Distance from pin 11 to pin 12

SW: Over temperature detection and protection pin

VDD: Primary power supply pin

It can be better understood from the following description of specific embodiments of the present creation in conjunction with the drawings The present invention, wherein: FIG. 1A shows a top view of an exemplary IC package device according to an embodiment of the invention; FIG. 1B shows a cross-sectional view along A-A of the IC package device shown in FIG. 1A ; FIG. 2A shows a top view of a lead frame in an exemplary integrated circuit chip package device according to an embodiment of the present invention; FIG. 2B shows a cross-sectional view along B-B of the lead frame shown in FIG. 2A ; A top view of an exemplary IC package device of another embodiment of the invention; FIG. 3B shows a cross-sectional view along C-C of the IC package device shown in FIG. 3A ; FIG. 4 shows an embodiment according to the invention The top view of the internal package structure of the exemplary integrated circuit chip package device; FIG. 5 shows a schematic diagram of the pins of an exemplary power management chip package device according to an embodiment of the present invention.

FIG. 6 shows a schematic circuit connection diagram of a flyback power converter applying the exemplary power management chip package device shown in FIG. 5 .

Features and exemplary embodiments of various aspects of the present invention are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present creation by illustrating an example of the present creation. This creation is by no means limited to any specific configurations and algorithms presented below, but covers any modification, substitution and improvement of elements, components and algorithms without departing from the spirit of this creation. In the drawings and description below, well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the present invention.

With the increasing use of power-based ICs, how to realize the packaging of high-power ICs with high heat dissipation performance has become a common concern in the semiconductor industry. Kam In view of this problem, the present invention provides a novel integrated circuit chip packaging device.

The integrated circuit chip packaging device and the lead frame applied in the packaging device according to the embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1A illustrates a top view of an exemplary integrated circuit die packaging device according to an embodiment of the present invention. FIG. 1B shows a cross-sectional view along A-A of the IC chip package device shown in FIG. 1A . The integrated circuit chip package device may employ a lead frame as shown in FIGS. 2A and 2B . The integrated circuit chip packaging device is, for example, a chip structure, and may include a high-power integrated circuit chip, a lead frame and a package, wherein the lead frame includes a pin 1, a pin 2, ..., a pin 10, a pin 11 , 12 pins, a total of 12 pins, and a wafer stage 2A-1 for carrying high-power integrated circuit chips. As shown in FIG. 1A, six pins (Pin 1 to Pin 6) of Pin 1 to Pin 12 and another group of six pins (Pin 7 to Pin 12) are respectively set on the carrier On both sides of the wafer stage 2A-1, the pins 7, 8, 9, 10 and the mutual pin spacing spaces located on one side of the wafer stage are connected together to form an integral widening lead. pin, and the pin 11 adjacent to the same side of the widened pin is vacant, so that the widened pin is actually adjacent to the same side of the pin 12 that is not vacant. Since the pins 11 are vacant, the distance L1 of the widened pins across the vacant pins 11 to the adjacent non-vacant pins 12 on the same side is larger.

It should be noted here that FIG. 1A only shows an exemplary IC chip package device according to an embodiment of the present invention, and the IC chip package device according to the present invention is not limited to the pin structure shown in FIG. 1A . For example, a lead frame in an IC chip package device according to the present invention may include fewer or more pins, and widened pins may connect two, three or more adjacent pins on the same side and their There can be more than one vacant pin adjacent to the same side of the widened pin as the pin spacing space.

1A and 1B, it can be seen that the wafer stage has a concave and sunk plane with respect to the plane where the pins 1 to 12 are located (indicated by the dotted line in FIG. 1A). The recessed and recessed plane is inside the package and used to carry the high-power integrated circuit chip, and at least a part of the recessed portion of the stage (eg, is different from the recessed and recessed surface of the stage) Opposite side) can be exposed on the outside of the package body of the IC chip packaging device to form a high power IC chip and the external environment cooling channel. In addition, the widened pins formed by connecting pins 7, 8, 9, and 10 together can be connected to the wafer stage 2A-1 to further expand the heat dissipation between the high-power integrated circuit chip and the external environment aisle. The surface mount structure can be applied not only to the traditional reflow soldering process of the printed circuit board (Printed Circuit Board Assembly, PCBA) assembly factory, but also to the wave soldering process traditionally used for the plug-in structure. The assembly-like processing factory applies the assembly patch, which greatly reduces the assembly cost.

The structure of the lead frame applied in the integrated circuit chip package device according to the embodiment of the present invention will be described in more detail below with reference to FIGS. 2A and 2B . As shown in FIG. 2A , the lead frame 2A includes pins 1, 2, . 1 is connected with pin 7, pin 8, pin 9, pin 10; pin 7, pin 8, pin 9, pin 10 themselves are also connected together and are widened to form an integral plus Wide pin; pin 11 adjacent to the same side of the widened pin is left empty.

FIG. 2B shows a cross-sectional view along B-B of the lead frame shown in FIG. 2A. 2A and 2B, it can be seen that the slide table 2A-1 has a concave plane with respect to the plane where the pins 1 to 12 are located, and is different from the pins 7, 8, 9, and 12. 10 are connected together and not connected to other pins.

When the lead frame 2A is applied to the integrated circuit chip package device, since the stage 2A-1 is connected with the pins 7, 8, 9, and 10, it is carried on the stage 2A. The heat dissipation channel between the high-power integrated circuit chip and the external environment on -1 includes four pins. Further, since the pins 7, 8, 9, and 10 themselves are connected together and widened, the high-power integrated circuit chip carried on the wafer stage 2A-1 is further expanded from the outside world. Ambient cooling channel.

In addition, when the lead frame 2A is applied to the integrated circuit chip package device, it is possible to further expand the carrying capacity by exposing at least a part of the sunk portion of the stage 2A-1 to the outside of the integrated circuit chip package device. The heat dissipation channel between the high-power integrated circuit chip on the wafer stage 2A-1 and the external environment. In order to expose the sunk portion of the stage 2A-1 to the outside of the integrated circuit chip package, the thickness of the integrated circuit chip package may be reduced.

In some embodiments, the spacing between some or all of the adjacent pins of the lead frame 2A may be adjusted to a larger spacing. For example, the spacing can be designed to be larger than 0.85mm (for example, in the range of 0.85-3.6mm), to prevent cracking between adjacent pins (especially high-voltage and low-voltage pins) under certain application conditions, especially in humid environments. fire problem, thereby ensuring the reliability and safety of the integrated circuit chip package device to which the lead frame 2A is applied. In addition, at least one pin adjacent to the same side of the widened pin can be vacant, so that the distance between the widened pin and the non-vacant pin adjacent to the actual same side becomes larger, and the integrated circuit chip is further improved. Reliability and safety of packaged devices. For example, the distance of a widened pin across at least one pin that is vacant to an actual same-side adjacent pin that is not vacant can be designed to be greater than 1 mm.

In addition, in some embodiments, the size of the stage 2A-1 can be made larger, for example, its area accounts for 10%-90% of the total area of the package body of the IC chip package device, so as to carry more A large-sized high-power integrated circuit chip can have a larger heat dissipation area exposed to the outside of the integrated circuit chip package device. For example, the area of the sunken portion of the stage 2A-1 exposed on the surface of the package body may account for more than 30% of the surface area of the same side of the package body.

FIG. 3A shows a top view of an integrated circuit chip packaging device according to another embodiment of the present invention. 3B shows a cross-sectional view along C-C of the integrated circuit chip package device shown in FIG. 3A. The integrated circuit chip packaging device shown in FIGS. 3A and 3B is a dual-in-line structure, which can be easily applied to the plug-in assembly of single-sided PCBA design, and has less requirements and restrictions on the design and process of the assembly factory. And the manufacturing process is simple. Other aspects are similar to the IC chip package device described in conjunction with FIGS. 1A and 1B , and will not be repeated here.

FIG. 4 shows a top view of an internal package structure of an integrated circuit chip package device according to an embodiment of the present invention. As shown in FIG. 4, the wafer stage 4-3 is realized to have a larger size (which can be enlarged according to actual needs) to carry a larger high-power integrated circuit chip 4-1, which is A control IC chip 4-2 with a smaller size can be pasted on the 4-1; The heat dissipation channel between the integrated circuit chip 4-1 and the external environment includes four pins; the pin 7, the pin 8, the pin 9, and the pin 10 themselves are connected together, which further expands the high-power integrated circuit chip 4-1. with outside The heat dissipation channel of the surrounding environment.

As described above, the integrated circuit chip packaging device according to the embodiment of the present invention is suitable for the packaging of high-power power-type integrated circuit chips. For example, the high power integrated circuit die may be a power management type die. FIG. 5 shows a schematic diagram of pins of an exemplary power management chip package device according to an embodiment of the present invention.

As shown in FIG. 5 , the power management chip package device has 12 pins, of which there are six pins 1, 2, 3, 4, 5, 6 and 12 independent pins, while pins 7, 8, 9 and 10 are connected together to form an integral widened pin, and the pin 11 adjacent to the widened pin is left empty.

FIG. 6 shows a schematic circuit connection diagram of a flyback power converter applying the exemplary power management chip package device shown in FIG. 5 . As shown in Figure 5 and Figure 6, pin 1 is set as the VDD (Virtual Device Driver) pin, that is, the primary power supply pin; pin 2 is set as the SW pin, that is, the over-temperature detection and protection pin; Pin 3 is set as AUX (Auxiliary) pin, namely auxiliary power pin; Pin 4 is set as FB (Voltage Feedback) pin, namely loop compensation pin; Pin 5 is set as GND (Ground) The pin is the chip ground pin; the pin 6 is set as the CS (Current Sensor) pin, that is, the power MOS field effect transistor current detection pin; the pin 12 is set as the HV (High Voltage) pin, That is, the high-voltage startup pin; the overall widened pin formed by pin 7, pin 8, pin 9 and pin 10 is set as the DRAIN pin, that is, the power MOS field effect power in the power management chip is connected. Crystal drain pin; pin 11 is left open to increase the high-voltage isolation spacing between the high-voltage DRAIN pin and other adjacent pins.

The pin arrangement of the integrated circuit chip package device and the lead frame according to the embodiment of the present invention has been described above by taking a high-power power management chip as an example. However, it should be understood that the IC chip packaging device and the lead frame according to the embodiments of the present invention can be used for packaging various high-power IC chips.

In addition, although the above takes the package structure of twelve pins as an example to describe the pin arrangement of the IC package device according to the present inventive embodiment, it should be understood that the IC package according to the present inventive embodiment The device is not limited to include only twelve pins, but can to include fewer or more pins.

In addition, those skilled in the related art can add holes of any size and shape, chamfering designs at corners, and Frame surface coating settings, etc.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the foregoing description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present invention. However, one skilled in the art will appreciate that the technical solutions of the present invention may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical idea of the present creation.

Those skilled in the art should understand that the above-mentioned embodiments are all illustrative and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Those skilled in the art should be able to understand and implement other modified embodiments of the disclosed embodiments on the basis of studying the drawings, the description and the scope of the patent claims. The presence of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12: pins

L1: Distance from pin 11 to pin 12

a1: Length of stage with exposed backside

b1: Width of the backside exposed stage

A: The A-A section line of the cross-sectional view of FIG. 1B is a schematic diagram of the position of the plan view of FIG. 1A

Claims (15)

An integrated circuit chip packaging device, comprising a high-power integrated circuit chip, a lead frame, and a package body, wherein: the lead frame includes a stage and a plurality of pins; at least two of the plurality of pins Adjacent pins and pin spacing spaces on the same side are connected together and widened to form a widened pin, at least one pin adjacent to the same side of the widened pin is vacant, and the widened pin The pins are connected with the wafer stage to form a heat dissipation channel between the high-power integrated circuit chip and the external environment; and the wafer stage has a concave and sunken plane relative to the plane where the plurality of pins are located is used for carrying the high-power integrated circuit chip, and at least a part of the sinking portion of the carrier table is exposed to the outside of the package body. The integrated circuit chip package device of claim 1, wherein the plurality of pins includes at least twelve pins, and a group of at least six pins and the other one of the at least twelve pins A group of at least six pins are respectively disposed on both sides of the wafer stage. The integrated circuit chip packaging device according to claim 1, wherein a spacing between some adjacent pins or all adjacent pins among the plurality of pins is greater than 0.85 mm. The integrated circuit chip package device of claim 1, wherein a distance between the widened lead across the vacant at least one lead to an adjacent non-empty lead on the same side is greater than 1 mm. The integrated circuit chip package device of any one of claims 1 to 4, wherein four adjacent pins on the same side of the plurality of pins and pin spacing spaces are connected together and separated by widening to form the widened pins. The integrated circuit chip packaging device according to claim 1, wherein the area of the sunken portion of the stage exposed on the surface of the package body accounts for more than 30% of the surface area on the same side of the package body. The integrated circuit chip packaging device of claim 1, wherein the product The bulk circuit chip package device is configured as a chip structure. The IC package of claim 1, wherein the IC package is configured in a dual in-line configuration. The integrated circuit chip packaging device according to claim 1, wherein the high-power integrated circuit chip is a power management chip. An integrated circuit chip packaging device at least includes a lead frame, the lead frame includes a carrier table and a plurality of pins, wherein: the carrier table has a concave sink relative to the plane where the plurality of pins are located a plane for carrying high-power integrated circuit chips; and at least two adjacent pins on the same side of the plurality of pins and the pin spacing spaces are connected together and widened to form widened pins , at least one pin adjacent to the same side of the widened pin is vacant, and the widened pin is connected to the wafer stage to form a heat dissipation between the high-power integrated circuit chip and the external environment aisle. The integrated circuit chip package device of claim 10, wherein the plurality of pins includes at least twelve pins, and a set of at least six pins and another of the at least twelve pins A group of at least six pins are respectively disposed on both sides of the wafer stage. The integrated circuit chip packaging device of claim 10, wherein a spacing between some adjacent pins, or all adjacent pins among the plurality of pins, is greater than 0.85 mm. The integrated circuit chip package device of claim 10, wherein a distance of the widened lead across the vacant at least one lead to an adjacent non-empty lead on the same side is greater than 1 mm. The integrated circuit chip package device of any one of claims 10 to 13, wherein four adjacent pins on the same side of the plurality of pins of the lead frame and the pin spacing spaces are connected in together and widened to form the widened pins. The integrated circuit chip packaging device according to claim 10, wherein the high-power integrated circuit chip is a power management chip.

Images