TWM518786U - In-line touch panel - Google Patents

In-line touch panel Download PDF

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Publication number
TWM518786U
TWM518786U TW104211731U TW104211731U TWM518786U TW M518786 U TWM518786 U TW M518786U TW 104211731 U TW104211731 U TW 104211731U TW 104211731 U TW104211731 U TW 104211731U TW M518786 U TWM518786 U TW M518786U
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Taiwan
Prior art keywords
conductive layer
layer
touch panel
cell touch
electrode
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TW104211731U
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English (en)
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李昆倍
林依縈
江昶慶
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瑞鼎科技股份有限公司
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Priority to US201562157251P priority
Priority to US201562162238P priority
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Publication of TWM518786U publication Critical patent/TWM518786U/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412Digitisers structurally integrated in a display
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/13338Input devices, e.g. touch-panels
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133512Light shielding layers, e.g. black matrix
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133514Colour filters
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134363Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Description

內嵌式觸控面板 In-line touch panel

本創作係與觸控面板(Touch panel)有關,特別是關於一種內嵌式(In-cell)觸控面板。 This creation is related to the touch panel, especially for an in-cell touch panel.

請參照圖1,圖1係繪示傳統具有On-Cell疊層結構的電容式觸控面板的疊層結構示意圖。如圖1所示,傳統On-Cell的電容式觸控面板之疊層結構1由下至上依序是:基板10、薄膜電晶體(TFT)元件層11、液晶層12、彩色濾光層13、玻璃層14、觸控感應層15、偏光片16、黏合劑17及上覆透鏡18。 Please refer to FIG. 1. FIG. 1 is a schematic diagram showing a laminated structure of a conventional capacitive touch panel having an On-Cell laminated structure. As shown in FIG. 1 , the stacked structure 1 of the conventional On-Cell capacitive touch panel is sequentially from bottom to top: a substrate 10, a thin film transistor (TFT) device layer 11, a liquid crystal layer 12, and a color filter layer 13. The glass layer 14, the touch sensing layer 15, the polarizer 16, the adhesive 17, and the overlying lens 18.

由圖1可知:傳統具有On-Cell疊層結構的電容式觸控面板則是將觸控感應層15設置於玻璃層14的上方,亦即設置於液晶顯示模組之外。雖然傳統具有On-Cell疊層結構的電容式觸控面板之厚度已較單片式玻璃觸控面板(One Glass Solution,OGS)來得薄,但在現今手機、平板電腦及筆記型電腦等可攜式電子產品強調輕薄短小之趨勢下,傳統具有On-Cell疊層結構的電容式觸控面板已達到其極限,無法滿足最薄化的觸控面板設計之需求。 As can be seen from FIG. 1 , the conventional capacitive touch panel having the On-Cell laminated structure has the touch sensing layer 15 disposed above the glass layer 14 , that is, disposed outside the liquid crystal display module. Although the thickness of the traditional capacitive touch panel with On-Cell laminate structure is thinner than that of the one-piece glass touch panel (One Glass Solution, OGS), it is portable in today's mobile phones, tablets and notebook computers. The emphasis on thin and light electronic products, the traditional capacitive touch panel with On-Cell laminated structure has reached its limit, can not meet the needs of the thinnest touch panel design.

因此,本創作提出一種內嵌式(In-cell)觸控面板,以改善先前技術所遭遇之種種問題。 Therefore, the present application proposes an in-cell touch panel to improve various problems encountered in the prior art.

根據本創作之一較佳具體實施例為一種內嵌式觸控面板。於此實施例中,內嵌式觸控面板包含複數個像素(Pixel)。每個像素之一疊層結構包含一基板、一薄膜電晶體元件層、一液晶層、一彩色濾光層及一玻璃層。薄膜電晶體元件層設置於基板上,薄膜電晶體元件層內係整合設置有一第一導電層及一第二導電層。液晶層設置於薄膜電晶體元件層上方。彩色濾光層設置於液晶層上方。玻璃層設置於彩色濾光層上方。 According to a preferred embodiment of the present invention, an in-cell touch panel is provided. In this embodiment, the in-cell touch panel includes a plurality of pixels (Pixel). One of the stacked structures of each pixel comprises a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer and a glass layer. The thin film transistor component layer is disposed on the substrate, and the first conductive layer and the second conductive layer are integrally disposed in the thin film transistor component layer. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer.

於一實施例中,第二導電層係與一共同電壓電極(Common Electrode)同時形成,但第二導電層與共同電壓電極彼此分離,第一導電層係形成於共同電壓電極之後。 In one embodiment, the second conductive layer is formed simultaneously with a common voltage electrode (Common Electrode), but the second conductive layer and the common voltage electrode are separated from each other, and the first conductive layer is formed after the common voltage electrode.

於一實施例中,第一導電層係設置於第二導電層之上方,第一導電層係電性連接至第二導電層,以作為一跨橋結構。 In one embodiment, the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer to serve as a bridge structure.

於一實施例中,第二導電層係與一共同電壓電極同時形成,但第二導電層與共同電壓電極彼此分離,第一導電層係形成於共同電壓電極之前。 In one embodiment, the second conductive layer is formed simultaneously with a common voltage electrode, but the second conductive layer and the common voltage electrode are separated from each other, and the first conductive layer is formed before the common voltage electrode.

於一實施例中,第二導電層係設置於第一導電層之上方,第二導電層係電性連接至第一導電層,以作為一跨橋結構。 In one embodiment, the second conductive layer is disposed above the first conductive layer, and the second conductive layer is electrically connected to the first conductive layer to serve as a bridge structure.

於一實施例中,第二導電層係形成於一共同電壓電極之前且第一導電層係形成於共同電壓電極之後,第二導電層係與薄膜電晶體元件層中之一源極及一汲極同時形成。 In one embodiment, the second conductive layer is formed before a common voltage electrode and the first conductive layer is formed after the common voltage electrode, and the second conductive layer is connected to one source and one of the thin film transistor element layers. Extremely formed at the same time.

於一實施例中,第一導電層係設置於第二導電層之上方,第一導電層係電性連接至第二導電層,以作為一跨橋結構。 In one embodiment, the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer to serve as a bridge structure.

於一實施例中,第二導電層係形成於第一導電層之前且第 一導電層係形成於一共同電壓電極之前,第二導電層係與薄膜電晶體元件層中之一源極及一汲極同時形成。 In an embodiment, the second conductive layer is formed before the first conductive layer and A conductive layer is formed before a common voltage electrode, and a second conductive layer is formed simultaneously with one source and one drain of the thin film transistor element layer.

於一實施例中,第一導電層係設置於第二導電層之上方,第一導電層係電性連接至第二導電層,以作為一跨橋結構。 In one embodiment, the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer to serve as a bridge structure.

於一實施例中,第二導電層係形成於一共同電壓電極之前且第一導電層係形成於共同電壓電極之後,第二導電層係與薄膜電晶體元件層中之一閘極同時形成。 In one embodiment, the second conductive layer is formed before a common voltage electrode and the first conductive layer is formed after the common voltage electrode, and the second conductive layer is formed simultaneously with one of the gates of the thin film transistor element layer.

於一實施例中,第一導電層係設置於第二導電層之上方,第一導電層係電性連接至第二導電層,以作為一跨橋結構。 In one embodiment, the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer to serve as a bridge structure.

於一實施例中,薄膜電晶體元件層中之閘極與另一閘極係彼此相鄰排列。 In one embodiment, the gate and the other gate of the thin film transistor element layer are arranged adjacent to each other.

於一實施例中,第二導電層係形成於第一導電層之前且第一導電層係形成於一共同電壓電極之前,第二導電層係與薄膜電晶體元件層中之一閘極同時形成。 In one embodiment, the second conductive layer is formed before the first conductive layer and the first conductive layer is formed before a common voltage electrode, and the second conductive layer is formed simultaneously with one of the gates of the thin film transistor device layer. .

於一實施例中,第一導電層係設置於第二導電層之上方,第一導電層係電性連接至第二導電層,以作為一跨橋結構。 In one embodiment, the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer to serve as a bridge structure.

於一實施例中,薄膜電晶體元件層中之閘極與另一閘極係彼此相鄰排列。 In one embodiment, the gate and the other gate of the thin film transistor element layer are arranged adjacent to each other.

於一實施例中,內嵌式觸控面板係為一內嵌式互電容(Mutual Capacitance)觸控面板,內嵌式互電容觸控面板之一驅動電極(TX)及一感測電極(RX)係由第一導電層以網格狀排列而成。 In one embodiment, the in-cell touch panel is an in-line Mutual Capacitance touch panel, and one of the in-cell mutual-capacitive touch panel drives the electrode (TX) and a sensing electrode (RX). ) is formed by arranging the first conductive layers in a grid shape.

於一實施例中,當第一導電層所組成的驅動電極(TX)與感 測電極(RX)彼此交錯時,係以第二導電層作為一跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。 In one embodiment, when the first conductive layer is composed of a driving electrode (TX) and a sense When the electrodes (RX) are staggered with each other, the second conductive layer is used as a cross-bridge structure to electrically connect the driving electrodes (TX) or electrically connect the sensing electrodes (RX).

於一實施例中,第一導電層還包含一第一連接部,第一連接部係與驅動電極(TX)及感測電極(RX)彼此分離,並且第一連接部係電性連接至共同電壓電極。 In one embodiment, the first conductive layer further includes a first connecting portion, the first connecting portion is separated from the driving electrode (TX) and the sensing electrode (RX), and the first connecting portion is electrically connected to the common Voltage electrode.

於一實施例中,第二導電層還包含一第二連接部,該第二連接部係電性連接至該共同電壓電極。 In one embodiment, the second conductive layer further includes a second connecting portion electrically connected to the common voltage electrode.

於一實施例中,彩色濾光層包含一彩色濾光片(Color Filter)及一黑色矩陣光阻(Black Matrix Resist),黑色矩陣光阻具有良好的光遮蔽性,第一導電層及第二導電層係位於黑色矩陣光阻之下方。 In one embodiment, the color filter layer includes a color filter and a black matrix resist, and the black matrix photoresist has good light shielding properties, the first conductive layer and the second layer. The conductive layer is located below the black matrix photoresist.

於一實施例中,當內嵌式觸控面板運作於一觸控模式時,一共同電壓電極係切換為一浮動(Floating)電位或施加一觸控相關訊號,以降低對觸控的寄生電容。 In an embodiment, when the in-cell touch panel operates in a touch mode, a common voltage electrode is switched to a floating potential or a touch-related signal is applied to reduce parasitic capacitance to the touch. .

於一實施例中,內嵌式觸控面板之一觸控模式與一顯示模式係分時驅動,並且內嵌式觸控面板係利用顯示週期之一空白區間(Blanking interval)運作於觸控模式。 In one embodiment, one touch mode and one display mode of the in-cell touch panel are time-divisionally driven, and the in-cell touch panel operates in a touch mode by using a blanking interval of the display period. .

於一實施例中,空白區間係包含垂直空白區間(Vertical Blanking Interval,VBI)、水平空白區間(Horizontal Blanking Interval,HBI)及長水平空白區間(Long Horizontal Blanking Interval)中之至少一種。長水平空白區間的時間長度等於或大於水平空白區間的時間長度。長水平空白區間係重新分配複數個水平空白區間而得或長水平空白區間包含垂直空白區間。 In an embodiment, the blank interval includes at least one of a Vertical Blanking Interval (VBI), a Horizontal Blanking Interval (HBI), and a Long Horizontal Blanking Interval. The length of the long horizontal blank interval is equal to or longer than the length of the horizontal blank interval. The long horizontal blank interval is a redistribution of a plurality of horizontal blank intervals and the long horizontal blank interval includes a vertical blank interval.

相較於先前技術,根據本創作之內嵌式觸控面板具有下列優點:(1)觸控感測電極及其走線之設計簡單,可有效降低成本;(2)其佈局方式可降低對液晶面板光學上之影響,提升面板開口率;(3)將不屬於觸控電極的部分第一導電層及第二導電層電性連接至共同電壓電極,以降低共同電壓電極本身的電阻電容負載(RC loading)。 Compared with the prior art, the in-cell touch panel according to the present invention has the following advantages: (1) the touch sensing electrode and its routing are simple in design, which can effectively reduce the cost; (2) the layout mode can be reduced. The optical effect of the liquid crystal panel increases the aperture ratio of the panel; (3) electrically connecting a portion of the first conductive layer and the second conductive layer that are not part of the touch electrode to the common voltage electrode to reduce the resistance and capacitance load of the common voltage electrode itself (RC loading).

關於本創作之優點與精神可以藉由以下的創作詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of this creation can be further understood by the following detailed description of the creation and the drawings.

1~2‧‧‧疊層結構 1~2‧‧‧Laminated structure

10、20、111‧‧‧基板 10, 20, 111‧‧‧ substrates

11、21、112‧‧‧薄膜電晶體(TFT)元件層 11, 21, 112‧‧ ‧ Thin film transistor (TFT) device layer

12、23、113‧‧‧液晶層 12, 23, 113‧‧‧ liquid crystal layer

13、24、114‧‧‧彩色濾光層 13, 24, 114‧‧‧ color filter layer

14、25、115‧‧‧玻璃層 14, 25, 115‧‧ ‧ glass layer

15‧‧‧觸控感應層 15‧‧‧Touch sensing layer

16、26‧‧‧偏光片 16, 26‧‧‧ polarizers

17‧‧‧黏合劑 17‧‧‧Binder

18‧‧‧上覆透鏡 18‧‧‧Overlay lens

22‧‧‧觸控元件層 22‧‧‧Touch element layer

CF‧‧‧彩色濾光片 CF‧‧‧ color filters

BM‧‧‧黑色矩陣光阻 BM‧‧‧ Black Matrix Resistor

M3、M2、MI、MG、321、323‧‧‧導電層 M3, M2, MI, MG, 321, 323‧‧‧ conductive layer

ISO、320、322、324‧‧‧絕緣層 ISO, 320, 322, 324‧‧ ‧ insulation

TE1~TE3‧‧‧觸控電極 TE1~TE3‧‧‧ touch electrode

W1~W3‧‧‧走線 W1~W3‧‧‧Wiring

B、B1、B2‧‧‧跨橋結構 B, B1, B2‧‧‧ cross-bridge structure

LC‧‧‧液晶單元 LC‧‧‧Liquid Crystal Unit

S‧‧‧源極 S‧‧‧ source

D‧‧‧汲極 D‧‧‧汲

G、G’‧‧‧閘極 G, G’‧‧‧ gate

TP‧‧‧內嵌式觸控面板 TP‧‧‧Inline touch panel

TX、TX1~TX3‧‧‧驅動電極及其走線 TX, TX1~TX3‧‧‧ drive electrodes and their traces

RX、RX1~RX2‧‧‧感測電極及其走線 RX, RX1~RX2‧‧‧ sensing electrodes and their traces

CITO‧‧‧共同電壓電極 CITO‧‧‧Common voltage electrode

VCOM、VCOM1~VCOM5‧‧‧共同電壓電極區域 VCOM, VCOM1~VCOM5‧‧‧ common voltage electrode area

SIM‧‧‧影像訊號 SIM‧‧‧ video signal

HSync‧‧‧水平同步訊號 HSync‧‧‧ horizontal sync signal

VSync‧‧‧垂直同步訊號 VSync‧‧‧ vertical sync signal

STH‧‧‧觸控驅動訊號 STH‧‧‧ touch drive signal

VBI‧‧‧垂直空白區間 VBI‧‧‧ vertical blank interval

HBI‧‧‧水平空白區間 HBI‧‧‧ horizontal blank

LHBI‧‧‧長水平空白區間 LHBI‧‧‧Long horizontal blank

G1~G3‧‧‧閘極驅動訊號 G1~G3‧‧‧ gate drive signal

S1~S3‧‧‧源極驅動訊號 S1~S3‧‧‧ source drive signal

圖1係繪示傳統具有On-Cell疊層結構的電容式觸控面板的疊層結構示意圖。 FIG. 1 is a schematic view showing a laminated structure of a conventional capacitive touch panel having an On-Cell laminated structure.

圖2係繪示本創作之內嵌式觸控面板的疊層結構示意圖。 FIG. 2 is a schematic view showing the laminated structure of the in-cell touch panel of the present invention.

圖3係繪示圖2中之觸控元件層22之一實施例的疊層結構示意圖。 FIG. 3 is a schematic diagram showing the laminated structure of an embodiment of the touch element layer 22 of FIG.

圖4係繪示圖3中之跨橋結構B1與觸控電極323的上視示意圖。 4 is a top view of the bridge structure B1 and the touch electrode 323 of FIG. 3 .

圖5係繪示觸控元件層22之另一實施例的疊層結構示意圖。 FIG. 5 is a schematic view showing a laminated structure of another embodiment of the touch element layer 22.

圖6係繪示圖5中之跨橋結構B2與觸控電極321的上視示意圖。 FIG. 6 is a schematic top view of the bridge structure B2 and the touch electrode 321 of FIG. 5 .

圖7係繪示採用網格狀的圖樣設計的導電層之示意圖。 FIG. 7 is a schematic view showing a conductive layer designed using a grid pattern.

圖8係繪示互電容觸控電極的跨橋結構之上視示意圖。 FIG. 8 is a schematic top view showing a cross-bridge structure of a mutual capacitance touch electrode.

圖9係繪示觸控電極及其走線之上視示意圖。 FIG. 9 is a schematic top view of the touch electrode and its traces.

圖10係繪示本創作之一實施例的內嵌式互電容觸控面板的疊層結構示意圖。 FIG. 10 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to an embodiment of the present invention.

圖11係繪示圖10中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。 11 is a top plan view showing a pixel design in which the first conductive layer and the second conductive layer of FIG. 10 are electrically connected.

圖12係繪示本創作之一實施例的內嵌式互電容觸控面板的疊層結構示意圖。 FIG. 12 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to an embodiment of the present invention.

圖13係繪示圖12中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。 13 is a top plan view showing a pixel design in which the first conductive layer and the second conductive layer of FIG. 12 are electrically connected.

圖14係繪示本創作之一實施例的內嵌式互電容觸控面板的疊層結構示意圖。 FIG. 14 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to an embodiment of the present invention.

圖15係繪示圖14中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。 15 is a top plan view showing a pixel design in which the first conductive layer and the second conductive layer of FIG. 14 are electrically connected.

圖16係繪示本創作之一實施例的內嵌式互電容觸控面板的疊層結構示意圖。 FIG. 16 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to an embodiment of the present invention.

圖17係繪示圖16中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。 17 is a top plan view showing a pixel design in which the first conductive layer and the second conductive layer of FIG. 16 are electrically connected.

圖18係繪示本創作之一實施例的內嵌式互電容觸控面板的疊層結構示意圖。 FIG. 18 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to an embodiment of the present invention.

圖19A及圖19B係分別繪示圖18中之第一導電層與第二導電層電性連接之不同畫素設計的上視示意圖。 19A and 19B are top schematic views respectively showing different pixel designs of the first conductive layer and the second conductive layer of FIG. 18 electrically connected.

圖20係繪示本創作之一實施例的內嵌式互電容觸控面板的疊層結構示意圖。 FIG. 20 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to an embodiment of the present invention.

圖21A及圖21B係分別繪示圖20中之第一導電層與第二導電層電性連接之不同畫素設計的上視示意圖。 21A and 21B are top plan views respectively showing different pixel designs of the first conductive layer and the second conductive layer of FIG. 20 electrically connected.

圖22係繪示內嵌式互電容觸控面板之觸控電極設計之示意圖。 FIG. 22 is a schematic diagram showing the design of a touch electrode of an in-cell mutual-capacitive touch panel.

圖23A至圖23C係分別繪示由網格狀的第一導電層排列而成的驅動電極與感測電極具有不同形狀之示意圖。 23A to 23C are schematic views respectively showing driving electrodes and sensing electrodes which are arranged by a grid-shaped first conductive layer.

圖24係繪示內嵌式互電容觸控面板之觸控模式與顯示模式分時驅動的時序圖。 FIG. 24 is a timing diagram showing the touch mode and the display mode time-division driving of the in-cell mutual-capacitive touch panel.

圖25係分別繪示垂直空白區間、水平空白區間及長水平空白區間的示意圖。 FIG. 25 is a schematic diagram showing a vertical blank interval, a horizontal blank interval, and a long horizontal blank interval, respectively.

圖26A及圖26B係分別繪示具有多個共同電壓電極區域之內嵌式互電容觸控面板的示意圖及其運作於觸控模式與顯示模式時之各訊號的時序圖。 26A and 26B are respectively a schematic diagram of an in-cell mutual-capacitive touch panel having a plurality of common voltage electrode regions, and timing diagrams of respective signals when operating in a touch mode and a display mode.

圖27A及圖27B係分別繪示具有單一個共同電壓電極區域之內嵌式互電容觸控面板的示意圖及其運作於觸控模式與顯示模式時之各訊號的時序圖。 27A and 27B are respectively a schematic diagram of an in-cell mutual-capacitive touch panel having a single common voltage electrode region and a timing diagram of each signal when operating in a touch mode and a display mode.

根據本創作之一較佳具體實施例為一種內嵌式的電容式觸控面板。實際上,由於內嵌式的電容式觸控面板可達成最薄化的觸控面板設計,可廣泛應用於智慧型手機、平板電腦及筆記型電腦等各種可攜式消費性電子產品上。 According to a preferred embodiment of the present invention, an in-cell capacitive touch panel is provided. In fact, because the in-cell capacitive touch panel can achieve the thinnest touch panel design, it can be widely used in various portable consumer electronic products such as smart phones, tablets and notebook computers.

於此實施例中,內嵌式的電容式觸控面板所適用的顯示器可以是採用橫向電場效應顯示技術(In-Plane-Switching Liquid Crystal,IPS)或 由其延伸的邊界電場切換廣視角技術(Fringe Field Switching,FFS)或高階超廣視角技術(Advanced Hyper-Viewing Angle,AHVA)之顯示器,但不以此為限。 In this embodiment, the display of the in-cell capacitive touch panel may be an In-Plane-Switching Liquid Crystal (IPS) or The boundary electric field extended by it switches the display of Fringe Field Switching (FFS) or Advanced Hyper-Viewing Angle (AHVA), but is not limited thereto.

一般而言,目前市場上的主流電容式觸控感測技術應為投射式電容觸控感測技術,可分為互電容(Mutual capacitance)及自電容(Self capacitance)兩種。互電容觸控感測技術就是當觸碰發生時,會在鄰近兩電極間產生電容耦合的現象,並由電容量變化來確定觸碰動作的發生;自電容觸控感測技術就是觸控物與電極間產生電容耦合,並量測電極的電容量變化,以確定觸碰動作的發生。 In general, the mainstream capacitive touch sensing technology currently on the market should be a projected capacitive touch sensing technology, which can be divided into Mutual capacitance and Self capacitance. Mutual capacitance touch sensing technology is a phenomenon in which capacitive coupling occurs between adjacent electrodes when a touch occurs, and the occurrence of a touch action is determined by a change in capacitance; a self-capacitive touch sensing technology is a touch object. A capacitive coupling is formed between the electrodes and the capacitance change of the electrodes is measured to determine the occurrence of a touch action.

需說明的是,此實施例中之內嵌式的電容式觸控面板可採用互電容(Mutual capacitance)或自電容(Self capacitance)觸控感測技術,其觸控電極係以網格狀分佈且可視實際需求形成不同佈局以分別應用於自電容式觸控或互電容式觸控上。 It should be noted that the in-cell capacitive touch panel in this embodiment may adopt a Mutual capacitance or a Self capacitance touch sensing technology, and the touch electrodes are distributed in a grid shape. Different layouts can be formed according to actual needs to be applied to self-capacitive touch or mutual capacitance touch.

此外,此實施例係將觸控電極設置於薄膜電晶體(TFT)元件層與液晶層之間,使得觸控電極整合至與顯示器的驅動元件(TFT元件)同側,但觸控電極在結構上是獨立的,並未使用到TFT元件的任何部分,藉以將觸控電極與TFT元件之間的驅動關係單純化,避免由於觸控電極與部分的TFT元件整合所導致的良率不佳問題。 In addition, in this embodiment, the touch electrode is disposed between the thin film transistor (TFT) device layer and the liquid crystal layer, so that the touch electrode is integrated on the same side as the driving element (TFT element) of the display, but the touch electrode is in the structure. The above is independent, and no part of the TFT component is used, so that the driving relationship between the touch electrode and the TFT element is simplified, thereby avoiding the problem of poor yield due to integration of the touch electrode and part of the TFT element. .

接下來,將分別就此實施例之內嵌式的電容式觸控面板的疊層結構進行詳細之說明。 Next, the laminated structure of the in-cell capacitive touch panel of this embodiment will be described in detail.

請參照圖2,圖2係繪示此實施例之內嵌式的電容式觸控面板之疊層結構示意圖。如圖2所示,於一實施例中,內嵌式的電容式觸控面板之疊層結構由下至上依序是:基板20、薄膜電晶體(TFT)元件層21、觸控 元件層22、液晶層23、彩色濾光層24、玻璃層25及偏光片層26。其中,需特別說明的是觸控元件層22係設置於TFT元件層21與液晶層23之間。TFT元件層21之結構並無特定之限制,可以是任何可能的設計。TFT元件層21中的半導體層係由半導體材料構成,例如低溫多晶矽(Low Temperature Poly-Silicon,LTPS)、氧化銦鎵鋅(Indium Gallium Zinc Oxide,IGZO)或非晶質矽(a-Si)等材料,但不以此為限。 Please refer to FIG. 2. FIG. 2 is a schematic diagram showing the laminated structure of the in-cell capacitive touch panel of the embodiment. As shown in FIG. 2, in an embodiment, the stacked structure of the in-cell capacitive touch panel is sequentially from bottom to top: substrate 20, thin film transistor (TFT) device layer 21, and touch. The element layer 22, the liquid crystal layer 23, the color filter layer 24, the glass layer 25, and the polarizer layer 26. Specifically, it is to be noted that the touch element layer 22 is disposed between the TFT element layer 21 and the liquid crystal layer 23. The structure of the TFT element layer 21 is not particularly limited and may be any possible design. The semiconductor layer in the TFT element layer 21 is made of a semiconductor material, such as Low Temperature Poly-Silicon (LTPS), Indium Gallium Zinc Oxide (IGZO), or amorphous germanium (a-Si). Material, but not limited to this.

於此實施例中,彩色濾光層24包含彩色濾光片(Color Filter)CF及黑色矩陣光阻(Black Matrix Resist)BM兩部分,其中黑色矩陣光阻BM具有良好的光遮蔽性,可應用於彩色濾光層24中,作為區隔紅(R)、綠(G)、藍(B)三種顏色的彩色濾光片之材料。此外,黑色矩陣光阻BM亦可用來與觸控元件層22中之觸控電極對準,藉以遮住觸控元件層22中之觸控電極,故觸控元件層22中之觸控電極除了可由透明的導電材料構成之外,亦可由不透明的導電材料構成,均不會影像到顯示器之像素的開口率。 In this embodiment, the color filter layer 24 includes a color filter CF and a black matrix photoresist (Black Matrix Resist) BM. The black matrix photoresist BM has good light shielding properties and can be applied. In the color filter layer 24, it is used as a material for color filters of three colors of red (R), green (G), and blue (B). In addition, the black matrix photoresist BM can also be used to align with the touch electrodes in the touch device layer 22 to cover the touch electrodes in the touch device layer 22, so that the touch electrodes in the touch device layer 22 are It may be composed of a transparent conductive material or an opaque conductive material, and will not image the aperture ratio of the pixels of the display.

接著,請參照圖3,圖3係繪示觸控元件層22之一實施例的疊層結構示意圖。如圖3所示,首先,在TFT元件層21上形成絕緣層320;再於絕緣層320上形成導電層321;接著,將絕緣層322覆蓋於導電層321上;然後,在絕緣層322製作通孔(VIA);之後,在通孔內與絕緣層322上分別形成導電層323,使得形成於通孔內的導電層323會與導電層321彼此電性連接,而形成一跨橋結構;最後,在導電層323上方形成絕緣層324。藉此,由導電層321與導電層323共同形成的跨橋結構B1係為一觸控電極(例如X方向感測電極),其可從另一觸控電極-導電層323(例如Y方向感測電極)的下方繞過,藉以達到觸控電極跨接之功效。 Next, please refer to FIG. 3 , which illustrates a laminated structure of an embodiment of the touch element layer 22 . As shown in FIG. 3, first, an insulating layer 320 is formed on the TFT element layer 21; a conductive layer 321 is formed on the insulating layer 320; then, an insulating layer 322 is overlaid on the conductive layer 321, and then formed on the insulating layer 322. a via hole (VIA); a conductive layer 323 is formed on the insulating layer 322, respectively, so that the conductive layer 323 formed in the via hole and the conductive layer 321 are electrically connected to each other to form a bridge structure; Finally, an insulating layer 324 is formed over the conductive layer 323. Thereby, the bridge structure B1 formed by the conductive layer 321 and the conductive layer 323 is a touch electrode (for example, an X-direction sensing electrode), which can be from another touch electrode-conductive layer 323 (for example, a Y-direction sense) The bottom of the measuring electrode is bypassed to achieve the effect of the touch electrode bridging.

需說明的是,由於此實施例中之跨橋結構B1(例如X方向感測電極)是從導電層323(例如Y方向感測電極)的下方繞過,故此實施例中之跨橋結構B1是較靠近於TFT元件層21之一側。請參照圖4,圖4係繪示圖3中之跨橋結構B1與觸控電極(導電層)323的上視示意圖。由圖4很明顯可看出:跨橋結構B1是從觸控電極(導電層)323的下方繞過。 It should be noted that since the bridge structure B1 (for example, the X-direction sensing electrode) in this embodiment is bypassed from below the conductive layer 323 (for example, the Y-direction sensing electrode), the bridge structure B1 in this embodiment is used. It is closer to one side of the TFT element layer 21. Please refer to FIG. 4 . FIG. 4 is a schematic top view of the bridge structure B1 and the touch electrode (conductive layer) 323 in FIG. 3 . As is apparent from FIG. 4, the bridge structure B1 is bypassed from below the touch electrode (conductive layer) 323.

於實際應用中,導電層321與導電層323可以是由相同的導電材料構成,亦可以是由不同的導電材料構成,並無特定之限制。同理,絕緣層320、322與324可以是由相同的有機或無機絕緣材料構成,亦可以是由不同的有機或無機絕緣材料構成,並無特定之限制。此外,由上述可知:作為X方向感測電極的跨橋結構B1係由導電層321與導電層323共同形成,這代表同一個方向的感測電極可由不同的導電層組成。 In practical applications, the conductive layer 321 and the conductive layer 323 may be composed of the same conductive material, or may be composed of different conductive materials, and are not particularly limited. Similarly, the insulating layers 320, 322, and 324 may be composed of the same organic or inorganic insulating material, or may be composed of different organic or inorganic insulating materials, and are not particularly limited. In addition, it can be seen from the above that the bridge structure B1 as the X-direction sensing electrode is formed by the conductive layer 321 and the conductive layer 323, which means that the sensing electrodes in the same direction can be composed of different conductive layers.

接著,請參照圖5,圖5係繪示觸控元件層22之另一實施例的疊層結構示意圖。如圖5所示,首先,在TFT元件層21上形成絕緣層320;再於絕緣層320上分別形成彼此分離的數個導電層321;接著,將絕緣層322覆蓋於該些導電層321上;然後,在絕緣層322製作通孔(VIA);之後,在通孔內與絕緣層322上分別形成導電層323,使得形成於通孔內的導電層323會與導電層321彼此電性連接,而形成一跨橋結構B2。藉此,由導電層321與導電層323共同形成的跨橋結構B2係為一觸控電極(例如X方向感測電極),其可從另一觸控電極-導電層321(例如Y方向感測電極)的上方繞過,藉以達到觸控電極跨接之功效。 Next, please refer to FIG. 5. FIG. 5 is a schematic diagram showing a laminated structure of another embodiment of the touch element layer 22. As shown in FIG. 5, first, an insulating layer 320 is formed on the TFT element layer 21; and a plurality of conductive layers 321 separated from each other are formed on the insulating layer 320; then, the insulating layer 322 is overlaid on the conductive layers 321 Then, a via hole (VIA) is formed in the insulating layer 322; then, a conductive layer 323 is formed on the insulating layer 322 in the via hole, respectively, so that the conductive layer 323 formed in the via hole and the conductive layer 321 are electrically connected to each other. And forming a bridge structure B2. Thereby, the bridge structure B2 formed by the conductive layer 321 and the conductive layer 323 is a touch electrode (for example, an X-direction sensing electrode), which can be from another touch electrode-conductive layer 321 (for example, a Y-direction sense) The upper side of the measuring electrode is bypassed to achieve the effect of the touch electrode bridging.

需說明的是,由於此實施例中之跨橋結構B2(例如X方向感測電極)是從導電層321(例如Y方向感測電極)的上方繞過,故此實施例中之 跨橋結構將會是較靠近於液晶層33之一側。請參照圖6,圖6係繪示圖5中之觸控電極(導電層)321與跨橋結構B2的上視示意圖。由圖6很明顯可看出:跨橋結構B2是從觸控電極(導電層)321的上方繞過。 It should be noted that since the bridge structure B2 (for example, the X-direction sensing electrode) in this embodiment is bypassed from the conductive layer 321 (for example, the Y-direction sensing electrode), in this embodiment, The cross-bridge structure will be closer to one side of the liquid crystal layer 33. Please refer to FIG. 6. FIG. 6 is a schematic top view of the touch electrode (conductive layer) 321 and the bridge structure B2 of FIG. As is apparent from Fig. 6, the bridge structure B2 is bypassed from above the touch electrode (conductive layer) 321.

接下來,將就觸控元件層22中之觸控電極的圖樣(Pattern)設計進行說明。 Next, a pattern design of the touch electrodes in the touch element layer 22 will be described.

於此實施例中,觸控電極係採用網格狀的圖樣設計,並可透過上述的跨橋結構B1或B2在適當位置進行觸控電極的跨接,再搭配斷開導電層形成斷路的方式,即可依照不同需求分別將網格狀的導電層設計為自電容觸控電極或互電容觸控電極。如圖7所示,圖7係繪示採用網格狀的圖樣設計的導電層,其中第一電極區域TE1與第二電極區域TE2之間係透過斷開導電層形成斷路的方式彼此分離;第一電極區域TE1與第三電極區域TE3之間則因B區並無斷開而彼此電性相連。 In this embodiment, the touch electrodes are designed in a grid pattern, and the touch electrodes can be bridged at appropriate positions through the above-mentioned bridge structure B1 or B2, and then the conductive layer is broken to form an open circuit. The grid-shaped conductive layer can be designed as a self-capacitance touch electrode or a mutual-capacitance touch electrode according to different needs. As shown in FIG. 7 , FIG. 7 illustrates a conductive layer designed by using a grid pattern, wherein the first electrode region TE1 and the second electrode region TE2 are separated from each other by breaking the conductive layer to form an open circuit; The electrode region TE1 and the third electrode region TE3 are electrically connected to each other because the B region is not disconnected.

請參照圖8,圖8係繪示互電容觸控電極的跨橋結構之上視示意圖。如圖8所示,第一觸控電極TX1與TX2之間係透過跨橋結構B從第二觸控電極RX1與RX2上方跨過而彼此電性相連。 Please refer to FIG. 8. FIG. 8 is a schematic top view of a cross-bridge structure of a mutual capacitance touch electrode. As shown in FIG. 8 , the first touch electrodes TX1 and TX2 are electrically connected to each other across the second touch electrodes RX1 and RX2 through the bridge structure B.

請參照圖9,圖9係繪示觸控電極及其走線之上視示意圖。如圖9所示,觸控電極TE1~TE3及其走線W1~W3可分別於在前述的不同導電層321及導電層323,可根據不同設計應用於互電容或自電容觸控感測上。 Please refer to FIG. 9. FIG. 9 is a schematic top view of the touch electrode and its traces. As shown in FIG. 9, the touch electrodes TE1~TE3 and the traces W1~W3 thereof can be respectively applied to the different conductive layers 321 and 323 in the foregoing, and can be applied to mutual capacitance or self-capacitive touch sensing according to different designs. .

根據本創作之另一較佳具體實施例為一種內嵌式(In-cell)互電容(Mutual Capacitance)觸控面板。於此實施例中,內嵌式互電容觸控面板包含複數個像素(Pixel)。每個像素之一疊層結構包含一基板、一薄膜電晶體元件層、一液晶層、一彩色濾光層及一玻璃層。 According to another preferred embodiment of the present invention, an in-cell mutual capacitance (Mutual Capacitance) touch panel is provided. In this embodiment, the in-cell mutual-capacitive touch panel includes a plurality of pixels (Pixel). One of the stacked structures of each pixel comprises a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer and a glass layer.

薄膜電晶體元件層設置於基板上,薄膜電晶體元件層內係整合設置有一第一導電層及一第二導電層。液晶層設置於薄膜電晶體元件層上方。彩色濾光層設置於液晶層上方。玻璃層設置於彩色濾光層上方。其中,彩色濾光層包含一彩色濾光片(Color Filter)及一黑色矩陣光阻(Black Matrix Resist)。黑色矩陣光阻具有良好的光遮蔽性,第一導電層及第二導電層係位於黑色矩陣光阻之下方。 The thin film transistor component layer is disposed on the substrate, and the first conductive layer and the second conductive layer are integrally disposed in the thin film transistor component layer. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer. The color filter layer includes a color filter and a black matrix resist. The black matrix photoresist has good light shielding properties, and the first conductive layer and the second conductive layer are located below the black matrix photoresist.

內嵌式互電容觸控面板之一驅動電極(TX)及一感測電極(RX)係由第一導電層以網格狀排列而成。當第一導電層所組成的驅動電極(TX)與感測電極(RX)彼此交錯時,係以第二導電層作為一跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。第一導電層還包含一第一連接部,用以電性連接至共同電壓電極。第一連接部係與驅動電極(TX)及感測電極(RX)彼此分離。第二導電層還包含一第二連接部,用以電性連接至共同電壓電極。 One of the driving electrodes (TX) and one sensing electrode (RX) of the in-cell mutual-capacitive touch panel are arranged in a grid shape by the first conductive layer. When the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer are staggered with each other, the second conductive layer is used as a bridge structure to electrically connect the driving electrode (TX) or the electrical connection sensing electrode. (RX). The first conductive layer further includes a first connecting portion for electrically connecting to the common voltage electrode. The first connection portion is separated from the drive electrode (TX) and the sense electrode (RX) from each other. The second conductive layer further includes a second connecting portion for electrically connecting to the common voltage electrode.

請參照圖10,圖10係繪示此實施例的內嵌式互電容觸控面板的疊層結構示意圖。如圖10所示,第二導電層MI係與共同電壓電極(Common Electrode)CITO同時形成,但第二導電層MI與共同電壓電極CITO彼此分離,第一導電層M3則是形成於第二導電層MI與共同電壓電極CITO之後。第一導電層M3係設置於第二導電層MI之上方。第一導電層M3係透過貫穿絕緣層ISO的通孔VIA電性連接至第二導電層MI,以形成一跨橋結構。當第一導電層M3所組成的驅動電極(TX)與感測電極(RX)彼此交錯時,第二導電層MI即可作為跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。 Please refer to FIG. 10. FIG. 10 is a schematic diagram showing the laminated structure of the in-cell mutual-capacitive touch panel of this embodiment. As shown in FIG. 10, the second conductive layer MI is formed simultaneously with a common voltage electrode CITO, but the second conductive layer MI and the common voltage electrode CITO are separated from each other, and the first conductive layer M3 is formed on the second conductive layer. Layer MI and common voltage electrode CITO. The first conductive layer M3 is disposed above the second conductive layer MI. The first conductive layer M3 is electrically connected to the second conductive layer MI through the through hole VIA penetrating the insulating layer ISO to form a bridge structure. When the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer M3 are interlaced with each other, the second conductive layer MI can be used as a cross-bridge structure to electrically connect the driving electrodes (TX) or electrical connection sensing. Electrode (RX).

請參照圖11,圖11係繪示圖10中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。如圖11所示,第一導電層M3與第二導電層MI透過通孔VIA彼此電性連接。需說明的是,此跨接畫素可於每個畫素都出現,或是每隔多個畫素(例如三個畫素,但不以此為限)出現一次,並無特定之限制。 Please refer to FIG. 11. FIG. 11 is a top plan view showing the pixel design of the first conductive layer and the second conductive layer electrically connected in FIG. As shown in FIG. 11 , the first conductive layer M3 and the second conductive layer MI are electrically connected to each other through the via hole VIA. It should be noted that the spanning pixel may appear in each pixel, or may appear once every multiple pixels (for example, three pixels, but not limited thereto), and there is no specific limitation.

請參照圖12,圖12係繪示本創作之另一實施例的內嵌式互電容觸控面板的疊層結構示意圖。如圖12所示,第二導電層MI係與共同電壓電極CITO同時形成,但第二導電層MI與共同電壓電極CITO彼此分離。第一導電層M3係形成於第二導電層MI與共同電壓電極CITO之前。第二導電層MI係設置於第一導電層M3之上方。第二導電層MI係透過貫穿絕緣層ISO的通孔VIA電性連接至第一導電層M3,以形成一跨橋結構。當第一導電層M3所組成的驅動電極(TX)與感測電極(RX)彼此交錯時,第二導電層MI即可作為跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。 Please refer to FIG. 12 , which is a schematic diagram of a stacked structure of an in-cell mutual-capacitive touch panel according to another embodiment of the present invention. As shown in FIG. 12, the second conductive layer MI is formed simultaneously with the common voltage electrode CITO, but the second conductive layer MI and the common voltage electrode CITO are separated from each other. The first conductive layer M3 is formed before the second conductive layer MI and the common voltage electrode CITO. The second conductive layer MI is disposed above the first conductive layer M3. The second conductive layer MI is electrically connected to the first conductive layer M3 through the through hole VIA penetrating the insulating layer ISO to form a bridge structure. When the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer M3 are interlaced with each other, the second conductive layer MI can be used as a cross-bridge structure to electrically connect the driving electrodes (TX) or electrical connection sensing. Electrode (RX).

請參照圖13,圖13係繪示圖12中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。如圖13所示,第一導電層M3與第二導電層MI透過通孔VIA彼此電性連接。需說明的是,此跨接畫素可於每個畫素都出現,或是每隔多個畫素(例如三個畫素,但不以此為限)出現一次,並無特定之限制。 Please refer to FIG. 13. FIG. 13 is a top plan view showing a pixel design in which the first conductive layer and the second conductive layer of FIG. 12 are electrically connected. As shown in FIG. 13 , the first conductive layer M3 and the second conductive layer MI are electrically connected to each other through the via VIA. It should be noted that the spanning pixel may appear in each pixel, or may appear once every multiple pixels (for example, three pixels, but not limited thereto), and there is no specific limitation.

請參照圖14,圖14係繪示本創作之另一實施例的內嵌式互電容觸控面板的疊層結構示意圖。如圖14所示,第二導電層M2係形成於共同電壓電極CITO之前且第一導電層M3係形成於共同電壓電極CITO之 後。需注意的是,第二導電層M2係與薄膜電晶體元件層TFT中之一源極S及一汲極D同時形成。第一導電層M3係設置於第二導電層M2之上方。第一導電層M3係透過貫穿不同絕緣層ISO的通孔VIA電性連接至第二導電層M2,以形成一跨橋結構。當第一導電層M3所組成的驅動電極(TX)與感測電極(RX)彼此交錯時,第二導電層M2即可作為跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。 Please refer to FIG. 14. FIG. 14 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to another embodiment of the present invention. As shown in FIG. 14, the second conductive layer M2 is formed before the common voltage electrode CITO and the first conductive layer M3 is formed on the common voltage electrode CITO. Rear. It should be noted that the second conductive layer M2 is formed simultaneously with one source S and one drain D of the thin film transistor element layer TFT. The first conductive layer M3 is disposed above the second conductive layer M2. The first conductive layer M3 is electrically connected to the second conductive layer M2 through the through holes VIA penetrating through the different insulating layers ISO to form a bridge structure. When the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer M3 are interlaced with each other, the second conductive layer M2 can be used as a cross-bridge structure to electrically connect the driving electrodes (TX) or electrical connection sensing. Electrode (RX).

請參照圖15,圖15係繪示圖14中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。如圖15所示,第一導電層M3與第二導電層M2透過通孔VIA彼此電性連接。需說明的是,此跨接畫素可於每個畫素都出現,或是每隔多個畫素(例如三個畫素,但不以此為限)出現一次,並無特定之限制。 Please refer to FIG. 15. FIG. 15 is a top plan view showing a pixel design in which the first conductive layer and the second conductive layer of FIG. 14 are electrically connected. As shown in FIG. 15, the first conductive layer M3 and the second conductive layer M2 are electrically connected to each other through the via hole VIA. It should be noted that the spanning pixel may appear in each pixel, or may appear once every multiple pixels (for example, three pixels, but not limited thereto), and there is no specific limitation.

請參照圖16,圖16係繪示本創作之另一實施例的內嵌式互電容觸控面板的疊層結構示意圖。如圖16所示,第二導電層M2係形成於第一導電層M3之前且第一導電層M3係形成於共同電壓電極CITO之前。需說明的是,第二導電層M2係與薄膜電晶體元件層TFT中之一源極S及一汲極D同時形成。第一導電層M3係設置於第二導電層M2之上方。第一導電層M3係透過貫穿不同絕緣層ISO的通孔VIA電性連接至第二導電層M2,以形成一跨橋結構。當第一導電層M3所組成的驅動電極(TX)與感測電極(RX)彼此交錯時,第二導電層M2即可作為跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。 Please refer to FIG. 16. FIG. 16 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to another embodiment of the present invention. As shown in FIG. 16, the second conductive layer M2 is formed before the first conductive layer M3 and the first conductive layer M3 is formed before the common voltage electrode CITO. It should be noted that the second conductive layer M2 is formed simultaneously with one source S and one drain D of the thin film transistor element layer TFT. The first conductive layer M3 is disposed above the second conductive layer M2. The first conductive layer M3 is electrically connected to the second conductive layer M2 through the through holes VIA penetrating through the different insulating layers ISO to form a bridge structure. When the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer M3 are interlaced with each other, the second conductive layer M2 can be used as a cross-bridge structure to electrically connect the driving electrodes (TX) or electrical connection sensing. Electrode (RX).

請參照圖17,圖17係繪示圖16中之第一導電層與第二導電層電性連接之畫素設計的上視示意圖。如圖17所示,第一導電層M3與第 二導電層M2透過通孔VIA彼此電性連接。需說明的是,此跨接畫素可於每個畫素都出現,或是每隔多個畫素(例如三個畫素,但不以此為限)出現一次,並無特定之限制。 Please refer to FIG. 17. FIG. 17 is a schematic top view showing the pixel design of the first conductive layer and the second conductive layer of FIG. As shown in FIG. 17, the first conductive layer M3 and the first The two conductive layers M2 are electrically connected to each other through the through holes VIA. It should be noted that the spanning pixel may appear in each pixel, or may appear once every multiple pixels (for example, three pixels, but not limited thereto), and there is no specific limitation.

請參照圖18,圖18係繪示本創作之另一實施例的內嵌式互電容觸控面板的疊層結構示意圖。如圖18所示,第二導電層MG係形成於共同電壓電極CITO之前且第一導電層M3係形成於共同電壓電極CITO之後。需注意的是,第二導電層MG係與薄膜電晶體元件層TFT中之一閘極G同時形成。第一導電層M3係設置於第二導電層MG之上方。第一導電層M3係透過貫穿不同絕緣層ISO的通孔VIA電性連接至第二導電層MG,以形成一跨橋結構。當第一導電層M3所組成的驅動電極(TX)與感測電極(RX)彼此交錯時,第二導電層MG即可作為跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。 Please refer to FIG. 18. FIG. 18 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to another embodiment of the present invention. As shown in FIG. 18, the second conductive layer MG is formed before the common voltage electrode CITO and the first conductive layer M3 is formed after the common voltage electrode CITO. It is to be noted that the second conductive layer MG is formed simultaneously with one of the gate electrodes G of the thin film transistor element layer TFT. The first conductive layer M3 is disposed above the second conductive layer MG. The first conductive layer M3 is electrically connected to the second conductive layer MG through the through holes VIA penetrating through the different insulating layers ISO to form a bridge structure. When the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer M3 are interlaced with each other, the second conductive layer MG can be used as a cross-bridge structure to electrically connect the driving electrodes (TX) or electrical connection sensing. Electrode (RX).

請參照圖19A及圖19B,圖19A及圖19B係分別繪示圖18中之第一導電層與第二導電層電性連接之不同畫素設計的上視示意圖。如圖19A及圖19B所示,第一導電層M3與第二導電層MG透過通孔VIA彼此電性連接。薄膜電晶體元件層TFT中之閘極G會與另一閘極G’彼此相鄰排列,藉以縮減所需黑色矩陣光阻BM的寬度。此一畫素設計可使內嵌式觸控面板具有較均勻的開口率配置並提升其顯示畫面之均勻度。需說明的是,此跨接畫素可於每個畫素都出現,或是每隔多個畫素(例如三個畫素,但不以此為限)出現一次,並無特定之限制。 Referring to FIG. 19A and FIG. 19B , FIG. 19A and FIG. 19B are schematic top views of different pixel designs of the first conductive layer and the second conductive layer electrically connected in FIG. 18 respectively. As shown in FIG. 19A and FIG. 19B, the first conductive layer M3 and the second conductive layer MG are electrically connected to each other through the via hole VIA. The gate G in the thin film transistor element layer TFT is arranged adjacent to each other with respect to the other gate G', thereby reducing the width of the desired black matrix photoresist BM. This pixel design allows the in-cell touch panel to have a more uniform aperture ratio configuration and improve the uniformity of its display. It should be noted that the spanning pixel may appear in each pixel, or may appear once every multiple pixels (for example, three pixels, but not limited thereto), and there is no specific limitation.

此外,如圖19B所示,第二導電層MG亦可電性連接共同電壓電極CITO,以進一步降低共同電壓電極CITO的阻值。 In addition, as shown in FIG. 19B, the second conductive layer MG can also be electrically connected to the common voltage electrode CITO to further reduce the resistance of the common voltage electrode CITO.

請參照圖20,圖20係繪示本創作之一實施例的內嵌式互電容觸控面板的疊層結構示意圖。如圖20所示,第二導電層MG係形成於第一導電層M3之前且第一導電層M3係形成於共同電壓電極CITO之前。需注意的是,第二導電層MG係與薄膜電晶體元件層TFT中之一閘極G同時形成。第一導電層M3係設置於第二導電層MG之上方。第一導電層M3係透過貫穿不同絕緣層ISO的通孔VIA電性連接至第二導電層MG,以形成一跨橋結構。當第一導電層M3所組成的驅動電極(TX)與感測電極(RX)彼此交錯時,第二導電層MG即可作為跨橋結構來電性連接驅動電極(TX)或電性連接感測電極(RX)。 Please refer to FIG. 20. FIG. 20 is a schematic diagram showing a laminated structure of an in-cell mutual-capacitive touch panel according to an embodiment of the present invention. As shown in FIG. 20, the second conductive layer MG is formed before the first conductive layer M3 and the first conductive layer M3 is formed before the common voltage electrode CITO. It is to be noted that the second conductive layer MG is formed simultaneously with one of the gate electrodes G of the thin film transistor element layer TFT. The first conductive layer M3 is disposed above the second conductive layer MG. The first conductive layer M3 is electrically connected to the second conductive layer MG through the through holes VIA penetrating through the different insulating layers ISO to form a bridge structure. When the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer M3 are interlaced with each other, the second conductive layer MG can be used as a cross-bridge structure to electrically connect the driving electrodes (TX) or electrical connection sensing. Electrode (RX).

請參照圖21A及圖21B,圖21A及圖21B係分別繪示圖20中之第一導電層與第二導電層電性連接之不同畫素設計的上視示意圖。如圖21A及圖21B所示,第一導電層M3與第二導電層MG透過通孔VIA彼此電性連接。薄膜電晶體元件層TFT中之閘極G會與另一閘極G’彼此相鄰排列,藉以縮減所需黑色矩陣光阻BM的寬度。此一畫素設計可使內嵌式觸控面板具有較均勻的開口率配置並提升其顯示畫面之均勻度。需說明的是,此跨接畫素可於每個畫素都出現,或是每隔多個畫素(例如三個畫素,但不以此為限)出現一次,並無特定之限制。 Referring to FIG. 21A and FIG. 21B , FIG. 21A and FIG. 21B are respectively top views of different pixel designs of the first conductive layer and the second conductive layer electrically connected in FIG. 20 . As shown in FIG. 21A and FIG. 21B, the first conductive layer M3 and the second conductive layer MG are electrically connected to each other through the via hole VIA. The gate G in the thin film transistor element layer TFT is arranged adjacent to each other with respect to the other gate G', thereby reducing the width of the desired black matrix photoresist BM. This pixel design allows the in-cell touch panel to have a more uniform aperture ratio configuration and improve the uniformity of its display. It should be noted that the spanning pixel may appear in each pixel, or may appear once every multiple pixels (for example, three pixels, but not limited thereto), and there is no specific limitation.

此外,如圖21B所示,第二導電層MG亦可電性連接共同電壓電極CITO,以進一步降低共同電壓電極CITO的阻值。 In addition, as shown in FIG. 21B, the second conductive layer MG can also be electrically connected to the common voltage electrode CITO to further reduce the resistance of the common voltage electrode CITO.

請參照圖22,圖22係繪示內嵌式互電容觸控面板之觸控電極設計之示意圖。如圖22所示,內嵌式互電容觸控面板的觸控電極包含第一方向觸控電極及第二方向觸控電極,可分別為驅動電極TX與感測電極 RX。於實際應用中,觸控電極可由金屬材料或其他導電材料構成,並無特定之限制。 Please refer to FIG. 22 , which illustrates a schematic diagram of a touch electrode design of an in-cell mutual-capacitive touch panel. As shown in FIG. 22, the touch electrodes of the in-cell mutual-capacitive touch panel include a first-direction touch electrode and a second-direction touch electrode, which are respectively a driving electrode TX and a sensing electrode. RX. In practical applications, the touch electrodes may be made of a metal material or other conductive materials, and are not particularly limited.

需說明的是,無論觸控電極是驅動電極TX或感測電極RX,均是由前述的第一導電層M3形成網格狀電極。其中,當第一導電層M3所組成的驅動電極TX與感測電極RX彼此交錯時,驅動電極TX或感測電極RX會透過前述第二導電層(M2、MI或MG)的跨橋結構形成跨層的電性連接。此外,第一導電層M3亦可適當地佈局於觸控電極的空缺處並與共同電壓電極CITO連接,以降低共同電壓電極CITO的阻值。 It should be noted that whether the touch electrode is the driving electrode TX or the sensing electrode RX, the grid electrode is formed by the first conductive layer M3. When the driving electrode TX and the sensing electrode RX composed of the first conductive layer M3 are interlaced with each other, the driving electrode TX or the sensing electrode RX is formed through the bridge structure of the second conductive layer (M2, MI or MG). Electrical connection across layers. In addition, the first conductive layer M3 may also be appropriately disposed on the vacancy of the touch electrode and connected to the common voltage electrode CITO to reduce the resistance of the common voltage electrode CITO.

請參照圖23A至圖23C,由網格狀的第一導電層M3排列而成的驅動電極TX與感測電極RX除了可以是傳統的矩形外,亦可以是如同圖23A至圖23C所分別繪示的各種不同形狀,但不以此為限。 Referring to FIG. 23A to FIG. 23C, the driving electrode TX and the sensing electrode RX which are arranged by the grid-shaped first conductive layer M3 may be different from the conventional rectangular shape as shown in FIG. 23A to FIG. 23C. Various shapes are shown, but not limited to them.

接著,請參照圖24,圖24係繪示內嵌式互電容觸控面板之觸控模式與顯示模式分時驅動的時序圖。如圖24所示,內嵌式互電容觸控面板可於不同時間分別運作於觸控模式與顯示模式下,亦即內嵌式互電容觸控面板的觸控模式與顯示模式係分時驅動。需說明的是,內嵌式互電容觸控面板係利用影像訊號SIM中之空白區間(Blanking interval)輸出觸控驅動訊號STH,以運作於觸控模式下。內嵌式互電容觸控面板會在非顯示時序(亦即空白區間)進行觸控感測。 Next, please refer to FIG. 24 , which is a timing diagram of the touch mode and the display mode time-division driving of the in-cell mutual-capacitive touch panel. As shown in FIG. 24, the in-cell mutual-capacitive touch panel can be operated in the touch mode and the display mode at different times, that is, the touch mode and the display mode of the in-cell mutual-capacitive touch panel are time-divisionally driven. . It should be noted that the in-cell mutual-capacitive touch panel outputs the touch driving signal STH by using a blanking interval in the image signal SIM to operate in the touch mode. The in-line mutual-capacitive touch panel performs touch sensing in non-display timing (ie, a blank interval).

於實際應用中,內嵌式互電容觸控面板可根據不同驅動方式調整其使用的空白區間種類多寡。如圖25所示,空白區間可包含垂直空白區間(Vertical Blanking Interval)VBI、水平空白區間(Horizontal Blanking Interval)HBI及長水平空白區間LHBI(Long Horizontal Blanking Interval)中之至少一種。其中,長水平空白區間LHBI的時間長度等於或大於水平空白區間HBI的時間長度。長水平空白區間LHBI可以是重新分配複數個水平空白區間HBI而得或是長水平空白區間LHBI包含有垂直空白區間VBI。 In practical applications, the in-line mutual-capacitive touch panel can adjust the number of blank intervals used by the embedded mutual-capacitance touch panel according to different driving modes. As shown in FIG. 25, the blank interval may include a Vertical Blanking Interval VBI, a Horizontal Blanking Interval HBI, and a Long Horizontal Blanking LHBI (Long Horizontal Blanking). At least one of Interval). Wherein, the length of the long horizontal blank interval LHBI is equal to or longer than the length of the horizontal blank interval HBI. The long horizontal blank interval LHBI may be a redistribution of a plurality of horizontal blank intervals HBI or a long horizontal blank interval LHBI including a vertical blank interval VBI.

當內嵌式互電容觸控面板運作於觸控模式時,可同時將共同電壓電極切換為浮動(Floating)電位或是施加一觸控相關訊號於共同電壓電極,以降低對觸控的寄生電容。 When the in-cell mutual-capacitive touch panel operates in the touch mode, the common voltage electrode can be switched to a floating potential or a touch-related signal can be applied to the common voltage electrode to reduce the parasitic capacitance to the touch. .

請參照圖26A,於一實施例中,共同電壓電極可在適當位置斷開而形成多個共同電壓電極區域VCOM1~VCOM5,並可在內嵌式觸控面板運作於觸控模式時施加不同訊號給不同的共同電壓電極區域VCOM1~VCOM5。其中,共同電壓電極區域VCOM1~VCOM3為與驅動電極TX1~TX3畫素重疊之部分;共同電壓電極區域VCOM4~VCOM5為與感測電極RX1~RX2畫素重疊之部分。 Referring to FIG. 26A, in an embodiment, the common voltage electrode can be disconnected at an appropriate position to form a plurality of common voltage electrode regions VCOM1 VVCOM5, and different signals can be applied when the in-cell touch panel operates in the touch mode. Give different common voltage electrode areas VCOM1~VCOM5. The common voltage electrode regions VCOM1 to VCOM3 are portions overlapping the driving electrodes TX1 to TX3, and the common voltage electrode regions VCOM4 to VCOM5 are portions overlapping the sensing electrodes RX1 to RX2.

亦請參照圖26B,圖26B係繪示圖26A之內嵌式互電容觸控面板運作於觸控模式與顯示模式時之各訊號的時序圖。如圖26B所示,當內嵌式互電容觸控面板運作於顯示模式時,會由閘極驅動器及源極驅動器分別輸出閘極驅動訊號G1~G3及源極驅動訊號S1~S3,以驅動內嵌式觸控面板的畫素顯示畫面;當內嵌式互電容觸控面板運作於觸控模式時,會對與驅動電極TX1~TX3畫素重疊的共同電壓電極區域VCOM1~VCOM3分別施加與驅動電極TX1~TX3觸控相關的驅動訊號,並將與感測電極RX1~RX2畫素重疊的共同電壓電極區域VCOM4~VCOM5維持於一定電壓。 Referring to FIG. 26B, FIG. 26B is a timing diagram of signals of the in-cell mutual-capacitive touch panel of FIG. 26A in a touch mode and a display mode. As shown in FIG. 26B, when the in-cell mutual-capacitive touch panel operates in the display mode, the gate driver signals G1 to G3 and the source driver signals S1 to S3 are respectively driven by the gate driver and the source driver to drive The pixel display screen of the in-cell touch panel; when the in-cell mutual-capacitive touch panel operates in the touch mode, the common voltage electrode regions VCOM1 to VCOM3 overlapping with the driving electrodes TX1 to TX3 are respectively applied and The driving electrodes TX1 to TX3 touch the driving signals, and maintain the common voltage electrode regions VCOM4 to VCOM5 overlapping the sensing electrodes RX1 to RX2 at a constant voltage.

請參照圖27A,於另一實施例中,共同電壓電極可為單一個共同電壓電極區域VCOM,其與驅動電極TX1~TX3及感測電極RX1~RX2均畫素重疊。 Referring to FIG. 27A, in another embodiment, the common voltage electrode may be a single common voltage electrode region VCOM, which overlaps with the driving electrodes TX1~TX3 and the sensing electrodes RX1 RRX2.

亦請參照圖27B,圖27B係繪示圖27A之內嵌式互電容觸控面板運作於觸控模式與顯示模式時之各訊號的時序圖。如圖27B所示,當內嵌式互電容觸控面板運作於顯示模式時,會由閘極驅動器及源極驅動器分別輸出閘極驅動訊號G1~G3及源極驅動訊號S1~S3,以驅動內嵌式互電容觸控面板的畫素顯示畫面;當內嵌式互電容觸控面板運作於觸控模式時,共同電壓電極區域VCOM會切換為一浮動(Floating)電位VF。 Please refer to FIG. 27B. FIG. 27B is a timing diagram of signals of the in-cell mutual-capacitive touch panel of FIG. 27A operating in the touch mode and the display mode. As shown in FIG. 27B, when the in-cell mutual-capacitive touch panel operates in the display mode, the gate driver signals and the source driver respectively output the gate driving signals G1 to G3 and the source driving signals S1 to S3 to drive The pixel display screen of the in-cell mutual-capacitive touch panel; when the in-cell mutual-capacitive touch panel operates in the touch mode, the common voltage electrode region VCOM is switched to a floating potential VF.

相較於先前技術,根據本創作之內嵌式觸控面板具有下列優點:(1)觸控感測電極及其走線之設計簡單,可有效降低成本;(2)其佈局方式可降低對液晶面板光學上之影響,提升面板開口率;(3)將不屬於觸控電極的部分第一導電層及第二導電層電性連接至共同電壓電極,以降低共同電壓電極本身的電阻電容負載(RC loading)。 Compared with the prior art, the in-cell touch panel according to the present invention has the following advantages: (1) the touch sensing electrode and its routing are simple in design, which can effectively reduce the cost; (2) the layout mode can be reduced. The optical effect of the liquid crystal panel increases the aperture ratio of the panel; (3) electrically connecting a portion of the first conductive layer and the second conductive layer that are not part of the touch electrode to the common voltage electrode to reduce the resistance and capacitance load of the common voltage electrode itself (RC loading).

藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本創作之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本創作之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本創作所欲申請之專利範圍的範疇內。 The features and spirit of the present invention are more clearly described in the above detailed description of the preferred embodiments, and the scope of the present invention is not limited by the preferred embodiments disclosed herein. On the contrary, it is intended to cover all kinds of changes and equivalences within the scope of the patent application to which the present invention is intended.

B‧‧‧跨橋結構 B‧‧‧cross-bridge structure

TX‧‧‧驅動電極 TX‧‧‧ drive electrode

RX‧‧‧感測電極 RX‧‧‧ sensing electrode

M3‧‧‧導電層 M3‧‧‧ conductive layer

Claims (23)

  1. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係整合設置有一第一導電層及一第二導電層;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;以及一玻璃層,設置於該彩色濾光層上方。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer Integrating a first conductive layer and a second conductive layer; a liquid crystal layer disposed above the thin film transistor element layer; a color filter layer disposed above the liquid crystal layer; and a glass layer disposed on the Above the color filter layer.
  2. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係與一共同電壓電極(Common Electrode)同時形成,但該第二導電層與該共同電壓電極彼此分離,該第一導電層係形成於該共同電壓電極之後。 The in-cell touch panel of claim 1, wherein the second conductive layer is formed simultaneously with a common voltage electrode, but the second conductive layer and the common voltage electrode are separated from each other. The first conductive layer is formed after the common voltage electrode.
  3. 如申請專利範圍第2項所述之內嵌式觸控面板,其中該第一導電層係設置於該第二導電層之上方,該第一導電層係電性連接至該第二導電層,以作為一跨橋結構。 The in-cell touch panel of claim 2, wherein the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer. As a cross-bridge structure.
  4. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係與一共同電壓電極同時形成,但該第二導電層與該共同電壓電極彼此分離,該第一導電層係形成於該共同電壓電極之前。 The in-cell touch panel of claim 1, wherein the second conductive layer is formed simultaneously with a common voltage electrode, but the second conductive layer and the common voltage electrode are separated from each other, the first conductive A layer is formed before the common voltage electrode.
  5. 如申請專利範圍第4項所述之內嵌式觸控面板,其中該第二導電層係設置於該第一導電層之上方,該第二導電層係電性連接至該第一導電層,以作為一跨橋結構。 The in-cell touch panel of claim 4, wherein the second conductive layer is disposed above the first conductive layer, and the second conductive layer is electrically connected to the first conductive layer. As a cross-bridge structure.
  6. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係形成於一共同電壓電極之前且該第一導電層係形成於該共同電壓電極之後,該第二導電層係與該薄膜電晶體元件層中之一源極及一 汲極同時形成。 The in-cell touch panel of claim 1, wherein the second conductive layer is formed before a common voltage electrode and the first conductive layer is formed after the common voltage electrode, the second conductive a layer and a source and a source in the thin film transistor element layer Bungee formation at the same time.
  7. 如申請專利範圍第6項所述之內嵌式觸控面板,其中該第一導電層係設置於該第二導電層之上方,該第一導電層係電性連接至該第二導電層,以作為一跨橋結構。 The in-cell touch panel of claim 6, wherein the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer. As a cross-bridge structure.
  8. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係形成於該第一導電層之前且該第一導電層係形成於一共同電壓電極之前,該第二導電層係與該薄膜電晶體元件層中之一源極及一汲極同時形成。 The in-cell touch panel of claim 1, wherein the second conductive layer is formed before the first conductive layer and the first conductive layer is formed before a common voltage electrode, the second The conductive layer is formed simultaneously with one of the source and the drain of the thin film transistor element layer.
  9. 如申請專利範圍第8項所述之內嵌式觸控面板,其中該第一導電層係設置於該第二導電層之上方,該第一導電層係電性連接至該第二導電層,以作為一跨橋結構。 The in-cell touch panel of claim 8, wherein the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer. As a cross-bridge structure.
  10. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係形成於一共同電壓電極之前且該第一導電層係形成於該共同電壓電極之後,該第二導電層係與該薄膜電晶體元件層中之一閘極同時形成。 The in-cell touch panel of claim 1, wherein the second conductive layer is formed before a common voltage electrode and the first conductive layer is formed after the common voltage electrode, the second conductive The layer is formed simultaneously with one of the gates of the thin film transistor element layer.
  11. 如申請專利範圍第10項所述之內嵌式觸控面板,其中該第一導電層係設置於該第二導電層之上方,該第一導電層係電性連接至該第二導電層,以作為一跨橋結構。 The in-cell touch panel of claim 10, wherein the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer. As a cross-bridge structure.
  12. 如申請專利範圍第10項所述之內嵌式觸控面板,其中該薄膜電晶體元件層中之該閘極與另一閘極係彼此相鄰排列。 The in-cell touch panel of claim 10, wherein the gate and the other gate of the thin film transistor element layer are arranged adjacent to each other.
  13. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係形成於該第一導電層之前且該第一導電層係形成於一共同電壓電極之前,該第二導電層係與該薄膜電晶體元件層中之一閘極同時形成。 The in-cell touch panel of claim 1, wherein the second conductive layer is formed before the first conductive layer and the first conductive layer is formed before a common voltage electrode, the second The conductive layer is formed simultaneously with one of the gates of the thin film transistor element layer.
  14. 如申請專利範圍第13項所述之內嵌式觸控面板,其中該第一導電層係設置於該第二導電層之上方,該第一導電層係電性連接至該第二導電層,以作為一跨橋結構。 The in-cell touch panel of claim 13 , wherein the first conductive layer is disposed above the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer. As a cross-bridge structure.
  15. 如申請專利範圍第13項所述之內嵌式觸控面板,其中該薄膜電晶體元件層中之該閘極與另一閘極係彼此相鄰排列。 The in-cell touch panel of claim 13, wherein the gate and the other gate of the thin film transistor element layer are arranged adjacent to each other.
  16. 如申請專利範圍第1項所述之內嵌式觸控面板,係為一內嵌式互電容(Mutual Capacitance)觸控面板,該內嵌式互電容觸控面板之一驅動電極(TX)及一感測電極(RX)係由該第一導電層以網格狀排列而成。 The in-cell touch panel as described in claim 1 is an in-line Mutual Capacitance touch panel, and one of the in-cell mutual-capacitive touch panels drives an electrode (TX) and A sensing electrode (RX) is formed by arranging the first conductive layers in a grid shape.
  17. 如申請專利範圍第16項所述之內嵌式觸控面板,其中當該第一導電層所組成的該驅動電極(TX)與該感測電極(RX)彼此交錯時,係以該第二導電層作為一跨橋結構來電性連接該驅動電極(TX)或電性連接該感測電極(RX)。 The in-cell touch panel of claim 16, wherein when the driving electrode (TX) and the sensing electrode (RX) composed of the first conductive layer are interdigitated with each other, the second The conductive layer is electrically connected to the driving electrode (TX) as a bridge structure or electrically connected to the sensing electrode (RX).
  18. 如申請專利範圍第16項所述之內嵌式觸控面板,其中該第一導電層還包含一第一連接部,該第一連接部係與該驅動電極(TX)及該感測電極(RX)彼此分離,並且該第一連接部係電性連接至一共同電壓電極。 The in-cell touch panel of claim 16, wherein the first conductive layer further comprises a first connecting portion, the first connecting portion is coupled to the driving electrode (TX) and the sensing electrode ( RX) are separated from each other, and the first connection portion is electrically connected to a common voltage electrode.
  19. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層還包含一第二連接部,該第二連接部係電性連接至一共同電壓電極。 The in-cell touch panel of claim 1, wherein the second conductive layer further comprises a second connecting portion electrically connected to a common voltage electrode.
  20. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該彩色濾光層包含一彩色濾光片(Color Filter)及一黑色矩陣光阻(Black Matrix Resist),該黑色矩陣光阻具有良好的光遮蔽性,該第一導電層及該第二導電層係位於該黑色矩陣光阻之下方。 The in-cell touch panel of claim 1, wherein the color filter layer comprises a color filter and a black matrix resist (Black Matrix Resist), the black matrix resist The light shielding property is good, and the first conductive layer and the second conductive layer are located under the black matrix photoresist.
  21. 如申請專利範圍第1項所述之內嵌式觸控面板,其中當該內嵌式觸控面板運作於一觸控模式時,一共同電壓電極係切換為一浮動(Floating)電位或施加一觸控相關訊號。 The in-cell touch panel of claim 1, wherein when the in-cell touch panel operates in a touch mode, a common voltage electrode is switched to a floating potential or a Touch related signals.
  22. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該內嵌式觸控面板之一觸控模式與一顯示模式係分時驅動,並且該內嵌式觸控面板係利用顯示週期之一空白區間(Blanking interval)運作於該觸控模式。 The in-cell touch panel of the first aspect of the invention, wherein the touch mode and the display mode of the in-cell touch panel are time-divisionally driven, and the in-cell touch panel is displayed by using One of the cycles, the blanking interval, operates in the touch mode.
  23. 如申請專利範圍第22項所述之內嵌式觸控面板,其中該空白區間係包含一垂直空白區間(Vertical Blanking Interval,VBI)、一水平空白區間(Horizontal Blanking Interval,HBI)及一長水平空白區間(Long Horizontal Blanking Interval)中之至少一種,該長水平空白區間的時間長度等於或大於該水平空白區間的時間長度,該長水平空白區間係重新分配複數個該水平空白區間而得或該長水平空白區間包含該垂直空白區間。 The in-cell touch panel of claim 22, wherein the blank interval includes a Vertical Blanking Interval (VBI), a Horizontal Blanking Interval (HBI), and a long horizontal level. At least one of a blank horizontal interval (Long Horizontal Blanking Interval), the length of the long horizontal blank interval being equal to or greater than a length of time of the horizontal blank interval, the long horizontal blank interval being redistributed by the plurality of horizontal blank intervals The long horizontal blank interval contains the vertical blank interval.
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