TWI833254B - Memory device having bit line with stepped profile - Google Patents

Abstract

The present application provides a memory device having a bit line (BL) with a stepped profile. The memory device includes a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

Description

Memory device with stepped bit lines

This application claims priority to U.S. Patent Application Nos. 17/729,250 and 17/730,065 (that is, the priority date is "April 26, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a memory device, and in particular to a memory device having a stepped bit line (BL).

Semiconductor components are indispensable for many modern applications. As electronic technology advances, semiconductor components become smaller and smaller in size while providing more functions and containing more integrated circuits. Due to the miniaturization of semiconductor devices, various types and sizes of semiconductor devices providing different functions are integrated and packaged in a single module. Furthermore, many manufacturing operations are performed to integrate various types of semiconductor components.

However, the manufacturing and integration of semiconductor components involves many complex steps and operations. The increased complexity of the manufacturing and integration of semiconductor components may cause defects, such as misalignment, bridging, short circuits, etc. of interconnect structures. Therefore, there is a need to continuously improve the manufacturing process and structure of semiconductor components.

The above description of "prior art" only provides background technology and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and the above description does not constitute prior art for the present disclosure. Any description of the "prior art" in this article shall not be regarded as any part of the "prior art" of this case and does not constitute the prior art of this disclosure.

One aspect of the present disclosure provides a memory device. The memory device includes: a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line It includes a first dielectric layer, a conductive layer disposed above the first dielectric layer, a second dielectric layer disposed above the conductive layer, and surrounding the first dielectric layer, the conductive layer and the a spacer of a second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer and a second portion disposed above the first portion and exposed from the spacer, and wherein the A first width of the first portion is substantially greater than a second width of the second portion.

In some embodiments, the first width of the first portion is substantially consistent with a height of the second dielectric layer.

In some embodiments, the second width of the second portion is substantially consistent with a height of the second dielectric layer.

In some embodiments, a top surface of the first portion and a top surface of the spacer are substantially coplanar.

In some embodiments, a first height of the first portion is substantially greater than or equal to a second height of the second portion.

In some embodiments, the first dielectric layer and the second dielectric layer include the same material.

In some embodiments, the first dielectric layer and the second dielectric layer include nitride.

In some embodiments, the conductive layer includes tungsten (W).

In some embodiments, the spacers include nitride and oxide.

In some embodiments, the spacer includes a first layer, a second layer and a third layer, wherein the second layer is disposed between the first layer and the third layer.

In some embodiments, the first layer contacts the first dielectric layer, the conductive layer, and the second dielectric layer.

In some embodiments, the second layer and the third layer are isolated from the first dielectric layer, the conductive layer, and the second dielectric layer.

In some embodiments, the first layer and the third layer include nitride.

In some embodiments, the second layer includes oxide.

In some embodiments, the second dielectric layer is partially surrounded by the spacer.

In some embodiments, the first dielectric layer and the conductive layer are completely surrounded by the spacer.

Another aspect of the present disclosure provides a memory device. The memory device includes: a semiconductor substrate including a first surface; a first bit line and a second bit line disposed on the third bit line of the semiconductor substrate. On a surface and adjacent to each other, the first bit line and the second bit line respectively include a first dielectric layer, a conductive layer disposed above the first dielectric layer, and a conductive layer disposed above the conductive layer. a second dielectric layer above, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; and a gap provided between the first element line and the second bit Between element lines, the gap has a first width and a second width substantially different from the first width.

In some embodiments, the first width is substantially smaller than the second width.

In some embodiments, the second width is above the first width.

In some embodiments, the void tapers toward the first surface of the semiconductor substrate.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The method includes: providing a semiconductor substrate having a first surface; disposing a first dielectric layer located above the first surface of the semiconductor substrate, and located above the first surface of the semiconductor substrate. a conductive layer above the first dielectric layer, and a second dielectric layer above the conductive layer; setting a patterned mask above the second dielectric layer; removing the second dielectric layer, the The portions of the conductive layer and the first dielectric layer exposed from the patterned mask form a first trench; forming a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer ; Set an energy decomposition mask above the second dielectric layer and the spacer; irradiate a part of the energy decomposition mask with an electromagnetic radiation; remove the part of the energy decomposition mask that is irradiated by the electromagnetic radiation; and remove A portion of the second dielectric layer is exposed from the energy decomposition mask.

In some embodiments, the method further includes removing a portion of the spacer exposed from the energy decomposition mask.

In some embodiments, at least a portion of the second dielectric layer is exposed from the spacer.

In some embodiments, the steps of removing the portion of the second dielectric layer and the step of removing the portion of the spacer are performed separately or simultaneously.

In some embodiments, the energy-decomposable mask is thermally decomposable, photon decomposable, or e-beam decomposable.

In some embodiments, the energy decomposition mask includes a cross-linked compound having a functional group or a double bond.

In some embodiments, the energy decomposition mask includes polymers, polyimides, resin or epoxy.

In some embodiments, the electromagnetic radiation illuminates the portion of the energy-decomposing mask laterally.

In some embodiments, the electromagnetic radiation is infrared (IR), ultraviolet (UV), or electron beam (e-beam).

In some embodiments, the first trench extends toward the first surface of the semiconductor substrate and is adjacent to the second dielectric layer, the conductive layer, and the first dielectric layer.

In some embodiments, the portion of the energy-decomposing mask illuminated by the electromagnetic radiation is located at the periphery of the energy-decomposing mask.

In some embodiments, the portion of the energy decomposition mask illuminated by the electromagnetic radiation contacts the spacer and the second dielectric layer.

In some embodiments, a width of the energy-decomposition mask after removing the portion of the energy-decomposition mask illuminated by the electromagnetic radiation is substantially less than a width of the second dielectric layer after forming the first trench. .

In some embodiments, after removing the portion of the second dielectric layer exposed from the energy decomposition mask, the second dielectric layer includes a first width and a second width, the second width being located at the A width above and substantially smaller than the first width.

In some embodiments, the method further includes removing the energy decomposition mask above the second dielectric layer after removing the portion of the second dielectric layer exposed from the energy decomposition mask.

In summary, since a portion of the second dielectric layer of the bit line is removed to form a stepped profile, the distance or critical dimension between adjacent bit lines can be increased, and adjacent bit lines can be prevented from Line bridging. More specifically, since the bit line has a peripheral edge surrounding the bit line The stepped profile makes it possible to subsequently fill the gaps between adjacent two-bit lines with conductive or insulating material more efficiently. The gaps between adjacent two-bit lines can be completely filled without forming holes while minimizing gaps, thereby improving the performance of the memory device and the process of manufacturing the memory device.

The foregoing has provided a rather broad overview of the features and technical advantages of the present disclosure in order to provide a better understanding of the detailed description of the present disclosure that follows. Additional features and advantages that form the subject of the patent claims of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

100:Memory components

101:Semiconductor substrate

101a: First surface

101b: Second surface

102:Bit line

102a: first dielectric layer

102b: Conductive layer

102c: Second dielectric layer

102d: Gap wall

102j:First layer

102j': first layer material

102k: Second level

102k': Second layer material

102m:Third floor

102m':Third layer material

102e:Part 1

102f:Part 2

102i: Top surface

102g: Top surface

102h: Top surface

102n: Top surface

102p: Top surface

102r: Top surface

102d': gap wall material

103: Gap

104:Patterned mask

104':Photoresist

105:First trench

106: Energy decomposition mask

106a: Part

106b: Peripheral

H1: first height

H2: second height

R: electromagnetic radiation

W1: first width

W2: second width

W3: third width

W4: fourth width

W5: Width

Embodiments of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion.

Figure 1 is a cross-sectional side view of a memory device according to some embodiments of the present disclosure.

FIG. 2 is an enlarged cross-sectional side view of a bit line of the memory device in FIG. 1 .

FIG. 3 is a flowchart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure.

4-26 illustrate cross-sectional views at intermediate stages of forming a memory device according to some embodiments of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure, and these are, of course, examples only and are not intended to be limiting. In the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, as well as embodiments in which the first feature and the second feature may be formed in direct contact. Additional features enable embodiments in which the first feature and the second feature are not in direct contact.

In addition, repeated reference symbols and/or words may be used in various examples of the present disclosure. The purpose of repetition is for simplicity and clarity of explanation, but is not intended to limit the relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "under", "below", "under", "above", "on", etc. are used to conveniently describe a component or feature Relative relationship to other components or features in the drawing. These spatially relative terms are intended to cover different orientations of the component in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Figure 1 is a cross-sectional side view of a memory device 100 in accordance with some embodiments of the present disclosure. In some embodiments, the memory device 100 includes a plurality of unit cells arranged in rows and columns.

In some embodiments, memory device 100 includes a semiconductor substrate 101 . In some embodiments, semiconductor substrate 101 includes a semiconductor material such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, semiconductor substrate 101 includes a semiconductor bulk. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (eg, silicon wafer) or a semiconductor-on-insulator (SOI) wafer (eg, silicon-on-insulator wafer). In some embodiments, semiconductor The substrate 101 is a silicon substrate. In some embodiments, semiconductor substrate 101 includes lightly doped single crystal silicon. In some embodiments, semiconductor substrate 101 is a p-type substrate.

In some embodiments, the semiconductor substrate 101 includes a first surface 101a and a second surface 101b opposite to the first surface 101a. In some embodiments, the first surface 101a is the front surface of the semiconductor substrate 101, where electronic components or components are subsequently formed over the first surface 101a and configured to be electrically connected to external circuits. In some embodiments, second surface 101b is the backside of semiconductor substrate 101 without electronic components or components present.

In some embodiments, the memory device 100 includes a bit line 102 disposed on a semiconductor substrate 101 . In some embodiments, the bit line 102 is disposed on the first surface 101a of the semiconductor substrate 101 and extends from the first surface 101a. In some embodiments, bit lines 102 are configured to read bits in memory element 100 or to allow electrical current to program the bits. In some embodiments, bit line 102 extends perpendicular to first surface 101 a of semiconductor substrate 101 .

In some embodiments, the bit line 102 includes a first dielectric layer 102a, a conductive layer 102b, a second dielectric layer 102c, and a spacer 102d. In some embodiments, the first dielectric layer 102a is disposed on the first surface 101a of the semiconductor substrate 101. In some embodiments, first dielectric layer 102a is completely surrounded by spacers 102d. In some embodiments, second dielectric layer 102c includes a dielectric material, such as nitride or similar materials. In some embodiments, first dielectric layer 102a includes silicon nitride.

In some embodiments, the conductive layer 102b is disposed above the first dielectric layer 102a. In some embodiments, conductive layer 102b contacts first dielectric layer 102a. In some embodiments, conductive layer 102b is completely surrounded by spacers 102d. In some embodiments, conductive layer 102b includes a conductive material, such as tungsten (W) or similar materials.

In some embodiments, the second dielectric layer 102c is disposed on the conductive layer 102b and the above a dielectric layer 102a. In some embodiments, the second dielectric layer 102c contacts the conductive layer 102b and is separated from the first dielectric layer 102a by the conductive layer 102b. In some embodiments, second dielectric layer 102c is partially surrounded by spacers 102d.

In some embodiments, second dielectric layer 102c includes a dielectric material, such as nitride or similar materials. In some embodiments, second dielectric layer 102c includes silicon nitride. In some embodiments, the first dielectric layer 102a and the second dielectric layer 102c include the same material or different materials.

In some embodiments, the spacers 102d surround the first dielectric layer 102a, the conductive layer 102b, and the second dielectric layer 102c. In some embodiments, spacers 102d include dielectric materials such as oxide, nitride, or similar materials. In some embodiments, spacers 102d include oxides and nitrides. In some embodiments, spacer 102d includes several layers. In some embodiments, spacer 102d is a nitride-oxide-nitride (NON) structure.

FIG. 2 is an enlarged view of bit line 102 illustrating several layers of spacers 102d. In some embodiments, spacer 102d includes a first layer 102j, a second layer 102k, and a third layer 102m. In some embodiments, the second layer 102k is disposed between the first layer 102j and the third layer 102m. In some embodiments, first layer 102j contacts second dielectric layer 102c, conductive layer 102b, and first dielectric layer 102a. In some embodiments, first layer 102j includes nitride or oxide. In some embodiments, first layer 102j includes nitride.

In some embodiments, the second layer 102k contacts the first layer 102j and the third layer 102m. In some embodiments, the second layer 102k is isolated from the first dielectric layer 102a, the conductive layer 102b, and the second dielectric layer 102c. In some embodiments, second layer 102k includes nitride or oxide. In some embodiments, second layer 102k includes oxide.

In some embodiments, third layer 102m contacts second layer 102k. In some practical In an embodiment, the third layer 102m is isolated from the first dielectric layer 102a, the conductive layer 102b, and the second dielectric layer 102c. In some embodiments, third layer 102m includes nitride or oxide. In some embodiments, third layer 102m includes nitride.

Referring back to FIG. 1, the second dielectric layer 102c has a stepped profile. In some embodiments, second dielectric layer 102c is at least partially exposed from spacer 102d. In some embodiments, the second dielectric layer 102c includes a first portion 102e and a second portion 102f disposed above the first portion 102e. In some embodiments, first portion 102e is surrounded by spacers 102d. In some embodiments, the second portion 102f is exposed from the spacer 102d.

In some embodiments, second portion 102f protrudes from first portion 102e. In some embodiments, a first width W1 of the first portion 102e is substantially different than a second width W2 of the second portion 102f. In some embodiments, the first width W1 of the first portion 102e is substantially greater than the second width W2 of the second portion 102f.

In some embodiments, the first portion 102e has a first height H1 and the second portion 102f has a second height H2. In some embodiments, the first height H1 of the first portion 102e is substantially greater than or equal to the second height H2 of the second portion 102f. In some embodiments, the first width W1 of the first portion 102e is substantially uniform at different distances above a bottom surface of the second dielectric layer 102c. In some embodiments, the second width W2 of the first portion 102e is substantially uniform at different distances above a bottom surface of the second dielectric layer 102c. In some embodiments, the second width W2 of the second portion 102f is substantially uniform at various distances above the lower surface of the second portion 102f.

In some embodiments, the first portion 102e has a top surface 102g that is substantially coplanar with a top surface 102i of the spacer 102d. In some embodiments, the second portion 102f has a top surface 102h disposed higher than the top surface 102g and the spacer of the first portion 102e Top surface 102i of 102d. In some embodiments, the second portion 102f is separated from the spacer 102d.

Referring back to FIG. 2 , the top surface 102i of the spacer 102d includes a top surface 102n of the first layer 102j, a top surface 102p of the second layer 102k, and a top surface 102r of the third layer 102m. In some embodiments, the top surface 102g of the first portion 102e is substantially coplanar with the top surface 102n of the first layer 102j, the top surface 102p of the second layer 102k, and the top surface 102r of the third layer 102m. In some embodiments, the top surface 102h of the second portion 102f is disposed higher than the top surface 102n of the first layer 102j, the top surface 102p of the second layer 102k, and the top surface 102r of the third layer 102m.

Referring back to FIG. 1 , a gap 103 is provided between adjacent two-bit lines 102 . In some embodiments, at least a portion of the first surface 101 a of the semiconductor substrate 101 is exposed from the void 103 . In some embodiments, void 103 is adjacent second portion 102f of second dielectric layer 102c and adjacent spacer 102d. In some embodiments, void 103 tapers toward first surface 101 a of semiconductor substrate 101 .

In some embodiments, the void 103 has a third width W3 and a fourth width W4 that is substantially different from the third width W3. In some embodiments, the fourth width W4 of the gap 103 is positioned higher than the third width W3 of the gap 103 . In some embodiments, the third width W3 is substantially smaller than the fourth width W4.

The stepped profile of the second dielectric layer 102c of the bit lines 102 increases the fourth width of the gap 103 between adjacent bit lines 102. In this way, bridging of adjacent two-bit lines 102 can be prevented, and the gaps 103 between adjacent two-bit lines 102 can be filled more effectively with conductive or insulating materials. The voids 103 can be completely filled without forming holes while minimizing voids, thus improving the performance of the memory device 100 .

3 is a flowchart illustrating a manufacturing method S200 of the memory device 100 according to some embodiments of the present disclosure, and FIGS. 4 to 26 illustrate cross-sectional views at an intermediate stage of forming the memory device 100 according to some embodiments of the present disclosure.

The stages shown in FIGS. 4 to 26 are also schematically illustrated in the flow chart of FIG. 3 . In the following discussion, Figures 4 through 26 are discussed with reference to the processing steps shown in Figure 3. Method S200 includes multiple operations, and its description and explanation are not considered to limit the order of operations. Method S200 includes several steps (S201, S202, S203, S204, S205, S206, S207, S208 and S209).

Referring to FIG. 4 , a semiconductor substrate 101 is provided according to step S201 in FIG. 3 . In some embodiments, semiconductor substrate 101 includes a semiconductor material such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 has a first surface 101a and a second surface 101b opposite to the first surface 101a.

Referring to FIGS. 5 to 7 , a first dielectric layer 102 a , a conductive layer 102 b and a second dielectric layer 102 c are provided according to step S202 in FIG. 3 . In some embodiments, as shown in FIG. 5 , the first dielectric layer 102a is disposed above the first surface 101a of the semiconductor substrate 101. In some embodiments, the first dielectric layer 102a is provided by deposition, chemical vapor deposition (CVD), or any other suitable process. In some embodiments, second dielectric layer 102c includes a dielectric material, such as nitride or similar materials. In some embodiments, first dielectric layer 102a includes silicon nitride.

In some embodiments, as shown in FIG. 6 , the conductive layer 102b is disposed above the first dielectric layer 102a. In some embodiments, conductive layer 102b is provided by deposition, chemical vapor deposition (CVD), or any other suitable process. In some embodiments, conductive layer 102b includes Conductive materials such as tungsten (W) or similar materials.

In some embodiments, as shown in FIG. 7 , the second dielectric layer 102c is disposed above the conductive layer 102b. In some embodiments, the second dielectric layer 102c is provided by deposition, chemical vapor deposition (CVD), or any other suitable process. In some embodiments, second dielectric layer 102c includes a dielectric material, such as nitride or similar materials. In some embodiments, second dielectric layer 102c includes silicon nitride. In some embodiments, the first dielectric layer 102a and the second dielectric layer 102c include the same material.

Referring to FIGS. 8 and 9 , a patterned mask 104 is disposed above the second dielectric layer 102c according to step S203 in FIG. 3 . 9 Patterned mask 104 is shown.

In some embodiments, photoresist 104' is provided by spin coating or any other suitable process. In some embodiments, portions of photoresist 104' are removed by etching or any other suitable process. In some embodiments, as shown in FIG. 9 , after the patterned mask 104 is formed, at least a portion of the second dielectric layer 102c is exposed from the patterned mask 104 .

Referring to FIGS. 10 to 12 , a portion of the first dielectric layer 102 a , the conductive layer 102 b and the second dielectric layer 102 c exposed from the patterned mask 104 is removed according to step S204 in FIG. 3 to form a first trench 105 . In some embodiments, the first trench 105 extends toward the first surface 101a of the semiconductor substrate 101 and is adjacent to the second dielectric layer 102c, the conductive layer 102b, and the first dielectric layer 102a.

In some embodiments, forming trench 105 includes removing a portion of second dielectric layer 102c as shown in Figure 10, removing a portion of conductive layer 102b as shown in Figure 11, and removing a portion of first dielectric layer 102a as shown in Figure 11. As shown in Figure 12.

In some embodiments, removing a portion of the second dielectric layer 102c, removing a portion of the conductive layer 102b, and removing a portion of the first dielectric layer 102a includes etching or any other suitable process. In some embodiments, at least a portion of the first surface 101a of the semiconductor substrate 101 is exposed after the first trench 105 is formed, as shown in FIG. 12 . In some embodiments, as shown in FIG. 13 , after the first trench 105 is formed, the patterned mask 104 is removed by etching, stripping, or any other suitable process.

Referring to FIGS. 14 and 15 , a spacer 102d surrounding the first dielectric layer 102a, the conductive layer 102b and the second dielectric layer 102c is formed according to step S205. In some embodiments, spacers 102d are formed by disposing a spacer material 102d' over the semiconductor substrate 101 and the second dielectric layer 102c and conforming to the first trench 105, as shown in FIG. 14, and then removed. Portions of the spacer material 102d' located above the semiconductor substrate 101 and above the second dielectric layer 102c are shown in FIG. 15 .

In some embodiments, spacer material 102d' includes nitride and oxide. In some embodiments, spacer material 102d' is provided by deposition, chemical vapor deposition (CVD), or any other suitable process. In some embodiments, portions of the spacer material 102d' disposed over the semiconductor substrate 101 and the second dielectric layer 102c are removed by etching or any other suitable process. In some embodiments, after the spacers 102d are formed, at least a portion of the first surface 101a of the semiconductor substrate 101 and at least a portion of the second dielectric layer 102c are exposed, as shown in FIG. 15 .

In some embodiments, the formation of spacers 102d includes forming a first layer 102j as shown in Figures 16 and 17, forming a second layer 102k as shown in Figures 18 and 19, and forming a third layer 102m as shown in Figure 20 and 21 shown. In some embodiments, the first layer 102j is formed by disposing a first layer of material 102j' over the semiconductor substrate 101 and conforming to the first trench 105, as shown in FIG. As shown in FIG. 16 , some portions of the first layer material 102j′ above the semiconductor substrate 101 and above the second dielectric layer 102c are then removed to form the first layer 102j, as shown in FIG. 17 .

In some embodiments, the second layer 102k is formed by disposing a second layer of material 102k' over the semiconductor substrate 101 and conforming to the first layer 102j, as shown in FIG. 18, and then removing the material 102k' above the semiconductor substrate 101 and conforming to the first layer 102j. portions of the second layer material 102k' above the second dielectric layer 102c to form the second layer 102k, as shown in FIG. 19 .

In some embodiments, the third layer 102m is formed by disposing a third layer of material 102m' above the semiconductor substrate 101 and conforming to the second layer 102k, as shown in FIG. 20, and then removing the material above the semiconductor substrate 101 and 102k. portions of the third layer material 102m' above the second dielectric layer 102c to form the third layer 102m, as shown in Figure 21. In some embodiments, a spacer 102d is formed including the first layer 102j, the second layer 102k, and the third layer 102m, as shown in FIG. 21 . In some embodiments, the first layer 102j and the third layer 102m include nitride, and the second layer 102k includes an oxide.

Referring to FIG. 22 , an energy decomposition mask 106 is disposed on the second dielectric layer 102 c and the spacer 102 d according to step S206 in FIG. 3 . In some embodiments, energy decomposition mask 106 is provided by deposition, CVD, or any other suitable process. In some embodiments, energy decomposable mask 106 is thermally decomposable, photon decomposable, electron beam (e-beam) decomposable, etc. In some embodiments, the energy-decomposing mask 106 can be decomposed by any suitable kind of energy, such as heat, infrared (IR), ultraviolet (UV), electron beam, or similar energy. In some embodiments, energy decomposition mask 106 includes a cross-linked compound having functional groups or double bonds. In some embodiments, energy decomposition mask 106 includes polymer, polyimide, resin, epoxy, or similar materials.

Referring to Figure 23, the energy fraction is irradiated with electromagnetic radiation R according to step S207 in Figure 3. Unmask a portion 106a of the mask 106. In some embodiments, the portion 106a of the energy-decomposing mask 106 illuminated by the electromagnetic radiation R is located at the periphery 106b of the energy-decomposing mask 106. In some embodiments, the portion 106a of the energy decomposition mask 106 illuminated by electromagnetic radiation contacts the spacer 102d and the second dielectric layer 102c.

In some embodiments, electromagnetic radiation R illuminates the periphery 106b of the energy-resolving mask 106 to process the portion 106a of the energy-resolving mask 106. As a result, portion 106a of energy decomposition mask 106 becomes easily removable. In some embodiments, electromagnetic radiation R illuminates portion 106a of energy-resolving mask 106 laterally. In some embodiments, the electromagnetic radiation R is infrared (IR), ultraviolet (UV), electron beam (e-beam) or similar radiation.

Referring to FIG. 24 , the portion 106 a of the energy decomposition mask 106 illuminated by the electromagnetic radiation R is removed according to step S208 in FIG. 3 . In some embodiments, portion 106a of energy decomposition mask 106 is removed by etching or any other suitable process. After the portion 106 a of the energy decomposition mask 106 is removed, at least part of the second dielectric layer 102 c and the spacer 102 d are exposed from the energy decomposition mask 106 . In some embodiments, a width W5 of the energy decomposition mask 106 after removing the portion 106a of the energy decomposition mask 106 illuminated by the electromagnetic radiation R is substantially smaller than the second dielectric layer 102c after the first trench 105 is formed. A first width W1.

Referring to FIG. 25 , a portion of the second dielectric layer 102 c exposed from the energy decomposition mask 106 is removed according to step S209 in FIG. 3 . In some embodiments, a portion of the second dielectric layer 102c exposed from the energy decomposition mask 106 is removed by etching or any other suitable process. After removing the portion of the second dielectric layer 102c exposed from the energy decomposition mask 106, the second dielectric layer 102c includes a portion with a first width W1 and a portion higher than the first width W1 and has a second width. A portion of W2, wherein the second width W2 is substantially smaller than the first width W1. In some embodiments, a structure is formed that includes a first portion 102e and a first portion located above the first portion 102e. The second dielectric layer 102c of the two portions 102f.

In some embodiments, a portion of spacer 102d exposed from energy decomposition mask 106 is removed, as shown in FIG. 25 . In some embodiments, a portion of spacer 102d exposed from energy decomposition mask 106 is removed by etching or any other suitable process. After removing a portion of the spacer 102d exposed from the energy decomposition mask 106, a second portion 102f of the second dielectric layer 102c is exposed from the spacer 102d. In some embodiments, the step of removing a portion of the second dielectric layer 102c exposed from the energy decomposition mask 106 and the step of removing a portion of the spacer 102d exposed from the energy decomposition mask 106 are performed separately or simultaneously.

After removing a portion of the second dielectric layer 102c exposed from the energy decomposition mask 106 and removing a portion of the spacer 102d exposed from the energy decomposition mask 106, one bit line 102 is formed between adjacent two bit lines 102 A gap 103 is formed. In some embodiments, a lower portion of the void 103 has a third width W3, and a higher portion of the void 103 has a fourth width W4 that is substantially greater than the third width W3.

In some embodiments, after forming void 103, energy decomposition mask 106 over second dielectric layer 102c is removed, as shown in Figure 26. In some embodiments, energy decomposition mask 106 is removed by etching or any other suitable process. In some embodiments, the memory device 100 of FIG. 1 is formed, as shown in FIG. 26 .

One aspect of the present disclosure provides a memory device. The memory device includes: a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line It includes a first dielectric layer, a conductive layer disposed above the first dielectric layer, a second dielectric layer disposed above the conductive layer, and surrounding the first dielectric layer, the conductive layer and the a spacer for the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a first portion disposed above the first portion and exposed from the spacer a second portion, and wherein a first width of the first portion is substantially greater than a second width of the second portion.

Another aspect of the present disclosure provides a memory device. The memory device includes: a semiconductor substrate including a first surface; a first bit line and a second bit line disposed on the third bit line of the semiconductor substrate. On a surface and adjacent to each other, the first bit line and the second bit line respectively include a first dielectric layer, a conductive layer disposed above the first dielectric layer, and a conductive layer disposed above the conductive layer. a second dielectric layer above, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; and a gap provided between the first element line and the second bit Between element lines, the gap has a first width and a second width substantially different from the first width.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The method includes: providing a semiconductor substrate having a first surface; disposing a first dielectric layer located above the first surface of the semiconductor substrate, and located above the first surface of the semiconductor substrate. a conductive layer above the first dielectric layer, and a second dielectric layer above the conductive layer; setting a patterned mask above the second dielectric layer; removing the second dielectric layer, the The portions of the conductive layer and the first dielectric layer exposed from the patterned mask form a first trench; forming a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer ; Set an energy decomposition mask above the second dielectric layer and the spacer; irradiate a part of the energy decomposition mask with an electromagnetic radiation; remove the part of the energy decomposition mask that is irradiated by the electromagnetic radiation; and remove A portion of the second dielectric layer is exposed from the energy decomposition mask.

In summary, since a portion of the second dielectric layer of the bit line is removed to form a stepped profile, the distance or critical dimension between adjacent bit lines can be increased, and adjacent bit lines can be prevented from Line bridging. More specifically, since the bit line has a peripheral edge surrounding the bit line The stepped profile makes it possible to subsequently fill the gaps between adjacent two-bit lines with conductive or insulating material more efficiently. The gaps between adjacent two-bit lines can be completely filled without forming holes while minimizing gaps, thereby improving the performance of the memory device and the process of manufacturing the memory device.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes discussed above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. A person of ordinary skill in the art can understand from the disclosure of this disclosure that existing or future development processes that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Machinery, manufacture, composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

100:Memory components 101:Semiconductor substrate 101a: First surface 101b: Second surface 102:Bit line 102a: first dielectric layer 102b: Conductive layer 102c: Second dielectric layer 102d: Gap wall 102e:Part 1 102f:Part 2 102i: Top surface 102g: Top surface 102h: Top surface 103: Gap H1: first height H2: second height W1: first width W2: second width W3: third width W4: fourth width

Claims (20)

A memory component including: a semiconductor substrate including a first surface; and A cell line is disposed on the first surface of the semiconductor substrate and includes a first dielectric layer, a conductive layer disposed above the first dielectric layer, and a second conductive layer disposed above the conductive layer. a dielectric layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, The second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed above the first portion and exposed from the spacer, and wherein a first width of the first portion is substantially greater than A second width of the second portion. The memory device of claim 1, wherein a first height of the first portion is substantially greater than or equal to a second height of the second portion. The memory device of claim 1, wherein the first width of the first portion is substantially consistent with a height of the second dielectric layer. The memory device of claim 1, wherein the second width of the second portion is substantially consistent with a height of the second dielectric layer. The memory device of claim 1, wherein a top surface of the first portion and a top surface of the spacer are substantially coplanar. The memory device of claim 1, wherein the first dielectric layer and the second dielectric layer include the same material. The memory device of claim 1, wherein the first dielectric layer and the second dielectric layer include nitride. The memory device of claim 1, wherein the conductive layer includes tungsten (W). The memory device of claim 1, wherein the spacer includes nitride and oxide. The memory device of claim 1, wherein the spacer includes a first layer, a second layer and a third layer, and the second layer is disposed between the first layer and the third layer. The memory device of claim 10, wherein the first layer contacts the first dielectric layer, the conductive layer and the second dielectric layer. The memory device of claim 10, wherein the second layer and the third layer are isolated from the first dielectric layer, the conductive layer and the second dielectric layer. The memory device of claim 10, wherein the first layer and the third layer include nitride. The memory device of claim 10, wherein the second layer includes oxide. The memory device of claim 1, wherein the second dielectric layer is partially surrounded by the spacer. The memory device of claim 1, wherein the first dielectric layer and the conductive layer are completely surrounded by the spacer. A memory component including: a semiconductor substrate including a first surface; A first bit line and a second bit line are disposed on the first surface of the semiconductor substrate and adjacent to each other, wherein the first bit line and the second bit line respectively include a first intermediary Electrical layer, a conductive layer disposed above the first dielectric layer, a second dielectric layer disposed above the conductive layer, and surrounding the first dielectric layer, the conductive layer and the second dielectric layer a spacer; and A gap is provided between the first bit line and the second bit line, The gap has a first width and a second width that is substantially different from the first width. The memory device of claim 17, wherein the first width is substantially smaller than the second width. The memory device of claim 17, wherein the second width is located above the first width. The memory device of claim 17, wherein the gap gradually becomes narrower toward the first surface of the semiconductor substrate.