TWI792942B - Integrated circuit package substrate - Google Patents

Abstract

An integrated circuit package substrate is provided, which includes a plurality of ball pads, a plurality of second conductive layers, a plurality of first dielectric layers, a plurality of first hollow parts and a plurality of dummy metal parts. The plurality of ball pads are arranged in a first conductive layer. The plurality of second conductive layers are disposed above the first conductive layer. The plurality of first dielectric layers separate, respectively, the first conductive layer and the plurality of second conductive layers from each other. The plurality of first void portions are formed in the second conductive layers corresponding to the ball pads. A plurality of first vertical projections of the first void portions on the first conductive layer respectively overlap the ball pads. The dummy metal parts are floatingly disposed in the first hollow parts, and a plurality of second vertical projections of the dummy metal parts on the first conductive layer overlap the ball pads, respectively.

Description

Integrated circuit package substrate

The invention relates to an integrated circuit packaging substrate, in particular to an integrated circuit packaging substrate that can reduce parasitic capacitance and provide better structural stability.

Due to the needs of increasing computing speed, miniaturization and vertical 3D integration, it is necessary to use package interconnects designed with high performance. Additionally, to improve IC package signal integrity, designers must optimize for the IC package.

The common high-speed differential signal line will add a hollow design. However, too much hollow design will cause the metal distribution ratio between multiple metal layers to be asymmetrical. At the same time, the plane of the metal layer may be too broken, causing stress problems.

The technical problem to be solved by the present invention is to provide an integrated circuit packaging substrate that can reduce parasitic capacitance and provide better structural stability for the deficiencies of the prior art.

In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide an integrated circuit packaging substrate, which includes a plurality of ball pads, a plurality of second conductive layers, and a plurality of first dielectric layers. , a plurality of first hollowed out parts and a plurality of dummy metal parts. The ball pads are disposed in a first conductive layer. The second conductive layers are disposed above the first conductive layer. The first dielectric layers separate the first conductive layer and the second conductive layers from each other. The first hollowed out parts are formed in the second conductive layers corresponding to the ball pads. A plurality of first vertical projections of the first hollowed out portions on the first conductive layer overlap with the ball pads respectively. The dummy metal pieces are floatingly disposed in the first hollowed-out parts, and a plurality of second vertical projections of the dummy metal pieces on the first conductive layer overlap with the ball pads respectively.

One of the beneficial effects of the present invention is that, in the integrated circuit packaging substrate provided by the present invention, since the hollowed out area is filled with floating dummy metal parts, in addition to reducing parasitic capacitance, it can also be strengthened by floating dummy metal parts. The metal distribution ratio of the metal layer below the package core layer does not require additional hollowing out parts to balance the metal distribution ratio on the metal layer above the package core layer, thereby maintaining structural stability and avoiding package warpage.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The following is an illustration of the implementation of the "integrated circuit packaging substrate" disclosed in the present invention through specific specific examples. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

FIG. 1 is a schematic top view of an integrated circuit package substrate according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view of the line A-A in FIG. 1 , and FIG. 3 is an enlarged schematic view of the first hollowed out part of FIG. 1 . 1 to 3, the first embodiment of the present invention provides an integrated circuit packaging substrate 1, which includes a plurality of ball pads (ball pads) 10-1, 10-2 disposed in the first conductive layer 100 , a plurality of second conductive layers 102-1, 102-2, 102-3, a plurality of first dielectric layers 103-1, 103-2, 103-3, a plurality of first hollowed out parts 104-1, 104 -2, 104-3 and multiple dummy metal parts 105-1, 105-2, 105-3.

As shown in FIG. 1 , in an embodiment of the present invention, the second conductive layer 102-1, 102-2, 102-3 is disposed above the first conductive layer 100, and the first conductive layer 100, the second conductive layer 102-1, 102-2, 102-3 are conductive layers made of copper or copper alloy, for example.

The first dielectric layers 103-1, 103-2, 103-3 respectively separate the first conductive layer 100 and the second conductive layers 102-1, 102-2, 102-3 from each other. The first dielectric layer 103-1, 103-2, 103-3 is an electrically insulating layer made of epoxy compound, for example.

A plurality of ball pads 10-1, 10-2 are formed in the first conductive layer 100, which can be used to electrically connect the IC packaging substrate 1 with a ball grid array (BGA) and a printed circuit board. The first dielectric layer 103-1, 103-2, 103-3 is provided with a via hole V1, which is filled with a conductive material, such as copper, so that the first conductive layer 100 and the second conductive layer 102-1, 102- 2. An electrical connection path is established between 102-3.

It should be noted that the first conductive layer 100 has relatively larger metal regions than the second conductive layers 102 - 1 , 102 - 2 , and 102 - 3 , so parasitic capacitance is likely to occur. For example, the ball pads 10-1, 10-2 tend to form parasitic capacitances with the second conductive layers 102-1, 102-2, 102-3 respectively.

Therefore, in the embodiment of the present invention, the first hollowed-out parts 104-1, 104-2, 104-3 are further respectively formed in the second conductive layers 102-1, 102-2, 102-3, and the first The hollowed out parts 104-1, 104-2, 104-3 correspond to the ball pads 10-1, 10-2 respectively.

In the embodiment of FIG. 3, the first vertical projections of the first hollowed out parts 104-1, 104-2, 104-3 on the first conductive layer 100 completely overlap the ball pads 10-1, 10-2 respectively, In other words, the first vertical projections of the first hollowed-out parts 104-1, 104-2, 104-3 on the first conductive layer 100 completely enclose the vertical projections of the ball pads 10-1, 10-2, and the vertical projections of the ball pads 10-1, 10-2 The areas of the first vertical projections are respectively larger than the areas of the corresponding ball pads. Since the first hollowed-out parts 104-1, 104-2, 104-3 can effectively avoid generating parasitic capacitance, it can further prevent the maximum operating frequency used in the integrated circuit from being limited by the parasitic capacitance.

It should be noted that what is shown in Figures 1 to 3 of the embodiment of the present invention is a multi-layer board packaging design for high-speed differential signal lines, so the first hollowed out parts 104-1, 104-2, 104-3 correspond to Two ball pads 10-1, 10-2, but the above is just an example, the present invention is not limited thereto, and the hollowed out part may at least correspond to one ball pad in position. In addition, for the package design with multiple pairs of high-speed differential signal pairs, if only the hollowed out design of the corresponding ball pads is used, the hollowed out part of the metal layer will be too much. Although the high-speed differential signal can have good electrical quality, the package The design will cause the metal distribution ratio to be unbalanced, and even affect the design of other power supply or ground terminals.

For this reason, in the embodiment of the present invention, a plurality of dummy metal parts 105-1, 105-2, 105-3 are further provided, as shown in the sectional view of Fig. 2, corresponding to the ball pad 10-1, the dummy metal parts 105-1, 105-2, 105-3 are floatingly arranged in the first hollowed out parts 104-1, 104-2, 104-3 respectively, and the dummy metal parts 105-1, 105-2, 105-3 are in The second vertical projections on the first conductive layer 100 overlap with the ball pads 10-1 respectively. In detail, the so-called floating connection means that the dummy metal parts 105-1, 105-2, 105-3 are not connected to the surrounding power supply or ground, and are not electrically connected to the ball pad 10-1.

In addition to dummy metal parts, a plurality of first micro-vias (micro-vias) MV1 are also provided in the first hollowed out parts 104-1, 104-2, 104-3, and these ball pads are respectively formed in the first A hollow portion 104-1, 104-2, 104-3 is electrically connected to the ball pad (such as the ball pad 10-2) through the through holes V1 respectively.

For example, in the first hollowed-out part 104-1, both the first micro via MV1 and the dummy metal piece 105-1 are set in the second conductive layer 102-1, and the dummy metal piece 105-1 is not connected to the first microvia. The via hole MV1 is electrically connected.

It should be noted that when applied to the positive and negative signals of high-speed differential signals, for example, the ball pad 10-1 is a positive signal, and the ball pad 10-2 is a negative signal, and the corresponding dummy metal parts are also independently designed, that is, The dummy metal parts corresponding to the ball pad 10-1 are not electrically connected to the dummy metal parts corresponding to the ball pad 10-2. Therefore, the dummy metal element used in the embodiment of the present invention is a completely floating design and does not belong to any electrical property.

Please refer to FIG. 2 again, the integrated circuit package substrate 1 can be, for example, a core package substrate, and therefore also includes a package core layer 106, a plurality of third conductive layers 107-1, 107-2, 107-3, 107-4 and A plurality of second dielectric layers 108-1, 108-2, 108-3. The core package substrate is structurally divided into two parts, the package core layer 106 in the middle part is set above the second conductive layers 102-1, 102-2, 102-3 as a core board, and the upper and lower parts are laminated boards. Due to the support of the core board, compared with the non-core package substrate, the core package substrate is not easy to be warped and deformed during manufacturing, and the laminate is not easy to break.

The third conductive layers 107-1, 107-2, 107-3, 107-4 are disposed above the package core layer 106, and the second dielectric layers 108-1, 108-2, 108-3 separate the third conductive layers 107-1, 107-2, 107-3, 107-4 are separated from each other. Similarly, the third conductive layer 107-1, 107-2, 107-3, 107-4 is, for example, a conductive layer made of copper or copper alloy, and the second dielectric layer 108-1, 108-2, 108- 3 is an electrical insulating layer made of epoxy compound, for example.

A plurality of plated through holes (PTH) P1, P2, corresponding to the ball pads 10-1, 10-2 are respectively formed in the first hollowed out part 105-3, and from the second part closest to the package core layer 106 The conductive layer 102-3 extends to and penetrates the package core layer 106, and is formed in the third conductive layer 107-1 at the same time. In some embodiments, the plated through holes P1 and P2 can be electrically connected to the ball pads 10-1 and 10-2 respectively through the corresponding first microvia MV1, and the plated through holes P1 and P2 are in the first conductive layer 100 A plurality of third vertical projections on , partially overlap with corresponding ball pads 10-1, 10-2, respectively. Moreover, each of the first hollowed out portions 104-1, 104-2, 104-3 completely surrounds the corresponding first micro via MV1 and the corresponding plated through holes P1, P2.

In detail, for the same metal conductive layer, asymmetric metal distribution ratio will cause the plane to be too broken, so that the bonding force between the metal conductive layer and the adjacent dielectric layer is unbalanced, and warping may occur during the manufacturing process. Therefore, when the hollow design is adopted, many additional holes are designed in the same metal conductive layer to strengthen the bonding force between the metal layer and the dielectric layer, thereby affecting the plane integrity of the power supply and ground terminals. Furthermore, taking an eight-layer board as an example (referring to the number of metal conductive layers), the relative layers on both sides of the core packaging layer, such as the second layer and the seventh layer, the third layer and the sixth layer, and the fourth layer The metal distribution ratio of the first layer and the fifth layer must be similar, otherwise it will cause stress problems, such as package warpage.

In order to achieve the purpose of improving the metal distribution ratio, the second vertical projection of the dummy metal parts 105-1, 105-2, 105-3 on the first conductive layer 100 can be, for example, a half-moon shape, and at least have the same shape as the ball pads 10- 1, 10-2 are projected on the first conductive layer 100 by overlapping 50% of the area, as shown in FIG. 3 . In a preferred embodiment, the shape of the second vertical projection may correspond to the projection shape of the ball pads 10-1, 10-2 on the first conductive layer 100, and the ball pads 10-1, 10-2 The projection is fully clad to minimize capacitive effects.

Furthermore, in size, the ball pad 10-1 has a diameter D1 in the range of 300-500 microns. The second vertical projection of the meniscus has a diameter D2 in the range of 400-500 microns. The shortest distance between the second vertical projection and the plated through hole P1 is D3, which is in the range of 50-150 microns. The diameter of the plated through hole P1 is D4, which is in the range of 180-280 microns. The diameter of the first micro-via MV1 is D5, which is in the range of 80-120 microns. The shortest distance between the second vertical projection and the edge of the first hollowed out area is D6, which is within the range of 150-200 microns.

Therefore, as shown in FIG. 3 , the second vertical projections may overlap with 50% to 100% of the projected areas of the ball pads 10-1, 10-2 on the first conductive layer 100, and only The areas required for the necessary elements of predetermined electrical interconnect lines overlap. In some embodiments, these second vertical projections are not consistent with the plurality of third vertical projections of the plated through holes P1, P2 on the first conductive layer 100 and the plurality of first microvias MV1 on the first conductive layer 100. The fourth vertical projection overlaps.

FIG. 4 is a perspective view of the first hollowed out portion and the second hollowed out portion of FIG. 1 . 2 and 4, the integrated circuit packaging substrate 1 also includes a plurality of second hollowed out parts 109-1, 109-2, 109-3, 109-4, corresponding to the plated through holes P1, P2 formed in the first Among the three conductive layers 107-1, 107-2, 107-3, and 107-4, the number of the second hollowed out parts 109-1, 109-2, 109-3, and 109-4 on the package core layer 106 A fifth vertical projection overlaps with the plated through holes P1, P2 respectively. Moreover, the areas of the fifth vertical projections are smaller than the areas of the sixth vertical projections of the first hollowed out parts 104 - 1 , 104 - 2 , 104 - 3 on the packaging core layer 106 . In addition, the integrated circuit packaging substrate 1 also includes a plurality of second micro-vias MV2, corresponding to these plated through holes are respectively formed in the second hollowed out parts 109-1, 109-2, 109-3, 109-4, And are electrically connected with the plated through holes P1 and P2 respectively.

For example, the embodiment of the present invention is an example of an eight-layer package substrate, the packages below the core layer 106 are designed to correspond to the first hollowed out parts 104-1, 104-2 of the ball pads 10-1, 10-2 , 104-3, above the package core layer 106, only the second hollowed-out parts 109-1, 109-2, 109-3, 109-4 are designed corresponding to the plated through holes P1, P2 and the second micro via MV2.

Therefore, as shown in FIG. 4, it can be seen that dummy metal parts 105-1, 105-2, and 105-3 are respectively set in the first hollowed out parts 104-1, 104-2, and 104-3, which can improve the second conductive The metal distribution ratio of the layers 102-1, 102-2, 102-3 is used to avoid affecting the plane integrity of the power supply and ground terminals, and it is also possible to improve the packaging core layer 106 by dummy metal parts 105-1, 105-2, 105-3 The lower metal distribution ratio does not need to be balanced by hollowing out the third conductive layers 107-1, 107-2, 107-3, 107-4 corresponding to the ball pads 10-1, 10-2 above the package core layer 106 Metal distribution ratio, thereby avoiding package warpage. In addition, it can also be roughly seen from FIG. 4 that the metal distribution ratios of the upper and lower regions of the packaging core layer 106 will not differ too much in the relative layers.

5 to 7 are the insertion loss simulation curves, reflection loss simulation curves and differential time domain reflectance diagrams of the integrated circuit package substrate, the hollowed-out design only and the hollowed-out design according to the embodiment of the present invention, respectively. From the insertion loss curve in FIG. 5 , it can be clearly seen that the improved effect of using the integrated circuit packaging substrate of the embodiment of the present invention and using only the hollowed-out design is better than that without the hollowed-out design. Moreover, the insertion loss performance of adding dummy metal parts in the hollowed-out part is almost the same as that of the hollow-out-only design, which means that the dummy metal parts will not affect the loss of high-speed differential signals.

On the other hand, from the reflection loss curve in Figure 6, no matter whether the integrated circuit packaging substrate of the embodiment of the present invention or only the hollowed-out design is used, it is significantly better than the no-hollowed design, and even below 30 GHz there are more than -10dB improvement. However, the addition of dummy metal parts will slightly reduce the effect of reducing parasitic capacitance, but the overall performance is still similar to that achieved by using only hollowed-out designs.

Furthermore, observing the performance in the time domain, it can be seen from the differential time domain reflectance diagram in Figure 7 that if there is no design of the hollowed out part, it will cause a strong parasitic capacitance, and the effect of reducing the parasitic capacitance will be slightly reduced by the dummy metal parts, but it can be Provide better copper deposition rate and bonding force.

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that, in the integrated circuit packaging substrate provided by the present invention, since the hollowed out area is filled with floating dummy metal parts, in addition to reducing parasitic capacitance, it can also be strengthened by floating dummy metal parts. The metal distribution ratio of the metal layer below the package core layer does not require additional hollowing out parts to balance the metal distribution ratio on the metal layer above the package core layer, thereby maintaining structural stability and avoiding package warpage.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not therefore limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

1: Integrated circuit packaging substrate 100: the first conductive layer 10-1, 10-2: ball cushion 102-1, 102-2, 102-3: second conductive layer 103-1, 103-2, 103-3: first dielectric layer 104-1, 104-2, 104-3: the first hollowed out part 105-1, 105-2, 105-3: virtual metal parts 106:Encapsulate the core layer 107-1, 107-2, 107-3, 107-4: the third conductive layer 108-1, 108-2, 108-3: second dielectric layer 109-1, 109-2, 109-3, 109-4: the second hollowed out part A-A: line D1, D2, D4, D5: Diameter D3, D6: the shortest distance MV1: The first microvia MV2: The second micro via P1, P2: Plated through holes V1: Through hole

FIG. 1 is a schematic top view of an integrated circuit packaging substrate according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the line A-A in FIG. 1 .

FIG. 3 is an enlarged schematic view of the first hollowed out portion in FIG. 1 .

FIG. 4 is a perspective view of the first hollowed out portion and the second hollowed out portion of FIG. 1 .

5 to 7 are the insertion loss simulation curves, reflection loss simulation curves and differential time domain reflectance diagrams of the integrated circuit package substrate, the hollowed-out design only and the hollowed-out design according to the embodiment of the present invention, respectively.

1: Integrated circuit packaging substrate

A-A: line

Claims (10)

An integrated circuit packaging substrate, which includes: a plurality of ball pads (ball pads), arranged in a first conductive layer; a plurality of second conductive layers, arranged above the first conductive layer; a plurality of first dielectric layers, respectively separating the first conductive layer and the second conductive layers from each other; a plurality of first hollowed out parts, corresponding to the ball pads formed in the second conductive layers, wherein the first hollowed out A plurality of first vertical projections of the first conductive layer are overlapped with the ball pads respectively; and a plurality of dummy metal parts are floatingly arranged in the first hollowed out parts, and the dummy metal parts are placed in the first hollowed out parts. A plurality of second vertical projections on the first conductive layer overlap with the ball pads respectively. The integrated circuit packaging substrate as claimed in claim 1, wherein a plurality of first vertical projections of the first hollowed out parts on the first conductive layer completely overlap the ball pads respectively, and the first vertical The projected areas are respectively larger than those of the corresponding ball pads. The integrated circuit package substrate as claimed in claim 1, wherein the second vertical projections overlap at least 50% of the area of the projections of the ball pads on the first conductive layer. The integrated circuit packaging substrate as described in claim 1, further comprising: a packaging core layer disposed above the second conductive layers; and a plurality of plated through holes (PTH), corresponding to the ball pads are respectively formed in the first hollowed-out parts, and extend from one of the second conductive layers closest to the packaging core layer to the packaging core layer and penetrate through the packaging core layer. The integrated circuit packaging substrate as claimed in claim 4, further comprising: a plurality of first micro-vias (micro-vias), corresponding to the ball pads formed on the The first hollowed out part is electrically connected to the ball pads respectively. The integrated circuit packaging substrate as claimed in claim 5, wherein the second vertical projections are a plurality of half-moon shapes. The integrated circuit packaging substrate as claimed in claim 5, wherein the plated through holes are electrically connected to the ball pads through the corresponding first micro-vias respectively, and the plated through holes are in the first A plurality of third vertical projections on the conductive layer partially overlap with the corresponding ball pads. The integrated circuit package substrate as claimed in claim 5, wherein each of the first hollowed out parts completely surrounds the corresponding first micro-vias and the corresponding plated through holes. The integrated circuit packaging substrate as claimed in claim 4, further comprising: a plurality of third conductive layers disposed above the packaging core layer; and a plurality of second dielectric layers separating the third conductive layers from each other . The integrated circuit package substrate as claimed in claim 9, further comprising: a plurality of second hollowed out parts formed in the third conductive layers corresponding to the plated through holes, wherein the second hollowed out parts are A plurality of fifth vertical projections on the package core layer overlap with the plated through holes respectively.

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