TWI792672B - Semiconductor device with contact check circuitry - Google Patents

Abstract

A semiconductor device with contact check circuitry is provided. The semiconductor device includes a plurality of pads, an internal circuit, and a contact check circuit. The plurality of pads includes a first pad and a second pad. The internal circuit is coupled to the plurality of pads. The contact check circuit, at least coupled to the first pad and the second pad, is used for checking, when the semiconductor device is under test, contact connections to the first pad and the second pad to generate a check result signal according to comparison of a first test signal and a second test signal received from the first pad and the second pad with at least one reference signal.

Description

Semiconductor device with contact check circuit

The invention relates to an integrated circuit, especially a semiconductor device with a contact inspection circuit.

In electronic products, electronic fuse (e-fuse) is a technology that allows real-time dynamic reprogramming of semiconductor devices (or chips). In theory, computer logic is usually "etched" or "hard-coded" onto the chip and cannot be changed after the chip is manufactured. By using a set of electronic fuses in a semiconductor device, a chip manufacturer can make changes to the circuitry on a chip while it is running, or before shipping the chip to a downstream customer.

In an electronic fuse blowing operation, signals from semiconductor test equipment are input to the semiconductor device through probes of the semiconductor test equipment that contact pads of the semiconductor device. If the probe does not make proper contact with the pad, the firing will not proceed properly.

An object of the present invention is to provide a semiconductor device having a contact inspection circuit. The semiconductor device includes a contact check circuit capable of contacting the first pad with the second pad when the semiconductor device is tested, for example, using semiconductor test equipment connected to at least two pads of the semiconductor device. A plurality of contact connections of the two pads are inspected to generate an inspection result signal.

To achieve at least the above objects, the present invention provides a semiconductor device having a contact inspection circuit. The semiconductor device includes a plurality of pads, an internal circuit and a contact inspection circuit. The pads include a first pad and a second pad. The internal circuit is coupled to the pads. The contact inspection circuit is at least coupled to the first pad and the second pad, and is used for inspecting a plurality of contact connections between the first pad and the second pad when the semiconductor device is tested To generate an inspection result signal, the inspection result signal is generated according to a comparison between a first test signal received from the first pad and a second test signal received from the second pad with at least one reference signal.

In some embodiments, the contact check circuit includes a voltage detection circuit and a comparison circuit. The voltage detection circuit is coupled to the first pad and the second pad, and is used for generating at least one voltage detection signal. The comparison circuit is coupled to the voltage detection circuit and used for generating the inspection result signal according to the at least one voltage detection signal and the at least one reference signal.

In some embodiments, the voltage detection circuit includes a voltage divider coupled between the first pad and the second pad for generating the at least one voltage detection signal.

In some embodiments, the comparison circuit includes a comparator for generating the inspection result signal according to the at least one voltage detection signal and the at least one reference signal.

In some embodiments, the at least one reference signal includes a first reference signal and a second reference signal. The comparison circuit is configured to generate a first comparison signal according to the at least one voltage detection signal and the first reference signal; and the comparison circuit is configured to generate a second voltage detection signal according to the at least one voltage detection signal and the second reference signal A comparison signal, wherein the comparison circuit is configured to generate the inspection result signal according to the first comparison signal and the second comparison signal.

In some embodiments, the comparison circuit includes a first comparator, a second comparator and a logic unit. The first comparator is used for detecting the signal according to the at least one voltage and the first reference The signal generates the first comparison signal. The second comparator is used for generating the second comparison signal according to the at least one voltage detection signal and the second reference signal. The logic unit is coupled to the first comparator and the second comparator, and is used for generating the inspection result signal according to the first comparison signal and the second comparison signal.

In some embodiments, the at least one voltage detection signal includes a first voltage detection signal and a second voltage detection signal, and the voltage detection circuit is configured to A signal generates the first voltage detection signal; and the voltage detection circuit is configured to generate the second voltage detection signal according to a second power supply signal and the second test signal.

In some embodiments, the at least one voltage detection signal includes a first voltage detection signal and a second voltage detection signal, and the voltage detection circuit includes a first voltage divider and a second voltage divider . The first voltage divider is coupled between the first welding pad and a first power supply end, and is used for generating the first voltage detection signal. The second voltage divider is coupled between a second power supply terminal and the second welding pad, and is used for generating the second voltage detection signal.

In some embodiments, the at least one voltage detection signal includes a first voltage detection signal and a second voltage detection signal; the at least one reference signal includes the first reference signal and the second reference signal; the comparison The circuit is configured to generate a first comparison signal according to the first voltage detection signal and the first reference signal; and the comparison circuit is configured to generate a second comparison signal according to the second voltage detection signal and the second reference signal , wherein the comparison circuit is configured to generate the inspection result signal according to the first comparison signal and the second comparison signal.

In some embodiments, the comparison circuit includes a first comparator, a second comparator and a logic unit. The first comparator is used for generating the first comparison signal according to the first voltage detection signal and the first reference signal. The second comparator is used to detect the signal according to the second voltage and the second The reference signal generates the second comparison signal. The logic unit is used for generating the inspection result signal according to the first comparison signal and the second comparison signal.

In some embodiments, the internal circuit includes an electronic fuse coupled between the first pad and the second pad.

In some embodiments, the semiconductor device further includes an output logic unit for generating a test result signal according to the inspection result signal and a response code.

Accordingly, embodiments of a semiconductor device having a contact check circuit are provided. The semiconductor device includes a contact checking circuit for checking a plurality of contact connections of at least two pads of the semiconductor device to generate A check result signal. The inspection result signal can be used to indicate whether the contact connection with the first pad and the second pad is invalid, and the semiconductor testing equipment can be configured to determine whether to continue testing according to the inspection result signal. In this way, the reliability of semiconductor device testing can be improved.

1: Semiconductor device

1A: Semiconductor device

10: Contact check circuit

110: Voltage detection circuit

120: Comparison circuit

111: Voltage divider

2: Internal circuit

20: Contact check circuit

220: comparison circuit

30: Contact check circuit

310: Voltage detection circuit

311: The first voltage divider

312: second voltage divider

320: comparison circuit

5: Contact check circuit

510: decoder

520: Electronic fuse unit

600: output logic unit

9: Semiconductor test equipment

CMD: command terminal

CMP: comparator

CMP1: the first comparator

CMP2: second comparator

DQ: data terminal

IN: response code

LU: logical unit

OUT: Test result signal

P1: The first pad

P2: Second pad

PS1: the first power supply terminal

PS2: Second power supply terminal

PB: Probe

R1: resistance

R11: Resistor

R12: Resistor

R2: resistance

R21: Resistor

R22: Resistor

S _n : voltage detection signal

S _C1 : The first comparison signal

S _C2 : The second comparison signal

S _CR : Check result signal

S _D1 : the first voltage detection signal

S _D2 : Second voltage detection signal

V _REF : Reference signal

V _REF1 : The first reference signal

V _REF2 : Second reference signal

FIG. 1 is a schematic diagram depicting an example architecture of a semiconductor device with a contact inspection circuit, which is tested by semiconductor test equipment, representing various embodiments of the present invention.

FIG. 2 is a block diagram of an embodiment of a contact check circuit for the example architecture of FIG. 1 .

FIG. 3 is a block diagram depicting another embodiment of a contact check circuit for use in the example architecture of FIG. 1 .

FIG. 4 is a block diagram depicting yet another embodiment of a contact check circuit for use in the example architecture of FIG. 1 .

FIG. 5 is a block diagram depicting an embodiment of a semiconductor device used in the example architecture of FIG. 1 .

FIG. 6 is a schematic diagram depicting an embodiment of an output logic unit used in the example architecture of FIG. 5 .

In order to fully understand the purpose, characteristics and effects of the present invention, the present invention will be described in detail by the following specific embodiments, and in cooperation with the attached drawings, as follows: With reference to Fig. 1, it depicts a representative Inventive Various Embodiments Example architecture of a semiconductor device 1 with a contact inspection circuit.

As shown in FIG. 1 , a semiconductor device 1 includes a plurality of pads, an internal circuit 2 and a contact inspection circuit 5 . The pads include a first pad P1 and a second pad P2. The internal circuit 2 is coupled to the pads. The contact inspection circuit 5 is at least coupled to the first pad P1 and the second pad P2, and is used to connect to the first pad P1 and the second pad P2 (for example, using a test probe). When the semiconductor testing equipment 9 tests the semiconductor device 1, it checks the contact connection between the first pad P1 and the second pad P2 to generate an inspection result signal. It is generated by comparing a first test signal and a second test signal received by the second pad P2 with at least one reference signal.

In a practical scenario, the internal circuit 2 may include circuits for specific purposes (for example, controllers, memories, logic circuits, etc.) and an electronic fuse unit, which includes one or more circuits for selectively changing The function or operation of an electronic fuse in that circuit. In the test of the electronic fuse blowing operation, signals from the semiconductor testing equipment 9 are input to the semiconductor device 1 through the plurality of probes PB of the semiconductor testing equipment 9 contacting the plurality of pads of the semiconductor device 1 . If the probes PB are not in proper contact with the solder pads, the firing cannot be performed correctly. In this case, the inspection result signal can be used to indicate whether the contact connection to the first pad P1 and the contact connection to the second pad P2 can be used correctly for testing.

In some embodiments, the contact check circuit 5 can be implemented to include a voltage detection circuit (such as 110 in FIG. 2 or 310 in FIG. 4 ) and a comparison circuit (such as 120 in FIG. 2 , 220 or 320 in Fig. 4). The voltage detection circuit is coupled to the first pad P1 and the second pad P2, and is used to generate at least one voltage detection signal (for example, represented by S _n in FIG. 2; S in FIG. 4 _D1 and S _D2 ). The comparison circuit is coupled to the voltage detection circuit, and is used for detecting the at least one voltage signal and the at least one reference signal (such as represented by V _REF in FIG. 2 ; or V _REF1 in FIGS. 3 and 4 ) and V _REF2 ), to generate the inspection result signal (such as represented by S _CR ). The at least one reference signal can be obtained, for example, by one or a plurality of bandgap voltage circuits of the semiconductor device 1 , or by an external power supply or voltage source.

Referring to FIG. 2 , an embodiment of a contact check circuit for the example architecture of FIG. 1 is depicted. In FIG. 2 , a contact check circuit 10 includes a voltage detection circuit 110 and a comparison circuit 120 .

In one embodiment, the voltage detection circuit 10 includes a voltage divider 111 . The voltage divider 111 coupled between the first pad P1 and the second pad P2 is used to generate a voltage detection signal S _n .

For example, the comparison circuit 120 includes a comparator CMP for generating a check result signal S _CR according to the voltage detection signal S _n and a reference signal V _REF .

With the embodiment depicted in FIG. 2, the contact checking circuit 10 can be configured or designed to indicate whether the contact connections of the probes to the first pad P1 and the second pad P2 have failed . For example, assuming that the semiconductor device 1 is implemented to include the first pad P1 and the second pad P2, the first pad P1 and the second pad P2 are designed to receive a required positive supply voltage and a negative supply voltage. The supply voltages are, for example, direct current (DC) voltages of 4 volts and -2 volts respectively. In order to indicate whether the contact connections are correct or reliable during the test, the voltage divider 111 can be designed by setting the resistance values of the resistors R1 and R2, so that when the first pad P1 and the second pad P2 are indeed receiving When the required voltage supply signal is obtained, the detection signal S _n (such as voltage signal level (magnitude)) is equal to or greater than the reference signal V _REF (such as V _REF =1.25 volts), plus the inspection result signal _SCR is then output at, for example, a logic high level to indicate that the contact connections are correct. On the contrary, in a test, if the first pad P1 and the second pad P2 are not in contact with the corresponding probes correctly, the detection signal S _n will be less than the reference signal V _REF (for example, V _REF =1.25 volts), the check result signal S _CR is then output at a logic low level, which indicates that the contact connections have failed.

In order to perform a contact check more accurately, the contact check circuit 5 can be implemented such that the detection signal (such as S _n in FIG. 2 ) is compared with two or a plurality of reference signals representing different reference values instead of the reference signal in FIG. 2 A reference signal (such as V _REF ) for comparison.

Referring to FIG. 3 , another embodiment of a contact check circuit for the example architecture of FIG. 1 is depicted. In FIG. 3 , a contact check circuit 20 includes a voltage detection circuit 110 and a comparison circuit 220 . The contact inspection circuit 20 of FIG. 3 is different from the contact inspection circuit 10 of FIG. 2 in that: the at least one reference signal includes a first reference signal V _REF1 and a second reference signal V _REF2 ; and the comparison of the contact inspection circuit 20 The circuit 220 is configured to generate a first comparison signal S C1 according to the voltage detection signal S _n and the first reference signal V _REF1 , and generate a first comparison signal S _C1 according to the voltage detection signal S _n and the second reference signal V _REF2 The comparison signal S _C2 , and the inspection result signal S _CR is generated according to the first comparison signal S _C1 and the first comparison signal S _C2 .

As shown in FIG. 3 , the comparison circuit 220 includes a first comparator CMP1 , a second comparator CMP2 and a logic unit LU.

The first comparator CMP1 is used for generating the first comparison signal S _C1 according to the voltage detection signal S _n and the first reference signal V _REF1 . For example, the first comparator CMP1 has a non-inverting terminal for receiving the voltage detection signal S _n and an inverting terminal for receiving the first reference signal V _REF1 .

The second comparator CMP2 is used for generating the second comparison signal S _C2 according to the voltage detection signal S _n and the second reference signal V _REF2 . For example, the second comparator CMP2 has a non-inverting terminal for receiving the second reference signal V _REF2 and an inverting terminal for receiving the voltage detection signal _Sn .

The logic unit LU coupled to the first comparator CMP1 and the second comparator CMP2 is used to generate the inspection result signal S _CR according to the first comparison signal S _C1 and the second comparison signal S _C2 . In one embodiment, the logic unit LU includes an AND gate. The AND gate is used for receiving the first comparison signal S _C1 and the second comparison signal S _C2 , and for outputting the inspection result signal S _CR .

S_n

V_REF2)。例如，該第一參考訊號V_REF1及該第二參考訊號V_REF2可分別設為V_REF-D及V_REF+D的電壓值(例如V_REF=1.25V,D=0.25V)。 As shown in FIG. 3, the comparison circuit 220 can be implemented to determine whether the voltage detection signal _Sn is between the first reference signal V _REF1 and the second reference signal V _REF2 (for example, the V _REF1

S _n

V _REF2 ). For example, the first reference signal V _REF1 and the second reference signal V _REF2 can be respectively set to the voltage values of V _REF −D and V _REF +D (eg V _REF =1.25V, D=0.25V).

S_n

V_REF2)，加上該檢查結果訊號S_CR接著在例如一邏輯高位準下輸出，來表示該等接觸連接是正確的。相反地，在一測試中，若該第一焊墊P1及該第二焊墊P2沒有與所對應的探針正確接觸，該偵測訊號S_n將會少於該第 一參考訊號V_REF1(例如V_REF1=1.0伏特)或大於該第二參考訊號V_REF2(例如V_REF2=1.5伏特)，該檢查結果訊號S_CR接著在一邏輯低位準下輸出，該邏輯低位準是表示該等接觸連接已失效。例如，若該第一焊墊P1正確地接收一正供應電壓(例如4伏特)且該第二焊墊P2沒有正確地接收到一負供應電壓(例如對應的探針沒有接觸第二焊墊P2或不正確的接觸)，該偵測訊號S_n(例如2伏特、3伏特、3.8伏特或4伏特)可能會大於該第二參考訊號V_REF2(例如V_REF2=1.5伏特)。在其他實施例中，相反地，若該第一焊墊P1沒有正確地接收到一正供應電壓(例如對應的探針沒有接觸第一焊墊P1或不正確的接觸)，且該第二焊墊P2正確地接收一負供應電壓(例如-2伏特)，該偵測訊號S_n(例如，-2伏特、-1伏特、0伏特或0.5伏特)可能會少於該第一參考訊號V_REF1(例如V_REF1=1.0伏特)。 With the embodiment depicted in FIG. 3 , the contact checking circuit 20 can be configured or designed to indicate whether the contact connection of the probe to the first pad P1 and the second pad P2 has failed. For example, assuming that the semiconductor device 1 is implemented to include the first pad P1 and the second pad P2, the first pad P1 and the second pad P2 are designed to receive a required positive supply voltage and a negative supply voltage. The supply voltages are, for example, direct current (DC) voltages of 4 volts and -2 volts respectively. In order to indicate whether the contact connections are correct or reliable during the test, the voltage divider 111 can be designed by setting the resistance values of the resistors R1 and R2, so that when the first pad P1 and the second pad P2 are indeed receiving When the required voltage supply signal, by the detection signal S _n (such as voltage signal level (magnitude)) between the first reference signal V _REF1 and the second reference signal V _REF2 (such as V _REF1

S _n

V _REF2 ), plus the check result signal S _CR is then output at eg a logic high level to indicate that the contact connections are correct. On the contrary, in a test, if the first pad P1 and the second pad P2 are not in contact with the corresponding probes correctly, the detection signal S _n will be less than the first reference signal V _REF1 ( For example, V _REF1 =1.0 volts) or greater than the second reference signal V _REF2 (for example, V _REF2 =1.5 volts), the inspection result signal S _CR is then output at a logic low level, which indicates that the contact connections expired. For example, if the first pad P1 correctly receives a positive supply voltage (for example, 4 volts) and the second pad P2 does not receive a negative supply voltage correctly (for example, the corresponding probe does not touch the second pad P2 or incorrect contact), the detection signal S _n (eg 2V, 3V, 3.8V or 4V) may be greater than the second reference signal V _REF2 (eg V _REF2 =1.5V). In other embodiments, on the contrary, if the first pad P1 does not correctly receive a positive supply voltage (for example, the corresponding probe does not touch the first pad P1 or is not in correct contact), and the second pad P1 Pad P2 correctly receives a negative supply voltage (eg -2V), the detection signal S _n (eg -2V, -1V, 0V or 0.5V) may be less than the first reference signal V _REF1 (eg V _REF1 =1.0 Volts).

In order to perform contact inspection more accurately, the contact inspection circuit 5 can be implemented such that the first test signal received from the first pad P1 and the second test signal received from the second pad P2 are used to obtain Two corresponding voltage detection signals (such as _SD1 or _SD2 in FIG. 4 ) instead of one detection signal (such as S _n ) in FIG. 2 or FIG. 3 .

Referring to FIG. 4 , another embodiment of a contact check circuit for the example architecture of FIG. 1 is depicted. In FIG. 4 , a contact check circuit 30 includes a voltage detection circuit 310 and a comparison circuit 320 . The contact inspection circuit 30 in FIG. 4 is different from the contact inspection circuit 20 in FIG. 3 in that: the at least one voltage detection signal includes a first voltage detection signal S _D1 and a second voltage detection signal S _D2 ; and The voltage detection circuit 310 of the contact inspection circuit 30 is configured to generate the first voltage detection signal S D1 according to the first test signal and a first power supply signal, and to generate the first voltage detection signal S _D1 according to a second power supply signal and the second The test signal is used to generate the second voltage detection signal S _D2 . In addition, the comparison circuit 320 of the contact inspection circuit 30 is configured to generate a first comparison signal S C1 according to the first voltage detection signal S _D1 and the first reference signal V _REF1 , and to generate a first comparison signal S _C1 according to the second voltage detection signal S _D2 and the second reference signal V _REF2 to generate a second comparison signal S _C2 .

As shown in FIG. 4 , the voltage detection circuit 310 includes, for example, a first voltage divider 311 and a second voltage divider 312 . The first voltage divider 311 coupled between the first pad P1 and a first power supply terminal PS1 is used to generate the first voltage detection signal S _D1 . The second voltage divider 312 coupled between a second power supply terminal PS2 and the second pad P2 is used to generate the second voltage detection signal S _D2 .

As shown in FIG. 4 , the comparison circuit 320 includes a first comparator CMP1 , a second comparator CMP2 and a logic unit LU. Compared with the comparison circuit 220 in FIG. 3 , the comparison circuit 320 receives the first voltage detection signal _SD1 and the second voltage detection signal _SD2 instead of receiving a voltage detection signal S _n .

The first comparator CMP1 of the comparison circuit 320 is used for generating the first comparison signal S _C1 according to the first voltage detection signal S _D1 and the first reference signal V _REF1 . For example, the first comparator CMP1 has a non-inverting terminal for receiving the first voltage detection signal _SD1 and an inverting terminal for receiving the first reference signal V _REF1 .

The second comparator CMP2 of the comparison circuit 320 is used for generating the first comparison signal S _C1 according to the second voltage detection signal _SD2 and the second reference signal V _REF2 . For example, the second comparator CMP2 has a non-inverting terminal for receiving the second reference signal V _REF2 and an inverting terminal for receiving the second voltage detection signal _SD2 .

The logic unit LU coupled to the first comparator CMP1 and the second comparator CMP2 is used to generate the inspection result signal S _CR according to the first comparison signal S _C1 and the second comparison signal S _C2 . For example, the comparison circuit 320 is similar to the logic unit LU of the comparison circuit 220 .

V_REF1且V_REF2

S_D2)。例如，該第一參考訊號V_REF1及該第二參考訊號V_REF2可設為相同電壓值或不同電壓值。 As shown in Figure 4, the comparison circuit 320 can be implemented to determine whether the first voltage detection signal S _D1 is greater than or equal to the first reference signal V _REF1 , and whether the second reference signal V _REF2 is greater than or equal to the second Voltage detection signal S _D2 (for example: S _D1

V _REF1 and V _REF2

_SD2 ). For example, the first reference signal V _REF1 and the second reference signal V _REF2 can be set to the same voltage or different voltages.

V_REF1且V_REF2

S_D2，其中V_REF1

V_REF2)，加上該檢查結果訊號S_CR接著在例如一邏輯高位準下輸出，來表示該等接觸連接是正確的。相反地，在測試中，若該第一焊墊P1及該第二焊墊P2的其中之一沒有正確的接觸於對應的探針，該第一電壓偵測訊號S_D1將會少於該第一參考訊號V_REF1(例如：S_D1<V_REF1)，或該第二參考訊號V_REF2小於該第二電壓偵測訊號S_D2(例如：V_REF2<S_D2)，該檢查結果訊號S_CR接著在例如一邏輯低位準下輸出，來表示該等接觸連接是失效的。如此一來，藉由接觸檢查電路30可更準確地進行接觸檢查。 By the method depicted in FIG. 4 , the contact inspection circuit 30 can be configured or designed to indicate whether the contact connection of the probes to the first pad P1 and the second pad P2 fails. For example, assume that the semiconductor device 1 is implemented to include the first pad P1 and the second pad P2. The first pad P1 and the second pad P2 are used to receive a required positive supply voltage and a negative supply voltage, such as direct current (DC) voltages of 4 volts and −2 volts respectively. In order to show whether these contact connections are correct or reliable during the test, the voltage divider 311 and the voltage divider 312 can be designed by setting the resistance values of the resistors R11, R12, R21 and R22, so that when the first pad When P1 and the second pad P2 do receive the voltage supply signal, the first voltage detection signal S _D1 is greater than or equal to the first reference signal V _REF1 , plus the second reference signal V _REF2 is greater than or equal to The second voltage detection signal S _D2 (for example: S _D1

V _REF1 and V _REF2

S _D2 , where V _REF1

V _REF2 ), plus the check result signal S _CR is then output at eg a logic high level to indicate that the contact connections are correct. On the contrary, in the test, if one of the first pad P1 and the second pad P2 is not correctly contacted with the corresponding probe, the first voltage detection signal S D1 will be less than the first voltage detection signal S _D1 A reference signal V _REF1 (for example: S _D1 <V _REF1 ), or the second reference signal V _REF2 is smaller than the second voltage detection signal S _D2 (for example: V _REF2 <S _D2 ), the inspection result signal S _CR is then output at eg a logic low level to indicate that the contact connections are disabled. In this way, the contact inspection can be performed more accurately by the contact inspection circuit 30 .

In some embodiments, the logic unit LU of the contact check circuit 20 or 30 may include one or more logic gates, such as an AND gate (AND), an OR gate (OR), an inverted gate (NOT), a mutual exclusion OR gate (XOR) or exclusive OR gate (XNOR), or any reasonable combination for the same purpose of outputting the check result signal S _CR . For example, when the configuration of the first comparator CMP1 of the contact inspection circuit 20 is modified so that its non-inverting terminal and inverting terminal respectively receive the first reference signal V _REF1 and the voltage detection signal _Sn , in order to output the inspection result signal For the same purpose of S _CR , the logic unit LU of the contact check circuit 20 can be changed to another logic circuit to implement the Boolean equation of (SC1'+SC2)' using reverse gate and exclusive OR gate (NOR) . The logic unit LU of the contact check circuit 30 can similarly be implemented in this way. In addition, the logic unit LU can also be modified in other ways. Therefore, the implementation of the present invention is not limited to these embodiments.

In some embodiments, the semiconductor device 1 can be configured to implement the contact inspection circuit 5 according to the contact inspection circuit 10, 20 or 30 shown in FIG. 2, 3 or 4, so that at least the first pad P1 and the second pad P2 are contact checked. In response to the test request signal of the semiconductor testing equipment 9, the semiconductor device 1 then outputs the inspection result signal S _CR to the semiconductor testing equipment 9 as a test result signal, or according to the inspection result signal S _CR and can be generated by the semiconductor device 1 output a test result signal based on one or more additional results obtained from the additional logic tests performed in the

Referring to FIG. 5 , an embodiment of a semiconductor device for the example architecture of FIG. 1 is depicted. In FIG. 5 , a semiconductor device 1A as an example of a semiconductor device 1 includes a plurality of pads, an internal circuit, and a contact inspection circuit 5 .

The pads include a first pad P1, a second pad P2, a data terminal DQ and a command terminal CMD. The internal circuit is coupled to the pads.

The internal circuit may include a decoder 510 and an electronic fuse unit 520 . The decoder 510 is coupled to the data terminal DQ, the command terminal CMD and the electronic fuse unit 520 . The electronic fuse unit 520 may include a plurality of electronic fuses. For example, at least one of these electronic fuses Two ends of one of them are coupled to the first pad P1 and the second pad P2. As shown in FIG. 5 , both the first pad P1 and the second pad P2 are coupled to the contact checking circuit 5 .

In response to a data signal and a command signal received from the data terminal DQ and the command terminal CMD, the decoder 510 can be implemented to perform different modes. For example, a test may be performed prior to the operation of blowing an electronic fuse. The semiconductor testing equipment 9 respectively generates a data signal, a command signal, a positive supply voltage and a negative supply voltage to the data terminal DQ, the command terminal CMD, the first pad P1 and the second pad P2. The data signal represents a specific code or address, and the command signal represents a test command for checking whether the semiconductor device 1A is ready for the electronic fuse blowing procedure. If the semiconductor device 1A is logically ready, the decoder 510 can generate a response code (for example: 110011001100) in response to the data signal and the command signal.

On the other hand, the contact checking circuit 5 depicted in FIG. 2 , FIG. 3 or FIG. 4 checks the contact connection between the first pad P1 and the second pad P2 to generate a check result signal S _CR , the check result signal _SCR is generated according to a comparison between a first test signal received from the first pad P1 and a second test signal received from the second pad P2 with at least one reference signal.

In one embodiment, the response code generated from the decoder 510 and the inspection result signal S _CR generated by the contact inspection circuit 5 can be sent back to the semiconductor testing equipment 9 .

In other embodiments, as shown in FIG. 6 , the semiconductor device 1A may further include an output logic unit 600 for generating a test result signal OUT according to the test result signal S _CR and the response code (for example, IN). For example, the output logic unit 600 may include a dedicated exclusive OR gate. If the response code IN is, for example, "110011001100" in binary, it indicates that the semiconductor device 1A is logically ready, and the check result signal S _CR (for example, logic 1) indicates that the contact connection is correct, and the test result signal OUT presents the same code as the response code IN. If the response code IN indicates that the semiconductor device 1A is logically ready, but the inspection result signal S _CR (for example, logic 0) indicates that the contact connection is incorrect, the test result signal OUT is represented as “001100110011” in binary. In other embodiments, the output logic unit 600 may include one or more logic gates, such as AND gate (AND), OR gate (OR), Inversion gate (NOT), exclusive OR gate (XOR) or mutual inversion XNOR, or any reasonable combination of the above.

In this way, the semiconductor testing equipment 9 can be implemented to terminate the test once it receives the test result signal OUT indicating that the contact connections are failed (for example: “001100110011”). In this way, the semiconductor device 1A using the contact inspection circuit 5 as shown in FIG. 2, FIG. 3 or FIG. Or even a blow operation (eg for electronic fuses).

As above, various embodiments of the semiconductor device with the contact inspection circuit have been provided. The semiconductor device includes a contact checking circuit. When the semiconductor device is tested using a semiconductor test equipment connected to the semiconductor device, for example, at least two pads, the contact checking circuit checks the contact connection of the at least two pads to generate A check result signal. The inspection result signal can be used to indicate whether the contact connection between the first pad and the second pad is invalid, and the semiconductor testing equipment can be configured to determine whether to continue the test according to the inspection result signal. Therefore, reliability for semiconductor device testing can be improved.

The present invention has been disclosed above with preferred embodiments, but those skilled in the art should understand that the embodiments are only used to describe the present invention, and should not be construed as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to the embodiment should be included in the scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the patent application.

1: Semiconductor device

2: Internal circuit

5: Contact check circuit

9: Semiconductor test equipment

P1: The first pad

P2: Second pad

PB: Probe

Claims (10)

A semiconductor device with a contact check circuit, comprising: a plurality of pads, including a first pad and a second pad; an internal circuit coupled to the pads; and a contact check circuit coupled to at least connected to the first pad and the second pad, and is used for inspecting a plurality of contact connections between the first pad and the second pad to generate an inspection result signal when the semiconductor device is tested, The inspection result signal is generated according to a comparison between a first test signal received from the first pad and a second test signal received from the second pad with at least one reference signal; wherein the contact inspection circuit includes : a voltage detection circuit, coupled to the first pad and the second pad and used to generate at least one voltage detection signal, the at least one voltage detection signal includes a first voltage detection signal and a first voltage detection signal Two voltage detection signals, the voltage detection circuit is configured to generate the first voltage detection signal according to the first test signal and a first power supply signal and generate the first voltage detection signal according to a second power supply signal and the second test signal a second voltage detection signal; and a comparison circuit coupled to the voltage detection circuit and used for generating the inspection result signal according to the at least one voltage detection signal and the at least one reference signal. The semiconductor device as claimed in claim 1, wherein the voltage detection circuit includes a voltage divider coupled between the first pad and the second pad to generate the at least one voltage detection signal. The semiconductor device according to claim 1, wherein the comparison circuit includes a comparator for generating the inspection result signal according to the at least one voltage detection signal and the at least one reference signal. The semiconductor device as described in Claim 1, wherein the at least one reference signal includes a first reference signal and a second reference signal, and the comparison circuit is configured to generate a voltage based on the at least one voltage detection signal and the first reference signal a first comparison signal; and the comparison circuit is configured to generate a second comparison signal based on the at least one voltage detection signal and the second reference signal; wherein the comparison circuit is configured to generate a second comparison signal based on the first comparison signal and the second comparison signal Generate the check result signal. The semiconductor device as described in claim 4, wherein the comparison circuit includes: a first comparator for generating the first comparison signal according to the at least one voltage detection signal and the first reference signal; a second comparator , for generating the second comparison signal according to the at least one voltage detection signal and the second reference signal; and a logic unit, coupled to the first comparator and the second comparator, and used for generating the second comparison signal according to the first The comparison signal and the second comparison signal generate the inspection result signal. The semiconductor device according to claim 1, wherein the voltage detection circuit includes: a first voltage divider, coupled between the first pad and a first power supply terminal, for generating the first voltage detection signal; and a second voltage divider coupled between a second power supply end and the second welding pad to generate the second voltage detection signal. The semiconductor device as described in claim 1, wherein the at least one reference signal includes a first reference signal and a second reference signal; the comparison circuit is configured to generate a voltage according to the first voltage detection signal and the first reference signal the first comparison signal; and The comparison circuit is configured to generate a second comparison signal according to the second voltage detection signal and the second reference signal; wherein the comparison circuit is configured to generate the inspection result signal according to the first comparison signal and the second comparison signal. The semiconductor device as described in claim 7, wherein the comparison circuit includes: a first comparator for generating the first comparison signal according to the first voltage detection signal and the first reference signal; a second comparator , for generating the second comparison signal according to the second voltage detection signal and the second reference signal; and a logic unit, for generating the inspection result signal according to the first comparison signal and the second comparison signal. The semiconductor device as claimed in claim 1, wherein the internal circuit includes an electronic fuse, and the electronic fuse is coupled between the first pad and the second pad. The semiconductor device as claimed in claim 1, wherein the semiconductor device further includes an output logic unit for generating a test result signal according to the inspection result signal and a response code.

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