TWI783121B - 半導體製程中之間隔物限定的直接圖案化方法 - Google Patents
半導體製程中之間隔物限定的直接圖案化方法 Download PDFInfo
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- TWI783121B TWI783121B TW108105641A TW108105641A TWI783121B TW I783121 B TWI783121 B TW I783121B TW 108105641 A TW108105641 A TW 108105641A TW 108105641 A TW108105641 A TW 108105641A TW I783121 B TWI783121 B TW I783121B
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Abstract
一種半導體製程中之間隔物限定的直接圖案化方法,包括:提供一具有線條的目標寬度之光阻結構;修整該等光阻結構,使得每個修整之光阻結構的寬度小於目標寬度;在該模板上沉積一氧化膜,從而以該氧化膜完全覆蓋模板暴露的上表面及修整之光阻結構;蝕刻該氧化膜覆蓋之模板,以移除氧化膜的不需要部分而不移除修整之光阻結構,以形成彼此隔離的垂直間隔物,每個間隔物大致保持目標寬度且由修整之光阻結構及覆蓋修整之光阻結構的側壁之氧化膜的一垂直部分構成;以及蝕刻該間隔物形式之模板,以將一由該等間隔物構成的圖案轉移至該模板。
Description
本發明大體上係有關於一種半導體製程中之圖案化方法,具體的是一種半導體製程中之間隔物限定的直接圖案化方法,其使用例如極紫外線(Extreme Ultra Violet,EUV)於微影術中。
為了對應於半導體裝置之小型化,進行用於微影術之光源的波長減小,例如,從ArF(氟化氬雷射)改變為EUV。迄今為止,由於如下所述之EUV微影衡的低生產率,半導體裝置的小型化已藉由使用間隔物限定的雙重圖案化(spacer-defined double patterning,SDDP)來實現。然而,由於有限的曝光準確度,SDDP的小型化存在限制,並且最近已出現實際使用EUV微影術的前景。於是,期望使用EUV微影術的直接圖案化將在未來的半導體製程中進行實際使用。
EUV微影術能夠進行圖案化,圖案尺寸為10至20nm(ArF雷射微影術中的最小尺寸約為40nm);然而,圖案化準確度為藉由線邊緣粗糙度(Line-Edge Roughness,LER)及線寬粗糙度(Line-Width Roughness,LWR)所評估之表面粗糙度,取決於構成光阻之聚合物的特性,因此,約5nm的表面粗糙度可能是下限且尚未被改善。因此,在用於微製程的精細佈線中,具有5nm寬之精細佈線的起伏或波紋係不可避免的且導致線間短路。本發明人進行研究,以改善半導體製程中的圖案化準確度。
關於相關技術之問題及解決方案的任何論述,僅為提供本發明之背景脈絡而包括於本揭示中,不應被視為同意該論述的任何或全部在本發明完成之際為已知。
在一些實施例中,藉由提供一具有以EUV微影術圖案化之光阻的模板;使用電漿增強型原子層沉積(plasma-enhanced atomic layer deposition,PEALD)設備進行該光阻的修整或蝕刻;以及以使得該預修整光阻的尺寸恢復之厚度在包括該修整光阻之該模板的暴露表面上沉積一SiO2
膜,以便覆蓋具有粗糙表面的該修整光阻,同時大致保持該光阻的原始尺寸,可以減少微製程的變化。
為了概述本發明之態樣及相對於相關技術所達成之優點,在本揭示中描述本發明之某些目的及優點。當然,應明瞭無須所有該等目的或優點皆可根據本發明之任何特定具體例來達成。因此,舉例而言,熟習此項技術者將認知到,可以如本文中所教示之達成或最佳化一個優點或一組優點而無須達成本文中可能教示或建議之其他目的或優點的方式來體現或實施本發明。
本發明之其他態樣、特徵及優點將由隨後之詳細描述而變得顯而易見。
在本揭示中,根據上下文,「氣體」可以包括汽化之固體及/或液體且可以由單一氣體或氣體混合物構成。同樣地,根據下文,冠詞「一」或「一個」意指一個物種或包括多個物種之種類。在本揭示中,經由噴灑頭(showerhead)引入至反應室之處理氣體可以由含矽前驅物及添加氣體構成、實質上由其組成或由其組成。添加氣體可以包括用於氮化及/或碳化前驅物之反應氣體及當向添加氣體施加RF功率時用於激發前驅物的惰性氣體(例如,稀有氣體)。惰性氣體可以作為載體氣體及/或稀釋氣體供給至反應室。再者,在一些實施例中,未使用反應氣體,而僅使用稀有氣體(作為載體氣體及/或稀釋氣體)。前驅物及添加氣體可以混合氣體方式或個別地引入至反應空間。前驅物可利用載體氣體(諸如稀有氣體或氮氣)來引入。除處理氣體外之氣體(亦即,沒有通過噴灑頭所引入之氣體)可用於例如密封反應空間,這種氣體包括諸如稀有氣體之密封氣體。在一些實施例中,術語「前驅物」一般意指參與產生另一個化合物之化學反應的化合物,及特別是意指構成膜基體或膜的主要架構之化合物,而術語「反應物」意指除前驅物外之化合物,其活化前驅物、改質前驅物或催化前驅物之反應,其中當施加RF功率時,反應物可向膜基體提供元素(諸如N、C)並成為膜基體之一部分。術語「惰性氣體」意指當施加RF功率時激發前驅物的氣體,但不同於反應物,其未成為膜基體之一部分。
在一些實施例中,「膜」意指在垂直於厚度方向之方向上連續延伸且實質上無小孔以覆蓋整個目標或有關表面的層,或僅僅係覆蓋目標或有關表面之層。在一些實施例中,「層」意指形成於表面上的具有特定厚度之結構或膜的同義詞或非膜結構。膜或層可由具有特定特性之離散單一膜或層或者多個膜或層構成,並且相鄰膜或層之間的邊界可以是或可以不是明顯的且可基於相鄰膜或層之物理、化學及/或任何其他特性、形成製程或順序及/或功能或用途而建立。再者,在本揭示中,變數之任何兩個數字可構成變數之可工作範圍,因為可工作範圍可根據例行工作來判定,並且所表示之任何範圍可以包括或不包括端點。此外,所表示的變數之任何數值(不管該等數值是否用「約」來表示)可以意指精確值或近似值且包括等效值,並且在一些實施例中可以意指平均值、中值、代表值、多數值等。再者,在本揭示中,一些實施例的術語「由……構成」及「具有」獨立地意指「通常或廣泛地包括」、「包括」、「實質上由……組成」或「由……組成」。在本揭示中,一些實施例中之任何定義的意思未必包括一般及慣用意思。
在未明確說明條件及/或結構之本揭示中,熟悉本技藝者有鑒於本揭示可按常規實驗輕易地提供這樣的條件及/或結構。
在所有所揭示實施例中,一個實施例中所使用之任何元件可由與之等效的任何元件替換,其包括為了預期目的之本文中明確地、必然地或固有地揭示之那些元件。再者,本發明同樣可適用於設備及方法。
實施例將就較佳實施例來進行說明。然而,本發明並非侷限於該等較佳實施例。
在一些實施例中,一種半導體製程中之間隔物限定的直接圖案化方法包括:(i)使用藉由微影術在一模板上形成的光阻結構,預先設定在該模板中待圖案化之線條的目標寬度;(ii)提供上面圖案化有該等光阻結構之該模板;(iii)修整該等光阻結構,使得每個修整之光阻結構的寬度小於該目標寬度;(iv)在該模板上沉積一氧化膜,從而以該氧化膜完全覆蓋該模板的暴露的上表面及該等修整之光阻結構;(v)蝕刻該氧化膜覆蓋之模板,以移除該氧化膜的不需要部分而不移除該等修整之光阻結構,以便形成彼此隔離的垂直間隔物,每個間隔物大致保持該目標寬度且由該等修整之光阻結構及覆蓋該等修整之光阻結構的側壁之該氧化膜的一垂直部分構成;以及(vi)蝕刻該間隔物形式之模板,以將一由該等間隔物構成的圖案轉移至該模板。
在一些實施例中,該目標寬度通常為5nm至30nm,較佳地為10nm至20nm。在一些實施例中,在步驟(iii)中,寬度方向上的修整量通常為每側1nm至5nm(亦即,在步驟(iii)中,該光阻結構的寬度減少2nm至10nm)。在一些實施例中,高度方向上的修整量亦是1nm至5nm,其大致等於寬度方向上的修整量,因為修整主要使用自由基來進行(然而,當在後面論述的步驟(iia)之前執行沉積薄氧化膜的步驟(iia)時,不僅使用自由基而且使用離子轟擊來進行修整)。在一些實施例中,在步驟(iii)之前可以在每個光阻結構的上表面上沉積SiO2
預塗層,以便可以主要在寬度方向上而不是在高度方向上進行修整。
在一些實施例中,步驟(ii)中之該等光阻結構具有與該目標寬度大致相同的寬度。在本揭示中,「大致相同」、「大致均勻」等可以意指熟悉技藝人士所認知之不重要的差異或差異,例如,取決於主題技術而定,在一些實施例中,小於30%,小於10%,小於5%或其任何範圍的那些差異(在一些實施例中,即使兩者之間的差異高達約50%,這兩者亦將被認為是大致相同的)。或者,在一些實施例中,步驟(ii)中之該等光阻結構的寬度實質上大於該目標寬度,因為光阻結構經受下面的修整處理。在揭示中,「實質上大於」、「實質上不同於」等可以意指熟悉技藝人士所認知之重要差異或差異,例如,取決於主題技術而定,在一些實施例中,至少1%、5%、10%、20%、30%、40%、50%、60%、70%、80%或其任何範圍之那些差異。
在一些實施例中,在步驟(iv)中所沉積之該氧化膜具有一厚度,使得每個氧化膜覆蓋之修整的光阻結構具有與該目標寬度大致相同的寬度,因為期望在步驟(v)(亦即,蝕刻步驟)期間大致保持該氧化膜覆蓋之修整的光阻結構之厚度。在一些實施例中,步驟(iv)中所沉積之該氧化膜具有一厚度,使得在步驟(v)(亦即,蝕刻步驟)期間稍微減少氧化膜覆蓋之修整的光阻結構之厚度的情況下,每個氧化膜覆蓋之修整的光阻結構之寬度稍微大於目標寬度(根據這個實施例,「稍微」可以意指小於10%的差異)。
在一些實施例中,在步驟(iv)中,該氧化膜係藉由電漿增強型原子層沉積(PEALD)所沉積之保形膜,因為氧化膜覆蓋之修整的光阻結構用作垂直間隔物。在一些實施例中,在步驟(iv)中,該氧化膜係藉由電漿增強型原子層沉積(PEALD)來沉積,其中控制壓力、溫度及/或RF功率,使得在每個修整之光阻結構的上表面上所沉積之該氧化膜的一部分具有比在每個修整之光阻結構的側壁上所沉積之該氧化膜的一部分高之乾蝕刻速率(例如,兩倍或更多倍),以致於在步驟(v)中,可以形成垂直間隔物同時大致保持該等修整之光阻結構的高度(例如,20nm至150nm,較佳地30nm至80nm)。
在一些實施例中,在步驟(iii)中修整每個光阻結構,以便將該光阻結構之每一側的寬度減少1nm至5nm。藉由減小該等光阻結構的寬度,可以改善圖案化線條的CD、LER及LWR。但是,如果該寬度的減少超過5nm,則CD、LER及LWR可能不再改善;更確切地說,他們開始變差。
在一些實施例中,該等光阻結構形成在該模板之一抗反射層上,並且在步驟(v)中,當移除該氧化膜的不需要部分時,亦移除在該氧化膜的不需要部分下面所形成之該抗反射層的一部分,使得該圖案化的抗反射層可以作為一光罩,以將該圖案轉移至該模板。在一些實施例中,該氧化物膜的不需要部分包括在光阻結構的上面所沉積之氧化膜的一部分以及在抗反射層的暴露表面上所沉積之氧化膜的一部分,亦即,氧化膜的水平延伸部分。在上文中,在一些實施例中,該光阻結構的上面所沉積之該氧化膜的部分具有化學抗性(例如,低的乾蝕刻速率),使得該部分在移除該抗反射層的暴露表面上所沉積之該氧化膜的部分及該抗反射層之前沒有完全被移除,從而防止在步驟(iv)中以該氧化膜覆蓋之該光阻結構的剝離。
在一些實施例中,在步驟(i)中,該預設目標寬度係在10nm至20nm的範圍內。在一些實施例中,步驟(ii)包括藉由使用EUV(極紫外線)光之微影術來形成該等光阻結構。因為藉由使用EUV微影術與其等效的其他微影術,該預設目標寬度可以小至10nm至20nm,所以可以有效地實現間隔物限定的直接圖案化。
在一些實施例中,該方法在步驟(iii)之前進一步包括(iia)藉由電漿增強型原子層沉積(PEALD)在該模板上沉積一具有約2nm或更小厚度之薄氧化膜,從而以該薄氧化膜完全覆蓋該模板的暴露的上表面及該等光阻結構。如後面所述,藉由進行步驟(iia),即使當該等光阻結構係稀疏排列的光阻結構及密集排列的光阻結構之混合時,亦可以有效地改善「負荷效應(loading effect)」,從而改善CD、LER及LWR。
在一些實施方案中,當進行步驟(iia)時,步驟(iii)中之修整藉由直接電漿蝕刻來進行。因為直接電漿不僅包含自由基而且包含離子,所以與遠程電漿不同,可以更有效地改善「負荷效應」。
在一些實施例中,步驟(iia)中之該薄氧化膜與步驟(iv)中之該氧化膜由相同的材料構成,並且除沉積過程的持續時間,亦即,膜的厚度外(通常,步驟(iia)中之該氧化膜的厚度為2nm或更小,而步驟(iv)中之該氧化膜的厚度大於2nm),在相同的條件下沉積,從而可以實現有效的操作。在一些實施例中,步驟(iia)中之該薄氧化膜及步驟(iv)中之該氧化膜獨立地由SiO2
、TiO、HfO或AlO構成,其可以在傳統條件下沉積,例如,美國專利第8,252,691及No.8,298,951號所揭露之那些傳統條件,在此以提及方式將所述美國專利的每個揭示全部併入本文。
在一些實施例中,步驟(ii)中之該等光阻結構由具有不同線距的稀疏排列及密集排列的光阻結構構成。
在一些實施例中,在步驟(iii)之前,該等光阻結構具有大於5nm的LER(線邊緣粗糙度)及大於3.5nm的LWR(線寬粗糙度)。LER及LWR的測量方法在業界係已知的(例如,J. S. Villarrubia and B. D. Bunday, “Unbiased Estimation of Linewidth Roughness”, Proc. of SPIE Vol 5752, 480 (2005),其揭示內容以提及方式全部併入本文)。
在一些實施例中,在步驟(iv)之前,該等修整的光阻結構具有小於5nm的LER及小於3.5nm的LWR。在一些實施例中,在步驟(v)之前,該等氧化膜覆蓋之修整的光阻結構具有4nm或更小的LER及3nm或更小的LWR。
雖然後面論述程序條件,但是一些實施例特徵在於:步驟(iii)中所使用之反應氣體不包含氧氣,步驟(ii)至(v)在150℃或更低的溫度下進行,及/或步驟(ii)至(iv)在同一個反應室中連續進行。
實施例將就圖式所述之實施例來進行說明。然而,本發明並非侷限於圖式所述的實施例。
圖4顯示使用先進間隔物限定的雙重圖案化(SDDP)之圖案轉移(步驟(a)至(f))的示意圖及使用間隔物限定的直接圖案化之圖案轉移(步驟(a')、(b')及(f'))的示意圖。
在先進SDDP中,另外進行步驟(b),以便降低光阻圖案的CD,因為使用ArF雷射微影術很難形成寬度為約20nm或更小的光阻圖案。在步驟(a)中,層狀結構係由通常藉由旋塗或CVD製程來製備之作為目標層的非晶碳層(αC)45(例如,其形成在基板(未顯示)上);沉積在其上作為蝕刻硬罩之氮化矽層(SiN)44;沉積在其上作為間隔物之非晶矽層(αSi)43;作為用於雙重圖案化之模板的非晶碳層(αC)48;沉積在其上之含矽抗反射塗層(silicon-containing anti-reflective coating,SiARC)42;沉積在其上之底部抗反射塗層(BARC)41(通常由有機材料製成);以及通常藉由ArF雷射微影術所形成之光阻圖案46(由例如東京JSR公司所製造之JSR3030、ARX 2014或ARX 1532JE或者其等效材料構成)構成。藉由ArF雷射微影術所形成之光阻圖案46具有例如45nm的寬度。
在先進SDDP製程中,執行步驟(b),以藉由乾蝕刻修整光阻46(使用例如O2
、N2
O、CO2
、H2
或Ar,或者前述任意兩種或更多種的混合物作為蝕刻氣體,其根據構成光阻的材料來選擇),進而藉由將其寬度從45nm減少至22.5nm來減小光阻圖案的CD,從而形成修整的光阻46'。在步驟(b)中還以光阻圖案修整BARC 41,以形成修整的BARC 41',步驟(b)係將圖案轉移至作為模板的αC 48之步驟。在步驟(c)中,藉由使用修整的光阻46'及修整的BARC 41',蝕刻SiARC 42及αC 48(例如對於矽使用:HBr、Cl2
、BCl3
、Ar、O2
、含氟氣體(氟碳化物、SF6
、NF3
);對於碳使用:O2
、N2
O、CO2
、H2
、Ar、H2
、含氟氣體(氟碳化合物、SF6
、NF3
)作為蝕刻氣體),以便將修整的光阻46'之圖案轉移至SiARC 42及αC 48,形成蝕刻的SiARC 42'及蝕刻的αC 48'。在此實施例中,使用BARC 41、SiARC 42及αC 48;然而,可以將這些層共同視為用作模板的抗反射層,其可以由單層或多層構成。
在步驟(d)中,在相對低的溫度下沉積金屬氧化層(LT-SiO2)47(由例如氧化矽構成),然後在步驟(e)中進行蝕刻,步驟(e)係間隔物RIE(反應離子蝕刻)步驟(使用例如HBr、Cl2
、BCl3
、Ar、O2
、含氟氣體(氟碳化合物、SF6
、NF3
)作為蝕刻氣體),以蝕刻金屬氧化層47,形成蝕刻的LT-SiO2 47’。藉由以灰化(ashing)使蝕刻的SiARC 42'及蝕刻的αC 48'之材料剝離,以在αSi 43上留下蝕刻的LT-SiO2 47'作為垂直隔離物84。因為金屬氧化隔離物(47')具有高的蝕刻選擇性,所以用於在其上形成隔離物之蝕刻的SiARC 42'及蝕刻的αC 48'(模板)可以是薄的,並且在蝕刻期間可以支撐金屬氧化隔離物(47')。在一些實施例中,抗反射層(由BARC 41、SiARC 42及αC 48共同構成)之厚度係約5至50 nm(通常是10至30 nm),而金屬氧化層(LT-SiO2 47)之厚度係約5至50 nm(通常是10至20 nm)。在步驟(f)中,藉由使用蝕刻的LT-SiO2 47',蝕刻αSi 43(使用例如HBr、Cl2
、BCl3
、Ar、O2
、含氟氣體(氟碳化合物、SF6
、NF3
)作為蝕刻氣體),以形成具有例如22.5nm的線寬之蝕刻的αSi 43',其可以作為第二模板。因此,根據先進SDDP,即使使用ArF雷射微影術,可以形成具有例如約22.5nm的線寬之模板。
然而,如上面關於圖4中之步驟(a)至(f)所論述,先進SDDP需要中間模板(例如,αC 48)以及包含額外蝕刻及沈積步驟的相關步驟(c)至(e)。相反地,在間隔物限定的直接圖案化中,如圖4之步驟(a')、(b')及(f')所示,可以完全去除額外步驟(c)至(e)及中間模板(例如,αC 48)。
在直接圖案化中,在步驟(a')中,藉由使用EUV微影術,在由層55、54、53、52及51所構成的層狀結構上形成具有例如約20nm的線寬之光阻圖案56,所述層55、54、53、52及51相當於或等同於非晶碳層(αC)45、氮化矽層(SiN)44、非晶矽層(αSi)43、含矽抗反射塗層(SiARC)42及底部抗反射塗層(BARC)41。在步驟(a')中,以步驟(a')中之光阻圖案修整BARC 51,因而形成修整的BARC 51',並且在步驟(f')中,藉由使用修整的BARC 51',蝕刻SiARC 52及αSi 53,以將步驟(b')中之光阻圖案轉移至αSi 53,因而形成具有例如20nm線寬之蝕刻的αSi 53'。於是,藉由使用EUV微影術,可以在不使用中間模板的情況下將線寬為10nm至20nm的光阻圖案直接轉移至模板。
然而,如先前所述,雖然EUV微影術能夠進行圖案化,圖案尺寸為10至20nm,但是圖案化準確度為藉由LER(線邊緣粗糙度)及LWR(線寬粗糙度)所評估之表面粗糙度,取決於構成光阻之聚合物的特性,因此,約5nm的表面粗糙度可能是下限且尚未被改善。
圖5顯示依據本發明的一個實施例之使用間隔物限定的直接圖案化之圖案轉移(步驟(a)至(e))的示意圖,其中可以有效地解決上述問題。
在依據此實施例的直接圖案化中,在步驟(a)中,藉由使用EUV微影術,在由層35、34、33、32及31所構成的層狀結構上形成具有例如約20nm(通常是10nm至20nm)的線寬之光阻圖案36,所述層35、34、33、32及31相當於或等同於圖4中之非晶碳層(αC)55、氮化矽層(SiN)54、非晶矽層(αSi)53、含矽抗反射塗層(SiARC)52及底部抗反射塗層(BARC)51。
當使用EUV微影術或其等同技術時,光阻圖案的線寬可以小至20nm或更小。然而,光阻圖案的LER(線邊緣粗糙度)及LWR(線寬度粗糙度)通常分別為大於3.5nm及大於5nm,其高於用於半導體裝置的微製程之期望的LER及LWR,期望的LER及LWR例如分別為3.5nm或更小(較佳地,3nm或更小)及5nm或更小(較佳地,4nm或更小)。在圖5的步驟(a)中,LER及LWR分別是例如3.87nm及5.26nm(參見後面所述的實例)。
依據此實施例,在圖5的步驟(b)中,修整光阻36,使得光阻36的寬度從20nm減小至10nm(通常是5nm至10nm),以形成修整的光阻36’。藉由此乾蝕刻製程,可以顯著地改善LER及LWR。例如,在步驟(b)中,LER及LWR分別從4.1nm及3.07nm減小至5.26nm及3.87nm。在一些實施例中,可以在下面表1所示的條件下進行修整。
在本揭示中,用於300-mm晶圓之任何表示的RF功率可以轉換成W/cm2
(每晶圓單位面積之瓦數),其可適用於具有不同直徑(諸如200 mm或450 mm)之晶圓。
依據此實施例,在步驟(c)中,藉由例如PEALD在相對低的溫度下在暴露的表面上沉積保形的金屬氧化層(LT-SiO2)37(由例如氧化矽構成),以補償修整的光阻36'的寬度之減少,以致於可以藉由具有5nm(通常為2nm至10nm)厚度之沉積的LT-SiO2 37,將由修整的光阻36'所構成之線條的寬度增加至或重建至例如20nm(通常為10nm至25nm,其可以大致相同於、厚於或薄於步驟(a)中之光阻的寬度)。因為LT-SiO2 37藉由PEALD等來沉積且具有高的保形性,所以它可以均勻厚度均勻地覆蓋修整的光阻36',以致於它可以在不降低其表面粗糙度的情況下增加線條的寬度。例如,由氧化物覆蓋之修整的光阻所構成之線條的LER及LWR分別為2.63nm及3.64nm。因為在圖5的步驟(e)中將線條圖案轉移至模板的同時期望保持LER及LWR,所以模板的線條可以具有期望的LER及LWR。
在一些實施例中,步驟(c)中之氧化膜由SiO2
、TiO、HfO或AlO構成,其可以在傳統條件下沉積,例如,美國專利第8,252,691及No.8,298,951號所揭露之那些傳統條件,在此以提及方式將所述美國專利的每個揭示全部併入本文。在一些實施例中,用於PEALD之前驅物係烷基胺基矽烷(alkylaminosilane)。在一些實施例中,烷基胺基矽烷係選自由下列所組成之群:雙-二乙基胺基矽烷(BDEAS)、雙-二甲基胺基矽烷(BDMAS)、己基乙基胺基矽烷(HEAD)、四乙基胺基矽烷(TEAS)、第三丁基胺基矽烷(TBAS)、雙-第三丁基胺基矽烷(BTBAS)、雙-二甲基胺基二甲基胺基矽烷(BDMADMS)、七甲基矽氮烷(HMDS)、三甲基矽烷基二乙胺(TMSDEA)、三甲基矽烷基二甲胺(TMSDMA)、三甲基三乙烯基環三矽氮烷(TMTVCTS)、三-三甲基羥基胺(TTMSHA)、雙-二甲基胺基甲基矽烷(BDMAMS)及二甲基矽烷基二甲胺(DMSDMA)。前驅物可以由單一前驅物或者兩個或更多前驅物之混合物構成。在一些實施例中,氧化膜具有80%至100%(通常約90%或更高)的保形性,其中「保形性」藉由比較在凹槽的側壁或底部上之某一點(通常為中間點)所沉積之膜厚與正好在凹槽外的平坦表面上所沉積之膜厚來判定。
在圖5的步驟(d)中,以步驟(c)中之光阻圖案修整BARC 31,因而形成修整的BARC 31',並且在步驟(e)中,藉由使用修整的BARC 31',蝕刻SiARC 32及αSi 33,以將步驟(c)中之光阻圖案轉移至αSi 33,因而形成具有例如20nm線寬之蝕刻的αSi 33'。依據此實施例,藉由使用EUV微影術,可以將線寬為10nm至20nm的光阻圖案直接轉移至模板,同時改善LER及LWR。在一些實施例中,在步驟(c)之後的步驟(d)中之蝕刻可以在下面表2所示的條件下進行。
在圖5的步驟(c)中,在一些實施例中,可以操縱金屬氧化層37的薄膜輪廓及薄膜品質,以便在步驟(d)及(e)中(亦即,在將光阻圖案轉移至模板時)實現期望的結果。例如,藉由以下面這樣的方式沉積金屬氧化膜37,即,沉積在修整的光阻36'之上表面上的膜選擇性地具有大於沉積在修整的光阻36'之側表面上的膜之厚度及/或具有高於沉積在修整的光阻36'之側表面上的膜之化學抗性(以乾蝕刻速率及/或濕蝕刻速率表示。),使得當BARC 31的乾或濕蝕刻在步驟(d)中進行時,可以保持氧化物覆蓋之修整的光阻之高度。例如,沉積在側表面上之膜的濕蝕刻速率係沉積在上表面上之膜的濕蝕刻速率之至少兩倍(例如,2至5倍)。可以依據在例如2016年2月19日所提出之美國序號第15/048,422號、2017年5月11日所提出之美國序號第15/592,730號及2017年7月14日所提出之美國序號第15/650,686號中所揭露之技術由與本申請案相同的申請人實現這種膜的厚度及品質的選擇性調整,在此以提及方式將其每個揭示內容全部併入本文。
在圖5的步驟(b)中,修整製程可以藉由傳統方法來進行。然而,因為光阻的修整速度主要由光阻周圍的自由基密度來控制,所以修整速度根據光阻圖案的密度(亦即,圖案是稀疏還是密集,其由例如線間之距離或間隔來定義)而變化。修整速度的變化取決於圖案的密度稱為「負荷效應」。因此,由於負荷效應,當光阻圖案由以不同間距或間隔排列的線條構成時,密集排列之線條的修整速度低於稀疏排列之線條的修整速度(較少的自由基進入窄的凹部(溝槽)而不是寬的凹部(溝槽)),導致線寬或CD的變化。
在本揭示中,將相鄰的光阻線條、垂直間隔物之間的凹槽及任何其他凹槽圖案稱為「線距」。在一些實施例中,圖案由具有從約10nm變化至約100nm(通常為約20nm至約50nm)之不同線距的線條構成。在這種情況下,出現「負荷效應」,導致線寬的化及LER/LWR的降低。
圖6顯示依據本發明的另一實施例之使用間隔物限定的直接圖案化之圖案轉移(步驟(a)至(e)及額外的步驟(a’))的示意圖,其中除步驟(a')外,步驟(a)至(e)等同於圖5所示之那些步驟。考慮到在傳統修整方法中的上述問題,在此實施例中,另外進行步驟(a'),其中藉由PEALD在相對低的溫度下以較小厚度(通常為0.5nm至5nm,例如,2nm或更小,更通常為1nm至2nm)沉積保形的薄金屬氧化層(LT-SiO2,其由例如氧化矽構成)38。藉由沉積接觸且覆蓋光阻36的暴露表面之薄氧化層38,當在步驟(b)中使氧化物覆蓋的光阻暴露於氧自由基時,因為薄氧化層覆蓋光阻表面,所以光阻的修整速度不是主要或直接受自由基密度控制,而是受氧自由基通過薄氧化層的擴散速度及/或對薄氧化層的離子轟擊所產生的活性氧(自由基)的數量之控制,從而減輕負載效應且改善整個圖案中線寬及線距的均勻性。薄氧化層的厚度可以根據光阻與氧化層之間的相容性或親和性等來判定。然而,當氧化層的厚度大於5nm時,自由基無法通過氧化層到達光阻表面,因此,不能有效地進行修整。當使薄氧化層暴露於氧自由基時,薄氧化物層當作緩衝層,並且氧自由基通過薄氧化層再生,以修整光阻,其中當修整進行時,光阻的寬度逐漸減小,同時保持薄氧化層附著至光阻,其中薄氧化層的厚度亦逐漸減小。在一些實施例中,在步驟(a’)之後的步驟(d)中之修整可以在下面表3所示的條件下進行。
應該注意,當藉由PEALD在光阻上沉積薄氧化層時,因為PEALD比熱ALD或自由基ALD(遠程電漿)產生更多的自由基且產生更多的離子轟擊,所以光阻表面在步驟(a’)中被修整至一定程度,但是在圖6的步驟(a')中沒有說明這種現象(電漿CVD可能不適合於沉積氧化層,因為它不適合於沉積保形層)。因此,光阻的寬度不僅在步驟(b)中減小,而且在步驟(a')中減小。藉由觀察光阻之橫截面的STEM照片或藉由測量步驟(a')中線寬的增加,可以看到或確認上述現象(在沉積時進行修整),上述增加比在相同條件下沉積相同層的情況(除這個層沉積在化學穩定的非光阻材料上外)下之線寬還低。當步驟(a')充當上述修整/沉積步驟時,可以使用基板溫度及電漿功率作為製程參數來控制光阻的修整量,其中當基板溫度較高(氧的反應性較高)及電漿功率較高(氧的反應性亦較高)時,修整量變得較高。
在一些實施例中,步驟(a')中所沉積的氧化層與步驟(c)中所沉積的氧化層相同或不同。在一些實施例中,在PEALD設備的相同反應室中連續地進行圖6中之步驟(a)至(c),然後,在蝕刻設備中連續地進行步驟(d)及(e)。在上文中,「連續地」意指沒有從同一個腔室移動基板、沒有顯著不同的介入步驟或沒有顯著不同的配方之介入步驟。在一些實施例中,步驟(b)中的修整通常藉由使用直接電漿(原位電漿蝕刻)來進行,或者,只要光阻可以直接暴露於電漿,它可以使用遠程等離子體等來進行。然而,相較於圖5中沒有步驟(a')的步驟(b)中之修整,當在圖6中的步驟(a')之後進行步驟(b)中之修整時,直接電漿係較佳的,因為相較於遠程電漿,直接電漿不僅包含自由基,而且還包含大量離子(步驟(b)緊接在步驟(a')的後面需要自由基及離子)。在一些實施例中,步驟(b)中之修整使用Ar/N2
電漿而不是O2
電漿來進行,因為Ar/N2
電漿蝕刻涉及緩慢的蝕刻速度,因此,更容易控制或操縱修整量。另一方面,在步驟(a')中(以及在一些實施例中,亦在步驟(c)中)之氧化層的沉積使用氧電漿來進行。
圖5中之步驟(b)至步驟(d)的製程順序及圖6中之步驟(a')至步驟(d)的製程順序可以在同一個反應室中連續地進行,其中每個步驟由一個特定配方來控制,並且在沒有從反應室輸送基板之情況下或在沒有使基板暴露於外部空氣之情況下,可以在不同配方之間進行清洗/氣體穩定步驟。這些製程可以使用任何合適的設備(例如,包括圖1所述的設備)來進行。圖1係PEALD設備的示意圖,其期望地結合可編程以進行下述程序之控制且可用於本發明的一些實施例。在此圖中,藉由在反應室3的內部11(反應區)中設置彼此平行且面對的一對導電平板電極4、2,施加HRF功率(13.56MHz或27MHz)20至一側及將另一側12電接地,在電極之間激發電漿。溫度調節器設置在下台(lower stage)2(下電極)中,並且放置在其上之基板1的溫度在一個給定溫度下保持恆定。上電極4亦充當噴灑板(shower plate),並且根據為每個步驟設定的給定配方,將反應氣體及/或稀釋氣體(如果有的話)以及前驅氣體及蝕刻氣體經由氣體管線21及氣體管線22(省略其它氣體管線)且經由噴灑板4分別引入反應室3中。此外,在反應室3中,設置具有排氣管線7之圓管13,經由所述排氣管線將反應室3之內部11中之氣體排出。另外,配置在反應室3下方之傳送室5具有密封氣體管線24,以經由傳送室5的內部16(傳送區)將密封氣體引入反應室3的內部11,其中設置用於使反應區與傳送區隔開之分隔板14(此圖省略閘閥,經由此閘閥將晶圓傳送至傳送室5或從傳送室5傳送晶圓)。傳送室亦具有排氣管線6。
在一些實施例中,步驟(e)(蝕刻步驟)可以在包括傳統設備的任何蝕刻設備中進行。根據構成待移除層的材料,亦即,根據其對例如HF、HCl及TMAH濕蝕刻;例如BCl₃,BCl₃/Ar乾蝕刻;或者例如氧化、濕蝕刻化學交替氧化與HF的組合(常見於半導體製程中)或以例如氧或CF4
為基礎的乾蝕刻之抗性或敏感性,選擇蝕刻條件,並且據此進行蝕刻。
熟悉技術者應理解,設備包括一個或多個控制器(未顯示),其可經編程或另外構造成進行本文中別處所描述之沉積及反應器清潔製程。如熟悉技藝人士所理解,該(等)控制器係與各種電源、加熱系統、泵、機器人及反應器的氣體流量控制器或閥連接。
在一些實施例中,可使用雙腔室反應器(用於處理彼此緊密地安置之晶圓的兩個區域或隔室),其中反應氣體及稀有氣體可經由共用管線來供應,而前驅氣體經由非共用管線來供應。
本發明將就下面工作實例來進一步說明。然而,所述實例沒有意欲限制本發明。在未明確說明條件及/或結構之實例中,熟悉本技藝者有鑒於本揭示可按常規實驗輕易地提供這樣的條件及/或結構。此外,在一些實施例中,特定實例中所應用之數字可在至少±50%之範圍內進行修改,並且這些數字係近似的。
實例
實例
1
在下面表4所示之條件下使用圖1A所示的PEALD設備對在300mm基板的SiOC層上所形成且具有約35nm的初始CD之光阻圖案(由例如設計用於EUV微影術之Novolacs構成)進行修整。
圖3係顯示光阻之CD(「PR CD」)與修整的處理時間(「處理時間」)之間的關係之曲線圖。確認光阻的CD隨著修整的處理時間成線性地降低至少達到CD低至約20nm的程度。
實例
2
縱使EUV微影術具有比ArF雷射還高的曝光準確度,很難將光阻圖案的CD(臨界尺寸)降低到低至12nm或更低的程度。在此實例中,除光阻的初始CD為約17.9nm外,以大致相似於實例1之方式對光阻進行修整。圖2顯示在沒有修整的EUV微影術之後(「在微影術之後」)、在修整0.5秒(「0.5s」)之後、在修整1.0秒(「1s」)之後、在修整1.5秒(「1.5s」)之後及在修整2.0秒(「2s」)之後的圖案化表面之STEM照片,其中下面照片(b)以比上面照片(a)更高的放大倍數來拍攝。
從圖2可以看出,隨著光阻圖案的修整之進行,光阻圖案的CD從約17.9nm(沒有修整)、約16nm(修整0.5秒)、約15.1nm(修整1秒)、約14.5nm(修整1.5秒)及約12.3nm(修整2秒)開始減少。然而,亦可以從圖2看出,隨著修整的進行,線條區域與非線條區域之間的對比變低,亦即,開始出現線條中斷。確認很難將光阻圖案的CD減少至約12nm或更低。
實例
3
在此實例中,在下面表5所示的條件下以相似於實例1之方式對光阻(具有約7.90nm(平均值)的初始CD之ArF光阻)進行修整。
然後,藉由PEALD對修整的光阻圖案進行SiO2
沉積,其在下面表6所示的條件下進行。
圖7顯示藉由微影術(在(a)中之「在微影術之後」)及在氧化矽膜的沉積(在(b)中的「PEALD-SIO2間隔物沉積」)之後所形成的光阻之圖案化線條的STEM照片,其中「3σ」代表平均值的3個標準偏差。在此實例中,雖然如圖7之(a)所示,光阻圖案的初始CD約為38nm(平均值),而如圖7之(b)所示,氧化物覆蓋之修整的光阻之CD約為29nm(平均值),但是氧化物覆蓋之修整的光阻圖案之寬度被認為與初始光阻的寬度大致相同(因為修整的光阻圖案之寬度約為9nm,而氧化物的覆蓋之修整的光阻圖案之寬度約為29nm,這相對於38nm的寬度被認為是實質尺寸恢復。如圖7所示,相較於初始光阻圖案,氧化物覆蓋之修整的光阻圖案顯示出對LWR及LER的顯著改善。
實例
4
在此實例中,除光阻的初始CD為約44.5nm,修整進行9秒以及氧化物覆蓋之修整的光阻之CD恢復至約62.8nm外,以大致相似於實例3之方式對光阻進行修整,接著進行氧化物沉積。雖然光阻圖案的初始CD約為45nm,而氧化物覆蓋之修整的光阻之CD約為63nm。但是氧化物覆蓋之修整的光阻圖案之寬度被認為與初始光阻的寬度大致相同(因為修整的光阻圖案之寬度約為28nm,而氧化物的覆蓋之修整的光阻圖案之寬度約為63nm,這相對於約45nm的寬度被認為是實質尺寸恢復。
圖8顯示藉由微影術(「在微影術之後」)、在修整9秒之後(「在9秒修整之後」)及在氧化膜的沉積之後(「在間隔物沉積之後」)所形成的光阻之圖案化線條的STEM照片。圖8亦顯示其CD、LWR及LER。如圖8所示,相較於初始光阻圖案,氧化物覆蓋之修整的光阻圖案顯示出對LWR及LER的顯著改善。
實例
5
在此實例中,除如圖9所示改變修整時間外,以大致相似於實例4之方式對光阻進行修整。圖9係顯示光阻的LER及LWR(「LER/LWR」)與修整的處理時間(「修整時間」)之間的關係之曲線圖,其中「POR」意指「參考點」。如圖9所示,當增加修整時間,修整的光阻圖案顯示出對LWR和LER的顯著改善,直到達到一個穩定水準為止。圖10係顯示與圖9所示之測量點對應的CD之表。如圖10所示,CD亦藉由增加修整的處理時間而減少。
實例
6
在此實施例中,除膜厚為約2nm外,藉由PEALD以大致相似於實例3之方式對光阻(具有約11nm的初始CD之EUV光阻)進行SiO沉積,,然後,除如圖12所示改變修整時間外,以大致相似於實例1之方式進行修整。圖11顯示藉由微影術(在(a)中的「初始」)及在上面藉由ALD沉積SiO層(在(b)中的「SiO ALD(~2nm)」)之後所形成的光阻之圖案化線條的剖面圖之STEM照片。圖12顯示在圖11之(b)所示藉由ALD沉積SiO層(在(b)中的「SiO ALD(~2nm)」)之後、在修整圖案化線條10秒(在(c)中的「ALD+修整(10s)」)之後、在修整圖案化線條15秒(在(d)中的「ALD+修整(15s)」)之後及在修整圖案化線條20秒(在(e)中的「ALD+修整(20s)」)之後的圖案化線條之剖面圖的STEM照片。圖13係顯示當如圖12所示改變修整時間時圖案化線條的高度及CD(nm)之變化的曲線圖。
如圖11所示,在包括其側壁及底部區域的光阻圖案上均勻地沉積保形的SiO薄膜(具有約2nm的厚度)。如圖12所示,確認可以在實質上沒有降低間隔物(圖案化的光阻)的高度之情況下進行修整。這似乎是因為SiO薄膜可以充當活性物種的來源,例如,當暴露於電漿時,氧自由基被產生且供應至光阻的下表面,以進行蝕刻。亦即,SiO薄膜可以藉由減輕由電漿之離子轟擊所造成的撞擊來顯著地保護光阻,從而抑制光阻的頂部及底部區域的主要蝕刻,並且可以相當均勻地將活性物種釋放至光阻表面,以進行蝕刻,藉此蝕刻側壁區域比光阻的頂部及底部區域更多,因為側壁區域比頂部及底部區域的化學抗性低得多(例如,側壁層的緻密性較低且具有比頂部及底部層高兩倍或更高的WER,其亦可以代表DER)。基於相同的理由,可以改善負荷效應(亦即,無論光阻圖案具有窄間隔或寬間隔,皆可以進行均勻蝕刻),從而降低光阻圖案的CD而不降低圖案的高度。然而,如圖13所示,當修整時間超過20秒時,圖案的高度傾向於開始減小。
實例
7
在此實施例中,以大致相似於實例6之方式,藉由PEALD對光阻(具有約11nm的初始CD之EUV光阻)進行SiO沉積,接著進行修整。圖14係顯示當改變修整時間時圖案化線條的高度、寬度(nm)及LWR(nm)之變化的曲線圖。圖15顯示在對應於圖14之「初始」的(a)中藉由ALD沉積SiO層之前、在對應於圖14之「沉積」的(b)中藉由ALD沉積SiO層之後、在對應於圖14之「沉積+修整(10s)」的(c)中修整圖案化線條10秒之後及在對應於圖14之「沉積+修整(15s)」的(d)中修整圖案化線條15秒之後的圖案化線條之剖面圖的STEM照片。如圖14所示,結果與實例6所示的結果相似。此外,如圖14所示,藉由沉積SiO薄膜來改善LWR,並且在修整間隔物(圖案化的光阻)的同時保持對LWR的改善。
預示實例
1
根據圖6所示的順序,首先,製備具有光阻圖案(EUV光阻)36的基板,其具有圖6之(a)所示的層狀結構。接下來,如圖6之(a')所示,以大致相似於實例3所示之方式,在低溫下對光阻圖案進行SiO薄膜38的沉積(可以調整沉積時間等)。如圖6之(b)所示,接著以大致相似於實例1所示之方式對氧化物覆蓋之光阻圖案進行修整(可以調整修整時間等),以獲得具有窄寬度而不降低高度的光阻圖案36'。之後,如圖6之(c)所示,以大致相似於實例3所示之方式對修整的光阻圖案進行SiO沉積(可以調整沉積時間等),以便用SiO膜37(稱為「間隔物」)覆蓋修整的光阻,使得間隔物37的寬度與初始光阻36的寬度大致相同。接下來,如圖6之(d)所示,在下面表7所示之條件下,使用間隔物作為蝕刻光罩,使間隔物36經受模板蝕刻(非等向性蝕刻),以蝕刻BARC層31。然後,如圖6之(e)所示,使用由間隔物37'及蝕刻的BARC 31'所構成的蝕刻光罩,在下面表8所示之條件下進一步對模板進行非等向性蝕刻,以便將蝕刻光罩圖案轉移至αSi層33,以獲得圖案化的αSi層33'。
結果,可以獲得具有大致相同於初始光阻圖案36的CD且顯著改善(降低)LWR及LER之圖案化的αSi 33',此確認可成功地執行如圖4之(a')、(b’)及(f’)所示的直接圖案化。
預示實例
2
根據圖5所示的順序,除省略預示實例1的步驟(a')外,以大致相似於預示實例1之方式將光阻圖案(EUV光阻)36轉移至模板的αSi層33。
結果,可以獲得具有大致相同於初始光阻圖案36的CD且顯著改善(降低)LWR及LER之圖案化的αSi33',此確認可成功地執行如圖4之(a')、(b’)及(f’)所示的直接圖案化。
熟悉技藝人士將理解在不脫離本發明之精神下可實施許多不同的修飾。因此,應該清楚理解本發明之形式僅為說明性而不是意欲限制本發明之範圍。
1‧‧‧基板
2‧‧‧導電平板電極
3‧‧‧反應室
4‧‧‧導電平板電極
5‧‧‧傳送室
6‧‧‧排氣管線
7‧‧‧排氣管線
11‧‧‧反應室
12‧‧‧電接地
13‧‧‧圓管
14‧‧‧分隔板
16‧‧‧傳送室
20‧‧‧功率
21‧‧‧氣體管線
22‧‧‧氣體管線
24‧‧‧密封氣體管線
31‧‧‧底部抗反射塗層(BARC)
31'‧‧‧修整的BARC
32‧‧‧含矽抗反射塗層(SiARC)
33‧‧‧非晶矽層(αSi)
33'‧‧‧蝕刻的αSi
34‧‧‧氮化矽層(SiN)
35‧‧‧非晶碳層(αC)
36‧‧‧光阻
36'‧‧‧修整的光阻
37‧‧‧金屬氧化層
37'‧‧‧間隔物
38‧‧‧薄金屬氧化層
41‧‧‧底部抗反射塗層(BARC)
41'‧‧‧修整的BARC
42‧‧‧含矽抗反射塗層(SiARC)
42'‧‧‧蝕刻的SiARC
43‧‧‧非晶矽層(αSi)
43'‧‧‧蝕刻的αSi
44‧‧‧氮化矽層(SiN)
45‧‧‧非晶碳層(αC)
46‧‧‧光阻圖案
46'‧‧‧修整的光阻
47‧‧‧金屬氧化層(LT-SiO2)
47'‧‧‧蝕刻的LT-SiO2
48‧‧‧非晶碳層(αC)
48'‧‧‧蝕刻的αC
51‧‧‧底部抗反射塗層(BARC)
51'‧‧‧修整的BARC
52‧‧‧含矽抗反射塗層(SiARC)
53‧‧‧非晶矽層(αSi)
53'‧‧‧蝕刻的αSi
54‧‧‧氮化矽層
55‧‧‧非晶碳層(αC)
56‧‧‧光阻圖案
現在將參考意欲說明而非限制本發明之較佳實施例的圖式來描述本發明之這些及其他特徵。該等圖式經大大簡化以用於說明性目的且未必按比例繪製。
[圖1A]係用以沉積可用於本發明之一個實施例中的介電膜之電漿增強型原子層沉積(PEALD)設備的示意圖。
[圖1B]說明使用可用於本發明之一個實施例中的流通系統(flow-pass system,FPS)之前驅物供應系統的示意圖。
[圖2]顯示在沒有修整的EUV微影術之後(「在微影術之後」)、在修整0.5秒(「0.5s」)之後、在修整1.0秒(「1s」)之後、在修整1.5秒(「1.5s」)之後及在修整2.0秒(「2s」)之後的圖案化表面之STEM照片,其中下面照片(b)以比上面照片(a)更高的放大倍數來拍攝。
[圖3]係顯示依據本發明之一個實施例的光阻之CD(「PR CD」)與修整的處理時間(「處理時間」)之間的關係之曲線圖。
[圖4]顯示使用間隔物限定的雙重圖案化(SDDP)之圖案轉移(步驟(a)至(f))的示意圖及使用間隔物限定的直接圖案化之圖案轉移(步驟(a')、(b')及(f'))的示意圖。
[圖5]顯示依據本發明的一個實施例之使用間隔物限定的直接圖案化之圖案轉移(步驟(a)至(e))的示意圖。
[圖6]顯示依據本發明的另一實施例之使用間隔物限定的直接圖案化之圖案轉移(步驟(a)至(e)及額外的步驟(a’))的示意圖。
[圖7]顯示依據本發明的一個實施例之藉由微影術(在(a)中之「在微影術之後」)及在氧化膜的沉積(在(b)中的「PEALD-SIO2間隔物沉積」)之後所形成的光阻之圖案化線條的STEM照片。
[圖8]顯示依據本發明的一個實施例之藉由微影術(「在微影術之後」)、在修整9秒之後(「在9秒修整之後」)及在氧化膜的沉積之後(「在間隔物沉積之後」)所形成的光阻之圖案化線條的STEM照片。圖8亦顯示其CD、LWR及LER。
[圖9]係顯示依據本發明的一個實施例之光阻的LER及LWR(「LER/LWR」)與修整的處理時間(「修整時間」)之間的關係之曲線圖。
[圖10]係顯示與圖9所示之測量點對應的CD之表。
[圖11]顯示依據本發明的一個實施例之藉由微影術(在(a)中的「初始」)及在上面藉由ALD沉積SiO層(在(b)中的「SiO ALD(~2nm)」)之後所形成的光阻之圖案化線條的剖面圖之STEM照片。
[圖12]顯示依據本發明的一個實施例之在圖11之(b)所示藉由ALD沉積SiO層(在(b)中的「SiO ALD(~2nm)」)之後、在修整圖案化線條10秒(在(c)中的「ALD+修整(10s)」)之後、在修整圖案化線條15秒(在(d)中的「ALD +修整(15s)」)之後及在修整圖案化線條20秒(在(e)中的「ALD+修整(20s)」)之後的圖案化線條之剖面圖的STEM照片。
[圖13]係顯示當依據圖12所示之實施例改變修整時間時圖案化線條的高度及CD(nm)之變化的曲線圖。
[圖14]係顯示當依據本發明之一個實施例改變修整時間時圖案化線條的高度、寬度(nm)及LWR(nm)之變化的曲線圖。
[圖15]顯示在對應於圖14之「初始」的(a)中藉由ALD沉積SiO層之前、在對應於圖14之「沉積」的(b)中藉由ALD沉積SiO層之後、在對應於圖14之「沉積+修整(10s)」的(c)中修整圖案化線條10秒之後及在對應於圖14之「沉積+修整(15s)」的(d)中修整圖案化線條15秒之後的圖案化線條之剖面圖的STEM照片。
1‧‧‧基板
2‧‧‧導電平板電極
3‧‧‧反應室
4‧‧‧導電平板電極
5‧‧‧傳送室
6‧‧‧排氣管線
7‧‧‧排氣管線
11‧‧‧反應室
12‧‧‧電接地
13‧‧‧圓管
14‧‧‧分隔板
16‧‧‧傳送室
20‧‧‧功率
21‧‧‧氣體管線
22‧‧‧氣體管線
24‧‧‧密封氣體管線
Claims (20)
- 一種半導體製程中之間隔物限定的直接圖案化方法,其包括以下步驟:(i)使用藉由微影術在一模板上形成的光阻結構,預先設定在該模板中待圖案化之線條的目標寬度;(ii)提供上面圖案化有該等光阻結構之該模板;(iii)修整該等光阻結構,使得每個修整之光阻結構的寬度小於該目標寬度;(iv)在該模板上沉積一氧化膜,從而以該氧化膜完全覆蓋該模板的暴露的上表面及該等修整之光阻結構;(v)蝕刻該氧化膜覆蓋之模板,以移除該氧化膜的不需要部分而不移除該等修整之光阻結構,以便在該模板上形成彼此隔離的垂直間隔物,該模板稱為間隔物形式之模板,每個垂直間隔物大致保持該目標寬度且由該等修整之光阻結構及覆蓋該等修整之光阻結構的側壁之該氧化膜的一垂直部分構成;以及(vi)蝕刻該間隔物形式之模板,以將一由該等垂直間隔物全體構成的圖案轉移至該模板以形成具有該目標寬度之線條。
- 如請求項1之方法,其中步驟(ii)中之該等光阻結構具有與該目標寬度大致相同的寬度。
- 如請求項1之方法,其中在步驟(iv)中所沉積之該氧化膜具有一厚度,使得每個氧化膜覆蓋之修整的光阻結構具有與該目標寬度大致相同的寬度。
- 如請求項1之方法,其中在步驟(iv)中,該氧化膜係藉由電漿增強型原子層沉積(PEALD)所沉積之保形膜。
- 如請求項1之方法,其中在步驟(iv)中,該氧化膜係藉由電漿增強型原子層沉積(PEALD)來沉積,其中控制壓力、溫度及/或RF功率,使得在 每個修整之光阻結構的上表面上所沉積之該氧化膜的一部分具有比在每個修整之光阻結構的側壁上所沉積之該氧化膜的一部分高之乾蝕刻速率。
- 如請求項1之方法,其中在步驟(iii)中修整每個光阻結構,以便將該光阻結構之每一側的寬度減少1nm至5nm。
- 如請求項1之方法,其中該等光阻結構形成在該模板的一抗反射層上,並且在步驟(v)中,當移除該氧化膜的不需要部分時,亦移除在該氧化膜的不需要部分下面所形成之該抗反射層的一部分。
- 如請求項1之方法,其中在步驟(i)中,該目標寬度係預設在10nm至20nm的範圍內。
- 如請求項1之方法,其中步驟(ii)包括藉由使用EUV(極紫外線)光之微影術來形成該等光阻結構。
- 如請求項1之方法,其在步驟(iii)之前進一步包括以下步驟:(iia)藉由電漿增強型原子層沉積(PEALD)在該模板上沉積一具有約2nm或更小厚度之薄氧化膜,從而以該薄氧化膜完全覆蓋該模板的暴露的上表面及該等光阻結構。
- 如請求項10之方法,其中步驟(iii)中之修整藉由直接電漿蝕刻來進行。
- 如請求項10之方法,其中步驟(iia)中之該薄氧化膜及步驟(iv)中之該氧化膜由相同的材料構成。
- 如請求項10之方法,其中步驟(ii)中之該等光阻結構由具有不同線距的稀疏排列及密集排列的光阻結構構成。
- 如請求項10之方法,其中步驟(iia)中之該薄氧化膜由SiO2、TiO、HfO或AlO構成。
- 如請求項1之方法,其中在步驟(iii)之前,該等光阻結構具有 大於3.5nm的線邊緣粗糙度(LER)及大於5nm的線寬粗糙度(LWR)。
- 如請求項15之方法,其中在步驟(iv)之前,該等修整的光阻結構具有小於3.5nm的LER及小於5nm的LWR。
- 如請求項16之方法,其中在步驟(v)之前,該等氧化膜覆蓋之修整的光阻結構具有3nm或更小的LER及4nm或更小的LWR。
- 如請求項1之方法,其中在步驟(iii)中所使用之反應氣體不包含氧氣。
- 如請求項1之方法,其中步驟(ii)至(v)在150℃或更低的溫度下進行。
- 如請求項1之方法,其中步驟(ii)至(iv)在同一個反應室中連續進行。
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KR20190100035A (ko) | 2019-08-28 |
TW201937575A (zh) | 2019-09-16 |
US10658181B2 (en) | 2020-05-19 |
US20190259612A1 (en) | 2019-08-22 |
CN110176392A (zh) | 2019-08-27 |
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