TWI776937B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI776937B
TWI776937B TW107128363A TW107128363A TWI776937B TW I776937 B TWI776937 B TW I776937B TW 107128363 A TW107128363 A TW 107128363A TW 107128363 A TW107128363 A TW 107128363A TW I776937 B TWI776937 B TW I776937B
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gate structure
channel
semiconductor device
protruding portion
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TW107128363A
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TW201916361A (zh
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宋昇珉
朴雨錫
梁正吉
裵金鐘
裵東一
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南韓商三星電子股份有限公司
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Abstract

本揭露提供半導體裝置。一種半導體裝置包括基底及在 所述基底上的閘極結構。所述半導體裝置包括在所述基底上的通道。所述半導體裝置包括在所述通道上的源極/汲極層。此外，所述半導體裝置包括在所述閘極結構的側壁上的間隔件。所述間隔件包括在垂直方向上與所述通道交疊的中心部分以及從所述中心部分突出的突出部分。本揭露的半導體裝置可具有良好的電特性。

Description

半導體裝置
本發明是有關於一種半導體裝置。
[相關申請的交叉參考]
本申請主張在2017年9月28日在韓國知識產權局(Korean Intellectual Property Office，KIPO)提出申請的韓國專利申請第10-2017-0126077號的優先權，所述韓國專利申請的內容全文併入本申請供參考。
在形成多路橋接型通道金屬氧化物半導體場效應電晶體(multi-bridge-channel MOSFET，MBCFET)時，可形成鰭結構，可在鰭結構上形成虛設閘極結構及覆蓋虛設閘極結構的側壁的閘極間隔件，且可使用虛設閘極結構及閘極間隔件作為蝕刻掩模來對鰭結構進行蝕刻。在形成與閘極結構相鄰的源極/汲極層之後，可通過閘極結構來替換虛設閘極結構。如果閘極結構與源極/汲極層未彼此電絕緣，則在閘極結構與源極/汲極之間可能發生電短路。
本發明的示例性實施例提供一種電特性良好的半導體裝置。
本發明的示例性實施例提供一種製造電特性良好的半導體裝置的方法。
根據示例性實施例，提供一種半導體裝置。所述半導體裝置可包括基底。所述半導體裝置可包括在所述基底的上表面上在垂直方向上彼此間隔開的多個通道。所述半導體裝置可包括在所述通道上的閘極結構。所述半導體裝置可包括在所述閘極結構的側壁上的第一間隔件。所述第一間隔件可包括在所述垂直方向上與所述通道交疊的中心部分。所述第一間隔件可包括從所述中心部分突出的突出部分。所述突出部分在所述垂直方向上可不與所述通道交疊。此外，所述半導體裝置可包括在所述通道的側壁上的源極/汲極層。
根據各種實施例，一種半導體裝置可包括基底。所述半導體裝置可包括在所述基底上的閘極結構。所述半導體裝置可包括延伸穿過所述閘極結構的通道。所述半導體裝置可包括在所述通道上的源極/汲極層。此外，所述半導體裝置可包括第一間隔件，所述第一間隔件在所述閘極結構的側壁上且將所述閘極結構與所述源極/汲極層電絕緣。所述第一間隔件可包括在垂直方向上與所述通道交疊的中心部分。所述第一間隔件可包括從所述中心部分突出的突出部分。所述突出部分在所述垂直方向上可不與所述通道交疊。
根據各種實施例，一種半導體裝置可包括基底。所述半導體裝置可包括在所述基底上的源極/汲極層。所述半導體裝置可包括在所述源極/汲極層的第一側的第一閘極結構。所述半導體裝置可包括延伸穿過所述第一閘極結構且連接到所述源極/汲極層的第一通道。此外，所述半導體裝置可包括在所述第一閘極結構的與所述源極/汲極層面對的側壁上的第一間隔件。所述第一間隔件可將所述第一閘極結構與所述源極/汲極層電絕緣。所述第一間隔件可包括在與所述基底的上表面實質上垂直的垂直方向上不與所述第一通道交疊的第一突出部分。
根據各種實施例，一種製造半導體裝置的方法可包括在基底上形成鰭結構。所述鰭結構可包括交替地且重複地堆疊的犧牲線與半導體線。所述方法可包括在所述鰭結構及所述基底上形成虛設閘極結構。所述虛設閘極結構可包括依序堆疊的虛設閘極絕緣圖案與虛設閘極電極。所述方法可包括使用所述虛設閘極結構作為蝕刻掩模來對所述鰭結構進行蝕刻以暴露出所述基底的上表面。所述方法可包括對所述犧牲線的側壁進行蝕刻以形成第一凹槽。所述方法可包括對所述虛設閘極絕緣圖案的被所述第一凹槽暴露出的部分進行蝕刻以形成第二凹槽。所述方法可包括在所述第一凹槽及所述第二凹槽中形成第一間隔件。所述方法可包括在所述基底的所述上表面上形成源極/汲極層。此外，所述方法可包括利用閘極結構替換所述虛設閘極結構。
根據各種實施例，一種製造半導體裝置的方法可包括在 基底上形成鰭結構。所述鰭結構可在第一方向上延伸。所述方法可包括在所述鰭結構及所述基底上形成虛設閘極結構。所述虛設閘極結構可包括虛設閘極絕緣圖案與虛設閘極電極，所述虛設閘極絕緣圖案與所述虛設閘極電極依序堆疊並在與所述第一方向實質上垂直的第二方向上延伸。所述虛設閘極絕緣圖案的突出部分在與所述基底的上表面實質上垂直的垂直第三方向上可不與所述虛設閘極電極交疊。所述方法可包括在所述虛設閘極結構的側壁上形成第二間隔件。所述方法可包括使用所述虛設閘極結構及所述第二間隔件作為蝕刻掩模來對所述鰭結構進行蝕刻以暴露出所述基底的所述上表面。所述方法可包括對所述虛設閘極結構的一部分進行蝕刻以形成第一凹槽。所述方法可包括對所述虛設閘極絕緣圖案的所述突出部分進行蝕刻以形成第二凹槽。所述方法可包括在所述第一凹槽及所述第二凹槽中形成第一間隔件。所述方法可包括在所述基底的所述上表面上形成源極/汲極層。所述方法可包括利用閘極結構替換所述虛設閘極結構。
在根據示例性實施例的半導體裝置中，位於閘極結構的側壁上(例如，覆蓋閘極結構的側壁)的MBCFET的間隔件結構可包括不與所述通道垂直交疊的突出(即，突出的)部分，且因此可改善/確保閘極結構與源極/汲極層之間的電隔離。
100:基底
105:主動區
110:犧牲層
112:犧牲線
114:犧牲圖案
120:半導體層
122:半導體線
124:半導體圖案
130:隔離圖案
145:虛設閘極絕緣圖案
145a、220:突出部分
155:虛設閘極電極
165:虛設閘極掩模
175:虛設閘極結構
185:第二間隔件
190:第一開口
195:第一凹槽
200:第二凹槽
210:中心部分
230:第一間隔件
240:外延層
250:絕緣層
260:第二開口
270:界面圖案
280:閘極絕緣圖案
290:功函數控制圖案
300:閘極電極
310:閘極結構
A-A'、B-B'、C-C'、D-D':線
X:區域
圖1是示出根據示例性實施例的半導體裝置的平面圖。圖2是示出半導體裝置的放大的水平剖視圖。圖3至圖5是示出半導體裝置的垂直剖視圖。
圖6至圖32包括示出根據示例性實施例的製造半導體裝置的方法的平面圖及剖視圖。具體來說，圖6、圖8、圖10、圖15、圖19、圖22、圖24、圖27及圖29是平面圖，圖7、圖9、圖12至圖14、圖17、圖18、圖21、圖26、圖28、圖31及圖32是垂直剖視圖，且圖11、圖16、圖20、圖23、圖25及圖30是放大的水平剖視圖。
圖33至圖37是示出根據示例性實施例的半導體裝置的剖視圖。
圖1至圖5是示出根據示例性實施例的半導體裝置的平面圖及剖視圖。圖1是平面圖，圖2是水平剖視圖，且圖3至圖5是垂直剖視圖。
圖3是沿圖1所示線A-A'截取的剖視圖，圖4是沿圖1所示線B-B'截取的剖視圖，且圖5是沿圖1所示線C-C'截取的剖視圖。圖2是圖1所示區域X的水平剖視圖，其可沿圖3至圖5所示線D-D'截取。
在下文中，可將與基底100的上表面實質上平行且彼此交叉的兩個方向分別稱為第一方向與第二方向，且可將與基底100 的上表面實質上垂直的方向稱為第三方向。在示例性實施例中，第一方向與第三方向可實質上彼此垂直。
參照圖1至圖5，所述半導體裝置可包括位於基底100上的半導體圖案124、閘極結構310、外延層240及第一間隔件230。半導體裝置還可包括主動區105、隔離圖案130、第二間隔件185及絕緣層250。
基底100可包含以下材料：半導體材料，例如矽、鍺、矽鍺等；或III-V族半導體化合物，例如磷化鎵(GaP)、砷化鎵(GaAs)、銻化鎵(GaSb)等。在一些實施例中，基底100可為絕緣體上矽(silicon-on-insulator，SOI)基底或絕緣體上鍺(germanium-on-insulator，GOI)基底。
主動區105可在第三方向上從基底100突出，且可在第一方向上延伸。在所附圖式中示出兩個主動區105。然而，本發明概念並非僅限於此。因此，多於兩個主動區105可在第二方向上彼此間隔開。每一個主動區105均可通過部分地移除基底100的上部部分來形成，且因此可包含與基底100的材料實質上相同的材料。
主動區105的側壁可被隔離圖案130覆蓋。隔離圖案130可包含氧化物，例如氧化矽。
相對於主動區105的上表面，多個半導體圖案124可分別形成在多個水平高度處以在第三方向上彼此間隔開。在所附圖式中，示出分別處於三個水平高度的半導體圖案124。然而，本發 明概念並非僅限於此。
在所附圖式中，在沿第一方向延伸的主動區105上的每一水平高度上僅示出在第一方向上彼此間隔開的兩個半導體圖案124。然而，本發明概念並非僅限於此。因此，可將多於兩個半導體圖案124形成為在主動區105上的每一水平高度處在第一方向上彼此間隔開。
在示例性實施例中，半導體圖案124可為包含半導體材料(例如，矽、鍺等)的納米片或納米線。在示例性實施例中，半導體圖案124可用作電晶體的通道，所述電晶體的通道可被稱為通道。
外延層240可在第三方向上從主動區105的上表面延伸，且可共同地接觸處於所述多個水平高度上的各自半導體圖案124的側壁以連接到半導體圖案124。外延層240可接觸第一間隔件230的外側壁以及第二間隔件185的下部外側壁。如圖4所示，第一間隔件230的側壁和/或第二間隔件185的側壁可包括位於閘極結構310與外延層240之間的傾斜(例如，彎曲的/斜的)部分。此可由於在位於閘極結構310之前的虛設結構的傾斜部分上形成第一間隔件230和/或第二間隔件185而引起。
在示例性實施例中，外延層240可包含摻雜有n型雜質的單晶矽碳化物或摻雜有n型雜質的單晶矽，且因此可用作NMOS電晶體的源極/汲極層。作為另外一種選擇，外延層240可包含摻雜有p型雜質的單晶矽鍺，且因此可用作PMOS電晶體的源極/汲 極層。外延層240可被稱為源極/汲極層。
閘極結構310可形成在基底100上，且可在第一方向上環繞半導體圖案124的中心部分。在所附圖式中，閘極結構310被示出為覆蓋兩個主動區105上的半導體圖案124。然而，本發明概念並非僅限於此。也就是說，閘極結構310可在第二方向上延伸，且可覆蓋在第二方向上彼此間隔開的多於兩個主動區105上的半導體圖案124或者覆蓋僅一個主動區105上的半導體圖案124。
在所附圖式中，在基底100上示出兩個閘極結構310。然而，本發明概念並非僅限於此。因此，可在基底100上形成在第一方向上彼此間隔開的多於兩個閘極結構310。
閘極結構310可包括從半導體圖案124中的每一者的表面或主動區105的上表面依序堆疊的界面圖案270、閘極絕緣圖案280、功函數控制圖案290及閘極電極300。
界面圖案270可形成在主動區105的上表面以及半導體圖案124的表面上，且閘極絕緣圖案280可形成在界面圖案270的表面上以及第一間隔件230的內側壁及第二間隔件185的內側壁上。功函數控制圖案290可形成在閘極絕緣圖案280上，且閘極電極300可填充在第三方向上彼此間隔開的各個半導體圖案124之間的空間以及在各個半導體圖案124中最上一個半導體圖案124上由第二間隔件185的內側界定的空間。
界面圖案270可包含氧化物(例如，氧化矽)，且閘極絕 緣圖案280可包含具有高k介電常數(high-k dielectric constant)的金屬氧化物(例如，氧化鉿、氧化鉭、氧化鋯等)。
功函數控制圖案290可包含例如氮化鈦、氮氧化鈦、碳氮氧化鈦、氮化鈦矽、氮氧化鈦矽、氮氧化鈦鋁、氮化鉭、氮氧化鉭、氮化鉭鋁、氮氧化鉭鋁、氮化鎢、碳氮化鎢、氧化鋁等。閘極電極300可包含金屬(例如，鈦、鋁等)、金屬合金或金屬的氮化物或碳化物。
閘極結構310可與用作源極/汲極層的外延層240和用作通道的半導體圖案124一起形成電晶體。電晶體可根據在外延層240中摻雜的雜質的導電類型而為NMOS電晶體或PMOS電晶體。電晶體可包括在第三方向上依序堆疊的所述多個半導體圖案124，且因此可為MBCFET。
第一間隔件230可覆蓋閘極結構310的在第一方向上相對的兩個側壁中的每一者的下部部分，且第二間隔件185可覆蓋閘極結構310的在第一方向上相對的兩個側壁中的每一者的上部部分。第一間隔件230及第二間隔件可被稱為間隔件結構。
具體來說，第一間隔件230可形成在處於多個水平高度處的半導體圖案124之間或者形成在主動區105的上表面與半導體圖案124中的最下一個半導體圖案124之間，且第二間隔件185可形成在半導體圖案124中所述最上一個半導體圖案124上以覆蓋閘極結構310的側壁的上部部分。因此，閘極結構310可通過第一間隔件230及第二間隔件185而與外延層240電絕緣。
在示例性實施例中，第一間隔件230可包括在第三方向上與半導體圖案124交疊的中心部分210以及在第二方向上從中心部分210突出的突出部分220。也就是說，第一間隔件230的中心部分210可在各個半導體圖案124之間延伸或者在主動區105的上表面與半導體圖案124中的最下一個半導體圖案124之間延伸，且第一間隔件230的突出部分220可在第二方向上從中心部分210的相對兩端中的每一端突出而不在第三方向上與半導體圖案124交疊。在示例性實施例中，第一間隔件230的中心部分210的相對兩端處的突出部分220可具有彼此對稱的形狀。此外，如圖2所示，在一些實施例中，兩個第一間隔件230各自的水平橫截面可相對於經過所述兩個第一間隔件230之間的外延(例如，源極/汲極)層240的中心(即，中間)點在第二方向上延伸的軸線對稱。
在示例性實施例中，第一間隔件230的突出部分220的端部可接觸外延層240。因此，如果在第一間隔件230處未形成突出部分，則所述空間可被閘極結構310填充，且閘極結構310與外延層240可彼此接觸。然而，在示例性實施例中，第一間隔件230可包括突出部分220，且因此閘極結構310與外延層240可不彼此直接接觸，且可獲得閘極結構310與外延層240之間的電絕緣。這種特徵可在隨後參照圖6至圖32所示出的製造半導體裝置的方法中加以解釋。
在示例性實施例中，第一間隔件230可在第三方向上至 少部分地與上覆的第二間隔件185交疊。在所附圖式中，第一間隔件230的中心部分210的外側壁在第三方向上不與第二間隔件185的外側壁對準，且第一間隔件230的中心部分210的內側壁在第三方向上不與第二間隔件185的內側壁對準。然而，本發明概念並非僅限於此。
在一些示例性實施例中，第一間隔件230的內側壁在第三方向上可與半導體圖案124中最上一個半導體圖案124上的閘極結構310的一部分交疊，且因此位於半導體圖案124中最上一個半導體圖案124下方的閘極結構310的一部分在第一方向上的寬度可小於位於半導體圖案124中最上一個半導體圖案124上的閘極結構310的一部分的寬度。然而，本發明概念並非僅限於此。也就是說，位於半導體圖案124中最上一個半導體圖案124下方的閘極結構310的所述一部分在第一方向上的寬度也可等於或大於位於半導體圖案124中最上一個半導體圖案124上的閘極結構310的所述一部分的寬度。
第一間隔件230可包含氮化物(例如，氮化矽、碳氮化矽、氮化矽硼、碳氮氧化矽等)，且第二間隔件185可包含氮化物(例如，氮化矽)。
絕緣層250可環繞第二間隔件185的側壁以覆蓋外延層240。絕緣層250可包含氧化物(例如，氧化矽)。
所述半導體裝置還可包括電連接到外延層240和/或閘極結構310的接觸塞、配線等。
如上所述，在所述半導體裝置中，閘極結構310和與閘極結構310相鄰的外延層240可通過第一間隔件230及第二間隔件185而彼此電絕緣。具體來說，第一間隔件230可包括在第三方向上不與半導體圖案124交疊的突出部分220，且因此可確保閘極結構310與外延層240之間的電絕緣。舉例來說，在垂直剖視圖中，突出部分220與半導體圖案124在第三方向上可不交疊。
圖6至圖32是示出根據示例性實施例的製造半導體裝置的方法的平面圖及剖視圖。圖6、圖8、圖10、圖15、圖19、圖22、圖24、圖27及圖29是平面圖，圖7、圖9、圖12至圖14、圖17至圖18、圖21、圖26、圖28以及圖31至圖32是垂直剖視圖，且圖11、圖16、圖20、圖23、圖25及圖30是水平剖視圖。
圖7、圖9及圖12是沿對應的平面圖的線A-A'截取的剖視圖，圖13、圖17、圖21、圖26、圖28及圖31是沿對應的平面圖的線B-B'截取的剖視圖，且圖14、圖18及圖32是沿對應的平面圖的線C-C'截取的剖視圖。圖11、圖16、圖20、圖23、圖25及圖30是對應的平面圖的區域X的水平剖視圖，其可沿對應的平面圖的線D-D'截取。
參照圖6及圖7，可在基底100上交替地堆疊犧牲層110與半導體層120。
在所附圖式中示出將在基底100上形成三個犧牲層110及三個半導體層120。然而，本發明概念並非僅限於此。
犧牲層110可包含對基底100及半導體層120具有蝕刻 選擇性的材料，基底100及半導體層120可包含例如矽鍺。
參照圖8及圖9，可在半導體層120中最上一個半導體層120上將硬掩模形成為在第一方向上延伸，且可使用硬掩模作為蝕刻掩模來對半導體層120、犧牲層110及基底100的上部部分進行蝕刻。
因此，可在基底100上將主動區105形成為在第一方向上延伸，且可在主動區105上形成鰭結構，所述鰭結構包括交替地及重複地堆疊的犧牲線112與半導體線122。在示例性實施例中，可在基底100上將多個鰭結構形成為在第二方向上彼此間隔開。
在移除硬掩模之後，可在基底100上形成隔離圖案130以覆蓋主動區105的側壁。
參照圖10至圖14，可在基底100上形成虛設閘極結構175以部分地覆蓋鰭結構及隔離圖案130。
具體來說，可在上面具有鰭結構及隔離圖案130的基底100上依序形成虛設閘極絕緣層、虛設閘極電極層及虛設閘極掩模層，可在虛設閘極掩模層上形成光刻膠圖案，且可使用光刻膠圖案作為蝕刻掩模來對虛設閘極掩模層進行蝕刻以形成虛設閘極掩模165。
虛設閘極絕緣層可包含氧化物(例如，氧化矽)，虛設閘極電極層可包含例如多晶矽，且虛設閘極掩模層可包含氮化物(例如，氮化矽)。
可使用虛設閘極掩模165作為蝕刻掩模來對虛設閘極電極層及虛設閘極絕緣層進行蝕刻，以分別形成虛設閘極電極155及虛設閘極絕緣圖案145。
依序堆疊在主動區105以及隔離圖案130的與主動區105相鄰的一部分上的虛設閘極絕緣圖案145、虛設閘極電極155及虛設閘極掩模165可形成虛設閘極結構175。在示例性實施例中，虛設閘極結構175可在第二方向上延伸以覆蓋鰭結構的上表面及鰭結構在第二方向上的相對的兩個側壁以及隔離圖案130的在第二方向上與鰭結構相鄰的一部分。
在示例性實施例中，虛設閘極結構175的與鰭結構的表面及隔離圖案130的上表面接觸的部分可具有不與鰭結構的表面或隔離圖案130的上表面垂直的側壁，而是相對於鰭結構的表面或隔離圖案130的上表面傾斜的側壁。也就是說，在用於形成虛設閘極結構175的蝕刻製程期間，位於虛設閘極電極層下方且與鰭結構的表面或隔離圖案130的上表面接觸的虛設閘極絕緣層可因蝕刻氣體的量的差异或材料的差异而無法被容易地蝕刻，且因此可相對於鰭結構的表面或隔離圖案130的上表面具有傾斜的側壁。
在示例性實施例中，可在鰭結構的在第二方向上的相對的兩個側壁中的每一者上形成虛設閘極絕緣圖案145的在第三方向上不與上覆的虛設閘極電極155交疊的一部分，所述一部分可被稱為虛設閘極絕緣圖案145的突出部分145a。
參照圖15至圖18，可在虛設閘極結構175的側壁上形成第二間隔件185。
具體來說，可在上面具有鰭結構、隔離圖案130及虛設閘極結構175的基底100上形成第二間隔件層，且可對第二間隔件層進行各向异性蝕刻以形成覆蓋虛設閘極結構175的在第一方向上相對的兩個側壁中的每一者的第二間隔件185。
可使用虛設閘極結構175及第二間隔件185作為蝕刻掩模來對鰭結構進行蝕刻以暴露出基底100的主動區105的上表面。
因此，可將位於虛設閘極結構175及第二間隔件185下方的閘極線112及半導體線122分別轉換成犧牲圖案114及半導體圖案124，且可將鰭結構劃分成在第一方向上彼此間隔開的多個部分。在示例性實施例中，半導體圖案124中的每一者可用作電晶體的通道。
在下文中，可將虛設閘極結構175、位於虛設閘極結構175的相對的兩個側壁中的每一者上的第二間隔件185以及位於虛設閘極結構175及第二間隔件185下方的鰭結構稱為第一結構。在示例性實施例中，第一結構可在第二方向上延伸，且可將多個第一結構形成為在第一方向上彼此間隔開。在各個第一結構之間可形成第一開口190以暴露出主動區105及隔離圖案130。
在示例性實施例中，虛設閘極絕緣圖案145的突出部分145a可被第二間隔件185覆蓋。
參照圖19至圖21，可分別對被第一開口190暴露出的犧 牲圖案114的在第一方向上相對的兩個側壁進行蝕刻以形成第一凹槽195。
在示例性實施例中，可在犧牲圖案114上通過濕蝕刻製程來形成第一凹槽195。作為另外一種選擇，可在犧牲圖案114上通過乾蝕刻製程來形成第一凹槽195。
在示例性實施例中，由於形成了第一凹槽195，因此可暴露出虛設閘極絕緣圖案145的在第二方向上從犧牲圖案114的在第一方向上相對的兩端中的每一端突出的突出部分145a。在一些示例性實施例中，由於形成了第一凹槽195，因此犧牲圖案114在第一方向上的寬度可小於上覆的虛設閘極結構175的寬度。然而，本發明概念並非僅限於此。也就是說，如果通過形成第一凹槽可只暴露出虛設閘極絕緣圖案145的突出部分，則第一凹槽195中的每一者的深度可不受限制，且因此犧牲圖案114在第一方向上的寬度可等於或大於上覆的虛設閘極結構175的寬度。
參照圖22及圖23，可將虛設閘極絕緣圖案145的被第一凹槽195暴露出的突出部分145a移除以形成第二凹槽200。
在示例性實施例中，可在虛設閘極絕緣圖案145上通過濕蝕刻製程來形成第二凹槽200。作為另外一種選擇，可在虛設閘極絕緣圖案145上通過乾蝕刻製程來形成第二凹槽200。
在示例性實施例中，在蝕刻製程期間，不僅可將虛設閘極絕緣圖案145的被第一凹槽195暴露出的突出部分145a移除，而且還可將虛設閘極絕緣圖案145的與突出部分145a相鄰的部分 (即，虛設閘極絕緣圖案145的在第三方向上與上覆的虛設閘極電極155交疊的部分)移除。
參照圖24至圖26，可形成第一間隔件230來填充第一凹槽195及第二凹槽200。
可通過在虛設閘極結構175、第二間隔件185、鰭結構、基底100的主動區105及隔離圖案130上形成第一間隔件層以填充第一凹槽195及第二凹槽200以及對第一間隔件層進行各向异性蝕刻來形成第一間隔件230。可通過沉積製程(例如，化學氣相沉積(chemical vapor deposition，CVD)製程、原子層沉積(atomic layer deposition，ALD)製程等)來形成第一間隔件層。
在示例性實施例中，第一間隔件230可包括填充第一凹槽195的中心部分210以及填充第二凹槽200的突出部分220。也就是說，第一間隔件230的突出部分220可在第二方向上從中心部分210在第二方向上的相對的兩端中的每一端突出，且位於中心部分的相對的兩端處的突出部分220可彼此對稱。
在示例性實施例中，第一間隔件230可在第三方向上至少部分地與上覆的第二間隔件185交疊。在所附圖式中，第一間隔件230的中心部分210的外側壁在第三方向上不與第二間隔件185的外側壁對準。然而，本發明概念並非僅限於此。
參照圖27及圖28，可在基底100的主動區105的被第一開口190暴露出的上表面上形成外延層240。
在示例性實施例中，可使用主動區105的被第一開口190 暴露出的上表面作為晶種通過選擇性外延生長(selective epitaxial growth，SEG)製程來形成外延層240。
在示例性實施例中，可使用例如二矽烷(Si2H6)等矽源氣體以及例如SiH3CH3等碳源氣體來執行SEG製程以形成單晶碳化矽(SiC)層。在一些示例性實施例中，可僅使用例如二矽烷(Si2H6)等矽源氣體來執行SEG製程以形成單晶矽層。外延層240可用作NMOS電晶體的源極/汲極層。
作為另外一種選擇，可使用例如二氯矽烷(SiH2Cl2)等矽源氣體以及例如鍺烷(GeH4)等鍺源氣體來執行SEG製程以形成單晶矽鍺(silicon germanium，SiGe)層。外延層240可用作PMOS電晶體的源極/汲極層。
在示例性實施例中，外延層240可形成在第一結構的在第一方向上的相對的兩個側壁中的每一側壁上。在示例性實施例中，外延層240可接觸鰭結構的半導體圖案124的側壁以及覆蓋犧牲圖案114的側壁的第一間隔件230的外側壁，且還在第三方向上生長以接觸第二間隔件185的側壁。
在一些實施例中，外延層240可通過雷射外延生長(laser epitaxial growth，LEG)製程或固相外延(solid phase epitaxy，SPE)製程形成。
外延層240可用作電晶體的源極/汲極層。還可對外延層240執行雜質摻雜製程及熱處理製程。舉例來說，當外延層240包含碳化矽或矽時，可向外延層240中摻雜n型雜質且可執行熱 處理。當外延層240包含矽鍺時，可向外延層240中摻雜p型雜質且可執行熱處理。
參照圖29至圖32，可在基底100上形成絕緣層250以覆蓋第一結構及外延層240，且可對絕緣層250進行平坦化直到可暴露出第一結構的虛設閘極電極155的上表面為止。在平坦化製程期間，也可移除虛設閘極掩模165，且可移除第二間隔件185的上部部分。
平坦化製程可通過化學機械拋光(chemical mechanical polishing，CMP)製程和/或回蝕製程(etch back process)來執行。
暴露出的虛設閘極電極155及虛設閘極絕緣圖案145可通過例如濕蝕刻製程和/或乾蝕刻製程被移除以形成第二開口260，第二開口260暴露出第二間隔件185的內側壁、第一間隔件230的內側壁、半導體圖案124的表面及主動區105的上表面。
在示例性實施例中，虛設閘極絕緣圖案145的突出部分145a已被移除從而被包含不同材料的第一間隔件230的突出部分220替換，且因此第一間隔件230的突出部分220在蝕刻製程中可不被移除。因此，外延層240可不被第二開口260暴露出。
再次參照圖1至圖5，可在基底100上形成閘極結構310以填充第二開口260。
具體來說，在對由第二開口260暴露出的主動區105的上表面及半導體圖案124的表面執行熱氧化製程以形成界面圖案270之後，可在界面圖案270的表面、第一間隔件230的內側壁及 第二間隔件185的內側壁以及絕緣層250的上表面上依序形成閘極絕緣層及功函數控制層，且可形成閘極電極層以填充第二開口260的其餘部分。
閘極絕緣層、功函數控制層及閘極電極層可通過例如CVD製程、ALD製程、物理氣相沉積(physical vapor deposition，PVD)製程等形成。也可使用CVD製程、ALD製程、PVD製程等代替熱氧化製程來形成界面圖案270，且在這種情形中，界面圖案270也可形成在第一間隔件230的內側壁上及第二間隔件185的內側壁上。
可對閘極電極層、功函數控制層及閘極絕緣層進行平坦化直到可暴露出絕緣層250的上表面為止，以分別形成閘極電極300、功函數控制圖案290及閘極絕緣圖案280。界面圖案270、閘極絕緣圖案280、功函數控制圖案290及閘極電極300可形成閘極結構310。
在示例性實施例中，閘極結構310可通過包括突出部分220的第一間隔件230及第二間隔件185而與外延層240電絕緣，且因此在閘極結構310與外延層240之間可不發生電短路。
圖33至圖37是示出根據示例性實施例的半導體裝置的剖視圖。圖33、圖35及圖36是圖1所示區域X的水平剖視圖，其可沿圖3至圖5所示線D-D，截取，且圖34及圖37是沿圖1所示線B-B'截取的垂直剖視圖。
除了第一間隔件之外，這些半導體裝置可與圖1所示半 導體裝置實質上相同。因此，相同的參考編號指代相同的元件，且在本文中可省略對這些元件的重複的詳細說明。
參照圖33及圖34，不同於圖1至圖5所示，第一間隔件230的中心部分210的內側壁可在第三方向上與第二間隔件185的內側壁對準。因此，位於半導體圖案124中最上一個半導體圖案124下方的閘極結構310的所述一部分在第一方向上的寬度可實質上等於位於半導體圖案124中最上一個半導體圖案124上/上方的閘極結構310的所述一部分的寬度。
參照圖35，第一間隔件230的突出部分220可具有比圖34及圖35所示第一間隔件230的突出部分220的面積小的面積。
參照圖36及圖37，不同於圖1至圖5所示，第一間隔件230的中心部分210的外側壁可在第三方向上與第二間隔件185的外側壁對準。因此，第一間隔件230的厚度可等於或大於第二間隔件185的厚度。
上述主題將被視為說明性的而非約束性的，且隨附申請專利範圍旨在涵蓋落於真實的精神及範圍內的所有這種修改形式、改進形式及其他實施例。因此，就法律所允許的最大程度而言，所述範圍將由以上申請專利範圍及其等效形式所許可的最廣範圍的解釋來確定，且不應受以上詳細說明的約束或限制。
185:第二間隔件
210:中心部分
220:突出部分
230:第一間隔件
240:外延層
250:絕緣層
280:閘極絕緣圖案
290:功函數控制圖案
300:閘極電極
X:區域

Claims (18)

  1. 一種半導體裝置，包括：基底；多個通道，在所述基底的上表面上在垂直方向上彼此間隔開，所述通道中的每一者在實質上平行於所述基底的所述上表面的第一方向上延伸；閘極結構，在所述通道上；第一間隔件，在所述閘極結構的側壁上，所述第一間隔件包括：中心部分，在所述垂直方向上與所述通道交疊；以及突出部分，從所述中心部分突出，所述突出部分在所述垂直方向上不與所述通道交疊，其中所述中心部分在第二方向上較所述突出部分長，所述第二方向實質上平行於所述基底的所述上表面且實質上垂直於所述第一方向；以及源極/汲極層，在所述通道的側壁上，其中所述閘極結構和所述源極/汲極層在所述第一方向上彼此間隔開來，其中所述第一間隔件的所述突出部分在所述第二方向上自所述第一間隔件的所述中心部分突出，且其中所述第一間隔件的所述中心部分在所述第一方向上較所述第一間隔件的所述突出部分長。
  2. 如申請專利範圍第1項所述的半導體裝置， 其中所述第一間隔件的所述突出部分包括第一突出部分與第二突出部分，所述第一突出部分與所述第二突出部分在所述第二方向上分別從所述第一間隔件的所述中心部分的相對的第一端與第二端突出，其中所述第一突出部分與所述第二突出部分在所述第二方向上彼此間隔開來，且其中所述第一突出部分與所述第二突出部分在所述第一間隔件的所述中心部分的相對的所述第一端與所述第二端處彼此對稱。
  3. 如申請專利範圍第1項所述的半導體裝置，其中所述源極/汲極層通過所述第一間隔件來與所述閘極結構電絕緣，且其中，在平面視圖中，所述第一間隔件的所述突出部分的面積小於所述第一間隔件的所述中心部分的面積的一半。
  4. 如申請專利範圍第1項所述的半導體裝置，其中所述第一間隔件在所述閘極結構的下部部分的相對側壁上，其中所述半導體裝置更包括第二間隔件，所述第二間隔件在所述閘極結構的上部部分的相對側壁上，且其中所述閘極結構通過所述第一間隔件及所述第二間隔件來與所述源極/汲極層電絕緣。
  5. 如申請專利範圍第4項所述的半導體裝置，其中所述第一間隔件與所述第二間隔件在所述垂直方向上至少部分地彼此交疊。
  6. 如申請專利範圍第4項所述的半導體裝置，其中所述閘極結構的所述下部部分在所述第一方向上的第一寬度比所述閘極結構的所述上部部分在所述第一方向上的第二寬度窄。
  7. 如申請專利範圍第1項所述的半導體裝置，其中所述第一間隔件包括在所述垂直方向上彼此間隔開的多個第一間隔件。
  8. 一種半導體裝置，包括：基底；閘極結構，在所述基底上，所述閘極結構包括依序地在垂直方向上堆疊的下部部分和上部部分；通道，延伸穿過所述閘極結構，所述閘極結構的所述下部部分位在實質上相同於或低於所述通道的底表面的高度的高度處；源極/汲極層，在所述通道上；以及第一間隔件，在所述閘極結構的所述下部部分的側壁上且將所述閘極結構與所述源極/汲極層電絕緣，所述第一間隔件與所述閘極結構的所述上部部分在所述垂直方向上至少部分地交疊，所述第一間隔件包括：中心部分，在垂直方向上與所述通道交疊；以及突出部分，從所述中心部分突出，所述突出部分在所述垂直方向上不與所述通道交疊， 其中所述中心部分與所述突出部分皆接觸所述閘極結構的所述側壁。
  9. 如申請專利範圍第8項所述的半導體裝置，其中所述通道包括在所述垂直方向上彼此間隔開的多個通道，且其中所述第一間隔件在所述多個通道之間，且在所述基底與所述多個通道中最靠近所述基底的一個通道之間。
  10. 如申請專利範圍第8項所述的半導體裝置，其中所述閘極結構在第二方向上延伸，且所述通道在第一方向上延伸，所述第二方向與所述基底的上表面實質上平行，所述第一方向與所述基底的所述上表面實質上平行且與所述第二方向實質上垂直。
  11. 如申請專利範圍第10項所述的半導體裝置，其中所述通道在所述第一方向上的寬度比所述閘極結構在所述第一方向上的寬度寬。
  12. 如申請專利範圍第10項所述的半導體裝置，其中所述源極/汲極層接觸所述通道的相對側壁及所述第一間隔件的外側壁。
  13. 如申請專利範圍第10項所述的半導體裝置，其中所述第一間隔件在所述閘極結構的下部部分的相對側壁上，其中所述半導體裝置更包括第二間隔件，所述第二間隔件在所述閘極結構的上部部分的相對側壁上，且其中所述第一間隔件與所述第二間隔件在所述垂直方向上至 少部分地彼此交疊。
  14. 一種半導體裝置，包括：基底；源極/汲極層，在所述基底上；第一閘極結構，在所述源極/汲極層的第一側，所述第一閘極結構包括依序地在垂直方向上堆疊的下部部分和上部部分；第一通道，延伸穿過所述第一閘極結構且連接到所述源極/汲極層，所述閘極結構的所述下部部分位在實質上相同於或低於所述第一通道的底表面的高度的高度處；以及第一間隔件，在所述第一閘極結構的與所述源極/汲極層面對的側壁上，所述第一間隔件將所述第一閘極結構與所述源極/汲極層電絕緣，且所述第一間隔件包括第一突出部分和第二突出部分，所述第一突出部分和所述第二突出部分在與所述基底的上表面實質上垂直的所述垂直方向上不與所述第一通道交疊，其中所述第一通道在第一方向上延伸，所述第一方向與所述基底的所述上表面實質上平行，其中所述源極/汲極層與所述第一閘極結構在所述第一方向上彼此間隔開，其中所述第一間隔件更包括第一中心部分，所述第一中心部分在所述垂直方向上與所述第一通道交疊，且其中所述第一突出部分和所述第二突出部分在第二方向上分別自所述第一中心部分的相對端突出，所述第二方向實質上平行 於所述基底的所述上表面且實質上垂直於所述第一方向。
  15. 如申請專利範圍第14項所述的半導體裝置，其中所述第一中心部分包括在所述第一閘極結構與所述源極/汲極層之間的傾斜側壁。
  16. 如申請專利範圍第15項所述的半導體裝置，更包括：第二閘極結構，在所述源極/汲極層的第二側；第二通道，延伸穿過所述第二閘極結構且連接到所述源極/汲極層；以及第二間隔件，在所述第二閘極結構的與所述源極/汲極層面對的側壁上，所述第二間隔件使所述第二閘極結構與所述源極/汲極層電絕緣，且所述第二間隔件包括第二突出部分，所述第二突出部分在所述垂直方向上不與所述第二通道交疊，其中相對於經過所述源極/汲極層的中心點在所述第二方向上延伸的軸線，所述第一間隔件與所述第二間隔件各自的沿水平方向截取的橫截面對稱，所述水平方向與所述基底的所述上表面實質上平行。
  17. 如申請專利範圍第14項所述的半導體裝置，其中所述第一通道包括在所述垂直方向上彼此間隔開的多個第一通道，且其中所述第一間隔件在所述多個第一通道之間，且在所述基底與所述多個第一通道中最靠近所述基底的一個第一通道之間。
  18. 如申請專利範圍第17項所述的半導體裝置，更包括：第三間隔件，在所述第一閘極結構的上部部分上及所述多個 第一通道中的最上第一通道上，其中所述第三間隔件使所述第一閘極結構的所述上部部分與所述源極/汲極層電絕緣，且其中所述第一間隔件與所述第三間隔件在所述垂直方向上至少部分地彼此交疊。
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