TWI753067B - Monolithic integrated device - Google Patents

Monolithic integrated device Download PDF

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TWI753067B
TWI753067B TW106144256A TW106144256A TWI753067B TW I753067 B TWI753067 B TW I753067B TW 106144256 A TW106144256 A TW 106144256A TW 106144256 A TW106144256 A TW 106144256A TW I753067 B TWI753067 B TW I753067B
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electronic circuit
integrated device
monolithic integrated
interlayer dielectric
layer
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TW201929276A (en
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潘迪安 莫罕拉吉 紹達拉
偉松 陳
凡卡德希 馬達梵
阿君 庫馬爾 坎提馬翰提
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馬來西亞商矽特拉有限公司
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Abstract

This disclosure describes a monolithic integrated device having an architecture that allows the acoustic device to transduce either the surface acoustic waves or the bulk acoustic waves. The monolithic integrated device comprises a substrate layer (101) being the base of the monolithic integrated device; an inter-layer dielectric (102) disposed on top of the substrate layer (101); an electronic circuitry substantially formed in the inter-layer dielectric (102) and supported by the substrate layer (101), the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals (204); and a piezoelectric (301)being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is a metal (204) of an upper metal layer belonging to the electronic circuitry and the bottom electrode is a metal (204) of a lower metal layer belonging to the electronic circuitry. In order to transduce bulk acoustic waves, the inter-layer dielectric is formed with a top cavity (105) above the top electrode and a bottom cavity (106) below the bottom electrode.

Description

單石積體裝置 Single stone integrated device

本發明是關於半導體領域中的元件,特別是關於可應用於受控頻率電路設計應用中的單石積體裝置(monolithic integrated device)。 The present invention relates to components in the semiconductor field, and more particularly to monolithic integrated devices that can be used in controlled frequency circuit design applications.

聲波元件有利於頻率過濾以實現特定頻寬的信號的發送和接收。習知上此種元件通常用於廣播無線電、電視和移動通信應用中。這些無源(passive)聲波元件的眾多功能是通過將它們與有源(active)電路集成(integration)來形成各種元件,如振盪器、有源濾波器、低噪音放大器、質量傳感器、溫度傳感器等。這些由互補金屬氧化物半導體(complementary-metal-oxide semiconductor,CMOS)技術製造的電子電路和由微電子機械系統(micro-electro mechanical systems,MEMS)技術製造的聲學元件被安裝在層壓板(laminated board)或矽中介層(silicon interposer)上。 Acoustic elements facilitate frequency filtering to enable transmission and reception of signals of specific bandwidths. Such elements are conventionally used in broadcast radio, television and mobile communications applications. The numerous functions of these passive acoustic wave components are by integrating them with active circuits to form various components such as oscillators, active filters, low noise amplifiers, mass sensors, temperature sensors, etc. . These electronic circuits fabricated by complementary-metal-oxide semiconductor (CMOS) technology and acoustic elements fabricated by micro-electro mechanical systems (MEMS) technology are mounted on a laminated board (laminated board). ) or silicon interposer.

通常,電子電路和聲學元件的集成是通過單石或異構(heterogeneous)集成方法來實現的,其中聲學元件被構建在電子電路的頂部。與異構集成相比,單石集成提供了更佳的解決方案。US20060202779A1描述了一種單石積體裝置的示例,其包括基底、由基底支撐的電子電路、在電子電路上方的聲學隔離器以及在聲學隔離器上的聲學諧振器,其用於傳導(transduce)體聲波(bulk acoustic wave)。聲學諧 振器與電子電路垂直集成在單個單石元件中。此種元件具有縮短聲學諧振器和電子電路之間的信號傳播距離並且減少連接的數量的特徵,因此導致單石積體裝置的性能和靈敏度的提高,並減小單石積體裝置的尺寸,同時與聲學諧振器與電子電路橫向集成的單石積體裝置相比,增加了可在基底的給定區域內製造的聲學諧振器元件和電子電路元件的數量。 Typically, the integration of electronic circuits and acoustic components is achieved by monolithic or heterogeneous integration methods, where the acoustic components are built on top of the electronic circuits. Monolithic integration provides a better solution than heterogeneous integration. US20060202779A1 describes an example of a monolithic integrated device comprising a substrate, an electronic circuit supported by the substrate, an acoustic isolator over the electronic circuit, and an acoustic resonator on the acoustic isolator for transducing bulk acoustic waves (bulk acoustic wave). acoustic harmonics The vibrator is vertically integrated with the electronic circuit in a single monolithic element. Such elements have the characteristics of shortening the signal propagation distance between the acoustic resonator and the electronic circuit and reducing the number of connections, thus resulting in improved performance and sensitivity of the monolithic integrated device, and reduced size of the monolithic integrated device, while being compatible with the Acoustic resonators increase the number of acoustic resonator elements and electronic circuit elements that can be fabricated within a given area of a substrate compared to monolithic integrated devices in which electronic circuits are laterally integrated.

在US5260596A中揭示的單石積體裝置的另一個例子描述了與體結構諧振器(bulk structure resonator)集成的單石電路晶片。該晶片包含多個積體電路元件,其被製造作為安裝有用於支撐質量的彈簧的半導體基底的一部分。該發明包括一激發裝置,其用於對質量施加變化的靜電力以引起質量中的機械振動。製造於半導體基底上的空腔為機械振動的發生提供了空間。該發明的其它實施例包括使用能產生表面聲波(surface acoustic wave)或體聲波(bulk acoustic wave)的非壓電(non-piezoelectric)機械諧振器、石英晶體諧振器和薄膜壓電諧振器。 Another example of a monolithic integrated device disclosed in US5260596A describes a monolithic circuit die integrated with a bulk structure resonator. The wafer contains a plurality of integrated circuit elements fabricated as part of a semiconductor substrate mounted with springs for supporting the mass. The invention includes an excitation device for applying a varying electrostatic force to a mass to induce mechanical vibrations in the mass. Cavities fabricated on the semiconductor substrate provide room for mechanical vibrations to occur. Other embodiments of the invention include the use of non-piezoelectric mechanical resonators, quartz crystal resonators and thin film piezoelectric resonators capable of generating surface acoustic waves or bulk acoustic waves.

習知的單石積體裝置,特別是那些被配置成具有在CMOS元件的電子電路之上構建聲學元件的單石積體裝置,在聲學元件和CMOS元件之間造成了複雜性和兼容性問題,這會犧牲聲學元件的功能。因此,此處公開的本發明旨在為這些問題提供解決方案。 Conventional monolithic devices, especially those configured to have acoustic components built on top of the CMOS components' electronic circuitry, create complexity and compatibility issues between the acoustic components and the CMOS components, which can lead to sacrificing the functionality of the acoustic element. Accordingly, the invention disclosed herein aims to provide solutions to these problems.

本發明的目的之一在於提供一種單石積體裝置,其具有通過將聲學元件嵌入CMOS元件的電子電路內而利用電子電路的金屬層作為聲學元件的電極來減少互連電子寄生效應(interconnect electronic parasitic)的結構。 One of the objects of the present invention is to provide a monolithic integrated device having reduced interconnect electronic parasitic effects by embedding the acoustic element in the electronic circuit of the CMOS element and using the metal layer of the electronic circuit as the electrode of the acoustic element )Structure.

本發明的另一目的在於提供一種單石積體裝置,其具有通過將聲學元件嵌入CMOS元件的電子電路內而利用電子電路的金屬層作為聲學元件的電極來減少互連電子寄生效應(interconnect electronic parasitic)的結構。 Another object of the present invention is to provide a monolithic integrated device having reduced interconnect electronic parasitic effects by embedding the acoustic element within the electronic circuit of the CMOS element and utilizing the metal layer of the electronic circuit as the electrode of the acoustic element )Structure.

本發明的另一目的在於提供一種單石積體裝置,其具有允許聲學元件與具有或不具有鈍化層的電子電路集成的結構。 Another object of the present invention is to provide a monolithic integrated device having a structure that allows the integration of an acoustic element with an electronic circuit with or without a passivation layer.

本發明的另一個目的在於提供一種單石積體裝置,其能夠使得聲學元件與有源電子電路電子地斷開連接的單石積體裝置而使得聲學元件可以被用於無源元件。 Another object of the present invention is to provide a monolithic integrated device that enables an acoustic element to be electronically disconnected from an active electronic circuit so that the acoustic element can be used for a passive element.

本發明的另一個目的在於一種單石積體裝置,其具有簡化的元件結構和配置同時增強聲學元件和CMOS元件之間的兼容性,而不必犧牲聲學元件的功能。 Another object of the present invention is a monolithic integrated device having a simplified element structure and configuration while enhancing compatibility between acoustic elements and CMOS elements without sacrificing the functionality of the acoustic elements.

通過本發明全部或部分地滿足了上述方面中的至少一個,本發明的較佳實施例描述了一種單石積體裝置,其包括:一基底層,作為該單石積體裝置的基底;一層間介電質,配置在該基底層的頂部上;一電子電路,基本形成在該層間介電質中並由該基底層所支撐,該電子電路包括由一個或多個間隔開的金屬形成的多個金屬層;以及一壓電體,夾置在該層間介電質內的一頂部電極和一底部電極之間;其中該頂部電極是屬於該電子電路的上部金屬層的金屬並且該底部電極是屬於該電子電路的下部金屬層的金屬。此種結構允許表面聲波的傳導。為了傳導體聲波,在頂部電極上方和底部電極下方形成空腔。 Through the present invention satisfying at least one of the above aspects in whole or in part, a preferred embodiment of the present invention describes a monolithic integrated device, comprising: a base layer as the substrate of the monolithic integrated device; an electrical circuit disposed on top of the base layer; an electronic circuit formed substantially in the interlayer dielectric and supported by the base layer, the electronic circuit comprising a plurality of metals formed from one or more spaced-apart metal layer; and a piezoelectric body sandwiched between a top electrode and a bottom electrode within the interlayer dielectric; wherein the top electrode is a metal belonging to the upper metal layer of the electronic circuit and the bottom electrode is a metal belonging to the upper metal layer of the electronic circuit The metal of the lower metal layer of the electronic circuit. This structure allows the conduction of surface acoustic waves. To conduct bulk acoustic waves, cavities are formed above the top electrode and below the bottom electrode.

101:基底層 101: Substrate layer

102:層間介電質 102: Interlayer dielectric

103:鈍化層 103: Passivation layer

104:接合焊盤開口 104: Bond pad opening

105、106:空腔 105, 106: cavity

201:閘極 201: Gate

202:源極和汲極區 202: Source and drain regions

203:接觸元件 203: Contact element

204:金屬 204: Metal

205:通孔 205: Through hole

301:壓電體 301: Piezoelectric

圖1示出了具有允許聲學元件傳導表面聲波的結構的單石積體裝置的示意圖。 Figure 1 shows a schematic diagram of a monolithic integrated device having a structure that allows the acoustic element to conduct surface acoustic waves.

圖2示出了具有允許通過聲學元件傳導表面聲波或體聲波的結構的單石積體裝置的示意圖。 Figure 2 shows a schematic diagram of a monolithic integrated device having a structure that allows conduction of surface or bulk acoustic waves through the acoustic element.

為了更好地理解本發明,將詳細描述在附圖中示出的本發明的較佳實施例。 For a better understanding of the present invention, preferred embodiments of the present invention shown in the accompanying drawings will be described in detail.

此處公開的發明涉及一種將聲學元件與通過互補金屬氧化物半導體技術製造的電子電路集成在一起的單石積體裝置。根據電子電路和聲學元件的類型,單石積體裝置通過響應於施加的機械應力而產生電荷的聲學元件的集成可以形成為振盪器、有源濾波器、低噪音放大器、質量傳感器、溫度傳感器等。作為無源電子頻率產生器的聲波元件通常由夾在頂部電極和底部電極之間的壓電體(piezoelectric)形成。應當注意的是,這裡使用的術語“電子電路”是指包括通過諸如CMOS元件的電連接而連接的電子元件或多個電子元件的有源電路。 The invention disclosed herein relates to a monolithic integrated device that integrates an acoustic element with an electronic circuit fabricated by complementary metal oxide semiconductor technology. Depending on the type of electronic circuit and acoustic elements, monolithic integrated devices can be formed as oscillators, active filters, low noise amplifiers, mass sensors, temperature sensors, etc. through the integration of acoustic elements that generate electrical charges in response to applied mechanical stress. Acoustic wave elements, which are passive electronic frequency generators, are generally formed of piezoelectrics sandwiched between top and bottom electrodes. It should be noted that the term "electronic circuit" as used herein refers to an active circuit comprising an electronic element or electronic elements connected by electrical connections such as CMOS elements.

參照圖1和圖2,單石積體裝置具有充當元件基座的基底層(101)。基底層(101)由諸如但不限於矽的半導體製成。層間介電質(inter-layer dielectric)(102)設置在基底層(101)的頂部,其中電子電路基本上在基底層(101)和層間介電質(102)間形成並被基底層(101)支撐。 Referring to Figures 1 and 2, a monolithic integrated device has a base layer (101) that serves as a base for the element. The base layer (101) is made of a semiconductor such as but not limited to silicon. An inter-layer dielectric (102) is provided on top of the base layer (101), wherein electronic circuits are substantially formed between the base layer (101) and the inter-layer dielectric (102) and are supported by the base layer (101) )support.

電子電路包括基底層(101)中的至少一閘極(201)、位於層間介電質(102)中且具有分別連接到閘極(201)的源極和汲極的至少一源極和汲極區(202)、由一個或多個間隔開的金屬(204)形成的多個金屬層、至少一接觸元件(203),其用於將源極和汲極區(202)和閘極(201)中 的任何一個或其組合連接到多個金屬(204)之一、和用於連接不同金屬層的通孔(205)。 The electronic circuit comprises at least one gate (201) in a base layer (101), at least one source and drain in an interlayer dielectric (102) and having a source and a drain respectively connected to the gate (201) electrode regions (202), a plurality of metal layers formed from one or more spaced-apart metals (204), at least one contact element (203) for connecting the source and drain regions (202) and the gate (204) 201) in Any one or a combination of these are connected to one of a plurality of metals (204), and vias (205) for connecting different metal layers.

閘極(201)、源極和汲極是使用電場來控制電子電路的電流流動的場效電晶體(field-effect transistor,FET)的端子。在圖1和2所示的本發明的較佳實施例中,一對閘極(201)分別連接到源極和汲極。通過嵌入在基底層(101)中而與電子電路的其餘元件絕緣的閘極(201)被施以一電壓。所施加的閘極電壓將電場施加到電子電路中,導致電荷載體相對於嵌入在層間介電質(102)中的源極和汲極之間的區域的吸引或排斥。電荷的密度影響源極和汲極之間的導電性,從而控制電子電路的電流流動。如圖1和圖2所示,接觸元件(203)用於將閘極(201)連接到金屬(204)中的任何一個以及將源極和汲極區(202)連接到金屬(204)中的任何一個。不同的金屬層通過通孔(205)連接。 The gate (201), source and drain are the terminals of a field-effect transistor (FET) that uses an electric field to control the current flow of the electronic circuit. In the preferred embodiment of the invention shown in Figures 1 and 2, a pair of gate electrodes (201) are connected to the source and drain electrodes, respectively. A voltage is applied to the gate (201), which is insulated from the rest of the electronic circuit by being embedded in the base layer (101). The applied gate voltage applies an electric field into the electronic circuit, resulting in the attraction or repulsion of charge carriers relative to the region between the source and drain embedded in the interlayer dielectric (102). The density of charge affects the conductivity between the source and drain, which controls the flow of current in electronic circuits. As shown in Figures 1 and 2, contact elements (203) are used to connect the gate (201) to either of the metals (204) and the source and drain regions (202) into the metal (204) any of the . The different metal layers are connected by vias (205).

此處所描述的單石積體裝置其特徵在於電子電路和聲學元件之間的金屬(204)為共享。此共享通過利用來自兩個不同金屬層的兩個金屬(204)作為聲學元件的頂部電極和底部電極而成為可能。壓電體(301)夾在層間介電質(102)內的頂部電極和底部電極之間。因此,與習知的單石積體裝置不同,聲學元件不是形成在電子電路的頂部,而是嵌入在層間介電質(102)內。頂部電極是位於上部金屬層的金屬(204),而底部電極是位於下部金屬層的金屬(204)。此外,儘管聲學元件使用電子電路的金屬(204)作為電極,當聲學元件與有源電子電路電子地斷開時,這種單石積體裝置的元件結構和構造允許聲學元件用作無源元件。 The monolithic integrated device described herein is characterized by a shared metal (204) between the electronic circuit and the acoustic element. This sharing is made possible by using two metals (204) from two different metal layers as the top and bottom electrodes of the acoustic element. The piezoelectric body (301) is sandwiched between the top and bottom electrodes within the interlayer dielectric (102). Thus, unlike conventional monolithic integrated devices, the acoustic element is not formed on top of the electronic circuit, but embedded within the interlayer dielectric (102). The top electrode is metal (204) in the upper metal layer and the bottom electrode is metal (204) in the lower metal layer. Furthermore, although the acoustic element uses the metal (204) of the electronic circuit as electrodes, the element structure and configuration of this monolithic integrated device allows the acoustic element to function as a passive element when the acoustic element is electronically disconnected from the active electronic circuit.

充當電子電路和壓電體(301)的保護層的鈍化層(103)可選擇地形成在層間介電質(102)上。習知上,聲學元件被構建在鈍化層(103)的頂部上。通過使用電子電路的金屬(204)作為聲學元件的電極而將聲學 元件嵌入在層間介電質(102)內,即使沒有鈍化層(103),也可以實現聲學元件與電子電路的集成。該元件利用至少一延伸穿過鈍化層(103)並部分地進入層間介電質(102)直到到達多個金屬(204)之一的接合焊盤開口(bond-pad opening)(104)而形成,而該金屬(204)被用作單石積體裝置的焊盤。優選地,將這些接合焊盤開口(104)蝕刻到鈍化層(103)和層間介電質(102)中以暴露接合焊盤。 A passivation layer (103) that acts as a protective layer for the electronic circuit and piezoelectric body (301) is optionally formed on the interlayer dielectric (102). Conventionally, acoustic elements are built on top of the passivation layer (103). By using the metal (204) of the electronic circuit as the electrodes of the acoustic element The components are embedded in an interlayer dielectric (102), enabling integration of the acoustic components with electronic circuits even without a passivation layer (103). The device is formed using at least one bond-pad opening (104) extending through the passivation layer (103) and partially into the interlayer dielectric (102) until reaching one of the plurality of metals (204). , and the metal (204) is used as the pad for the monolithic integrated device. Preferably, these bond pad openings (104) are etched into the passivation layer (103) and the interlayer dielectric (102) to expose the bond pads.

本發明的主要特徵之一是其能夠傳導表面聲波或體聲波的結構。圖1示出了允許聲學元件傳導表面聲波的單石積體裝置的結構,而圖2示出了可用於傳導表面聲波或體聲波的單石積體裝置的結構。在圖1中,在電極的上方和下方不形成用於壓電體(301)振動的空腔。因此,圖1所示的單石積體裝置中的聲學元件傳導表面聲波。另一方面,圖2中的層間介電質(102)形成有在頂部電極上方的頂部空腔(105)和在底部電極下方的底部空腔(106)。這些空腔(105、106)為壓電體的振動提供空間,從而允許壓電體傳導體聲波或表面聲波。 One of the main features of the present invention is its structure capable of conducting surface acoustic waves or bulk acoustic waves. Figure 1 shows the structure of a monolithic integrated device that allows the acoustic element to conduct surface acoustic waves, while Figure 2 shows the structure of a monolithic integrated device that can be used to conduct surface acoustic waves or bulk acoustic waves. In Fig. 1, no cavities for vibration of the piezoelectric body (301) are formed above and below the electrodes. Therefore, the acoustic element in the monolithic integrated device shown in FIG. 1 conducts surface acoustic waves. On the other hand, the interlayer dielectric (102) in Figure 2 is formed with a top cavity (105) above the top electrode and a bottom cavity (106) below the bottom electrode. These cavities (105, 106) provide space for the vibration of the piezoelectric body, allowing the piezoelectric body to conduct bulk or surface acoustic waves.

儘管本發明已詳細描述和說明,但應該理解的是,本發明是通過說明和示例的方式,並非作為限制。本發明之精神和範圍僅受後附之申請專利範圍所界定者之限制。 While the present invention has been described and illustrated in detail, it is to be understood that the present invention has been presented by way of illustration and example, and not limitation. The spirit and scope of the present invention are limited only by those defined by the appended claims.

101:基底層 101: Substrate layer

102:層間介電質 102: Interlayer dielectric

103:鈍化層 103: Passivation layer

104:接合焊盤開口 104: Bond pad opening

105:空腔 105: cavity

106:空腔 106: Cavity

201:閘極 201: Gate

202:源極和汲極區 202: Source and drain regions

203:接觸元件 203: Contact element

204:金屬 204: Metal

205:通孔 205: Through hole

301:壓電體 301: Piezoelectric

Claims (8)

一種單石積體裝置,包括:一基底層(101),是該單石積體裝置的基底;一層間介電質(102),配置在該基底層(101)的頂部上;一電子電路,基本形成在該層間介電質(102)中並由該基底層(101)所支撐,該電子電路包括由兩個或多個間隔開的金屬(204)形成的多個金屬層;一鈍化層(103),形成於該層間介電質(102)的頂部上;以及一壓電體(301),夾置在在該層間介電質(102)內的一頂部電極和一底部電極之間,位於該鈍化層(103)附近的該頂部電極是屬於該電子電路的上部金屬層的金屬(204)並且該底部電極是屬於該電子電路的下部金屬層的金屬(204);其中,該單石積體裝置形成有接合焊盤開口(104),該接合焊盤開口(104)延伸穿過該鈍化層(103)並部分地進入該層間介電質(102),直到該接合焊盤開口(104)到達該電子電路的多個金屬(204)之一,其用以作為該頂部電極和一焊盤。 A monolithic integrated device, comprising: a base layer (101), which is the base of the monolithic integrated device; an interlayer dielectric (102) arranged on top of the base layer (101); an electronic circuit, basically Formed in the interlayer dielectric (102) and supported by the base layer (101), the electronic circuit includes a plurality of metal layers formed from two or more spaced apart metals (204); a passivation layer ( 103) formed on top of the interlayer dielectric (102); and a piezoelectric body (301) sandwiched between a top electrode and a bottom electrode within the interlayer dielectric (102), The top electrode located near the passivation layer (103) is metal (204) belonging to the upper metal layer of the electronic circuit and the bottom electrode is metal (204) belonging to the lower metal layer of the electronic circuit; wherein the monolithic The body device is formed with bond pad openings (104) extending through the passivation layer (103) and partially into the interlayer dielectric (102) until the bond pad openings (104) ) to one of the metals (204) of the electronic circuit, which serve as the top electrode and a pad. 如請求項1所述之單石積體裝置,其中,該層間介電質(102)形成有在該頂部電極上方的一頂部空腔(105)和在該底部電極下方的一底部空腔(106)。 The monolithic integrated device of claim 1, wherein the interlayer dielectric (102) is formed with a top cavity (105) above the top electrode and a bottom cavity (106) below the bottom electrode ). 如請求項1所述之單石積體裝置,其中該電子電路包括該基底層(101)中的至少一閘極(201)。 The monolithic integrated device of claim 1, wherein the electronic circuit comprises at least one gate (201) in the base layer (101). 如請求項3所述之單石積體裝置,其中該電子電路包括在該層間介電質(102)中的至少一源極和汲極區(202),該源極和汲極區(202)具有分別連接到該閘極(201)的一源極和一汲極。 The monolithic integrated device of claim 3, wherein the electronic circuit comprises at least one source and drain region (202) in the interlayer dielectric (102), the source and drain regions (202) There is a source and a drain connected to the gate (201), respectively. 如請求項4所述之單石積體裝置,其中,該電子電路包括用於將該源極和汲極區(202)和該閘極(201)中的任何一個或其組合連接到該多個金屬(204)之一的一接觸元件(203)。 The monolithic integrated device of claim 4, wherein the electronic circuit includes means for connecting any one or combination of the source and drain regions (202) and the gate (201) to the plurality of A contact element (203) of one of the metals (204). 如請求項1所述之單石積體裝置,還包括一個或多個通孔(205),用於連接不同的該金屬層。 The monolithic integrated device of claim 1, further comprising one or more through holes (205) for connecting different metal layers. 如請求項1所述之單石積體裝置,其中該電子電路是一CMOS元件。 The single-chip integrated device of claim 1, wherein the electronic circuit is a CMOS device. 一種單石積體裝置,包括:一基底層(101),是該單石積體裝置的基底;一層間介電質(102),配置在該基底層(101)的頂部上;一鈍化層(103),配置在該層間介電質(102)的頂部上的;一電子電路,基本形成在該層間介電質(102)中並由該基底層(101)所支撐,該電子電路包括由兩個或多個間隔開的金屬(204)形成的多個金屬層;以及一壓電體(301),夾置在在該層間介電質(102)內的一頂部電極和一底部電極之間,位於該鈍化層(103)附近的該頂部電極是屬於該電子電路的上部金屬層的金屬(204)並且該底部電極是屬於該電子電路的下部金屬層的金屬(204);其中該層間介電質(102)形成有在該頂部電極上方的一頂部空腔(105)和在該底部電極下方的一底部空腔(106),又該單石積體裝置形成有至少一個接 合焊盤開口(104),該接合焊盤開口(104)延伸穿過該鈍化層(103)並部分地進入該層間介電質(102),直到該接合焊盤開口(104)到達該電子電路的多個金屬(204)之一,其用以作為該頂部電極和一焊盤。 A monolithic integrated device, comprising: a base layer (101), which is the base of the monolithic integrated device; an interlayer dielectric (102) disposed on top of the base layer (101); a passivation layer (103) ), disposed on top of the interlayer dielectric (102); an electronic circuit formed substantially in the interlayer dielectric (102) and supported by the base layer (101), the electronic circuit comprising two A plurality of metal layers formed of one or more spaced-apart metals (204); and a piezoelectric body (301) sandwiched between a top electrode and a bottom electrode within the interlayer dielectric (102) , the top electrode located near the passivation layer (103) is metal (204) belonging to the upper metal layer of the electronic circuit and the bottom electrode is metal (204) belonging to the lower metal layer of the electronic circuit; wherein the interlayer The cell (102) is formed with a top cavity (105) above the top electrode and a bottom cavity (106) below the bottom electrode, and the monolithic integrated device is formed with at least one connection. bond pad opening (104) extending through the passivation layer (103) and partially into the interlayer dielectric (102) until the bond pad opening (104) reaches the electronic One of a plurality of metals (204) of the circuit that serves as the top electrode and a pad.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102933318A (en) * 2010-01-29 2013-02-13 三角形研究学会 Methods for forming piezoelectric ultrasonic transducers, and associated apparatuses
CN106877836A (en) * 2015-12-14 2017-06-20 中芯国际集成电路制造(上海)有限公司 A kind of FBAR and its manufacture method and electronic installation
CN107181472A (en) * 2016-03-10 2017-09-19 中芯国际集成电路制造(上海)有限公司 FBAR, semiconductor devices and its manufacture method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102933318A (en) * 2010-01-29 2013-02-13 三角形研究学会 Methods for forming piezoelectric ultrasonic transducers, and associated apparatuses
CN106877836A (en) * 2015-12-14 2017-06-20 中芯国际集成电路制造(上海)有限公司 A kind of FBAR and its manufacture method and electronic installation
CN107181472A (en) * 2016-03-10 2017-09-19 中芯国际集成电路制造(上海)有限公司 FBAR, semiconductor devices and its manufacture method

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