TWI744134B - Data storage device and control method for data storage device - Google Patents

Abstract

A data storage device and a control method of the data storage device are provided. The data storage device includes a memory array and a reading device. The memory array includes at least one memory cell and a global bit line. Each memory cell stores multiple bits. An input terminal of the reading device is coupled to the global bit line. The reading device includes a plurality of impedance elements, a plurality of latch circuits, and a latch reading circuit. The first terminal of each impedance element is mutually coupled to the input terminal of the reading device. The input terminal of each latch circuit is respectively coupled to a second terminal of each corresponding impedance element. The latch reading circuit reads latch bits in each of the latch circuits, respectively. A data stored in the memory cell is determined by the latch bit in each of the latch circuits read by the latch reading circuit.

Description

Data storage device and control method of data storage device

The present invention relates to a data access technology for a data storage device, and more particularly to a data storage device and a control method of the data storage device.

At present, most of the development of consumer electronic products is toward the field of wireless communication and automotive electronics, so it is hoped that non-volatile memory can have high reading and writing speed and high stability. In detail, as the data transmission rate of wireless transmission technology is gradually increasing, it is also hoped that non-volatile memory devices in electronic equipment will move towards large capacity and fast operation speed (also known as read and write speed). Moreover, under the booming development of automotive electronics, high stability and stable response speed (ie, data reading speed) of non-volatile memory devices are also very important.

NAND flash memory technology in non-volatile memory has developed a technology that uses a single flash memory cell to store two or more bits. In other words, the categories of NAND flash memory include Multi-Level Cells (MLC), Triple-Level Cells (TLC) and even Quad-Level Cells (QLC). ...And so on, so as to have a greater data density.

However, because there are multiple bits stored in each memory cell, and when a memory cell that stores multiple bits is read, it will take more reading time to determine this memory. What is the voltage level of the cell? For example, when performing an MLC reading operation, it is necessary to read the MLC twice to determine its potential; when performing a TLC reading operation, it is necessary to read the TLC three times to determine its potential, and so on. As a result, the read time for memory cells will be greatly increased. On the other hand, since the number of reads to the memory cell in the aforementioned read operation will increase in accordance with the number of bits stored in the memory cell, it will increase the power consumption of the read operation and reduce each The service life of the memory cell.

The present invention provides a data storage device and a control method thereof. By sensing and judging data in a memory cell capable of storing multiple bits in a current detection mode, the reading of multi-level cells during a read operation is reduced. The frequency of fetching improves the service life and reliability of the memory cell.

The data storage device of the present invention includes a memory array and a reading device. The memory array includes at least one memory cell and an overall bit line, and each memory cell stores a plurality of bits and is selectively connected to the overall bit line. The input terminal of the reading device is coupled to the overall bit line. The reading device includes a plurality of impedance elements, a plurality of latch circuits, and a latch read circuit. The first end of each impedance element is mutually coupled to the input end of the reading device. The input terminal of each latch circuit is respectively coupled to the second terminal of each corresponding impedance element. The latch reading circuit is coupled to the outputs of the latch circuits end. The latch reading circuit reads the respective latch bits in the latch circuits. The data stored in the at least one memory cell is determined by the latch bits in the latch circuits read by the latch read circuit.

The control method of the data storage device of the present invention is suitable for a data storage device including a memory array. The memory array includes at least one memory cell and an overall bit line, and each memory cell stores multiple bits. The control method includes the following steps: during the reading charging time of the reading operation, the output terminal of the selected at least one memory cell is coupled to the overall bit line, wherein the input terminal of the reading device is configured to be coupled Connected to the overall bit line, the reading device includes a plurality of impedance elements and a plurality of latch circuits, the first end of each impedance element is mutually coupled to the input end of the reading device, and the The input terminal is respectively coupled to the second terminal of each corresponding impedance element, and each latch circuit has a corresponding threshold voltage; after the charging time is read, the respective latch bits in the latch circuits are read ; And, determine the data stored in the at least one memory cell according to the read latch bits in the latch circuits.

Based on the above, the data storage device and its control method according to the embodiments of the present invention adjust the circuit structure of the reading device to read the threshold voltage of the memory cell multiple times from the original dichotomy compared with the preset voltage. Yes, instead, in this embodiment, the current detection method is used to sense and determine the data in the memory cell at one time. That is to say, the embodiment of the present invention adjusts the impedance value of each impedance element in the reading device and/or the threshold voltage of the latch circuit, so that the corresponding latch circuit flows through the corresponding Of the impedance element’s current while charging, and then adjusting The internal latch bit. In this way, the embodiment of the present invention can reduce the number of times to read multi-level cells during a read operation, and improve the service life and reliability of memory cells.

100: Data storage device

110: memory array

112, 112-1~112-4: Memory cell

120: Reading device

131~133: Impedance unit

141~143, 410, 510: latch circuit

150: latch read circuit

311~314: State distribution area

520, 530, INV1~INV4: inverter

800: Control method of data storage device

S810~S830: Steps of the control method of the data storage device

SL: select line

Sgs: Source selection gate

Sgd: Drain extreme selection gate

BL0~BL2: bit line

WL0~WLM: character line

R1~R3: Impedance value of impedance unit

I1~I3: current

P1~P3: path

PIN: the input terminal of the reading device

GBL: Global bit line

TI2~TI4: total current

PST: stylized state

EST: Erase status

NUM: the number of memory cells in each state

d: Adjacent distance between state distribution areas

RWL1~RWL3: Read signal

RBL: read bit line

T1~T3, T11~T13, T21~T23: Transistor

READ: read signal

RESET: reset signal

INN: The input terminal of the latch circuit

OUTN: The output terminal of the latch circuit

In11, In21: the first input terminal of reverse and gate

In12, In22: the second input terminal of reverse and gate

Out1, Out2: output terminal of reverse and gate

FIG. 1 is a schematic diagram of a data storage device according to an embodiment of the present embodiment.

2 is an embodiment of the present embodiment, in the case that the memory cell is a multi-level cell (MLC), the data stored in the memory cell and the latch circuit are locked after reading and charging time. Schematic diagram of bit storage.

3 is a schematic diagram of the relationship between the data stored in the memory cell and the threshold voltage distribution diagram of the memory cell in the case of using multi-level cells as the memory cell in an embodiment of the present embodiment.

FIG. 4 is an example circuit diagram of the latch circuit in FIG. 1 or FIG. 2.

FIG. 5 is another example circuit diagram of the latch circuit in FIG. 1 or FIG. 2. FIG.

FIG. 6 is an example circuit diagram of the latch reading circuit in FIG. 1. FIG.

FIG. 7 is a schematic diagram of a data storage device implemented by a volumetric volume circuit (3DIC) in an embodiment of this embodiment.

FIG. 8 is a flowchart of a control method of a data storage device in an embodiment of this embodiment.

FIG. 1 is a diagram of a data storage device 100 according to an embodiment of this embodiment. intention. The data storage device 100 may be a memory device used in a consumer electronic device, such as a NAND-type or NOR-type flash memory device.

Please refer to FIG. 1, the data storage device 100 includes a memory array 110 and a reading device 120. The memory array 110 includes at least one memory cell and a global bit line GBL. The memory cells of this embodiment are arranged in a matrix form, and have bit lines BL0~BL2 and word lines WL0~WLM. These memory cells are selectively connected to the global bit line GBL. When performing a corresponding operation (such as a read operation), the controller in the data storage device 100 can control the selection line SL, the source selection gate Sgs, the drain selection gate Sgd, and the word lines WL0~WLM. Select one of these memory cells (for example, the selected memory cell 112), and couple the output terminal of the selected memory cell 112 to the whole area through a bit line (for example, bit line BL1) Bit line GBL. In this way, the reading device 120 coupled to the global bit line GBL can determine the data stored in the memory cell 112 according to the voltage of the global bit line GBL.

In this embodiment, each memory cell stores multiple bits. In other words, the number of bits stored in each memory cell in this embodiment is N, and N is a positive integer greater than or equal to 2. In other words, the memory cells of this embodiment can be multi-level cells (Multi-Level Cells; MLC) (N is equal to 2), three-level cells (Triple-Level Cells; TLC) (N is equal to 3), or It is Quad-Level Cells (QLC) (N equals 4). In this embodiment, a multi-level cell is used as an example of a memory cell. That is, each memory cell in the memory array 110 of this embodiment can store two bits of data.

The input end of the reading device 120 is coupled to the global bit line GBL. The reading device 120 mainly includes a plurality of impedance elements (for example, the impedance elements 131 to 133 in FIG. 1), a plurality of latch circuits (for example, the latch circuits 141 to 143 in FIG. 1), and a latch reading circuit 150 . The impedance elements 131 to 133 of this embodiment can be realized by resistors. The first ends of the impedance elements 131 to 133 are mutually coupled to the input terminal PIN of the reading device 120. The input terminal of each latch circuit 141-143 is respectively coupled to the second terminal of each corresponding impedance element 131-133. For example, the input terminal of the latch circuit 141 is coupled to the second terminal of the impedance element 131, the input terminal of the latch circuit 142 is coupled to the second terminal of the impedance element 132, and the input terminal of the latch circuit 143 is coupled to the second terminal of the impedance element 133. Two ends. The latch reading circuit 150 is coupled to the output terminals of the latch circuits 141 to 143.

In this way, the embodiment of the present invention adjusts the circuit structure of the reading device 120, instead of comparing the threshold voltage of the memory cell with the preset voltage that is read multiple times by dichotomy, instead of comparing the threshold voltage of the memory cell with the preset voltage in this embodiment. Read the voltage of the memory cell and sense and determine the data in the cell at one time through current detection. In detail, this embodiment adjusts the impedance value of each impedance element 131~133 on each path P1~P3, the threshold voltage of each latch circuit 141~143, or adjusts both of the foregoing, so that the latch circuit 141 ~143 is charged by the current flowing through each corresponding impedance element 131~133 during the read charging time of the read operation, and the respective latch bit in each latch circuit 141~143 will be charged according to the previous reading Take the charging voltage charged during the charging time and the corresponding threshold voltage to adjust its value. In this way, the latch reading circuit 150 of this embodiment reads the respective latch bits in the latch circuits 141 to 143 after the charging time is read. In this way, the selected memory cell 112 stored The data is determined by the latch bits in the latch circuits 141 to 143 read by the latch read circuit 150.

Here is a detailed description of “adjusting the impedance value of each impedance element 131 to 133 on each path P1 to P3, the threshold voltage of each latch circuit 141 to 143, or adjusting the foregoing two at the same time". A method (also called the first method) that conforms to this embodiment is designed to adjust the impedance values R1~R3 of the impedance elements 131~133 on each path P1~P3 to be different, and let the latch circuit 141~ The threshold voltage of 143 is the same to achieve. Since the voltages on the global bit line GBL are the same, the currents I1~I3 on the paths P1~P3 will flow through the impedance elements 131~ because of the different impedance values R1~R3 of the impedance elements 131~133. 133 and different current values. In this way, the current values based on the currents I1~I3 are different from each other and the latch circuits 141~143 all have the same read charging time. The charging voltage raised by the latch circuits 141~143 due to charging may not be higher than that of the latch. Circuits 141 to 143 design their own critical voltages. In other words, the latch bits in the latch circuits 141 to 143 will have different presentation modes due to the voltage on the global bit line GBL, so as to determine the data stored in the memory cell 112.

Another method (also known as the second method) that conforms to this embodiment is designed to adjust the threshold voltages of the latch circuits 141 to 143 on each path P1 to P3 to be different from each other, and to allow the impedance elements 131 to 133 to be different from each other. The impedance values of R1~R3 are the same value to achieve. Since the voltage on the global bit line GBL is the same, the current values based on the currents I1~I3 are the same, but the threshold voltages designed by the latch circuits 141~143 are different from each other, different latch circuits 141~143 The required charging time is Are not the same. Therefore, based on the same read charging time, the charging voltage raised by each of the latch circuits 141 to 143 due to charging is not necessarily higher than the threshold voltage designed by the latch circuits 141 to 143 itself. In other words, the latch bits in the latch circuits 141 to 143 will have different presentation modes due to the voltage on the global bit line GBL, so as to determine the data stored in the memory cell 112.

2 is an example of this embodiment, in the case that the memory cell 112 is an MLC, the data stored in the memory cell 112 and the latch circuit after the read charge time has elapsed the respective latch bits Schematic. Here, the embodiment of the present invention will be described with the aforementioned first method in conjunction with FIG. 2. It is assumed here that the impedance value R1 in the impedance element 131 is greater than the impedance value R2 in the impedance element 132, and the impedance value R2 in the impedance element 132 is greater than the impedance value R3 in the impedance element 133. Therefore, the current I1 flowing through the impedance element 131 will be less than the current I2 flowing through the impedance element 132, and the current I2 flowing through the impedance element 132 will be less than the current I3 flowing through the impedance element 133. Since the memory cell 112 is MLC, the memory cell 112 can store two bits of data, that is, it can store four states (ie, "00", "10", "01" or "11" ")data of.

The latch circuits 141 to 143 in parts (A) to (D) in FIG. 2 have corresponding latch bits marked. When the latch bit is "0", it means that the charging voltage stored by the latch circuit during the read charging time is not greater than the threshold voltage preset by the latch circuit; when the latch bit is "1", it means The charging voltage stored in the latch circuit during the read charging time is greater than the threshold voltage preset by the latch circuit.

The upper left part (A) of FIG. 2 is used to show that the memory cell 112 stores data in the state of "00" in voltage mode, and latches the circuit during the read charge time The latch bits in 141~143 are sequentially expressed as "0", "0", and "0". In this embodiment, the output voltage of the memory cell 112 storing the "00" state is set to the minimum output voltage relative to other states, which means that the total current in the "00" state is shown in part (A) TI1 will be smaller than the total current TI2~TI4 representing the states of "10", "01" and "11" in parts (B) to (D). Because the total current TI1 will also be divided to flow through paths P1~P3 Therefore, the charging voltage stored in each latch circuit 141-143 during the read charging time is not greater than the threshold voltage preset by the latch circuit, resulting in the latching of each latch circuit 141-143 The bit is “0.” Therefore, when the latch reading circuit 150 of this embodiment reads the latched bits in the latch circuits 141 to 143 as “0”, “0”, and “0”, It is determined that the memory cell 112 stores data in the "00" state.

The upper right part (B) of FIG. 2 is used to show that the memory cell 112 stores data "10", and the latch bits in the latch circuits 141 to 143 in the read charge time are sequentially expressed as "0", "0", "1". In this embodiment, the output voltage of the memory cell 112 storing the "10" state is set to be greater than the output voltage of the memory cell 112 in the "00" state, but higher than that of the memory cells in the "01" and "11" states. The output voltage of the cell 112 is small. That is, part (B) indicates that the total current TI2 of the "10" state will be greater than the total current TI1 of the part (A), but less than the total current TI3 of the part (C) and the total current TI4 of the (D) part . In this way, the shunted current I3 in part (B) will be larger than the currents I1~I2, so that it is easier to make the charging voltage of the latch circuit 143 during the read charging time greater than its threshold voltage. This embodiment can be designed so that the charging voltage stored in the latch circuit 143 during the read charging time will be greater than the threshold preset by the latch circuit 143 Voltage (that is, the latch bit of the latch circuit 143 is "1"), but the charging voltage stored by the latch circuits 141~142 in the same read charging time will be less than the preset value of the latch circuit 141~142 (Ie, the latch bits of the latch circuits 141 to 142 are "0"). Therefore, the latch reading circuit 150 of this embodiment determines the memory cell 112 when the latch bits in the latch circuits 141 to 143 are "0", "0", or "1". Store the data with "10" status.

The lower left part (C) of FIG. 2 is used to show that the memory cell 112 stores data "01", and the latch bits in the latch circuits 141 to 143 are sequentially expressed as "0" during the read charge time, "1", "1". In this embodiment, the output voltage of the memory cell 112 storing the "01" state is set to be greater than the output voltage of the memory cell 112 in the "00" and "10" states, but higher than the output voltage of the memory cell 112 in the "11" state The output voltage of the cell 112 is small. That is, part (C) indicates that the total current TI3 of the "10" state will be greater than the total current TI1 of the part (A) and the total current TI2 of the part (B), but less than the total current TI4 of the part (D) . In this way, the shunted currents I3 and I2 in part (C) will be larger than the currents I3 and current I2 in parts (A) and (B), making it easier for the latch circuits 142 to 143 to operate in Read that the charging voltage during the charging time is greater than its critical voltage. This embodiment can be designed so that the charging voltage stored in the latch circuits 142~143 during the read charging time will be greater than the threshold voltage preset by the latch circuits 142~143 (that is, the latch circuits 142~143 The bit is “1”), but the charging voltage stored by the latch circuit 141 during the same read charging time will be less than the threshold voltage preset by the latch circuit 141 (that is, the latch bit of the latch circuit 141 Is "0"). As a result, the latch read circuit 150 of this embodiment reads the latches in the latch circuits 141 to 143 When the stored bits are "0", "1", or "1", it is determined that the memory cell 112 stores data in the "01" state.

The lower right part (D) of FIG. 2 is used to show that the memory cell 112 stores data "01", and the latch bits in the latch circuits 141 to 143 in the read charge time are sequentially expressed as "1", "1", "1". In this embodiment, the output voltage of the memory cell 112 that stores the "11" state is set to the maximum output voltage relative to the other states, which means that the total current in the "11" state is shown in part (D) TI4 will be greater than the total current TI1~TI3 of the states "00", "10" and "01" in parts (A) to (C). Since the total current TI4 will also be divided to become the currents I1~I3 flowing through the paths P1~P3, the charging voltage stored by each latch circuit 141~143 during the read charging time will be greater than that of the latch circuit 141~143 The preset threshold voltage makes the latch bit of each latch circuit 141-143 all be "1". Therefore, the latch reading circuit 150 of this embodiment determines the memory cell 112 when the latch bits in the latch circuits 141 to 143 are "1", "1", and "1". Store the data with "11" status.

μA，並且鎖存電路143在讀取充電時間T後的鎖存位元為”1”；當圖2(D)中加總電流TI4設定為100μA時，圖2(D)中電流I1則可計算其為(100μA×

μA，且鎖存電路141在讀取充電時間T後的鎖存位元 為”1”。如此一來，基於鎖存電路141與143具有相同的臨界電壓的情況下，圖2(B)中電流I3在讀取充電時間T中所累積出來的充電電壓將會超過鎖存電路143的臨界電壓，且圖2(D)中電流I1在讀取充電時間T中所累積出來的充電電壓將會超過鎖存電路141的臨界電壓。因此，可藉由下述方程式(1)約略計算出讀取充電時間T的數值：

Those applying this embodiment can set the respective impedance values R1 to R3 of the impedance units 131 to 133 according to the aforementioned requirements. This embodiment uses the following example to explain how to easily derive the aforementioned impedance values R1 to R3. Suppose here that the reading charge time is expressed as T; when the total current T12 in Figure 2(B) is set to 10 microamperes (μA), the current I3 in Figure 2(B) can be calculated as

μA, and the latch bit of the latch circuit 143 after reading the charging time T is "1"; when the total current TI4 in Figure 2 (D) is set to 100 μA, the current I1 in Figure 2 (D) can be Calculate it as (100μA×

μA, and the latched bit of the latch circuit 141 after reading the charging time T is "1". In this way, based on the situation that the latch circuits 141 and 143 have the same threshold voltage, the charging voltage accumulated by the current I3 in the read charging time T in FIG. 2(B) will exceed the threshold of the latch circuit 143 The charging voltage accumulated by the current I1 in the reading charging time T in FIG. 2(D) will exceed the threshold voltage of the latch circuit 141. Therefore, the value of the read charging time T can be roughly calculated by the following equation (1):

In this way, the corresponding relationship between the read charging time T and the impedance values R1~R3 can be known through the aforementioned calculation method.

On the other hand, those applying this embodiment can also design the impedance values R1 to R3 in the impedance elements 131 to 133 to the same value, and the corresponding threshold voltages in the latch circuits 141 to 143 are designed to be different from each other. Therefore, as long as the latch circuits 141 to 143 can generate corresponding latch bit states through the corresponding current during the read charging time T, the embodiments of the present invention can also be implemented.

The embodiment in FIG. 2 is an embodiment in which a multi-level cell (MLC) is used as a memory cell, that is, the number of bits stored in the memory cell is two. Therefore, the number of latch circuits 141 to 143 in the reading circuit 120 is equal to 3 (2 minus 1), and the number of impedance elements 131 to 133 is also equal to the number of latch circuits 141 to 143. If a three-level cell (TLC) is used as an embodiment of the memory cell, that is, the number of bits stored in the memory cell is three. Therefore, the number of latch circuits in the read circuit of this embodiment is 7 (2 to the third power minus 1), and the number of impedance elements is equal to the number of latch circuits. If a four-level cell (QLC) is used as an embodiment of the memory cell, That is, the number of bits stored in the memory cell is 4. Therefore, the number of latch circuits in the read circuit of this embodiment is 15 (2 to the 4th power minus 1), and the number of impedance elements is equal to the number of latch circuits. By analogy, when the number of bits stored in the memory cell in accordance with the embodiment of the present invention is N (N is a positive integer greater than or equal to 2), the number of latch circuits is equal to the number of impedance elements, both of which are 2. Minus 1 to the Nth power.

FIG. 3 is a diagram showing the relationship between the data stored in the memory cell 112 and the threshold voltage distribution diagram of the memory cell 112 in the case of using multi-level cells as the memory cell 112 in an embodiment of the present embodiment Schematic. From right to left in the upper part of Figure 3 are the "00" state (marked as (A)), "10" state (marked as (B)), "01" state (marked as (C)) and "11" State (marked as (D)) memory cells 112-1~112-4. The middle part of FIG. 3 is used to show a schematic diagram of the current flowing through the memory cell in each state. The lower part of FIG. 3 shows a distribution diagram of the threshold voltages of the memory cells 112-1 to 112-4. The horizontal axis of the critical voltage distribution diagram in FIG. 3 shows the output voltage of the memory cell in each state. The vertical axis of the critical voltage distribution diagram in FIG. 3 shows the number NUM of memory cells in each state. In other words, the threshold voltage distribution diagram of FIG. 3 is used to present the threshold voltage distribution of the memory cells in the state distribution regions 311 to 314. The state distribution areas 311~314 respectively correspond to the memory cells 112-1~112- in the "00" state (A), "10" state (B), "01" state (C) and "11" state (D) 4.

In this embodiment, the current detection method is used to sense and determine the state of the data in the memory cell 112 at one time, instead of using voltage as in the past. The way of detection. In the past, the voltage detection method can only put a single state distribution area in the erased state of the critical voltage distribution map, and other state distribution areas need to be placed in the programmed state of the critical voltage distribution map. Therefore, because the adjacent state distribution areas in the programmed state are very close, there is still a high probability of misjudgment when the aforementioned voltage detection method is used for the reading operation.

In this embodiment, the read verify judge of the read operation does not need to use the previous negative voltage (negative voltage) type to verify the data in the memory cell 112, so that the MLC type in FIG. 3 In the threshold voltage distribution map of the memory cells, an equal number of state distribution regions 311 to 314 are evenly arranged in a program state (program state) PST and an erase state (erase state) EST. In the critical voltage distribution diagram of the memory cells 112-1~112-4 in FIG. 3, the number of state distribution regions 311~312 in the programmed state PST (that is, 2) is equal to the state distribution region in the erased state EST The number of 313~314 (that is, 2). In other words, in this embodiment, the erasure state EST of the threshold voltage distribution graph may include two or more state distribution regions (eg, state distribution regions 313 to 314). As a result, the adjacent distance d between the state distribution areas 313 to 314 in FIG. 3 of the present embodiment is longer than the conventional voltage detection method, and the number of state distribution areas in the erased state EST can also be increased. , To get rid of the problem that the voltage detection method can only have a single state distribution area in the erased state EST.

FIG. 4 is an example circuit diagram of the latch circuits 141 to 143 in FIG. 1 or FIG. 2. Here, the latch circuit 410 in FIG. 4 is taken as an example circuit of the latch circuits 141 to 143 in FIG. 1 or FIG. 2. The latch circuit 410 is an SR latch. In detail, The latch circuit 410 mainly includes two NAND gates 420 and 430, an input terminal INN and an output terminal OUTN. The input terminal INN of the latch circuit 410 is used to couple to one of the corresponding impedance units 131 to 133 in FIGS. 1 and 2. The output terminal OUTN of the latch circuit 410 is coupled to the latch read circuit 150 of the read circuit 120 in FIG. 1. The first input terminal In11 of the inverter gate 420 is coupled to the input terminal INN of the latch circuit 410, the second input terminal In12 of the inverter gate 420 is coupled to the output terminal Out2 of the inverter gate 430, and the output terminal of the inverter gate 420 Out1 is coupled to the output terminal OUTN of the latch circuit 410. The first input terminal In21 of the inverter gate 430 is coupled to the output terminal Out1 of the inverter gate 420, and the second input terminal In22 of the inverter gate 430 is coupled to the input terminal INN of the latch circuit 410. In other words, the latch circuit 410 can be implemented by a static random access memory (SRAM) cell composed of NAND gates. Thereby, the accumulated charging voltage through the current provided by the input terminal INN of the latch circuit 410 during the reading of the charging time T is sufficient to drive the inverters 420 and 430 so that the voltage value on the output terminal Out1 of the inverter 420 is high. If it is below the threshold voltage, it can be regarded as the latch bit in the latch circuit 410 is "1". On the contrary, the accumulated charging voltage through the current provided by the input terminal INN of the latch circuit 410 during the reading of the charging time T is not enough to drive the inverters 420 and 430 and the voltage value on the output terminal Out1 of the inverter 420 If the voltage is higher than the threshold voltage, it can be regarded that the latch bit in the latch circuit 410 is "0".

FIG. 5 is another example circuit diagram of the latch circuits 141 to 143 in FIG. 1 or FIG. 2. Here, the latch circuit 510 in FIG. 5 is taken as an example circuit of the latch circuits 141 to 143 in FIG. 1 or FIG. 2. The latch circuit 510 is mainly realized by the control of two inverters 520 and 530 combined with multiple transistors (eg, transistors T1 to T3). inverter The input terminal of the 520 and the output terminal of the inverter 530 are coupled to the input terminal INN of the latch circuit 510 through a transistor. The output terminal of the inverter 520 and the input terminal of the inverter 530 are simultaneously coupled to the output terminal OUTN of the latch circuit 510. In other words, the latch circuit 510 can be implemented by a static random access memory cell composed of an inverter and a plurality of transistors. For example, the read signal READ can be used to guide the current provided by the input terminal INN of the latch circuit 510 to the transistor T1 to determine whether the transistor T1 is turned on. In addition, the charge on the output terminal OUTN of the latch circuit 510 can be removed by coupling to the ground by the reset signal RESET, thereby resetting the latch circuit 510 (that is, the output terminal OUTN of the latch circuit 510 is reset). The voltage on is cleared to 0).

FIG. 6 is an exemplary circuit diagram of the latch reading circuit 150 in FIG. 1. This embodiment uses a circuit for reading static random access memory (SRAM) cells as a suitable example of the latch reading circuit 150. The latch reading circuit 150 includes a plurality of transistors T11 to T13 and T21 to T23 and inverters INV1 to INV4. The transistor T21 is controlled by the read signal RWL1, so that when the read signal RWL1 is enabled, the latched bit in the latch circuit 141 is guided to the inverter INV1 through the transistor T21 and the read bit line RBL ~INV4 for temporary storage and reading; transistor T22 is controlled by the read signal RWL2, so that when the read signal RWL2 is enabled, the latched bit in the latch circuit 142 passes through the transistor T22 and the read bit line RBL is guided to inverters INV1~INV4 for temporary storage and reading; transistor T23 is controlled by the read signal RWL3, so that when the read signal RWL3 is enabled, the latch bit in the latch circuit 143 passes through The transistor T23 and the read bit line RBL are guided to the inverters INV1~INV4 for temporary storage and reading. The latch read circuit 150 of this embodiment is based on the read latch circuits 141 to 143 and judges To read whether the latch bit is "0" or "1", the application of this embodiment can also use other circuit structures to simultaneously read the latch bits in the read latch circuits 141 to 143 in a parallel manner. "0" or "1".

FIG. 7 is a schematic diagram of the data storage device 100 implemented by a volumetric volume circuit (3DIC) in an embodiment of this embodiment. In FIG. 7, the memory array 110 of the data storage device 100 can be originally implemented by means of a volumetric circuit, and the global bit line GBL can be arranged where it is coupled with the reading device 120. The impedance units 131 to 133, the latch circuits 141 to 143, and the latch read circuit 150 of the reading device 120 can all be arranged above the memory array 110, so that the data storage device 100 can be easily realized by a volumetric circuit. .

FIG. 8 is a flowchart of a control method of a data storage device in an embodiment of this embodiment. This control method 800 is applicable to the data storage device 100 in FIG. 1 and FIG. 2. That is, referring to FIG. 1, the data storage device 100 includes a memory array 110. The memory array 110 includes at least one memory cell 112 and a global bit line GBL. Each memory cell stores multiple bits.

Referring to FIGS. 1 and 8, in step S810, during the reading of the charging time of the reading operation, the output terminal of the selected memory cell 112 is coupled to the global bit line GBL. The input PIN of the reading device 120 is configured to be coupled to the global bit line GBL. The reading device 120 includes impedance elements 131 to 134 and latch circuits 141 to 143. The first ends of the impedance elements 131 to 134 are mutually coupled to the input terminal PIN of the reading device 120. The input terminal of each latch circuit 141-143 is respectively coupled to the second terminal of each corresponding impedance element 131-134. Each latch circuit 141~143 has a corresponding threshold voltage. Pressure. In step S820, after the aforementioned charging time is read, the respective latch bits in the latch circuits 141 to 143 are read. In step S830, the data stored in the memory cell is determined according to the read latch bits in the latch circuits 141 to 143. The control method 800 can also be referred to as a method for reading memory cells in a data storage device. For detailed operations of the control method 800, please refer to the foregoing embodiments.

In summary, the data storage device and its control method according to the embodiment of the present invention reads the threshold voltage and the preset voltage of the memory cell multiple times by adjusting the circuit structure in the reading device. Compared with each other, the current detection method is used in this embodiment to sense and determine the data in the cell at one time. That is to say, the embodiment of the present invention adjusts the impedance value of each impedance element in the reading device and/or the threshold voltage of the latch circuit, so that the corresponding latch circuit flows through the corresponding The current of the impedance element is charged, and then the internal latch bit is adjusted. In this way, the embodiment of the present invention can reduce the number of times to read multi-level cells during a read operation, and improve the service life and reliability of memory cells.

100: Data storage device

110: memory array

112: memory cell

120: Reading device

131~133: Impedance unit

141~143: latch circuit

150: latch read circuit

SL: select line

Sgs: Source selection gate

Sgd: Drain extreme selection gate

BL0~BL2: bit line

WL0~WLM: character line

R1~R3: Impedance value of impedance unit

I1~I3: current

P1~P3: path

PIN: the input terminal of the reading device

GBL: Global bit line

Claims (16)

A data storage device includes: a memory array, including at least one memory cell and a global bit line, each memory cell stores a plurality of bits and is selectively connected to the global bit line; and read A device in which the input terminal of the reading device is coupled to the global bit line, wherein the reading device includes: a plurality of impedance elements, wherein the first end of each impedance element is mutually coupled to the input terminal of the reading device Multiple latch circuits, wherein the input end of each latch circuit is respectively coupled to the second end of each corresponding impedance element; and a latch read circuit, coupled to the output end of the latch circuits, to read Fetch the respective latch bits in the latch circuits, wherein the data stored in the at least one memory cell is read by the latch read circuit and the latch bits in the latch circuits To judge. The data storage device according to claim 1, wherein each latch circuit has a corresponding threshold voltage, wherein each latch circuit passes through the corresponding impedance element during the read charging time of the read operation The current is charged, and the respective latch bit in each latch circuit is adjusted according to the charging voltage charged during the read charging time and the corresponding threshold voltage. The data storage device according to claim 1, wherein the impedance value in each impedance element is different, and the corresponding threshold voltages in the latch circuits are the same value. The data storage device according to claim 1, wherein the impedance values in the impedance elements are the same value, and the corresponding threshold voltages in the latch circuits are different from each other. The data storage device according to claim 1, wherein the number of bits stored in each memory cell is N, where N is a positive integer greater than or equal to 2, and the number of latch circuits is equal to the impedance The number of components is 2 to the Nth power minus 1. The data storage device according to claim 1, wherein the memory array is a NAND or NOR memory array. The data storage device according to claim 1, wherein the impedance elements are resistors. The data storage device according to claim 1, wherein the latch circuits are static random access memory (SRAM) cells. The data storage device according to claim 1, wherein, in the threshold voltage distribution diagram of the at least one memory cell, the number of state distribution regions in the program state is equal to that in the erase state The number of state distribution areas. A control method of a data storage device, wherein the data storage device includes a memory array and a reading device, the memory array includes at least one memory cell and a global bit line, and each memory cell stores a plurality of bits , The control method includes: when the charging time of the reading operation is read, the selected at least one memory The output terminal of the cell is coupled to the global bit line, wherein the input terminal of the reading device is configured to be coupled to the global bit line, the reading device includes a plurality of impedance elements and a plurality of latch circuits, each The first end of the impedance element is mutually coupled to the input end of the reading device, the input end of each latch circuit is respectively coupled to the second end of each corresponding impedance element, and each latch circuit has a corresponding Threshold voltage; after the read charging time, read the respective latch bits in the latch circuits; and determine the at least one latch bit in the latch circuits that are read Data stored in memory cells. The control method according to claim 10, wherein each latch circuit has a corresponding threshold voltage, and the control method further includes: during the read charging time, each latch circuit flows through each corresponding The current of the impedance element is charged, and the respective latch bit in each latch circuit is adjusted according to the charging voltage charged during the read charging time and the corresponding threshold voltage. The control method according to claim 10, wherein the impedance value in each impedance element is different, and the corresponding threshold voltages in the latch circuits are the same value. The control method according to claim 10, wherein the impedance values in the impedance elements are the same value, and the corresponding threshold voltages in the latch circuits are different from each other. The control method according to claim 10, wherein the non-volatile memory array is a NAND or NOR memory array. The control method according to claim 10, wherein the impedance elements are multiple resistors. The control method according to claim 10, wherein the latch circuits are static random access memory (SRAM) cells.

Images