TWI736495B - Program method for memory device - Google Patents

Abstract

A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program cycle. The program method comprising performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell.

Description

Programming method for memory device

This disclosure relates to a programming method for a memory device, and more particularly relates to a programming method for a 3-dimentional memory device.

As the critical size of the components in the integrated circuit gradually shrinks to the limit of the process technology, designers have begun to look for technologies that can achieve greater memory density, thereby achieving lower costs per bit. However, as the technology trend develops towards reducing the size and spacing of the memory cells, the problem of program interference during the programming operation of the memory cells becomes more and more serious.

Therefore, it is very important to reduce the problem of program disturbance when the memory device is programmed.

This disclosure relates to a programming method for a memory device.

According to one aspect of the present disclosure, a programming method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line electrically connected to the plurality of memory cells, and a plurality of character lines. When the memory device is in a programming operation, a plurality of memory cells include One selected memory cell and multiple unselected memory cells. The programming method includes: performing multiple precharging steps, performing multiple programming steps, and performing a verification step on the selected memory cell after the precharging step and the programming step. Each precharging step includes applying a precharging voltage to the bit lines electrically connected to unselected memory cells. Each programming step includes applying a programming voltage to the word lines electrically connected to the selected memory cell among the plurality of word lines.

According to another aspect of the present disclosure, a programming method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and a plurality of character lines electrically connected to the plurality of memory cells. When the memory device is in a programming operation, the plurality of memory cells include a selection memory cell and a plurality of unselected memory cells. Choose memory cells. The programming method includes: performing a first precharging step, performing a first programming step, performing a plurality of second precharging steps, and performing a plurality of second programming steps. The first precharging step includes applying a precharging voltage to the bit lines electrically connected to the unselected memory cells. The first programming step includes applying a first programming voltage to the word lines electrically connected to the selected memory cell among the plurality of word lines. Each second precharging step includes applying a precharging voltage to the bit lines electrically connected to the unselected memory cells. Each second programming step includes applying a second programming voltage to the word lines electrically connected to the selected memory cell among the plurality of word lines. The second programming voltage is different from the first programming voltage.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

101: First memory serial

102: second memory serial

201,202,301~303,604,609,613,618,622,626: pre-charge steps

211,212,311~313,601,606,611,615,620,624,628: programming steps

231~234,331~336,602,605,607,610,612,614,616,619,621,623,625,627,629: processing steps

222,322,603,608,617,630: verification steps

BL_1, BL_2: bit line

CSL: Common Source Line

DWLB0, DWLB1, DWLT0, DWLT1: Dummy character line

GSL: Ground selection line

MC_01, MC_11, MC_231, MC_241, MC_251, MC_461, MC_471, MC_02, MC_12, MC_232, MC_242, MC_252, MC_462, MC_472: memory cells

S1, S1_1, S2, S2_1, S3, S3_1, S4, S4_1: programming phase

SSL_1,SSL_2: serial selection line

T1~T8: time point

V _a : pulse voltage

V _dmy1 ,V _dmy2 : dummy voltage

V _pass : pass voltage

V _pgm , V _pgm 1, V _pgm 2, V _pgm 3, V _pgm 4: programming voltage

V _pgm 1_1, V _pgm 2_1, V _pgm 3_1, V _pgm 4_1: programming voltage

V _pre : precharge voltage

WL0~WL47: Character line

Figure 1 shows the memory device; Fig. 2A shows a programming method for a memory device according to an embodiment; Fig. 2B shows a voltage timing diagram of a programming method for a memory device according to an embodiment; Fig. 3 shows an implementation according to an embodiment Example of a programming method for a memory device; Figure 4 shows a test result of a memory cell programmed with the programming method of an embodiment; Figure 5 shows a test result of a memory cell programmed with the programming method of an embodiment Results; Figure 6 shows a programming method for a memory device according to an embodiment; and Figure 7 shows a programming method for a memory device according to an embodiment.

In the embodiment of the present disclosure, a programming method for a memory device is proposed, which can reduce the programming interference of the memory device. The programming method can be used for three-dimensional memory devices, such as three-dimensional NAND flash memory.

It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn in proportion to the actual products. Therefore, the contents of the description and illustrations are only used to describe the embodiments, rather than to limit the scope of protection of this disclosure. In addition, the descriptions in the embodiments, such as detailed structure, process steps, material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of protection of the present disclosure. Details of the steps and structure of the embodiment The section can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of this disclosure. In the following description, the same/similar symbols represent the same/similar elements.

Furthermore, the ordinal numbers used in the specification and the scope of the patent application, such as the terms "first", "second", "third", etc., are used to modify the elements or steps of the claim, and they do not imply or represent the The requested component or step has any previous ordinal number, and it does not represent the order of a requested component or step and another requested component or step, or the order of execution. The use of these ordinal numbers is only used to make A requested component or step with a certain name can be clearly distinguished from another requested component or step with the same name.

In addition, the term "electrical connection" in the specification and the scope of the patent application can mean that multiple elements form an ohmic contact, that current flows between multiple elements, or that multiple elements are operationally related. sex. The operational relevance can be, for example, that one element is used to drive another element, but the current may not directly flow between the two elements. For example, the bit line electrically connected to the memory cell can represent the bit line used to drive the memory cell, that is, when the voltage applied to any bit line changes, it acts on the bit line electrically connected to this bit line. The electric field value of the memory cell can be changed accordingly. For another example, a character line electrically connected to a memory cell can represent a character line used to drive the memory cell, that is, when the voltage value applied to any character line changes, it acts on the memory electrically connected to this character line The electric field value of the cell can be changed accordingly.

The memory device suitable for the programming method of the present disclosure may include multiple memory strings, multiple bit lines, multiple string selection lines, and multiple characters Word lines, multiple ground selection lines, and multiple common source lines (common source lines). For ease of description, Figure 1 only exemplarily shows two memory series.

Figure 1 shows the memory device. The memory device includes a first memory series 101, a second memory series 102, a plurality of bit lines BL, a plurality of serial selection lines SSL, a plurality of word lines WL, a ground selection line GSL, and a common source line CSL. The first memory string 101 is different from the second memory string 102, and the first memory string 101 is adjacent to the second memory string 102.

The first memory string 101 includes a plurality of memory cells MC (MC_01, MC_11...MC_231, MC_241, MC_251...MC_461, MC_471) electrically connected in series with each other. The second memory string 102 includes a plurality of memory cells MC (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) electrically connected in series with each other. The multiple character lines WL include a character line WL0 electrically connected to the memory cell MC_01 and the memory cell MC_02, a word line WL47 electrically connected to the memory cell MC_471 and the memory cell MC_472, and sequentially arranged on the word line WL0 A plurality of character lines WL1-WL46 between the character line WL47, the memory cell MC_01 and the memory cell MC_02 are respectively arranged at the lower end of the first memory string 101 and the second memory string 102, the memory cell MC_471 and the memory cell The cell MC_472 is respectively arranged at the upper end of the first memory string 101 and the second memory string 102. Each of the word lines WL1-WL46 is electrically connected to each of the memory cells MC_11...MC_231, MC_241, MC_251...MC_461 of the first memory string 101, respectively. Each of the word lines WL1-WL46 is electrically connected to each of the memory cells MC_12...MC_232, MC_242, MC_252...MC_462 of the second memory string 102, respectively.

The first memory string 101 is electrically connected between the bit line BL_1 and the common source line CSL. The second memory string 102 is electrically connected between the bit line BL_2 and the common source line CSL. Specifically, the channel line of the first memory string 101 is electrically connected between the bit line BL_1 and the common source line CSL, and the channel line of the second memory string 102 is electrically connected to the bit line BL_2 and Between common source lines CSL. In one embodiment, the first memory string 101 and the second memory string may be electrically connected to the same bit line. The serial selection line SSL_1 and the ground selection line GSL are electrically connected to opposite ends of the first memory string 101. The serial selection line SSL_2 and the ground selection line GSL are electrically connected to opposite ends of the second memory string 102. Specifically, the serial selection line SSL_1 is electrically connected between the bit line BL_1 and the memory cell MC_471 of the first memory string 101; the serial selection line SSL_2 is electrically connected between the bit line BL_2 and the second memory Between the memory cells MC_472 of the series 102; the ground selection line GSL is electrically connected between the common source line CSL and the memory cell MC_01 of the first memory series 101 and is electrically connected to the common source line CSL and the second Between the memory cells MC_02 of the memory string 102. In one embodiment, the memory device may include a plurality of serial select lines SSL electrically connected between the bit line BL_1 and the memory cell MC_471, and/or electrically connected between the bit line BL_2 and the memory cell MC_472. The memory device may further include dummy word lines DWLT0, DWLT1 disposed between the word line WL47 and the bit line BL, and dummy word lines DWLB0 disposed between the word line WL0 and the common source line CSL ,DWLB1.

When the memory device shown in FIG. 1 is during the programming operation, one of the multiple memory cells MC is selected for programming, and the other memory cells MC can be understood as unselected memory cells. For example, the memory cell MC_241 is selected and can be understood as a selected memory cell, Other memory cells (ie memory cells MC_01, MC_11...MC_231, MC_251...MC_461, MC_471 and MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) can be understood as unselected memory cells, The first memory string 101 including the selected memory cell (MC_241) can be understood as the selected memory string, and includes unselected memory cells (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) The second memory series 102 can be understood as an unselected memory series.

During the programming operation, the programming method of the present disclosure includes performing one or more precharging steps on the unselected memory cells (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) of the second memory string 102 , To close the unselected memory cells of the second memory string 102 (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472), and suppress the unselected memory cells of the second memory string 102 ( MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) programming. During the programming operation, the programming method further includes performing more than one programming steps on the selected memory cell (MC_241) of the first memory string 101 to program the selected memory cell (MC_241). Each precharge step is performed before each programming step. During the programming operation, the programming method further includes a verification step on the selected memory cell (MC_241) after the precharge step and the programming step to verify whether the selected memory cell (MC_241) is properly programmed.

Please refer to Figure 1, Figure 2A and Figure 2B at the same time. FIG. 2A shows a programming method for a memory device according to an embodiment. FIG. 2B is a voltage (or bias) timing diagram of the programming method for the memory device shown in FIG. 2A. The vertical axis of Figure 2B represents the character line WL24 and the electrical Connect to unselected memory cells (MC_01, MC_11...MC_231, MC_251...MC_461, MC_471 and MC_02, MC_12...MC_232, MC_252...MC_462, MC_472) character lines WL0-WL23, WL25-WL47 , Dummy word lines DWLT0, DWLT1, DWLB0, DWLB1, serial selection line SSL_2, electrically connected to unselected memory cells in the second memory series 102, and the voltage (or bias) of the bit line BL_2 . The horizontal axis of Figure 2B represents time, which can include time point T1, time point T2... to time point T8 in sequence.

The programming method for the memory device includes performing a plurality of precharge steps 201, 202, performing a plurality of programming steps 211, 212, and performing a verification step 222 after the plurality of precharge steps 201, 202 and the plurality of programming steps 211, 212 during the programming operation. The programming method may further include, during the programming operation, the processing step 231 between the precharging step 201 and the programming step 211, the processing step 232 between the programming step 211 and the precharging step 202, and the precharging step 202. The processing step 233 between the programming step 212 and the programming step 212 and the processing step 234 between the programming step 212 and the verifying step 222 are performed. Specifically, the pre-charging step 201, the processing step 231, the programming step 211, the processing step 232, the pre-charging step 202, the processing step 233, the programming step 212, the processing step 234, and the verification step 222 can be performed in sequence.

For example, the pre-charging step 201 may include during the period from time T1 to time T2 (the first pre-charging period), for unselected memory cells (MC_02, MC_12..) electrically connected to the second memory string 102.. MC_232, MC_242, MC_252...MC_462, MC_472) bit lines BL_2 apply a precharge voltage V _pre to increase the channel voltage of the second memory string 102, and during the period from time T1 to time T2 V _a pulse voltage is applied to the serial select lines SSL_2, so that the second memory 102 is connected to bit line series BL_2. In the precharging step 201, the word lines WL0-WL47 and the dummy word lines DWLT0, DWLT1, DWLB0, DWLB1 may be 0 volts (V). _{The programming step 211 may include applying a programming voltage V pgm} to the word line WL24 electrically connected to the selection memory cell (MC_241) during the period from time T3 to time T4 (the first programming period) to program the selection memory cell _{(MC_241), and the pass} voltage Vpass is applied to the word lines WL0-WL23, WL25-WL47 during the period from the time point T3 to the time point T4. In one embodiment, the pass voltage V _{pass is} less than the programming voltage V _pgm . In the programming step 211, the dummy voltage V _{dmy1 is} applied to the dummy word lines DWLT0 and DWLB1, and the dummy voltage V dmy2 is applied to the dummy word lines DWLT1 and _DWLB0 . In the programming step 211, the serial selection line SSL_2 and the bit line BL_2 can be 0 volts.

The pre-charging step 202 may include during the period from time T5 to time T6 (the second pre-charging period), for unselected memory cells (MC_02, MC_12...MC_232) electrically connected to the second memory string 102 , MC_242, MC_252...MC_462, MC_472) apply a precharge voltage V _pre to the bit line BL_2 to increase the channel voltage of the second memory string 102, and the string is applied during the period from time T5 to time T6 applying a column select line SSL_2 pulse voltage V _a, the second memory so that the bit line 102 is connected in series BL_2. In the precharging step 202, the word lines WL0-WL47 and the dummy word lines DWLT0, DWLT1, DWLB0, DWLB1 may be 0 volts. _{The programming step 212 may include applying a programming voltage V pgm} to the word line WL24 electrically connected to the selection memory cell (MC_241) during the period from time T7 to time T8 (the second programming period) to program the selection memory cell _{(MC_241), and the pass} voltage Vpass is applied to the word lines WL0-WL23, WL25-WL47 during the period from the time point T7 to the time point T8. In the programming step 212, the dummy voltage V _{dmy1 is} applied to the dummy word lines DWLT0 and DWLB1, and the dummy voltage V dmy2 is applied to the dummy word lines DWLT1 and _DWLB0 . In the programming step 212, the serial select line SSL_2 and the bit line BL_2 can be 0 volts. The dummy voltage V _dmy1 may be greater than the dummy voltage V _dmy2 . Dummy voltage value _V dmy1 the dummy voltage _V dmy2 may be a value of the pulse voltage V _a sum between a value of the voltage V _pass.

The processing step 231 may be performed during the time period from the time point T2 to the time point T3. The processing step 232 may be performed during the time period from the time point T4 to the time point T5. The processing step 233 may be performed during the time period from the time point T6 to the time point T7. The processing step 234 may be performed after the time point T8. The verification step 222 can be performed after the time point T8 and after the processing step 234.

In one embodiment, the precharge voltage V _pre may be 4V, the pulse voltage V _a may be 3V, the program voltage V _pgm may be 24V, the pass voltage V _pass may be 8V, dummy voltage _V dmy1 the dummy voltage _V dmy2 Can be between 3V and 8V. The first precharge period may be equal to the second precharge period. For example, the first precharge period and the second precharge period may be 6 microseconds (μs). The first precharge period may be different from the second precharge period, for example, the first precharge period may be 7 microseconds, and the second precharge period may be 5 microseconds. In one embodiment, the precharge voltage V _pre used in different precharge steps can be a fixed value.

FIGS. 2A and 2B show a programming method including two precharge steps and two programming steps before a verification step during the programming operation. However, the programming method may include more verification steps and more programming steps. For example, the programming method may include N precharge steps and N programming steps, each of the N precharge steps is performed before each of the N programming steps, and N is greater than 1. In an embodiment, each of the N precharge steps may include applying a precharge voltage V _pre to the bit line BL_2 during a precharge period, and each of the N programming steps may include a program period _{The programming voltage V pgm is} applied to the word line WL24 electrically connected to the selected memory cell (MC_241). The precharge period decreases as the value of N increases, and the programming period decreases as the value of N increases. In one embodiment, the precharge period is inversely proportional to the N value, and the programming period is inversely proportional to the N value. For example, when the N value is equal to 2, the precharge period can be 6 microseconds, and the programming period can be 6 microseconds; when the N value is 3, the precharge period can be 4 microseconds and the programming period can be 4 microseconds; when N The value is equal to 6, the precharge period can be 2 microseconds, and the programming period can be 2 microseconds. This disclosure is not limited to this. In an embodiment, any verification step may not be included between the N precharge steps, and/or any verification step may not be included between the N programming steps. For example, the pre-charging step 201 and the pre-charging step 202 do not include any verification step, and/or the programming step 211 and the programming step 212 do not include any verification step.

FIG. 3 shows a programming method for a memory device according to another embodiment. The programming method may include performing three pre-charge steps 301, 302, 303 and three programming steps 311, 312, 313 (N=3) before the verification step 322 during the programming operation. In the programming method shown in Figure 3, the precharge step 301, the processing step 331, the programming step 311, the processing step 332, the precharging step 302, the processing step 333, the programming step 312, the processing step 334, the precharging step 303, The processing step 335, the programming step 313, the processing step 336, and the verification step 322 can be performed sequentially. The pre-charging steps 301, 302, and 303 can be similar to the pre-charging steps 201, 202 shown in Fig. 2A and Fig. 2B, except that the pre-charging period is different. The programming steps 311, 312, 313 can be similar to the programming steps 211, 212 shown in Figure 2A and Figure 2B, except that the programming steps The duration of the journey is different. In one embodiment, the precharge steps 301, 302, and 303 can be performed during the precharge period of 4 microseconds, and the programming steps 311, 312, and 313 can be performed during the program period of 4 microseconds.

Fig. 4 shows the test result of the memory cell programmed by the programming method of an embodiment. In the comparative example, during the programming operation, the programming method only includes one pre-charging step (N=1), this pre-charging step is performed before a verification step, and the pre-charging step is performed with a pre-charging period of 12 microseconds. In Embodiment 1, during the programming operation, the programming method includes two precharge steps (N=2). The two precharge steps are performed before a verification step, and each precharge step is precharged in 6 microseconds. During the period. In Embodiment 2, during the programming operation, the programming method includes three pre-charging steps (N=3), the three pre-charging steps are performed before a verification step, and each pre-charging step is pre-charged in 4 microseconds. During the period. In Embodiment 3, during the programming operation, the programming method includes six pre-charging steps (N=6). The six pre-charging steps are performed before a verification step, and each pre-charging step is pre-charged in 2 microseconds. During the period. As shown in FIG. 4, compared with the comparative example, the program disturb suppression of the embodiment 1 to the embodiment 3 is better. Specifically, the program disturb suppression of Embodiment 3 is better than the program disturb suppression of Embodiment 2, and the program disturb suppression of Embodiment 2 is better than the program disturb suppression of Embodiment 1.

Figure 5 shows the test results of the memory cells programmed with the programming methods of Comparative Example and Examples 1 to 3. As shown in Figure 5, the program capabilities of Comparative Example and Example 1 to Example 3 are similar. In other words, the programming method provided in the present disclosure can improve the suppression effect of programming disturbance and still maintain the programming ability.

Please refer to Figure 1 and Figure 6 at the same time. Fig. 6 shows a programming method for a memory device according to another embodiment. When the memory device shown in FIG. 1 is during the programming operation, one of the multiple memory cells MC is selected for programming, and the other memory cells MC can be understood as unselected memory cells. For example, the memory cell MC_241 is selected and can be understood as the selected memory cell, other memory cells (ie memory cells MC_01, MC_11...MC_231, MC_251...MC_461, MC_471 and MC_02, MC_12...MC_232, MC_242, MC_252 ...MC_462, MC_472) can be understood as unselected memory cells, and the first memory string 101 including the selected memory cell (MC_241) can be understood as the selected memory string and includes the unselected memory cell (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) of the second memory series 102 can be understood as an unselected memory series.

The programming method may include applying a series of increasing programming voltages during the programming operation to program the selected memory cell (MC_241). In a series of programming voltages, the programming voltage may (but not limited to) gradually increase; that is, the programming voltage may increase by a fixed difference. The programming method may include multiple programming stages. Each programming stage corresponds to a programming voltage in a series of programming voltages. Each programming stage includes a verification step for the selected memory cell (MC_241) and at least one programming step earlier than the verification step. The programming step includes applying corresponding programming to the word line WL24 electrically connected to the selected memory cell (MC_241) Voltage. For ease of description, Figure 6 only exemplarily shows four programming stages.

In Figure 6, the programming method includes programming stages S1, S2, S3, and S4 that are sequentially performed. Each programming stage S1, S2, S3, S4 corresponds to each programming voltage V _pgm 1, V _pgm 2, V _pgm 3, V _pgm 4, respectively. In this embodiment, the programming voltage can be gradually increased by the difference of x volts (x is greater than 0). In other words, the programming voltage V _pgm 2 can be understood as V _pgm 1+x, and the programming voltage V _pgm 3 can be understood as V _pgm 1+ 2x, the programming voltage V _pgm 4 can be understood as V _pgm 1+3x.

The programming stage S1 includes a programming step 601 and a verification step 603 after the programming step 601. The programming stage S1 may further include a processing step 602, which is performed between the programming step 601 and the verification step 603. _{The programming step 601 may include applying a programming voltage V pgm} 1 to the word line WL24 electrically connected to the selection memory cell (MC_241) to program the selection memory cell (MC_241). The verification step 603 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed.

If the verification step 603 of the programming phase S1 fails (indicating that the selected memory cell is not successfully programmed), the programming phase S2 will continue, and the programming phase S2 includes an increased programming voltage V _pgm 2 and a precharge step. The programming stage S2 may include a precharging step 604, a processing step 605, a programming step 606, a processing step 607, and a verification step 608 in sequence. The precharging step 604 may include precharging the bit lines BL_2 of the unselected memory cells (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) electrically connected to the second memory string 102 Voltage V _pre to turn off the unselected memory cells (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472) of the second memory series 102, and suppress the non-selection of the second memory series 102 Programming of memory cells (MC_02, MC_12...MC_232, MC_242, MC_252...MC_462, MC_472). The programming step 606 may include applying a programming voltage V _pgm 2 to the word line WL24 to program the selected memory cell (MC_241). A verification step 608 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed.

If the verification step 608 of the programming phase S2 fails (indicating that the selected memory cell is not successfully programmed), the programming phase S3 will continue, and the programming phase S3 includes, compared to the programming phase S2, a more increased programming voltage V _pgm 3 and more Multiple pre-charge steps. The programming stage S3 may include a pre-charging step 609, a processing step 610, a programming step 611, a processing step 612, a pre-charging step 613, a processing step 614, a programming step 615, a processing step 616, and a verification step 617 in sequence. The precharge step 609 may include applying a precharge voltage V _pre to the bit line BL_2. The programming step 611 may include applying a programming voltage V _pgm 3 to the word line WL24. The pre-charging step 615 may be similar to the pre-charging step 609. The programming step 615 may be similar to the programming step 611. The verification step 617 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed. The programming stage S3 may be similar to the operation mode shown in Fig. 2A and Fig. 2B.

If the verification step 617 of the programming phase S3 fails (indicating that the selected memory cell is not successfully programmed), the programming phase S4 will continue, and the programming phase S4 includes, compared to the programming phase S3, a more increased programming voltage V _pgm 4 and more Multiple pre-charge steps. The programming stage S4 may include sequentially performing a pre-charge step 618, a processing step 619, a programming step 620, a processing step 621, a pre-charge step 622, a processing step 623, a programming step 624, a processing step 625, a pre-charging step 626, and a processing step 627. , A programming step 628, a processing step 629, and a verification step 630. Each pre-charge step 618, 622, 626 may include applying a pre-charge voltage V _pre to the bit line BL_2. Each programming step 620, 624, 628 may include applying a programming voltage V _pgm 4 to the word line WL24. The verification step 630 is performed on the selected memory cell (MC_241) to verify whether the selected memory cell (MC_241) is properly programmed. The programming stage S4 may be similar to the operation mode shown in Figure 3.

In Figure 6, the programming method includes four programming stages. However, the programming method may include more than four programming stages or less than four programming stages. In an embodiment, the programming method may include performing more programming stages after the programming stage S4, and using more increased programming voltages. The programming voltage V _pgm can be incrementally increased in the above-mentioned manner until the selected memory cell (MC_241) is properly programmed, or until the selected memory cell (MC_241) reaches a predetermined threshold voltage. In one embodiment, in a programming phase, any verification step may not be included between the precharge steps, and/or any verification step may not be included between the programming steps. In another embodiment, one programming phase includes only one verification step, and the verification step is performed after all the programming steps of the programming phase are completed.

In Figure 6, the precharge step 604 may include applying a precharge voltage V _pre to the bit line BL_2 during the first precharge period, and each precharge step 609,613 may include applying a precharge voltage V pre to the bit line BL_2 during the second precharge period. The pre-charge voltage V _pre , each pre-charge step 618, 622, 626 may include applying the pre-charge voltage V _pre to the bit line BL_2 during the third pre-charge period. The first precharge period may be longer than the second precharge period, and the second precharge period may be longer than the third precharge period. In an embodiment, the first precharge period may be 12 microseconds, the second precharge period may be 6 microseconds, and the third precharge period may be 4 microseconds. In one embodiment, in a programming phase, the precharge period depends on the number of precharge steps. Specifically, the pre-charging period decreases as the number of pre-charging steps increases. In one embodiment, the precharge voltage V _pre used in different programming stages can be a fixed value.

In Figure 6, the programming step 606 may include applying the programming voltage V _pgm 2 to the word line WL24 during the first programming period, and each programming step 611,615 may include applying the programming voltage V _{pgm to the word line WL24 during the second programming period.} 3. Each programming step 620, 624, 628 may include applying a programming voltage V _pgm 4 to the word line WL24 during the third programming period. The first programming period may be greater than the second programming period, and the second programming period may be greater than the third programming period. In one embodiment, the first programming period can be 12 microseconds, the second programming period can be 6 microseconds, and the third programming period can be 4 microseconds. In one embodiment, in a programming phase, the programming period depends on the number of programming steps. Specifically, the programming period decreases as the number of programming steps increases.

When the programming voltage is low, the programming disturbance may be slight. Therefore, when the programming voltage is low, the precharge step may be unnecessary. For example, in Figure 6, the programming phase S1 does not include a pre-charging step because the programming voltage V _pgm 1 is low.

In one embodiment, the number of programming steps in each programming stage may increase as the programming voltage V _pgm increases, and the programming period in each programming stage may decrease as the programming voltage V _pgm increases. In one embodiment, the number of pre-charge steps in each programming stage can increase as the programming voltage V _pgm increases, and the pre-charge period in each programming stage can decrease as the programming voltage V _pgm increases. The number of precharge steps can be equal to the number of programming steps.

FIG. 7 shows a programming method for a memory device according to an embodiment. The difference between the programming method shown in Figure 7 and the programming method shown in Figure 6 is that the programming method shown in Figure 7 can include more programming stages between the programming stages S1, S2, S3, and S4. For example, the programming method shown in FIG. 7 may include a programming stage S1_1 between the programming stage S1 and the programming stage S2. The programming phase S1_1 is similar to the programming phase S1 except that the programming voltage V _pgm 1_1 used in the programming phase S1_1 is different from the programming voltage V _{pgm 1 used in the programming phase S1.} The programming voltage V _pgm 1_1 is greater than the programming voltage V _pgm 1 used in the programming phase S1 and is smaller than the programming voltage V _pgm 2 used in the programming phase S2. The programming method may include a programming stage S2_1 between the programming stage S2 and the programming stage S3. The programming stage S2_1 is similar to the programming stage S2 except that the programming voltage V _pgm 2_1 used in the programming stage S2_1 is different from the programming voltage V _{pgm 2 used in the programming stage S2.} The programming voltage V _pgm 2_1 is greater than the programming voltage V _pgm 2 used in the programming phase S2 and is smaller than the programming voltage V _pgm 3 used in the programming phase S3. The programming method may include a programming stage S3_1 between the programming stage S3 and the programming stage S4. The programming stage S3_1 is similar to the programming stage S3 except that the programming voltage V _pgm 3_1 used in the programming stage S3_1 is different from the programming voltage V _{pgm 3 used in the programming stage S3.} The programming voltage V _pgm 3_1 is greater than the programming voltage V _pgm 3 used in the programming phase S3 and is smaller than the programming voltage V _pgm 4 used in the programming phase S4. The programming method may include the programming stage S4_1 after the programming stage S4. The programming stage S4_1 is similar to the programming stage S4 except that the programming voltage V _pgm 4_1 used in the programming stage S4_1 is different from the programming voltage V _{pgm 4 used in the programming stage S4.} The programming voltage V _pgm 4_1 is greater than the programming voltage V _pgm 4 used in the programming phase S4.

In an embodiment, the programming method may be between the programming stage S1 and the programming stage S2, and/or between the programming stage S2 and the programming stage S3, and/or between the programming stage S3 and the programming stage S4, and/or programming After stage S4, more than one programming stage is included. _{The programming voltage V pgm} used for multiple programming stages increases with each programming stage.

In one embodiment, the number of precharge steps in each programming phase can correspond to the programming voltage range, that is, when the programming voltage V _pgm used in a programming phase falls within the programming voltage range, the programming phase The number of pre-charge steps in can be a fixed value. In other words, when the programming voltage V _pgm used in a programming phase increases to a specific voltage value, the number of precharge steps in the programming phase will increase. For example, as shown in Figure 7, before reaching the programming voltage V _pgm 2, the number of precharge steps in each of the programming phases S1, S1_1... is maintained at 0; when the programming voltage V _pgm 2, programming The number of pre-charging steps in phase S2 is increased to one. For example, as shown in Figure 7, before reaching the programming voltage V _pgm 3, the number of precharge steps in each of the programming stages S2, S2_1... is maintained at 1; when the programming voltage V _pgm 3 is reached, the programming The number of pre-charging steps in stage S3 is increased to two.

In this embodiment, the number of programming steps in each programming stage can correspond to the programming voltage range, that is, when the programming voltage V _pgm used in a programming stage falls within the programming voltage range, The number of programming steps can be a fixed value. In other words, when the programming voltage V _pgm used in a programming phase increases to a specific voltage value, the number of programming steps in the programming phase will increase. For example, as shown in Figure 7, before reaching the programming voltage V _pgm 3, the number of programming steps in each of the programming phases S2, S2_1... is maintained at 1; when the programming voltage V _pgm 3 is reached, the programming phase The number of programming steps in S3 is increased to 2. The number of precharge steps can be equal to the number of programming steps.

In a comparative example, the programming method includes only one pre-charging step and only one programming step. Since the potential difference between the unselected memory cells may induce band to band leakage, it may occur in the unselected memory series. The local self-boosting phenomenon in the channel of the unselected memory cell in the memory cell may collapse during the programming step. Collapse. In addition, as the programming period of the programming step increases, the collapse of the local self-boost phenomenon will become more serious. The collapse of the local self-boosting phenomenon may reduce the control gate-to-channel potential differences between the control gate-to-channel potential differences of the unselected memory cell, and cause serious programming interference. In contrast, the programming method provided in the present disclosure includes more than one precharge step. Performing more than one precharge step in a programming operation is beneficial to establish a stable local self-boost phenomenon, and can reduce or avoid local self-boost. The collapse of the pressure phenomenon can reduce or suppress programming interference. Moreover, compared to a comparative example of a programming method including only one pre-charge step and only one programming step, the pre-charge step of the programming method of the present disclosure is performed in a short pre-charge period, and the programming step of the programming method of the present disclosure It is done in a short programming period. In a programming operation, a large number of pre-charge steps and a short pre-charge period to perform each pre-charge step are beneficial to efficiently establish a local self-boosting phenomenon, and make the unselected memory cells in a strong state. Disabled. The short programming period is also beneficial to establish a local self-boosting phenomenon and can reduce or suppress programming disturbance. Therefore, through the programming method of the present disclosure, the program interference suppression effect of the memory device can be improved, and the program window can be increased while maintaining the programming ability of the memory device.

The concept according to this disclosure can also be extended to other changes.

The memory string can be a vertical channel structure, or a single gate vertical channel structure, or a vertical gate structure, etc. can be used. The memory cell can be a floating gate memory cell or a nitride capture memory cell, etc. The memory cell may be a single-level memory cell, a multi-level memory cell, or a third-level memory cell, etc.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

201, 202: Pre-charge step

211, 212: Programming steps

231,232,233,234: processing steps

222: Verification Step

Claims (8)

A programming method for a memory device, the memory device comprising a plurality of memory cells, a bit line and a plurality of word lines electrically connected to the plurality of memory cells, when the memory device is in a programming operation, The plurality of memory cells include a selected memory cell and a plurality of unselected memory cells. The programming method includes: performing N precharging steps, each of the N precharging steps includes electrically connecting to each other during a precharging period A precharge voltage is applied to the bit lines of the unselected memory cells, and the precharge period decreases as the N increases; multiple programming steps are performed, and each of the programming steps includes the characters The line is electrically connected to a word line of the selected memory cell to apply a programming voltage; and after the N precharging steps and the programming steps, a verification step is performed on the selected memory cell. The programming method according to claim 1, wherein the N precharging steps include a first precharging step and a second precharging step, and the second precharging step is performed after the first precharging step. The programming step includes a first programming step and a second programming step. The second programming step is performed after the first programming step, and the first programming step is performed between the first precharge step and the second precharge step. between. The programming method according to claim 2, wherein the second programming step is performed between the second precharging step and the verifying step. The programming method according to claim 1, wherein the programming method includes N programming steps, and each of the N programming steps includes a programming period The programming voltage is applied to the word line electrically connected to the selected memory cell, and the programming period decreases as the N increases. A programming method for a memory device, the memory device comprising a plurality of memory cells, a bit line and a plurality of word lines electrically connected to the plurality of memory cells, when the memory device is in a programming operation, The plurality of memory cells include a selected memory cell and a plurality of unselected memory cells. The programming method includes: performing a first pre-charging step. The first pre-charging step includes electrically connecting to the unselected memory cells. A precharge voltage is applied to the bit line; a first programming step is performed, and the first programming step includes applying a word line of the word lines that is electrically connected to the selected memory cell during a first programming period A first programming voltage; performing a plurality of second precharging steps, each of the second precharging steps includes applying the precharging voltage to the bit line electrically connected to the unselected memory cells; and A plurality of second programming steps are performed, and each of the second programming steps includes applying a second programming to the word lines that are electrically connected to the selected memory cell among the word lines during a second programming period Wherein the second programming voltage is different from the first programming voltage, the first programming step is performed before the second programming steps, and the first programming period is greater than the second programming period. The programming method according to claim 5, wherein the first programming voltage is less than the second programming voltage. The programming method according to claim 5, wherein the first precharging step is performed before the second precharging steps, and the first precharging step includes A first precharge period applies the precharge voltage to the bit line, each of the second precharge steps includes applying the precharge voltage to the bit line in a second precharge period, the first A precharge period is longer than the second precharge period. The programming method according to claim 5, wherein the programming method further comprises: performing a plurality of the first pre-charging steps, and each of the plurality of the first pre-charging steps includes a pair of electrical connections to the Select the bit line of the memory cell to apply the precharge voltage; perform a plurality of the first programming steps, and each of the plurality of the first programming steps includes the word lines in the first programming period The word line electrically connected to the selected memory cell applies the first programming voltage, wherein the plurality of the first precharging steps and the plurality of the first programming steps are performed on the second precharging steps and the Before the second programming steps, the number of the first precharge steps is less than the number of the second precharge steps.

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