TWI714909B - High electron mobility transistor device and manufacturing method thereof - Google Patents

Abstract

A high electron mobility transistor (HEMT) device and a manufacturing method thereof are provided. The HEMT device includes a first channel layer, a first barrier layer, a second barrier layer, a first gate electrode, a first drain electrode and a first source electrode. The first channel layer is disposed on a substrate. The first barrier layer is disposed on the first channel layer. The second barrier layer is disposed on the first barrier layer. The second barrier layer has a first opening extending to the first barrier layer. The first gate electrode is disposed on the first barrier layer in the first opening. The first drain electrode and the first source electrode are disposed on the second barrier layer at opposite sides of the first opening.

Description

High electron mobility transistor element and manufacturing method thereof

The present invention relates to a transistor element and a manufacturing method thereof, and particularly relates to a high electron mobility transistor element and a manufacturing method thereof.

High electron mobility transistor (HEMT) is a type of field effect transistor. HEMT includes two kinds of semiconductor materials with different energy gaps, which form a heterojunction and can be used as a conductive channel. Since HEMT has the advantages of low resistance, high breakdown voltage and fast switching frequency, it is widely used in the field of high-power electronic components.

HEMTs can be classified as depletion mode or enhancement mode HEMTs according to whether the channel is normally open or normally closed. Generally speaking, the method of manufacturing an enhanced HEMT includes etching or doping the barrier layer of the heterojunction in the active region. However, the etching may damage the barrier layer, thereby affecting the two dimensional electron gas (2DEG) formed in the underlying channel layer. In addition, regarding doping, the dopants in the barrier layer may diffuse outward due to other high-temperature processes. Therefore, the manufacturing process and reliability of the current enhanced HEMT are limited.

The invention provides a HEMT element and a manufacturing method thereof, which can improve the reliability of an enhanced HEMT.

The HEMT device of the embodiment of the present invention includes a first channel layer, a first barrier layer, a second barrier layer, a first gate, a first drain, and a first source. The first channel layer is disposed on the substrate. The first barrier layer is disposed on the first channel layer. The second barrier layer is disposed on the first barrier layer. The second barrier layer has a first opening extending to the first barrier layer. The first gate is disposed on the first barrier layer in the first opening. The first drain and the first source are respectively disposed on the second barrier layer on opposite sides of the first opening.

In some embodiments, the material of the first barrier layer and the second barrier layer are the same or similar in structure (for example, the first barrier layer is AlGaN and the second barrier layer is AlN, or the first barrier layer is AlN and The second barrier layer is AlGaN), and there is an interface between the first barrier layer and the second barrier layer.

In some embodiments, the HEMT device has a first region and a second region. The first channel layer, the first barrier layer and the second barrier layer are located in the first region and the second region. The first opening of the second barrier layer is located in the first region.

In some embodiments, the HEMT device further includes a second gate, a second drain, and a second source. The second gate, the second drain and the second source are arranged on the second barrier layer and located in the second region. The second gate is located between the second drain and the second source.

In some embodiments, the first barrier layer and the second barrier layer are discontinuous at the interface between the first region and the second region.

In some embodiments, the HEMT device further includes a second channel layer, a third barrier layer, and a fourth barrier layer. The second channel layer is disposed on the second barrier layer and located in the second region. The third barrier layer is disposed on the second channel layer and located in the second region. The fourth barrier layer is disposed on the third barrier layer and located in the second region. The fourth barrier layer has a second opening extending to the third barrier layer.

In some embodiments, the HEMT device further includes a second gate, a second drain, and a second source. The second gate is arranged on the third barrier layer in the second opening. The second drain and the second source are respectively disposed on the fourth barrier layer on opposite sides of the second opening.

In some embodiments, the HEMT device further includes a heavily doped layer. The heavily doped layer is disposed between the fourth barrier layer and the second drain, and between the fourth barrier layer and the second source.

The manufacturing method of the HEMT element of the embodiment of the present invention includes: forming a first channel layer on a substrate; forming a first barrier layer on the first channel layer; forming a first mask pattern on the first barrier layer; A second barrier layer is formed on the portion of the barrier layer exposed by the first mask pattern; the first mask pattern is removed to expose a part of the first barrier layer; the exposed portion of the first barrier layer A first gate is partially formed; and a first drain and a first source are formed on the second barrier layer on opposite sides of the first gate.

In some embodiments, the HEMT device has a first region and a second region. The first channel layer, the first barrier layer and the second barrier layer are located in the first area and the second area, and the first mask pattern is disposed in the first area.

In some embodiments, the manufacturing method of the HEMT device further includes: forming a second gate, a second drain, and a second source on the second barrier layer in the second region. The second gate is located between the second drain and the second source.

In some embodiments, the manufacturing method of the HEMT device further includes: forming a second channel layer on the second barrier layer in the second region; forming a third barrier layer on the second channel layer; and forming a third barrier layer on the third barrier layer. A second mask pattern is formed on the layer; a fourth barrier layer is formed on the portion of the third barrier layer exposed by the second mask pattern; and the second mask pattern is removed to expose the third barrier Part of the layer.

In some embodiments, the manufacturing method of the HEMT element further includes: forming a second gate on the exposed portion of the third barrier layer; and forming a second gate on the fourth barrier layer on opposite sides of the second gate. Drain and second source.

In some embodiments, the manufacturing method of the HEMT device further includes: forming a heavily doped layer on the fourth barrier layer. The heavily doped layer is located between the fourth barrier layer and the second drain, and between the fourth barrier layer and the second source.

Based on the above, the embodiment of the present invention includes forming a second barrier layer having an opening exposing the first barrier layer on the first barrier layer. In this way, the heterojunction that overlaps the opening includes the first barrier layer and the underlying first channel layer, but does not include the second barrier layer. The thickness of the first barrier layer is not enough to enable the heterojunction to generate a conductive channel without applying a bias voltage. Therefore, the heterojunction can be used as an active area of an enhanced (or normally-off) HEMT. In addition, the embodiment of the present invention uses a selective epitaxy method to form the second barrier layer with openings, and the first barrier layer or the second barrier layer is not etched. Therefore, the first barrier layer and the second barrier layer can be prevented from being damaged by etching. Furthermore, the embodiment of the present invention can avoid doping the first barrier layer and the second barrier layer. Therefore, the problem of dopant diffusion due to other high-temperature processes can be avoided. In other words, the reliability of the HEMT element can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1 is a flowchart of a method of manufacturing a HEMT device 10 according to some embodiments of the present invention. 2A to 2I are schematic cross-sectional views of the structure of each stage in the method of manufacturing the HEMT device 10 shown in FIG. 1. In some embodiments, the manufacturing method of the HEMT device 10 (shown in FIG. 2I) may include the following steps.

1 and 2A, step S100 is performed to provide a substrate 100. In some embodiments, the substrate 100 includes a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or the SOI substrate may include elemental semiconductors or compound semiconductors. For example, the elemental semiconductor may include Si or Ge. The compound semiconductor may include SiGe, SiC, SiGeC, III-V group semiconductor materials, or II-VI group semiconductor materials. Group III-V semiconductor materials can include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAS, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdTe, ZnSe, CdZnSe CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. In addition, the semiconductor substrate may be doped into a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N type, and the second conductivity type may be P type. In some embodiments, the substrate 100 may have a first region R1 and a second region R2. In the subsequent steps, the first conductivity type enhancement mode HEMT can be formed in the first region R1, and the first conductivity type depletion mode HEMT or the first conductivity type can be formed in the second region R2. Two conductivity type HEMT.

1 and 2B, step S102 is selectively performed to form a buffer layer 102 on the substrate 100. The buffer layer 102 may be located in the first region R1 and the second region R2. In some embodiments, the buffer layer 102 may substantially completely cover the surface of the substrate 100. In some embodiments, the material of the buffer layer 102 may include a group III nitride or a group III-V compound semiconductor material. For example, the material of the buffer layer 102 may include InAlGaN, AlGaN, AlInN, InGaN, AlN, GaN, or a combination thereof. The formation method of the buffer layer 102 may include an epitaxial process. The thickness of the buffer layer 102 affects the breakdown voltage of the device, and its thickness can range from 800 nm to 10000 nm depending on the device specification. By providing the buffer layer 102, the stress caused by the difference in lattice constants and/or the difference in thermal expansion coefficient between the substrate 100 and the first channel layer 104 (please refer to FIG. 2C) subsequently formed on the substrate 100 can be reduced.

1 and FIG. 2C, step S104 is performed to form a first channel layer 104 on the buffer layer 102. The first channel layer 104 is located in the first region R1 and the second region R2. In some embodiments, the first channel layer 104 may substantially cover the buffer layer 102 completely. In the embodiment where the buffer layer 102 is not formed, the first channel layer 104 may be directly formed on the substrate 100. In some embodiments, the material of the first channel layer 104 may include a group III nitride or a group III-V compound semiconductor material. For example, the material of the first channel layer 104 includes GaN. The method for forming the first channel layer 104 may include an epitaxial process. The thickness of the first channel layer 104 may range from 800 nm to 3000 nm.

1 and 2D, step S106 is performed to form a first barrier layer 106 on the first channel layer 104. The first barrier layer 106 is located in the first region R1 and the second region R2. In some embodiments, the first barrier layer 106 may substantially completely cover the first channel layer 104. In some embodiments, the material of the first barrier layer 106 may include a group III nitride or a group III-V compound semiconductor material. For example, the material of the first barrier layer 106 includes III-nitride or III-V compound semiconductor materials, such as InAlGaN, AlGaN, AlInN, AlN, or a combination thereof. In some embodiments, the material of the first barrier layer 106 is Al _x Ga _1-x N, where x is 0 to 1. In other embodiments, the material of the first barrier layer 106 is In _y Al _z Ga _1-yz N, where y is 0 to 1 and z is 0 to 1. In some embodiments, the method for forming the first barrier layer 106 includes an epitaxial process. In addition, the thickness of the first barrier layer 106 is less than 10 nm, so that the region of the first channel layer 104 close to the first barrier layer 106 does not form two dimensional electron gas (2DEG) at this time. In other words, no conductive channels are formed in the first channel layer 104 at this time. For example, the thickness of the first barrier layer 106 may range from 1 nm to 10 nm.

Please refer to FIG. 1 and FIG. 2E to perform step S108 to form a first mask pattern 108 on the first barrier layer 106. The first mask pattern 108 is located in the first region R1. In some embodiments, the method of forming the first mask pattern 108 includes forming a mask layer (not shown) on the first barrier layer 106 by, for example, a chemical vapor deposition process, and then patterning the mask Layer to form the first mask pattern 108. In some embodiments, the first mask pattern 108 may be a hard mask pattern. For example, the material of the first mask pattern 108 may include silicon oxide, silicon nitride, or a combination thereof. In addition, in some embodiments, the thickness of the first mask pattern 108 may range from 10 nm to 500 nm.

1 and 2F, step S110 is performed to form a second barrier layer 110 on the portion of the first barrier layer 106 exposed by the first mask pattern 108. The second barrier layer 110 is formed in the first region R1 and the second region R2. In some embodiments, the second barrier layer 110 may be formed by an epitaxial process. In these embodiments, only the exposed surface of the first barrier layer 110 will grow epitaxially, but not the surface of the first mask pattern 108. Therefore, the method of forming the second barrier layer 110 by an epitaxial process can also be referred to as a selective epitaxial method. In some embodiments, the thickness of the initially formed second barrier layer 110 may exceed the height of the first mask pattern 108, and may be performed by, for example, chemical mechanical polishing (CMP) or etching back (etching). The back) method thins the second barrier layer 110 so that the surface of the thinned second barrier layer 110 and the top surface of the first mask pattern 108 are substantially coplanar. In these embodiments, the thickness of the thinned second barrier layer 110 and the thickness of the first mask pattern 108 may be substantially the same.

In some embodiments, the first barrier layer 106 and the second barrier layer 110 may be made of the same or similar materials. Nevertheless, since the first barrier layer 106 and the second barrier layer 110 are not formed in the same epitaxial process, an interface F still exists between the first barrier layer 106 and the second barrier layer 110. In some embodiments, the total thickness of the second barrier layer 110 and the first barrier layer may exceed 15 nm, so that the heterogeneity including the first barrier layer 106, the second barrier layer 110 and the first channel layer 104 The junction (hetero junction) HJ1 can form a two-dimensional electron gas EG without applying a bias voltage. In other words, the heterojunction HJ1 can be used as the active region of a depletion mode HEMT (also known as a normally on HEMT), and the depletion mode HEMT belongs to the first conductivity type (for example, N-type). For example, the thickness of the second barrier layer 110 ranges from 5 nm to 20 nm. In some embodiments, the heterojunction HJ1 does not overlap the first mask pattern 108. On the other hand, the heterojunction HJ2 overlapping the first mask pattern 108 includes the first barrier layer 106 and the first channel layer 104, but does not include the second barrier layer 110. Since the thickness of the first barrier layer 106 is less than 10 nm, no two-dimensional electron gas will be formed in the heterojunction HJ2 without applying a bias voltage. Therefore, the heterojunction HJ2 can be used as an active area of an enhancement mode HEMT (also known as a normally off HEMT), and this enhanced HEMT belongs to the first conductivity type (for example, an N-type).

1 and 2G, step S112 is performed to remove the first mask pattern 108 to expose a part of the first barrier layer 106. In this way, the second barrier layer 110 is discontinuous at the original position of the first mask pattern 108, or it can be regarded as the second barrier layer 110 having the first opening P1. The first opening P1 is located in the first region R1, and the first opening P1 extends to the top surface of the first barrier layer 106 along the stacking direction, exposing a part of the first barrier layer 106. In addition, the position of the first opening P1 is the original position of the first mask pattern 108. It can be seen that the heterojunction HJ1 does not overlap with the first opening P1, and the heterojunction HJ2 overlaps with the first opening P1.

1 and 2H, step S114 is performed to form a first gate electrode G1 on the exposed portion of the first barrier layer 106. It can be seen from the above that the first gate G1 is located in the first opening P1 and in the first region R1. In some embodiments, the first gate G1 fills the first opening P1 and extends to the surface of the second barrier layer 110. In addition, step S116 is performed to form the first drain electrode D1 and the first source electrode S1. The first drain electrode D1 and the first source electrode S1 are located in the first region R1, and the first drain electrode D1 and the first source electrode S1 are disposed on the second barrier layer 110 on opposite sides of the first gate electrode G1. In other words, the first drain electrode D1 and the first source electrode S1 are located on opposite sides of the first opening P1. It should be noted that the positions of the first drain electrode D1 and the first source electrode S1 can be reversed, and the present invention is not limited to the configuration shown in FIG. 2H. In addition, a person with ordinary knowledge in the field can change the sequence of step S114 and step S116, and the present invention is not limited thereto. In some embodiments, the material of the first gate G1 may include metal or metal nitride (such as Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or a combination thereof), metal silicide (such as WSix ) Or other materials that can form a schottky contact with the first barrier layer 106. The material of the first drain electrode D1 and the first source electrode S1 may include metal (for example, Al, Ti, Ni, Au or an alloy thereof), or other materials that can form an ohmic contact with the second barrier layer 110. The method of forming the first gate G1, the first drain D1, and the first source S1 may include a chemical vapor deposition method, a physical vapor deposition method (for example, sputtering, etc.), or a combination thereof. In some embodiments, the thickness of the first gate G1, the first drain D1, and the first source S1 may be 100 nm to 3000 nm, respectively. So far, the transistor T1 has been formed in the first region R1. The transistor T1 includes a first channel layer 104, a first barrier layer 106, and a portion of the second barrier layer 110 located in the first region R1, and includes a first gate G1, a first drain D1, and a first source极 S1. The transistor T1 may be an enhanced HEMT (or referred to as a normally-off HEMT), and may belong to the first conductivity type (for example, an N-type). In addition, the heterojunction HJ2 can be used as the active area of the transistor T1.

Step S118 is performed to form a second gate electrode G2, a second drain electrode D2, and a second source electrode S2 on the second barrier layer 110 in the second region R2. The second gate electrode G2 is located between the second drain electrode D2 and the second source electrode S2. It should be noted that the positions of the second drain electrode D2 and the second source electrode S2 can be reversed, and the present invention is not limited to the configuration shown in FIG. 2H. In addition, a person with ordinary knowledge in the field can change the sequence of step S114, step S116, and step S118, and the present invention is not limited thereto. In some embodiments, the material of the second gate G2 may include metal or metal nitride (such as Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or a combination thereof), metal silicide (such as WSix ) Or other materials that can form Schottky contact with the second barrier layer 110. The material of the second drain electrode D2 and the second source electrode S2 may include metal (for example, Al, Ti, Ni, Au or alloys thereof), or other materials that can form an ohmic contact with the second barrier layer 110. The method of forming the second gate electrode G2, the second drain electrode D2 and the second source electrode S2 may include a chemical vapor deposition method, a physical vapor deposition method (for example, sputtering, etc.), or a combination thereof. In some embodiments, the thickness of the second gate G2, the second drain D2, and the second source S2 may be 100 nm to 3000 nm, respectively. So far, the transistor T2 has been formed in the second region R2. Transistor T2 includes the first channel layer 104, the first barrier layer 106, the portion of the second barrier layer 110 located in the second region R2, and includes a second gate G2, a second drain D2, and a second source极 S2. The transistor T2 may be a depletion type (or called a normally-on type) HEMT, and may belong to the first conductivity type (for example, an N type). In addition, the section of the heterojunction HJ1 located in the second region R2 can be used as the active region of the transistor T2.

1 and 2I, step S120 is performed to remove the portions of the first barrier layer 106 and the second barrier layer 110 located near the boundary between the first region R1 and the second region R2. In this way, the opening P exposing the first channel layer 104 can be formed in the stack structure including the first barrier layer 106 and the second barrier layer 110. By forming the opening P, the first channel layer 104 located under the opening P no longer forms two-dimensional electron gas. Therefore, the two-dimensional electron gas EG in the transistor T1 and the two-dimensional electron gas EG in the transistor T2 can be disconnected from each other. In other words, the transistor T1 and the transistor T2 can be electrically isolated from each other.

So far, the manufacture of the HEMT device 10 of some embodiments of the present invention has been completed. The HEMT device 10 may include a transistor T1 located in the first region R1 and a transistor T2 located in the second region R2. Transistor T1 is an enhanced HEMT, while transistor T2 is a depleted HEMT. In addition, the transistor T1 and the transistor T2 are both of the first conductivity type (for example, N-type), and a logic gate can be formed by combining the transistor T1 and the transistor T2. For example, the logic gate is, for example, an inverter.

Based on the above, the embodiment of the present invention includes forming a second barrier layer having an opening exposing the first barrier layer on the first barrier layer. In this way, the heterojunction that overlaps the opening includes the first barrier layer and the underlying first channel layer, but does not include the second barrier layer. The thickness of the first barrier layer is not enough to make the heterojunction produce two-dimensional electron gas (or conductive channel) without applying a bias voltage, so the heterojunction can be used as an enhanced (or normally-closed) ) Active area of HEMT. In addition, the embodiment of the present invention uses a selective epitaxy method to form the second barrier layer with openings, and the first barrier layer or the second barrier layer is not etched. Therefore, the first barrier layer and the second barrier layer can be prevented from being damaged by etching. Furthermore, the embodiment of the present invention can avoid doping the first barrier layer and the second barrier layer. Therefore, the problem of dopant diffusion due to other high-temperature processes can be avoided. In other words, the reliability of the HEMT element can be improved.

FIG. 3 is a flowchart of a method of manufacturing the HEMT device 20 according to some embodiments of the present invention. 4A to 4L are schematic cross-sectional views of the structure of each stage in the manufacturing method of the HEMT device 20 shown in FIG. 3. The embodiments shown in FIGS. 3 and 4A to 4L are similar to the embodiments shown in FIGS. 1 and 2A to 2I. Only the differences between the two will be described below, and the same or similarities will not be repeated. In addition, the same or similar element symbols represent the same or similar components.

Please refer to FIG. 1, FIG. 3, and FIG. 4A, and perform step S100 to step S112 as shown in FIG. In this way, the buffer layer 102, the first channel layer 104, the first barrier layer 106, and the second barrier layer 110 can be sequentially formed on the substrate. The buffer layer 102, the first channel layer 104, the first barrier layer 106, and the second barrier layer 110 extend in the first region R1 and the second region R2. The first area R1 shown in FIG. 4A is located on the right and the second area R2 is located on the left, but the invention is not limited to this. In some embodiments, as shown in FIGS. 2A to 2I, the first region R1 may also be located on the left and the second region R2 may be located on the right. The second barrier layer 110 can be regarded as having a first opening P1 exposing the first barrier layer 106, and the first opening P1 is located in the first region R1. The heterojunction HJ1 that does not overlap the first opening P1 includes a first barrier layer 106, a second barrier layer 110 and a first channel layer 104. Since the total thickness of the first barrier layer 106 and the second barrier layer 110 is greater than 15 nm, the two-dimensional electron gas EG can be formed without applying a bias to the heterojunction HJ1. On the other hand, the heterojunction HJ2 overlapping the first opening P1 includes the first barrier layer 106 and the first channel layer 104, but does not include the second barrier layer 110. Since the thickness of the first barrier layer 106 is insufficient (for example, less than 10 nm), the two-dimensional channel layer 104 in the heterojunction HJ2 will not be formed without biasing the heterojunction HJ2. Electronic gas. Therefore, the heterojunction HJ2 can be used as the active region of the enhanced HEMT (for example, the transistor T1 shown in FIG. 4L), and the enhanced HEMT may belong to the first conductivity type (for example, the N-type).

Next, an enhanced HEMT of the second conductivity type (for example, P-type) will be formed in the second region R2.

3 and 4B, step S200 is performed to form a mask pattern 202 on the second barrier layer 110 and the first barrier layer 106 in the first region R1. In the first region R1, the mask pattern 202 may extend from the top surface of the second barrier layer 110 into the first opening P1, and may fill the first opening P1. In addition, the mask pattern 202 may expose a portion of the second barrier layer 110 located in the second region R2. In some embodiments, the material of the mask pattern 202 includes silicon oxide, silicon nitride, or a combination thereof. In addition, the thickness of the mask pattern 202 may range from 10 nm to 500 nm. In some embodiments, a mask layer (not shown) covering the second barrier layer 110 and the first barrier layer 106 may be formed by a method such as a chemical vapor deposition process. Then, the mask layer is patterned to form a mask pattern 202.

3 and 4C, step S202 is performed to form a second channel layer 204 on the second barrier layer 110 in the second region R2. In some embodiments, the second channel layer 204 may be formed on the exposed portion of the second barrier layer 110 by, for example, a selective epitaxial method. In other words, the second channel layer 204 will only be epitaxially grown from the exposed portion of the second barrier layer 110, but not from the surface of the mask pattern 202. In some embodiments, the material of the second channel layer 204 may include a group III nitride or a group III-V compound semiconductor material. For example, the material of the second channel layer 204 includes AlGaN. In addition, the thickness of the second channel layer 204 may range from 10 nm to 50 nm.

3 and 4D, step S204 is performed to form a third barrier layer 206 on the second channel layer 204. In some embodiments, the third barrier layer 206 may be formed on the second channel layer 204 in the second region R2 by, for example, a selective epitaxial method. In other words, the third barrier layer 206 will only grow epitaxially from the exposed portion of the second channel layer 204, but not from the surface of the mask pattern 202. In an embodiment, the material of the third barrier layer 206 includes a group III nitride or a group III-V compound semiconductor material. For example, the material of the third barrier layer 206 includes InAlGaN, AlGaN, InGaN, InAlN, GaN or InN or a combination thereof, and is doped with second conductivity type dopants (for example, Mg). In some embodiments, the doping concentration of the third barrier layer 206 ranges from 1´10 ¹⁷ cm ^-3 to 1´10 ²⁰ cm ^-3 . In addition, the thickness of the third barrier layer 206 may be less than 20 nm, so that the region of the second channel layer 204 close to the third barrier layer 206 does not form two dimensional hole gas (2DHG) at this time . In other words, no conductive channels are formed in the second channel layer 204 at this time. For example, the thickness of the third barrier layer 206 may range from 5 nm to 20 nm.

Please refer to FIG. 3 and FIG. 4E to perform step S206 to form a second mask pattern 208 on the third barrier layer 206. The second mask pattern 208 is located in the second region R2. In some embodiments, the method of forming the second mask pattern 208 includes forming a mask layer (not shown) on the third barrier layer 206 by, for example, a chemical vapor deposition process, and then patterning the mask Layer to form a second mask pattern 208. In some embodiments, the second mask pattern 208 may be a hard mask pattern. For example, the material of the second mask pattern 208 may include silicon oxide, silicon nitride, or a combination thereof. In addition, in some embodiments, the thickness of the second mask pattern 208 may range from 10 nm to 500 nm.

3 and 4F, step S208 is performed to form a fourth barrier layer 210 on the portion of the third barrier layer 206 exposed by the second mask pattern 208. In some embodiments, the fourth barrier layer 210 may be formed on the third barrier layer 206 in the second region R2 by, for example, a selective epitaxial method. In other words, the fourth barrier layer 210 will only form epitaxial growth from the exposed portion of the third barrier layer 206, but not from the surface of the mask pattern 202 and the second mask pattern 208. In some embodiments, the third barrier layer 206 and the fourth barrier layer 210 may be composed of the same material, and may have substantially the same doping concentration. Nevertheless, since the third barrier layer 206 and the fourth barrier layer 210 are not formed in the same epitaxial process, there is still an interface F1 between the third barrier layer 206 and the fourth barrier layer 210. In some embodiments, the height of the fourth barrier layer 210 may be lower than the height of the second mask pattern 208.

In some embodiments, the total thickness of the fourth barrier layer 210 and the third barrier layer 206 may be greater than 30 nm. For example, the thickness of the fourth barrier layer 210 may range from 10 nm to 70 nm. In this way, the heterojunction HJ3 that does not overlap the second mask pattern 208 in the second region R2 includes the third barrier layer 206, the fourth barrier layer 210, and the second channel layer 204, and is not A two-dimensional hole gas HG can be formed when a bias voltage is applied. On the other hand, the heterojunction HJ4 overlapping the second mask pattern 208 in the second region R2 includes the third barrier layer 206 and the second channel layer 204, but does not include the fourth barrier layer 210. Since the thickness of the third barrier layer 206 is less than 20 nm, the heterojunction HJ4 does not form a two-dimensional electric hole in the second channel layer 204 without applying a bias voltage. In this way, the heterojunction HJ4 can be used as an active area of an enhanced HEMT (also known as a normally-off HEMT), and this enhanced HEMT belongs to the second conductivity type (for example, P-type).

3 and 4G, step S210 is performed to form a heavily doped layer 212 on the fourth barrier layer 210. In some embodiments, the heavily doped layer 212 may be formed on the fourth barrier layer 210 in the second region R2 by a selective epitaxial method. In other words, the heavily doped layer 212 will only form epitaxial growth from the exposed portion of the fourth barrier layer 210, but not from the surface of the mask pattern 202 and the second mask pattern 208. In some embodiments, the top surface of the heavily doped layer 212 may be substantially flush with the top surface of the second mask pattern 208. The material and dopants of the heavily doped layer 212 can be the same as those of the third barrier layer 206 and the fourth barrier layer 210, except that the dopants of the heavily doped layer 212 (the second conductivity type, for example, P Type) concentration is higher than the dopant concentration of the third barrier layer 206 and the fourth barrier layer 210. In some embodiments, the dopant concentration of the heavily doped layer 212 may be 1 to 100 times the dopant concentration of the third barrier layer 206 and the fourth barrier layer 210. By providing the heavily doped layer 212, the contact resistance between the fourth barrier layer 210 and subsequent electrodes formed thereon (for example, the second drain electrode D2 and the second source electrode S2 shown in FIG. 4K) can be reduced .

Please refer to FIG. 3 and FIG. 4H to proceed to step S212 to remove the mask pattern 202 and the second mask pattern 208. In this way, a part of the second barrier layer 110 and the first barrier layer 106 in the first region R1 is exposed, and a part of the third barrier layer 206 in the second region R2 is exposed. The fourth barrier layer 210 is discontinuous at the original position of the second mask pattern 208, or it can be regarded as the fourth barrier layer 210 having the second opening P2 there. In other words, the second opening P2 is located in the second region R2, and the second opening P2 extends to the top surface of the third barrier layer 206 along the stacking direction, exposing a part of the third barrier layer 206. In addition, the position of the second opening P2 is the original position of the second mask pattern 208. It can be seen that the heterojunction HJ3 does not overlap the second opening P2, and the heterojunction HJ4 overlaps the second opening P2.

Please refer to FIG. 3 and FIG. 4I to perform step S214 to form the first drain electrode D1 and the first source electrode S1. The first drain electrode D1 and the first source electrode S1 are located in the first region R1, and the first drain electrode D1 and the first source electrode S1 are disposed on the second barrier layer 110 on opposite sides of the first opening P1. In addition, the first drain electrode D1 and the first source electrode S1 include a conductive material capable of forming an ohmic contact with the second barrier layer 110.

Referring to FIG. 3 and FIG. 4J, proceed to step S216 to form a mask pattern 214. The mask pattern 214 covers the first region R1, but does not extend to the second region R2. In some embodiments, the mask pattern 214 covers the first drain electrode D1 and the first source electrode S1, and can fill the first opening P1. In some embodiments, the material of the mask pattern 214 includes silicon oxide, silicon nitride, or a combination thereof. In addition, the coverage area of the mask pattern 214 defines the area of the transistor T1 in the first region R1. In some embodiments, a mask layer (not shown) covering the structure shown in FIG. 4I may be formed by a method such as a chemical vapor deposition process. Then, the mask layer is patterned to form a mask pattern 214.

3 and 4K, step S218 is performed to form a second gate G2a, a second drain D2a, and a second source S2a. The second gate G2a can be disposed in the second opening P2 and electrically connected to the third barrier layer 206. The second drain electrode D2a and the second source electrode S2a are disposed on the fourth barrier layer 210 on opposite sides of the second opening P2, and are electrically connected to the fourth barrier layer 210, respectively. It should be noted that the positions of the second drain electrode D2a and the second source electrode S2a can be reversed, and the present invention is not limited to the configuration shown in FIG. 4K. In addition, those skilled in the art can adjust the order of forming the second gate G2a, the second drain D2a, and the second source S2a according to the process requirements, and the present invention is not limited thereto. In some embodiments, the material of the second gate electrode G2a may include metal or metal nitride (such as Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or a combination thereof), metal silicide (such as WSi _x ) or other materials that can form Schottky contact with the third barrier layer 206. The material of the second drain electrode D2a and the second source electrode S2a may include metal (for example, Al, Ti, Ni, Au or an alloy thereof), or other materials that can form an ohmic contact with the fourth barrier layer 210. The method for forming the second gate electrode G2a, the second drain electrode D2a and the second source electrode S2a may include a chemical vapor deposition method, a physical vapor deposition method (for example, sputtering, etc.) or a combination thereof. In some embodiments, the thickness of the second gate G2a, the second drain D2a, and the second source S2a may be 100 nm to 3000 nm, respectively.

So far, the transistor T2a has been formed in the second region R2. The transistor T2a includes a second channel layer 204, a third barrier layer 206, and a fourth barrier layer 210, and includes a second gate electrode G2a, a second drain electrode D2a, and a second source electrode S2a. In addition, the heterojunction HJ4 can be used as the active area of the transistor T2a. When the heterojunction HJ4 is not biased, no two-dimensional electrical hole gas will be generated, and when the heterojunction HJ4 is appropriately biased, a two-dimensional electrical hole gas (that is, a conductive channel) is formed. It can be seen that the transistor T2a can be an enhanced (or called normally-on) HEMT, and can belong to the second conductivity type (for example, a P-type).

3 and 4L, step S220 is performed, the mask pattern 214 is removed, and the first gate G1 is formed. The first gate G1 is formed in the first opening P1 and is electrically connected to the first barrier layer 106. In some embodiments, the first gate G1 fills the first opening P1 and extends to the surface of the second barrier layer 110. The material of the first gate electrode G1 may include a material capable of forming Schottky contact with the first barrier layer. So far, the transistor T1 has been formed in the first region R1. The transistor T1 includes a first channel layer 104, a first barrier layer 106, and a portion of the second barrier layer 110 located in the first region R1, and includes a first gate G1, a first drain D1, and a first source极 S1. The heterojunction HJ2 can be used as the active area of the transistor T1.

When the heterojunction HJ2 is not biased, no two-dimensional electron gas will be generated, but when the heterojunction HJ2 is appropriately biased, a two-dimensional electron gas (ie, conductive channel) is formed. The transistor T1 may be an enhanced (or normally-off) HEMT, and may belong to the first conductivity type (for example, an N-type).

So far, the manufacture of the HEMT device 20 according to some embodiments of the present invention has been completed. The HEMT element 20 may include a transistor T1 located in the first region R1 and a transistor T2 located in the second region R2. Transistor T1 and transistor T2 are both enhanced HEMTs, while transistor T1 belongs to the first conductivity type (for example, N-type) and transistor T2 belongs to the second conductivity type (for example, P-type). A logic gate can be formed by combining the transistor T1 and the transistor T2, such as an inverter. In addition, similar to the manufacturing method of the transistor T1, the manufacturing method of the transistor T2 can also avoid etching or doping the third barrier layer 206 and the fourth barrier layer 210. Therefore, the reliability of the transistor T2 can also be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 20: HEMT element 100: substrate 102: buffer layer 104: first channel layer 106: first barrier layer 108: first mask pattern 110: second barrier layer 202, 214: mask pattern 204: first Two channel layer 206: third barrier layer 208: second mask pattern 210: fourth barrier layer 212: heavily doped layer D1: first drain electrode D2, D2a: second drain electrode EG: two-dimensional electron gas F, F1: interface G1: first gate G2, G2a: second gate HG: two-dimensional electric hole gas HJ1, HJ2, HJ3, HJ4: heterogeneous junction P: opening P1: first opening P2: second opening R1: first zone R2: second zone S1: first source S2, S2a: second source S100, S102, S104, S106, S108, S110, S112, S114, S116, S118, S120, S200, S202, S204, S206, S208, S210, S212, S214, S216, S218, S220: Steps T1, T2, T2a: Transistor

FIG. 1 is a flowchart of a method of manufacturing a HEMT device according to some embodiments of the present invention. 2A to 2I are schematic cross-sectional views of the structure of each stage in the manufacturing method of the HEMT device shown in FIG. 1. FIG. 3 is a flowchart of a method of manufacturing a HEMT device according to some embodiments of the present invention. 4A to 4L are schematic cross-sectional views of the structure of each stage in the manufacturing method of the HEMT device shown in FIG. 3.

10: HEMT components

100: base

102: buffer layer

104: The first channel layer

106: first barrier layer

110: second barrier layer

D1: The first drain

D2: second drain

F: Interface

G1: first gate

G2: second gate

HJ1, HJ2: heterogeneous junction

P: opening

P1: First opening

R1: Zone 1

R2: Zone 2

S1: first source

S2: second source

T1, T2: Transistor

Claims (10)

A high electron mobility transistor element, comprising: a first channel layer arranged on a substrate; a first barrier layer arranged on the first channel layer; a second barrier layer arranged on the first barrier On the barrier layer, wherein the second barrier layer has a first opening extending to the first barrier layer, wherein the high electron mobility transistor has a first region and a second region, the first The channel layer, the first barrier layer and the second barrier layer are located in the first area and the second area, and the first opening of the second barrier layer is located in the first area. Area and the bottom surface of the first opening does not have the first barrier layer; the second channel layer is disposed on the second barrier layer and is located in the second area; the third barrier layer , Disposed on the second channel layer and located in the second region; a fourth barrier layer, disposed on the third barrier layer and located in the second region, wherein the fourth barrier The barrier layer has a second opening extending to the third barrier layer; a first gate is disposed on the first barrier layer in the first opening and fills the first opening and contacts The top surface of the second barrier layer; and the first drain and the first source are respectively disposed on the second barrier layer on opposite sides of the first opening. The high electron mobility transistor device described in the first item of the patent application, wherein the first barrier layer and the second barrier layer are made of the same material, and the first barrier layer and the second barrier layer There is an interface between the barrier layers. The high electron mobility transistor device as described in item 1 of the scope of patent application further includes: a second gate electrode, a second drain electrode and a second source electrode, which are arranged on the second barrier layer and located on the In the second region, the second gate is located between the second drain and the second source. The high electron mobility transistor device described in claim 1, wherein the interface between the first barrier layer and the second barrier layer is between the first region and the second region The place is not continuous. The high electron mobility transistor device described in the first item of the scope of patent application further includes: a second gate electrode disposed on the third barrier layer in the second opening; and a second drain electrode and The second source electrodes are respectively disposed on the fourth barrier layer on opposite sides of the second opening. The high electron mobility transistor device described in item 5 of the scope of the patent application further includes a heavily doped layer, which is disposed between the fourth barrier layer and the second drain and is located in the fourth Between the barrier layer and the second source. A method for manufacturing a high electron mobility transistor element includes: forming a first channel layer on a substrate; forming a first barrier layer on the first channel layer; forming a first barrier layer on the first barrier layer Mask pattern; on the portion of the first barrier layer exposed by the first mask pattern Direct epitaxial formation of the second barrier layer without forming the second barrier layer on the surface of the first mask pattern; removing the first mask pattern to expose the first barrier layer A first gate is formed on the exposed part of the first barrier layer and the first gate fills the first opening and contacts the second barrier layer Top surface; forming a first drain and a first source on the second barrier layer on opposite sides of the first gate; wherein the high electron mobility transistor has a first region and a first region In the second area, the first channel layer, the first barrier layer, and the second barrier layer are located in the first area and the second area, and the first mask pattern is disposed in the In the first region; forming a second channel layer on the second barrier layer in the second region; forming a third barrier layer on the second channel layer; in the third barrier layer Forming a second mask pattern on the layer; forming a fourth barrier layer on the portion of the third barrier layer exposed by the second mask pattern; and removing the second mask pattern to A part of the third barrier layer is exposed. The method for manufacturing a high electron mobility transistor device as described in item 7 of the scope of the patent application further includes: forming a second gate electrode and a second drain electrode on the second barrier layer in the second region And a second source, wherein the second gate is located between the second drain and the second source. The method for manufacturing a high electron mobility transistor device as described in the scope of patent application, further includes: forming a second gate electrode on the exposed portion of the third barrier layer; and forming a second gate electrode on the second gate electrode A second drain and a second source are formed on the fourth barrier layer on opposite sides of the As described in item 9 of the scope of patent application, the method for manufacturing a high electron mobility transistor element further includes forming a heavily doped layer on the fourth barrier layer, wherein the heavily doped layer is located on the fourth barrier layer. Between the barrier layer and the second drain, and between the fourth barrier layer and the second source.

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