TWI684206B - 金屬絕緣金屬電容裝置 - Google Patents

金屬絕緣金屬電容裝置 Download PDF

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TWI684206B
TWI684206B TW108104071A TW108104071A TWI684206B TW I684206 B TWI684206 B TW I684206B TW 108104071 A TW108104071 A TW 108104071A TW 108104071 A TW108104071 A TW 108104071A TW I684206 B TWI684206 B TW I684206B
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dielectric
dielectric layer
dielectric film
item
patent application
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夏立克 西迪奎
游漢
張洵淵
羅希特 蓋拉特吉
羅傑Ａ 魁昂
克里斯多福Ｊ 潘尼
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明一般係關於半導體結構，尤其關於金屬絕緣金屬電容裝置及其製造方法。該方法包括：沉積一底板；在該底板上沉積一介電膜；讓該介電膜暴露在一氣體中；固化該介電膜；以及在該介電膜之上沉積一頂板。

Description

金屬絕緣金屬電容裝置
本發明一般係關於半導體結構，尤其關於金屬絕緣金屬電容裝置及其製造方法。
金屬絕緣金屬電容(MIMCAP，Metal Insulator Metal Capacitor)裝置正在引起許多應用的興趣，包括RF和混合信號裝置等範例。在某些應用中，需要高電容MIMCAP來降低電壓波動以用於去耦合，從而提高裝置的速度和可靠性，以及其他益處。然而，絕緣體層的介電擊穿可能在高電容下發生，導致漏電。
在本發明的樣態中，一種方法包括：沉積一底板；在該底板上沉積一介電膜；讓該介電膜暴露在一氣體中；固化(curing)該介電膜；以及在該介電膜之上沉積一頂板。
在本發明的樣態中，一種方法包括：在一底板上沉積一第一高k介電層；讓該第一高k介電層暴露在一NH3或O3氣體內；使用UV輻射固化該第一高k介電層；以堆疊或分層結構在該第一高k介電層之上沉積至少一個額外高k介電層；暴露並固化該至少一個額外高k介電層；以及在該至少一個額外高k介電層之上沉積一頂板。
在本發明的樣態中，一種結構包括：一底板；在該底板上的一氮氣注入介電膜；以及在該氮氣注入介電膜之上的一頂板。
100‧‧‧金屬絕緣金屬電容裝置
105‧‧‧金屬板
105'‧‧‧金屬板
110‧‧‧介電膜
110"‧‧‧分層膜
110'‧‧‧堆疊膜
115‧‧‧高k介電層
120‧‧‧高k介電層
130‧‧‧燈具
135‧‧‧處理程序
利用本發明示範具體實施例的非限制範例，參考提及的許多圖式，從下列詳細描述當中描述本發明。
圖1顯示根據本發明態樣的其他部件之間一輸入結構與個別製程。
圖2A和圖2B顯示根據本發明態樣的其他部件之間許多介電膜具體實施例與個別製程。
圖3顯示根據本發明態樣的其他部件之間一電容器結構與個別製程。
本發明一般係關於半導體結構，尤其關於金屬絕緣金屬電容(MIMCAP)裝置及其製造方法。本文所提供的製程和結構改善MIMCAP電容並減少漏電。尤其是，本文所提供的製程和結構允許MIMCAP裝置的介電膜具有提高的電容，從而避免介電擊穿，減少高電容應用當中的漏電。
在具體實施例內，該介電膜的表面經過改性來提高電容。尤其是，該介電膜經過一氣體的改性，然後用紫外線(UV，ultra-violet)輻射來固化。如此，介電膜的改性使介電膜退火，其熱預算與後端線(BEOL，back end of line)溫度相容。這導致該介電膜具有增加的介電常數，造成電容增加以防止介電擊穿，從而減少高電容應用中的漏電。
本發明的結構可用許多不同工具以許多方式來製造。一般來說，該等方法與工具用來形成尺寸為毫米與奈米等級的結構。用來製造本發明結構的該等方法，即技術，採用積體電路(IC，integrated circuit)技術， 例如：這些結構建立在晶圓上，並且通過在晶圓頂部上以光微影蝕刻處理來製作圖案的材料膜來實現。尤其是，該等結構的製造使用三種基本構件：(i)將材料薄膜沈積在一基材上，(ii)利用光微影蝕刻成像將一製圖光罩應用於該等薄膜頂端上，以及(iii)依照該光罩的選擇來蝕刻該等薄膜。
圖1顯示根據本發明態樣的一輸入結構與個別製程。尤其是，圖1顯示一金屬絕緣金屬電容(MIMCAP)裝置100。MIMCAP裝置100包括一金屬板105，其可由傳統沉積處理來沉積，例如化學氣相沉積(CVD，chemical vapor deposition)或物理氣相沉積(PVD，physical vapor deposition)處理。如此，具有一底板，即金屬板105的沉積。在具體實施例內，在其他範例之間，金屬板105可由任何合適的導電材料構成，像是TiN。
一介電膜110由傳統沉積處理，例如原子層沉積(ALD，atomic layer deposition)，沉積在金屬105之上。尤其是，在該底板之上，即金屬板105之上，具有介電膜110的沉積。在具體實施例內，介電膜110可為例如高k閘極介電材料，例如鉿或鋯基介電質。尤其是，該等高k介電材料可包括但不受限於：Al2O3、HfO2、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括以上多層的組合。如此，介電膜110為高k介電膜。進一步，該高k介電膜可為鉿基介電質或鋯基介電質。在具體實施例內，介電膜110可為介電膜的堆疊，如圖2A內所示，或分層膜的堆疊，如圖2B內所示。
介電膜110進行一處理程序135，將介電膜110的表面改性。尤其是，介電膜110的表面經過改性，以提高介電膜110的介電常數，從而提高電容。在具體實施例內，處理程序135開始先供應氣體，接著通過使用燈具130固化介電膜110。尤其是，處理程序135一開始先將介電膜110暴露在氣體中。
在具體實施例內，該氣體可為例如氨(NH3)或臭氧(O3)。如此，該氣體由NH3或O3構成。在具體實施例內，例如NH3的濃度約 10%-80%，而O3的濃度約10%-100%。在進一步具體實施例內，考慮NH3與O3的任意組合，包括同時使用NH3和O3。在該處理程序期間應用該氣體允許將氮氣(N)注入介電膜110，從而製作更密的介電膜110。退火和N摻入可增加介電常數，導致電容增加。如此，介電膜110為該底板之上，即金屬板105之上的一氮氣注入介電膜。一後續頂板可置於該氮氣注入介電膜之上。
通過紫外線(UV)輻射使介電膜110固化。在具體實施例內，該UV輻射的波長小於例如400nm。如此，該UV輻射具有小於400nm的波長。進一步，該UV輻射的時間長度可在大約10秒至180秒的範圍內，較佳時間長度在大約30秒至90秒的範圍內。如此，該UV輻射持續30秒至90秒的時段。在具體實施例內，發出UV輻射的燈具130可為例如水銀(Hg)燈具或LED燈具。在具體實施例中，UV輻射固化溫度可在約150℃至最高400℃的範圍內，較佳為約200℃-350℃的範圍內。如此，通過UV輻射在約150℃-400℃的溫度範圍內固化。在具體實施例內，較佳溫度為約335℃，或不會熔化底下金屬板105及/或放在介電膜110之上任何後續頂金屬板。尤其是，該UV輻射的溫度低於任何後續頂板的熔點。
藉由使用處理程序135將介電膜110改質，介電膜110以與後端線(BEOL)相容的熱預算來進行退火。更特別是，介電膜110的表面改性導致介電常數提高，而讓電容增加。如此，避免介電擊穿，而降低MIMCAP裝置在高電容應用之下漏電。
圖2A和圖2B顯示介電膜110的許多具體實施例。例如：圖2A將一介電膜110例示為一堆疊膜110'。在堆疊膜110'內，高k介電層115、120彼此堆疊。在具體實施例內，高k介電層115、120可彼此對稱或不對稱。例如：高k介電層115可由43次循環的HfO2所構成，而高k介電層120可由3次循環的Al2O3所構成。針對任何所要的層數都可繼續此程序，在此以三層來顯示一個非限制具體實施例。
圖2B將一介電膜110例示為一分層膜110"。在分層膜110"內，例如可植入三或更多高k介電層。如此，相較於堆疊膜110'，分層膜110"可在介電膜110內提供更均勻的鋁(Al)分佈。在此範例中，該氮氣注入介電膜，即介電膜110，由分層的高k介電層115、120所構成。在分層膜110"內，高k介電層115、120可彼此對稱或不對稱。例如：高k介電層115可由9次循環的HfO2所構成，而高k介電層120可由1次循環的Al2O1所構成。分層膜110"內分層膜的其他變體包括[H-A]x、[A-H]x和[A-H-A]x，在其他範圍之間，其中H代表HfO2並且A代表Al2O3。
在具體實施例內，於許多方法和許多處理步驟上，在高k介電層115、120的每一沉積循環完成之後，處理程序135可套用至介電膜110，尤其是套用至堆疊膜110'或分層膜110"。例如：高k介電層115可由對堆疊層110'進行ALD處理，接著暴露在該氣體之下以及處理程序135的UV輻射之下來沉積。高k介電層120可沉積在高k介電層115之上，接著高k介電層115沉積在高k介電層120之上。在此範例中，該程序涉及第一高k介電層的沉積與處理，接著未經過處理程序135處理過的第二和第高k介電層之沉積。
在進一步具體實施例內，堆疊膜110'的高k介電層120可進行處理程序135，而在高k介電層120之上與之下的高k介電層115則不進行處理程序135。在此範例中，高k介電層115利用ALD處理來沉積，接著高k介電層120沉積在高k介電層115之上，然後經過處理程序135的處理。另一個高k介電層115沉積在現在已處理過的高k介電層120之上。在此範例中，該程序涉及該第一高k介電層的沉積，接著一第二高k介電層沉積在該第一高k介電層之上並經過處理，接著一第三高k介電層沉積在該已處理的第二高k介電層之上。尤其是，一第一高k介電層與一第三高k介電層都未處理，但是一第二高k介電層則經過處理。
在甚至進一步具體實施例內，每一高k介電層都可在堆疊膜 110'或分層膜110"內個別進行處理程序135來處理。如此，該高k介電膜包括堆疊的高k介電層或分層的高k介電層，當每一層該堆疊高k介電層或該分層高k介電層都已沉積之後，則分別進行曝氣與固化處理。例如：分層膜110"中的高k介電層115通過ALD沉積，然後用處理程序135處理，接著通過ALD沉積高k介電層120，然後用ALD沉積高k介電層120然後用處理程序135處理，接著通過ALD沉積高k介電層115在高k介電層120之上，然後用處理程序135處理等等。在該具體實施例內，該程序涉及沉積和處理介電膜110中的每個高k介電層。
在沉積之後處理每一高k介電層，導致較高濃度的氮氣注入介電層110。尤其是，沉積一第一高k介電層，即高k介電層115，在一底板，即金屬板105之上。該第一高k介電層暴露在一NH3或O3氣體內，然後用UV輻射固化。在具體實施例內，該第一高k介電層由鉿或鋯基介電質構成。接著沉積至少一個額外高k介電層，即高k介電層120，在該第一高k介電層之上，形成堆疊或分層結構，即成為堆疊膜110'或分層膜110"。此至少一個額外高k介電層暴露在NH3或O3氣體內，然後用UV輻射固化。然後在該至少一個額外高k介電層，即高k介電層120之上沉積一頂板。在此也考慮該高k介電膜包括堆疊的高k介電層或分層的高k介電層，並且在沉積堆疊高k介電層或分層高k介電層的任何層之後經過曝氣與固化。
圖3顯示在介電膜110之上的一金屬板105'，其當成MIMCAP裝置100的頂板。尤其是，在介電膜10之上沉積一頂板，即金屬板105'。金屬板105'可通過傳統沉積處理，例如CVD或PVD來沈積。在具體實施例內，在其他範例之間，金屬板105'可由任何合適的導電材料構成，像是TiN。如此，該底板，即金屬板105，以及該頂板，即金屬板105'，都為導電材料。尤其是，該底板，即金屬板105，以及該頂板，即金屬板105'，都由TiN構成。
上述該(等)方法用於積體電路晶片製造。結果積體電路晶片 可由製造廠以原始晶圓形式(也就是具有多個未封裝晶片的單一晶圓)、當成裸晶粒或已封裝形式來散佈。在後者案例中，晶片固定在單晶片封裝內(像是塑膠載體，具有導線黏貼至主機板或其他更高層載體)或固定在多晶片封裝內(像是一或兩表面都具有表面互連或內嵌互連的陶瓷載體)。然後在任何案例中，晶片與其他晶片、離散電路元件以及/或其他信號處理裝置整合成為(a)中間產品，像是主機板，或(b)末端產品。末端產品可為包括積體電路晶片的任何產品，範圍從玩具與其他低階應用到具有顯示器、鍵盤或其它輸入裝置以及中央處理器的進階電腦產品。
許多本發明具體實施例的描述已經為了說明而呈現，但非要將本發明受限在所公布形式中。在不脫離所描述具體實施例之範疇與精神的前提下，所屬技術領域中具有通常知識者將瞭解許多修正例以及變化例。本文內使用的術語係為了能最佳解釋具體實施例的原理、市場上所發現技術的實際應用或技術改進，或可讓所屬技術領域中具有通常知識者能理解本文所揭示的具體實施例。
100‧‧‧金屬絕緣金屬電容裝置
105‧‧‧金屬板
105'‧‧‧金屬板
110‧‧‧介電膜

Claims (20)

  1. 一種半導體結構的製造方法，包括：沉積一底板；在該底板上沉積一介電膜；讓該介電膜暴露在一NH3氣體中，以允許將氮(N)注入該介電膜；固化該介電膜；以及在該介電膜之上沉積一頂板。
  2. 如申請專利範圍第1項所述之方法，其中該底板和該頂板都由TiN構成。
  3. 如申請專利範圍第2項所述之方法，其中該介電膜為一高k介電膜。
  4. 如申請專利範圍第3項所述之方法，其中該高k介電膜為一鉿基介電質。
  5. 如申請專利範圍第3項所述之方法，其中該高k介電膜為一鋯基介電質。
  6. 如申請專利範圍第3項所述之方法，其中該高k介電層包括堆疊的高k介電層，當每一層該堆疊高k介電層都已沉積之後，則個別進行該曝氣與固化。
  7. 如申請專利範圍第3項所述之方法，其中該高k介電層包括分層的高k介電層，當每一層該分層高k介電層都已沉積之後，則個別進行該曝氣與固化。
  8. 如申請專利範圍第7項所述之方法，其中該高k介電膜包括堆疊的高k介電層，並且在沉積該堆疊的高k介電層之任何層之後經過該曝氣與該固化。
  9. 如申請專利範圍第8項所述之方法，其中該高k介電膜包括分層的高k介電層，並且在沉積該分層的高k介電層之任何層之後經過該曝氣與該固化。
  10. 如申請專利範圍第1項所述之方法，其中該NH3氣體的濃度為10%-80%。
  11. 如申請專利範圍第1項所述之方法，其中該固化由UV輻射在溫度約150℃-400℃的範圍內完成。
  12. 如申請專利範圍第11項所述之方法，其中該UV輻射具有小於400nm的波長。
  13. 如申請專利範圍第12項所述之方法，其中該UV輻射持續範圍30秒至90秒的時段。
  14. 一種半導體結構的製造方法，包括：在一底板上沉積一第一高k介電層；讓該第一高k介電層暴露在一NH3氣體內，以允許將氮(N)注入該介電膜；及使用UV輻射固化該第一高k介電層； 以堆疊或分層結構在該第一高k介電層之上沉積至少一個額外高k介電層；暴露並固化該至少一個額外高k介電層；以及在該至少一個額外高k介電層之上沉積一頂板。
  15. 如申請專利範圍第14項所述之方法，進一步包括讓該至少一個額外高k介電層暴露在NH3氣體以及UV輻射之下。
  16. 如申請專利範圍第15項之方法，其中該頂板和該底板都為導電材料。
  17. 如申請專利範圍第14項所述之方法，其中該第一高k介電膜由鉿或鋯基介電質構成。
  18. 如申請專利範圍第14項所述之方法，其中該UV輻射的溫度低於該頂板的熔點。
  19. 一種半導體結構，包括：一底板；在該底板上的一氮氣注入介電膜，其中形成該氮氣注入介電膜的製程包括使一介電膜暴露在濃度為10%-80%的一NH3氣體中，並以UV輻射固化該介電膜，其中該UV輻射具有小於400nm的波長，持續範圍30秒至90秒的時段，在溫度約150℃-400℃的範圍內完成；以及在該氮氣注入介電膜之上的一頂板。
  20. 如申請專利範圍第19項所述之結構，其中該氮氣注入介電膜由分層高k介電層構成。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200404911A (en) * 2002-07-19 2004-04-01 Asml Us Inc Metal organic chemical vapor deposition and atomic layer deposition of metal oxynitride and metal silicon oxynitride
US20060180844A1 (en) * 2000-02-23 2006-08-17 Agarwal Vishnu K Integrated circuitry and method of forming a capacitor
TW200947670A (en) * 2008-05-13 2009-11-16 Nanya Technology Corp Method for fabricating a semiconductor capacitor device
TW201246462A (en) * 2011-01-24 2012-11-16 Applied Materials Inc Pulse method of oxidizing sidewall dielectrics for high capacitance applications

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3863391B2 (ja) * 2001-06-13 2006-12-27 Ｎｅｃエレクトロニクス株式会社 半導体装置
US20050048795A1 (en) * 2003-08-27 2005-03-03 Chung-Chi Ko Method for ultra low-K dielectric deposition
TW200529325A (en) * 2003-09-30 2005-09-01 Aviza Tech Inc Growth of high-k dielectrics by atomic layer deposition
DE102005053322A1 (de) 2004-11-08 2006-06-08 Hynix Semiconductor Inc., Ichon Kondensator mit Zirkondioxid und Verfahren zur Herstellung desselben
KR100728962B1 (ko) * 2004-11-08 2007-06-15 주식회사 하이닉스반도체 지르코늄산화막을 갖는 반도체소자의 캐패시터 및 그 제조방법
US20070042130A1 (en) 2005-08-17 2007-02-22 Applied Materials, Inc. Method of treating films using UV-generated active species
KR100717768B1 (ko) * 2005-08-30 2007-05-11 주식회사 하이닉스반도체 반도체 소자의 캐패시터 및 그 형성방법과, 비휘발성메모리 소자 및 그 제조방법
KR100722989B1 (ko) * 2005-11-10 2007-05-30 주식회사 하이닉스반도체 캐패시터 및 그 제조 방법
US7659158B2 (en) * 2008-03-31 2010-02-09 Applied Materials, Inc. Atomic layer deposition processes for non-volatile memory devices
US8310807B2 (en) * 2009-06-12 2012-11-13 Micron Technology, Inc. Capacitors having dielectric regions that include multiple metal oxide-comprising materials
JP4988902B2 (ja) * 2009-07-31 2012-08-01 株式会社日立国際電気 半導体デバイスの製造方法及び基板処理装置
US8420208B2 (en) * 2010-08-11 2013-04-16 Micron Technology, Inc. High-k dielectric material and methods of forming the high-k dielectric material
US8772123B2 (en) * 2010-11-09 2014-07-08 Intermolecular, Inc. Band gap improvement in DRAM capacitors
US20120264284A1 (en) * 2011-04-14 2012-10-18 Wang shao-wei Manufacturing method for metal gate structure
US8815677B2 (en) * 2011-06-14 2014-08-26 Intermolecular, Inc. Method of processing MIM capacitors to reduce leakage current

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060180844A1 (en) * 2000-02-23 2006-08-17 Agarwal Vishnu K Integrated circuitry and method of forming a capacitor
TW200404911A (en) * 2002-07-19 2004-04-01 Asml Us Inc Metal organic chemical vapor deposition and atomic layer deposition of metal oxynitride and metal silicon oxynitride
TW200947670A (en) * 2008-05-13 2009-11-16 Nanya Technology Corp Method for fabricating a semiconductor capacitor device
TW201246462A (en) * 2011-01-24 2012-11-16 Applied Materials Inc Pulse method of oxidizing sidewall dielectrics for high capacitance applications

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