TWI683304B - Display device - Google Patents

Abstract

A display device includes multiple shift registers, multiple multiplexers, a driving chip, and multiple pixel circuits. The driving chip is configured to control the multiple shift registers and the multiple multiplexers. One of the multiple shift registers and one of the multiple multiplexers cooperatively drive part of the multiple pixel circuits. When the one of the multiple shift registers and the one of the multiple multiplexers are enabled in a first time period, other shift registers of the multiple shift registers and other multiplexers of the multiple multiplexers are enabled in a second time period within the first time period. The first time period is longer than the second time period.

Description

Display device

This disclosure relates to a display device, especially a partition-driven display device.

When the current mainstream mobile devices continue to display still images (for example, one of the desktop tabs is continuously displayed), the mobile device reduces the screen refresh rate of the display to reduce power consumption. However, when the user switches back to the desktop while playing multimedia files, the mobile device will operate the entire active area of the display at a high screen because the playback software will shrink and display a partition on the desktop and continue to play the multimedia files. Update rate to ensure users can get the best visual effect when watching multimedia files. In other words, even if only one partition actually needs a high frame update rate, the traditional mobile device still sets the entire active area to have a high frame update rate, thereby consuming a lot of power.

The present disclosure provides a display device including multiple shift register groups, multiplexer groups, drive chips, and multiple pixel circuits. The driving chip is used to control multiple shift register groups and multiple multiplexer groups group. One of the shift register groups of the plurality of shift register groups and one of the multiplexer groups of the multiplexer groups jointly drive a part of the pixel circuits in the plurality of pixel circuits. When one of the shift register groups and one of the multiplexer groups is enabled in the first period, the remaining shift register groups and the multiplexers of the multiple shift register groups The remaining multiplexer groups of the group are enabled in the second period of the first period, the first period is longer than the second period, so that some pixel circuits have the first frame update rate, and the Another part of the pixel circuit has a second picture update rate.

The above display device can operate multiple pixel circuits at different frame update rates to adaptively reduce power consumption.

100, 500, 1200‧‧‧ display device

110-1~110-y‧‧‧Shift register group

120-1~120-x‧‧‧multiplexer group

130‧‧‧Drive chip

140-1~140-x‧‧‧switch circuit

150‧‧‧ Active area

Ck1‧‧‧First Clock Group

Ck2‧‧‧Second Clock Group

Data‧‧‧Data signal

Sw-1~Sw-x‧‧‧switch signal

Mu-1~Mu-n‧‧‧multiplex signal

A1, A2‧‧‧ Division

1~x‧‧‧ordinate

1~y‧‧‧horizontal coordinate

P1‧‧‧ First period

P2‧‧‧Second period

P3‧‧‧The third period

310-1~310-x‧‧‧Peripheral signal cable

Tn-1~Tn-n‧‧‧switch

M1~M8‧‧‧First Transistor~Eighth Transistor

Clc‧‧‧capacitor unit

Ct‧‧‧Control signal

410‧‧‧Internal signal line

420‧‧‧conductive path

Px‧‧‧Pixel circuit

510‧‧‧Demultiplexer

De-1~De-m‧‧‧Demultiplex signal

In‧‧‧input signal

Mo‧‧‧Mode selection signal

610‧‧‧path selection unit

611‧‧‧The input terminal of the path selection unit

613, 615, 617, 619 Four outputs

620‧‧‧Mode decision circuit

621‧‧‧The input terminal of the mode determination circuit

623‧‧‧The first output terminal of the mode determination circuit

630‧‧‧ First selection circuit

631‧‧‧Input terminal of the first selection circuit

633, 635‧‧‧ First output and second output of the first selection circuit

640‧‧‧ Second selection circuit

641‧‧‧Input terminal of the second selection circuit

643, 645‧‧‧ The first output terminal and the second output terminal of the second selection circuit

650‧‧‧ Third selection circuit

651‧‧‧Input terminal of the third selection circuit

653, 655‧‧‧ The first output terminal and the second output terminal of the third selection circuit

Vref1‧‧‧First reference voltage

Vref2‧‧‧second reference voltage

V1‧‧‧ First output voltage

V2‧‧‧Second output voltage

In order to make the above and other objects, features, advantages and embodiments of the disclosed document more obvious and understandable, the drawings are described as follows: FIG. 1 is a simplified functional block diagram of a display device according to an embodiment of the disclosed document .

FIG. 2 is a simplified waveform diagram of multiple switching signals according to an embodiment of the present disclosure.

FIG. 3A is a schematic diagram of a routing method of a peripheral area according to an embodiment of the present disclosure.

FIG. 3B is a schematic diagram of a routing method of a peripheral area according to another embodiment of the present disclosure.

FIG. 4A is a simplified functional block diagram of a partition with a vertical coordinate of 1 in an active area according to an embodiment of the present disclosure.

FIG. 4B is a simplified functional block diagram of a partition with a vertical coordinate of 1 in an active area according to another embodiment of the present disclosure.

FIG. 4C is a simplified functional block diagram of a partition with a vertical coordinate of 1 in an active area according to another embodiment of the present disclosure.

FIG. 5 is a simplified functional block diagram of a display device according to another embodiment of the present disclosure.

FIG. 6 is a simplified functional block diagram of a demultiplexer according to an embodiment of the present disclosure.

FIG. 7 is a schematic circuit diagram of a first selection circuit according to an embodiment of the present disclosure.

FIG. 8 is a simplified waveform diagram of the demultiplexed signal, the first output voltage, and the second output voltage.

FIG. 9 is a schematic diagram of an equivalent circuit operation of the first selection circuit in the first operation stage.

FIG. 10 is a schematic diagram of an equivalent circuit operation of the first selection circuit in the second operation stage.

FIG. 11 is a schematic circuit diagram of a mode decision circuit according to an embodiment of the present disclosure.

FIG. 12 is a simplified functional block diagram of a display device according to another embodiment of the present disclosure.

The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numbers indicate the same or similar elements or methods Process.

FIG. 1 is a simplified functional block diagram of a display device 100 according to an embodiment of the present disclosure. The display device 100 includes a plurality of shift register groups 110-1~110-y, a plurality of multiplexer groups 120-1~120-x, a driving chip 130, and a plurality of switching circuits 140-1~140- x and active area 150. The active area 150 is arranged with a plurality of pixel circuits, and the active area 150 is based on the number of shift register groups 110-1~110-y (ie, y groups) and the multiplexer groups 120-1~ The number of 120-x (ie, x groups) is divided into x by y partitions, where each partition contains multiple pixel circuits. The display device 100 may operate one of the partitions at a higher frame update rate, and operate the other partitions at a lower frame update rate, so as to reduce the power consumption of the display device 100. In order to make the drawing simple and easy to explain, the other components and the connection relationship in the display device 100 are not shown in FIG. 1.

In practice, the multiplexer groups 120-1~120-x each contain multiple multiplexers, and each multiplexer can be implemented with 3 to 1 multiplexers or 4 to 1 multiplexers. For example, in an embodiment where the resolution of the active area 150 is 1920x1080, each of the multiplexer groups 120-1~120-x includes 1080/x multiplexers.

For ease of understanding, in this disclosure, the area outside the active area 150 will be referred to as the surrounding area. That is, the shift register groups 110-1~110-y, the multiplexer groups 120-1~120-x, the driving chip 130 and the switching circuits 140-1~140n-x are disposed in the peripheral area.

The driving chip 130 is used to provide the first clock signal group Ck1 or the second clock signal group Ck2 to the shift register group 110-1~110-y, where the first clock signal group Ck1 has a higher frequency and the second clock signal group Ck2 has a lower frequency. The shift register groups 110-1~110-y each operate at a corresponding frequency according to the received first clock signal group Ck1 or second clock signal group Ck2.

The selection circuits 140-1~140n-x are used for receiving the multiplex signals Mu-1~Mu-n from the driving chip 130 and correspondingly receiving the multiple switching signals Sw-1~Sw-x. For example, the selection circuit 140-1 receives the multiplex signals Mu-1~Mu-n and receives the switching signal Sw-1. The selection circuit 140-2 receives the multiplex signals Mu-1~Mu-n, and receives the switching signal Sw-2, and so on.

The lower case English indexes 1~x and 1~y in the component numbers and signal numbers used in the specification and drawings of this case are just for convenience to refer to individual components and signals, and are not intended to limit the number of the foregoing components and signals to specific number. In the specification and drawings of this case, if an element number or signal number is used without indicating the index of the element number or signal number, it means that the element number or signal number refers to the component group or signal group to which it belongs Any component or signal. For example, the object referred to by the component number 120-1 is the multiplexer group 120-1, and the object referred to by the component number 120 is an arbitrary multiplexer group among the multiplexer groups 120-1~120-x group. For another example, the object designated by the component number 140-1 is the selection circuit 140-1, and the object designated by the component number 140 is the arbitrary selection circuit among the selection circuits 140-1 to 140n-x. As another example, the object referred to by the signal number Sw-1 is the switching signal Sw-1, and the object referred to by the signal number Sw-1 is any unspecified switching signal among the switching signals Sw-1 to Sw-x.

In this embodiment, the driving chip 130 switches the switching signal Sw between the first voltage level (eg, high voltage level) and the second voltage level (eg, low voltage level). When the switching signal Sw received by the selection circuit 140 has the first voltage level, the selection circuit 140 outputs the received multiplex signals Mu-1~Mu-n to the corresponding multiplexer group coupled to the selection circuit 140 120, so that the selection circuit 140 corresponds to the coupled multiplexer group 120.

On the other hand, when the switching signal Sw received by the selection circuit 140 has the second voltage level, the selection circuit 140 does not output the received multiplex signals Mu-1~Mu-n. At this time, the multiplexer group 120 corresponding to the selection circuit 140 is in a disabled state.

The multiplexer group 120 is used to receive the data signal Data from the driving chip 130, and the selection circuit 140 correspondingly coupled from the multiplexer group 120 receives the multiplex signals Mu-1~Mu-n and the selection signal Sw. When the multiplexer group 120 is in the enabled state, the multiplexer group 120 transmits the switching signal Sw with the first voltage level to the pixel circuits in the partition to which the multiplexer group 120 is coupled, The pixel circuit coupled to the multiplexer group 120 is set to a state in which the data signal Data can be written. At this time, the multiplexer group 120 will also sequentially transmit the data signal Data to the pixel circuits coupled to the multiplexer group 120 according to the received multiplex signals Mu-1~Mu-n.

For example, when the multiplexer group 120-1 is in the enabled state, the multiplexer group 120-1 transmits the switching signal Sw with the first voltage level and the data signal Data to a plurality of vertical coordinates of 1. The pixel circuits in the partition.

On the other hand, when the multiplexer group 120 is disabled At this time, the multiplexer group 120 transmits the switching signal Sw with the second voltage level to the pixel circuits in the partition to which the multiplexer group 120 is coupled, to couple the multiplexer group 120 The pixel circuit is set to a state where the data signal Data cannot be written. The detailed operation mode and circuit architecture of the pixel circuit will be explained in the following paragraphs.

It is worth noting that the multiplex signals Mu-1~Mu-n are used to control the operation of the multiplexers in the multiplexer group 120. In the embodiment where the multiplexer in the multiplexer group 120 is implemented as a 3-to-1 multiplexer, the driving chip 130 provides a total of 3 multiplex signals Mu-1~Mu-3 to the multiplexer group 120 . In the embodiment where the multiplexer is implemented as a 4-to-1 multiplexer, the driving chip 130 provides a total of 4 multiplex signals Mu-1~Mu-4 to the multiplexer group 120.

In this embodiment, the multiple pixel circuits in each partition are driven jointly by a corresponding shift register group 110 and a multiplexer group 120. For example, the pixel circuits in the partition A1 with coordinates (1,2) are driven by the shift register group 110-2 and the multiplexer group 120-1. For another example, the pixel circuit in the partition A2 whose coordinates are (x, 2) is driven by the shift register group 110-2 and the multiplexer group 120-x.

When one of the partitions of the display device 100 requires a high screen refresh rate and the other partitions do not require a high screen refresh rate, the driver chip 130 sets one of the shift register groups 110 to be based on the first clock signal The group Ck1 operates at a higher frequency, and the other plurality of shift register groups 110 are set to operate at a lower frequency according to the second clock signal group Ck2. At this time, the driving chip 130 also sets one of the multiplexer groups 120 to be enabled for a long time, and sets the other multiplexer groups 120 to be enabled Shorter time.

In this way, the partitions jointly driven by the shift register group 110 operating at a higher frequency and the multiplexer group 120 enabled for a longer time will have a higher frame update rate. On the other hand, the partitions jointly driven by the shift register group 110 operating at a lower frequency and the multiplexer group 120 enabling a shorter time will have a lower frame update rate.

In the following, the method of setting different partitions to have different screen update rates will be specifically described using FIG. 1 and FIG. 2. FIG. 2 is a simplified waveform diagram of the switching signals Sw-1~Sw-x according to an embodiment of the present disclosure. The switching signal Sw-1 is set to maintain the first voltage level (eg, high voltage level) in the first period P1. The switching signals Sw-2~Sw-x are set to maintain the first voltage level in the second period P2, and maintain the second voltage level in the third period P3 after the second period P2 (for example, Low voltage level).

It is worth noting that the first period P1 includes a second period P2 and a third period P3, and the sum of the lengths of the second period P2 and the third period P3 is equal to the length of the first period P1. In this embodiment, the first period P1 is 1 second, and the second period P2 and the third period P3 are 1/60 second and 59/60 second, respectively. However, the present disclosure is not limited to this embodiment, and the lengths of the first period P1, the second period P2, and the third period P3 can be adjusted according to actual design requirements.

In the first period P1, the selection circuit 140-1 transmits the multiplex signals Mu-1~Mu-n to the multiplexer group 120-1, so that the multiplexer group 120-1 is in an enabled state. In the second period P2, the selection circuit 140-2~140n-x will correspondingly transmit the multiplex signals Mu-1~Mu-n to the multiplexer group 120-2~120-x, so that the multiplexer group 120-2~120-x is in Energy state. In addition, in the third period P3, the selection circuits 140-2~140n-x do not output the multiplex signals Mu-1~Mu-n, so the multiplexer groups 120-2~120-x are disabled.

In this embodiment, the driving chip 130 sets the shift register group 110-2 to operate according to a higher frequency, and sets the shift register group 110-1 and the shift register group 110-3~110-y are set to operate at a lower frequency. Therefore, the shift register group 110-2 drives the pixel circuits coupled thereto multiple times in the first period P1, that is, the pixel circuits in the multiple partitions with the horizontal coordinate of 2. The shift register group 110-1 and the shift register group 110-3~110-y will only drive the pixel circuits coupled thereto during the second period P2, that is, the abscissa is 1. Pixel circuits in multiple partitions from 2 to y.

In the second period P2, since the selection signals Sw-1~Sw-x all have the first voltage level, all the pixel circuits in the active area 150 are set to a state in which the data signal Data can be written. Driven by the shift register groups 110-1~110-y, all the pixel circuits in the active area 150 sequentially receive the data signal Data. Therefore, in the second period P2, the display images of all the partitions of the active area 150 are updated by one frame.

Next, since the shift register group 110-1 and the shift register group 110-3~110-y operate at a lower frequency, in the third period P3, the shift register group 110- 1 and the shift register group 110-3~110-y will not drive the pixel circuits coupled to them. Therefore, the shift register group The partitions driven by 110-1 and shift register groups 110-3~110-y will not update the display screen in the third period P3.

On the other hand, since the shift register group 110-2 operates at a higher frequency, in the third period P3, the shift register group 110-2 will drive the pixel circuit coupled thereto multiple times. Since the selection signal Sw-1 is maintained at the first voltage level in the third period P3, but the selection signals Sw-2~Sw-x have been switched to the second voltage level, the ordinates in the partition 2~n The pixel circuit will be set to a state where it cannot receive the data signal Data.

In this case, the pixel circuit in the partition A1 will be written to the data signal Data multiple times in the third period P3, so that the display screen of the partition A1 is updated in the third period P3 by multiple frames (for example, 59 frames ) Screen. On the other hand, since multiple partitions with a vertical coordinate of 2~x and a horizontal coordinate of 2 are set to be unable to write data signals Data, even if they are driven multiple times by the multiplexer group 110-2, the vertical coordinate is 2~ The display screens of multiple partitions with x and horizontal coordinate 2 will remain unchanged in the third period P3.

As a result, the partition A1 will have a frame refresh rate of 60 Hz, and the other partitions of the active area 150 will have a frame refresh rate of 1 Hz. However, this disclosure is not limited to this embodiment, and the frame update rate of each partition can be determined by adjusting the frequency of the first clock signal group Ck1 and the second clock signal group Ck2. In an embodiment, the picture update rate of one of the partitions of the active area 150 is set to 60 Hz, and the picture update rate of the other partitions is set to 15 Hz.

FIG. 3A is a schematic diagram of a routing method of a peripheral area according to an embodiment of the present disclosure. As shown in FIG. 3A, the switching circuit 140 includes multiple Switches Tn-1~Tn-n, and each of the switches Tn-1~Tn-n includes a control terminal, a first terminal, and a second terminal. The control terminals of the switches Tn-1~Tn-n are used to receive one of the switching signals Sw-1~Sw-x, and the first terminals of the switches Tn-1~Tn-n are respectively used to receive the multiplex signal Mu- 1~Mu-n, and the second ends of the switches Tn-1~Tn-n are coupled to the multiplexer group 120 to which the switching circuit 140 is coupled.

For example, the control terminals of the switches Tn-1~Tn-n of the switching circuit 140-1 are used to receive the switching signal Sw-1, and the first ends of the switches Tn-1~Tn-n of the switching circuit 140-1 are used to correspond To receive the multiplex signals Mu-1~Mu-n, the second ends of the switches Tn-1~Tn-n of the switching circuit 140-1 are coupled to the multiplexer group 120-1.

As shown in FIG. 3A, the display device 100 further includes a plurality of peripheral signal lines 310-1 to 310-x located in the peripheral area. The peripheral signal lines 310-1~310-x are correspondingly coupled to the control terminals of the switches Tn-1~Tn-n of the switching circuits 140-1~140n-x, and the peripheral signal lines 310-1~310-x correspondingly Transmit switching signals Sw-1~Sw-x. For example, the peripheral signal line 310-1 is coupled to the control terminals of the switches Tn-1~Tn-n of the switching circuit 140-1, and is used to transmit the switching signal Sw-1. For another example, the peripheral signal line 310-2 is coupled to the control terminals of the switches Tn-1 to Tn-n of the switching circuit 140-2, and is used to transmit the switching signal Sw-2, and so on.

Referring to FIGS. 1 and 3A at the same time, the peripheral signal lines 310-1 to 310-x extend from the first side (eg, left side) of the display device 100 toward the second side (eg, right side) of the display device 100, and The first side and the second side of the display device 100 are mutually opposite sides. In other words, the periphery of this embodiment The signal lines 310-1~310-x extend in the same direction.

In practice, the switches Tn-1~Tn-n can be implemented with various suitable types of N-type transistors, such as N-type thin-film transistors (TFTs).

FIG. 3B is a schematic diagram of a routing method of a peripheral area according to another embodiment of the present disclosure. The embodiment of FIG. 3B is similar to the embodiment of FIG. 3A, the difference is that in the embodiment of FIG. 3B, the peripheral signal lines 310-1 to 310-i are directed from the first side of the display device 100 toward the display device 100. The second side extends, and the peripheral signal lines 310-(i+1)~310-x extend from the second side of the display device 100 toward the first side of the display device 100. The first side and the second side of the display device 100 are mutually opposite sides, i is a positive integer and i is less than x.

By dividing the peripheral signal lines 310-1~310-x into two parts extending in opposite directions, the wiring space required for the peripheral signal lines 310-1~310-x can be saved. Therefore, the embodiment of FIG. 3B has the advantage of a narrow bezel.

FIG. 4A is a simplified functional block diagram of a partition with a vertical coordinate of 1 in the active area 150 according to an embodiment of the present disclosure. As shown in FIG. 4A, the active area 150 includes a plurality of pixel circuits Px, and the display device 100 further includes a plurality of internal signal lines 410. A plurality of internal signal lines 410 extend from the peripheral area into the active area 150, and the plurality of internal signal lines 410 are alternately arranged with the pixel circuits Px of a plurality of rows. One side (for example, the right side) of each internal signal line 410 is adjacent to a row of pixel circuits Px.

In this embodiment, a plurality of internal signal lines 410 are each coupled to a row of pixel circuits Px adjacent to the right side thereof, and a plurality of internal signal lines 410 One end of is commonly coupled to a conductive path 420. The plurality of internal signal lines 410 receive the switching signal Sw-1 from the multiplexer group 210-1 through the conductive path 420. In this way, multiple internal signal lines 410 can transmit the switching signal Sw-1 to all the pixel circuits Px in the partition with the vertical coordinate of 1, to determine whether the pixel circuit Px in the partition with the vertical coordinate of 1 can Be written into the data signal Data.

In addition, the pixel circuit Px includes a first transistor M1, a second transistor M2, and a capacitor unit Clc. The first transistor M1 includes a first end, a second end, and a control end. The first end of the first transistor M1 is used to receive the data signal Data, and the control end of the first transistor M1 is used to receive the control signal Ct. The control signal Ct is provided by the corresponding shift register group 110. The second transistor M2 includes a first end, a second end, and a control end, wherein the first end of the second transistor M2 is coupled to the second end of the first transistor M1, and the second end of the second transistor M2 is coupled Connected to the capacitor unit Clc, the control terminal of the second transistor M2 is coupled to one of the plurality of internal signal lines 410.

Please refer to FIG. 2 and FIG. 4A at the same time. During the first period P1, the second transistor M2 will remain in the on state because it receives the switching signal Sw-1 having the first voltage level. Therefore, when the shift register group 110 uses the control signal Ct to turn on the first transistor M1, the data signal Data can be transmitted to the capacitor unit Clc through the first transistor M1 and the second transistor M2.

In practice, the first transistor M1 and the second transistor M2 can be implemented with various suitable types of N-type transistors. The capacitor unit Clc can be realized by a liquid crystal layer filled between glass substrates.

In this embodiment, the connection method, components, implementations, and advantages of the partition with the vertical coordinate of 1 are also applicable to the partition with the vertical coordinate of 2 to n. also That is, the multiple internal signal lines 410 in the active area 150 are divided into multiple groups, and the number of the internal signal lines 410 is the same as the number of the multiplexer groups 120-1~120-x (for example, x groups ), and the internal signal lines 410 in the partitions with the same vertical coordinates belong to the same group.

Multiple internal signal lines 410 belonging to the same group are coupled to each other and to the corresponding multiplexer group 120. For example, multiple internal signals in the partition with the vertical coordinate of 2 are coupled to each other and to the multiplexer group 120-2. For another example, multiple internal signals in the partition with the vertical coordinate of 3 are coupled to each other and to the multiplexer group 120-3, and so on.

In some embodiments that have no special requirements on the thickness of the frame, the plurality of internal signal lines 410 of the active area 150 are not coupled to each other, but are directly connected to the driving chip 130. The switching signals Sw-1~Sw-x are directly provided by the driving chip 130 to the plurality of internal signal lines 410 of the active area 150, rather than being provided by the multiplexer groups 120-1~120-x. The remaining connection methods, components, embodiments, and advantages of the foregoing FIG. 4A are all applicable to this embodiment, and for the sake of brevity, they will not be repeated here.

FIG. 4B is a simplified functional block diagram of the partition with the vertical coordinate of 1 in the active area 150 according to another embodiment of the present disclosure. The embodiment of FIG. 4B is similar to the embodiment of FIG. 4A, the difference is that in the embodiment of FIG. 4B, a plurality of internal signal lines 410 are each located between two rows of pixel circuits Px, and a plurality of internal signal lines 410 Two lines of pixel circuits Px are spaced from each other. Each of the plurality of internal signal lines 410 is coupled to two rows of pixel circuits Px adjacent thereto to provide the switching signal Sw-1 to the two rows of pixel circuits Px coupled thereto.

In this embodiment, the connection method, components, implementations, and advantages of the partition with the vertical coordinate of 1 are also applicable to the partition with the vertical coordinate of 2 to n. In this embodiment, since two adjacent rows of pixel circuits Px share one internal signal line 410, this embodiment has the advantages of a small number of signal lines and a high aperture ratio.

FIG. 4C is a simplified functional block diagram of a partition with a vertical coordinate of 1 in the active area 150 according to another embodiment of the present disclosure. The embodiment of FIG. 4C is similar to the embodiment of FIG. 4A, the difference is that each of the plurality of internal signal lines 410 provides a switching signal Sw-1 to a plurality of rows of pixel circuits Px on one side and adjacent to each other . For example, the leftmost internal signal line 410 in FIG. 4C provides the switching signal Sw-1 to the two rows of pixel circuits on the right side.

Please note that the number of rows of pixel circuits Px enclosed by two adjacent switching signal lines 410 in this embodiment is only an exemplary description, and is not intended to limit the actual implementation of this embodiment. The number of rows of pixel circuits Px sandwiched between two adjacent switching signal lines 410 can be adjusted according to the actual impedance of the switching signal line 410 and other conditions.

In this embodiment, the connection method, components, implementations, and advantages of the partition with the vertical coordinate of 1 are also applicable to the partition with the vertical coordinate of 2 to n. In this embodiment, since a plurality of rows of pixel circuits Px adjacent to each other share an internal signal line 410, this embodiment also has the advantages of a small number of signal lines and a high aperture ratio.

FIG. 5 is a simplified functional block diagram of a display device 500 according to another embodiment of the present disclosure. The display device 500 is similar to the display device 100, the difference is that the switching signals Sw-1~Sw-x are caused by the demultiplexer 510 The output is to the switching circuits 140-1~140n-x instead of being directly output by the driving chip 130.

The demultiplexer 510 is used for receiving multiple demultiplexing signals De-1~De-m, the input signal In and the mode determining signal Mo from the driving chip 130, where m is a positive integer and x is equal to the power of m. The demultiplexer 510 is used to determine the voltage levels of the switching signals Sw-1 to Sw-x according to the demultiplexing signals De-1 to De-m and the mode decision signal Mo.

When the mode determination signal Mo has a third voltage level (for example, a high voltage level), the demultiplexer 510 will selectively set a switching signal Sw to have a demultiplexing signal De-1~De-m The first voltage level, and the other switching signal Sw is set to have the second voltage level. In this case, a partition of the active area 150 will have a high picture update rate.

On the other hand, when the mode decision signal Mo has a fourth voltage level (for example, a low voltage level), the demultiplexer 510 sets each of the switching signals Sw-1~Sw-x to have the first Voltage level. In this case, all partitions in the active area 150 will have a high picture update rate.

In other words, the driving chip 130 of the display device 500 can determine the operating state of the active area 150 using fewer signals. Therefore, the number of output pins required by the driving chip 130 of the display device 500 is small, so that the display device 500 has the advantage of low manufacturing cost.

FIG. 6 is a simplified functional block diagram of the demultiplexer 510 according to an embodiment of the present disclosure. The demultiplexer 510 includes multiple path selection units 610 and multiple mode decision circuits 620. Each path selection unit 610 It is used to receive the two consecutive numbers in the demultiplexing signals De-1~De-m. For example, one of the path selection units 610 receives the demultiplexing signal De-1 and the demultiplexing signal De-2, and the other 610 receives the demultiplexing signal De-2 and the demultiplexing signal De-3.

Each path selection unit 610 includes an input terminal 611, a first output 613, a second output terminal 615, a third output terminal 617, and a fourth output terminal 619. The input terminal 611 of the path selection unit 610 is used to receive the input signal In, or is coupled to the first output 613, the second output terminal 615, the third output terminal 617, or the fourth output terminal 619 of another path selection unit 610.

The first output terminal 613, the second output terminal 615, the third output terminal 617, and the fourth output terminal 619 of a portion of the path selection unit 610 are each coupled to the input terminal 611 of one of the other path selection units 610. The first output terminal 613, the second output terminal 615, the third output terminal 617, and the fourth output terminal 619 of the other partial routing unit 610 are each coupled to a mode decision circuit 620.

Each mode decision circuit 620 is used to receive the mode decision signal Mo and the first reference voltage Vref1, and includes an input terminal 621 and a first output terminal 623. The input terminal 621 of the mode decision circuit 620 is correspondingly coupled to a path selection unit 610, and the first output terminal 623 of the mode decision circuit 620 is coupled to one of the switching circuits 140-1~140n-x.

In this embodiment, the first reference voltage Vref1 has a first voltage level. The path selection unit 610 will connect the input terminal 611 with one of the first output 613, the second output terminal 615, the third output terminal 617, and the fourth output terminal 619 according to the two received demultiplexing signals De .

When the mode decision signal Mo has the third voltage level, each of the mode decision circuits 620 will turn on the switching circuits 140-1~140n-x and the corresponding path selection unit 610. In this way, the transmission path of the input signal In can be determined by the plurality of path selection units 610, so that the input signal In is selectively transmitted to the switching circuit 140-1 as the switching signal Sw having the first voltage level One of ~140n-x.

On the other hand, when the mode decision signal Mo has the fourth voltage level, the mode decision circuit 620 does not turn on the switching circuits 140-1 to 140n-x and the path selection unit 610, but outputs the first reference voltage Vref1 to the switching circuit Each of 140-1~140n-x. As a result, each of the switching circuits 140-1~140n-x will receive the switching signals Sw-1~Sw-x with the first voltage level.

As shown in FIG. 6, the path selection unit 610 includes a first selection circuit 630, a second selection circuit 640 and a third selection circuit 650. The circuit selection unit 610 receiving the demultiplexing signal De-1 and the demultiplexing signal De-2 will be taken as an example to further explain the circuit architecture of the path selection unit 610.

The first selection circuit 630 is used to receive the demultiplexing signal De-1, and includes an input terminal 631, a first output terminal 633, and a second output terminal 635. The input terminal 631 of the first selection circuit 630 is coupled to the input terminal 611 of the path selection unit 610.

The second selection circuit 640 is used to receive the demultiplexing signal De-2, and includes an input terminal 641, a first output terminal 643, and a second output terminal 645. The input terminal 641 of the second selection circuit 640 is coupled to the first output terminal 633 of the first selection circuit 630. The first output terminal 643 of the second selection circuit 640 It is coupled to the first output terminal 613 of the path selection unit 610. The second output terminal 645 of the second selection circuit 640 is coupled to the second output terminal 615 of the path selection unit 610.

The third selection circuit 650 is used to receive the demultiplexing signal De-2, and includes an input terminal 651, a first output terminal 653, and a second output terminal 655. The input terminal 651 of the third selection circuit 650 is coupled to the second output terminal 635 of the first selection circuit 630. The first output terminal 653 of the third selection circuit 650 is coupled to the third output terminal 617 of the path selection unit 610. The second output terminal 655 of the third selection circuit 650 is coupled to the fourth output terminal 619 of the path selection unit 610.

The other path selection units 610 in the demultiplexer 510 also have a circuit architecture similar to that described above. For brevity, they will not be repeated here.

FIG. 7 is a circuit schematic diagram of the first selection circuit 630 according to an embodiment of the present disclosure. As shown in FIG. 7, the first selection circuit 630 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The third transistor M3 includes a first end, a second end, and a control end. The first terminal of the third transistor M3 is coupled to the first output terminal 633 of the first selection circuit 630. The second terminal of the third transistor M3 is coupled to the input terminal 631 of the first selection circuit 630. The control terminal of the third transistor M3 is used to receive the demultiplexing signal De-1.

The fourth transistor M4 includes a first end, a second end, and a control end. The first terminal of the fourth transistor M4 is coupled to the second output terminal 635 of the first selection circuit 630. The second terminal of the fourth transistor M4 is coupled to the first selection circuit 630 The input 631. The control terminal of the fourth transistor M4 is used to receive the demultiplexing signal De-1.

The fifth transistor M5 includes a first end, a second end, and a control end. The first terminal of the fifth transistor M5 is used to receive the second reference voltage Vref2, wherein the second reference voltage Vref2 has the aforementioned second voltage level. The second terminal of the fifth transistor M5 is coupled to the first output terminal 633 of the first selection circuit 630. The control terminal of the fifth transistor M5 is used to receive the demultiplexing signal De-1.

The sixth transistor M6 includes a first end, a second end, and a control end. The first terminal of the sixth transistor M6 is used to receive the second reference voltage Vref2. The second terminal of the sixth transistor M6 is coupled to the second output terminal 635 of the first selection circuit 630. The control terminal of the sixth transistor M6 is used to receive the demultiplexing signal De-1.

In practice, the third transistor M3 and the sixth transistor M6 can be implemented with various suitable types of N-type transistors. The fourth transistor M4 and the fifth transistor M5 can be implemented with various suitable types of P-type transistors.

For convenience of description, the voltage of the first output terminal 633 of the first selection circuit 630 is referred to as a first output voltage V1, and the voltage of the second output terminal 635 of the first selection circuit 630 is referred to as a second output voltage V2. FIG. 8 is a schematic diagram illustrating the waveforms of the multiplexing signal De-1, the first output voltage V1 and the second output voltage V2. The operation of the first selection circuit 630 will be further described below with reference to FIG. 8.

In the first operation stage, the demultiplexing signal De-1 has a high voltage level, so that the third transistor M3 and the sixth transistor M6 are in an on state, and the fourth transistor M4 and the fifth transistor M5 are in an off state Broken state.

In this case, the first selection circuit 630 is equivalent to the equivalent circuit shown in FIG. 9. The input signal In is transmitted to the first output terminal 633 of the first selection circuit 630 through the third transistor M3, so that the first output voltage V1 has a high voltage level. In addition, the second reference voltage Vref2 is transmitted to the second output terminal 635 of the first selection circuit 630 through the sixth transistor M6, so that the second output voltage V2 has a low voltage level.

In the second operation stage, the demultiplexing signal De-1 has a low voltage level, so that the third transistor M3 and the sixth transistor M6 are in an off state, and the fourth transistor M4 and the fifth transistor M5 are in On state.

In this case, the first selection circuit 630 is equivalent to the equivalent circuit shown in FIG. 10. The input signal In is transmitted to the second output terminal 635 of the first selection circuit 630 through the fourth transistor M4, so that the second output voltage V2 has a high voltage level. In addition, the second reference voltage Vref2 is transmitted to the first output terminal 633 of the first selection circuit 630 through the fifth transistor M5, so that the first output voltage V1 has a low voltage level.

In an embodiment, the third transistor M3 and the sixth transistor M6 are implemented with P-type transistors, and the fourth transistor M4 and the fifth transistor M5 are implemented with N-type transistors. In this case, when the demultiplexing signal De-1 has a high voltage level, the first output voltage V1 will have a low voltage level, and the second output voltage V2 will have a high voltage level. When the demultiplexing signal De-1 has a low voltage level, the first output voltage V1 will have a high voltage level, and the second output voltage V2 will have a low voltage level.

As can be seen from the above, by adjusting the voltage level of the demultiplexing signal De-1, the transmission of the input signal In within the first selection circuit 630 can be determined path.

The second selection circuit 640 and the third selection circuit 650 are similar to the first selection circuit 630, the difference is that in the second selection circuit 640 and the third selection circuit 650, the control terminals of the third transistor M3 and the fourth transistor M4 It is used to receive the demultiplexing signal De-2. The remaining connection methods, components, implementations, and advantages of the first selection circuit 630 described above are applicable to the second selection circuit 640 and the third selection circuit 650. For brevity, they are not repeated here.

FIG. 11 is a schematic circuit diagram of a mode decision circuit 620 according to an embodiment of the present disclosure. The mode decision circuit 620 includes a seventh transistor M7 and an eighth transistor M8. The seventh transistor M7 includes a first end, a second end, and a control end. The first terminal of the seventh transistor M7 is coupled to the input terminal 621 of the mode determination circuit 620. The second terminal of the seventh transistor M7 is coupled to the first output terminal 623 of the mode decision circuit 620. The control terminal of the seventh transistor M7 is used to receive the mode decision signal Mo.

The eighth transistor M8 includes a first end, a second end, and a control end. The first terminal of the eighth transistor M8 is used to receive the first reference voltage Vref1. The second terminal of the eighth transistor M8 is coupled to the first output terminal 623 of the mode decision circuit 620. The control terminal of the eighth transistor M8 is used to receive the mode decision signal Mo.

In practice, the seventh transistor M7 can be implemented with various suitable types of N-type transistors. The eighth transistor M8 can be implemented with various suitable types of P-type transistors.

When the mode decision signal Mo has a high voltage level, the seventh The crystal M7 will be turned on and the eighth transistor M8 will be turned off. Therefore, the input terminal 621 and the first output terminal 623 of the mode decision circuit 620 are turned on, so that the first output voltage V1 or the second output voltage V2 from the second selection circuit 640 or the third selection circuit 650 can be used as the switching signal Sw is transferred to the switching circuit 140.

On the other hand, when the mode decision signal Mo has a low voltage level, the seventh transistor M7 will be turned off and the eighth transistor M8 will be turned on. Therefore, the first reference voltage Vref1 is transmitted to the first output terminal 623 of the mode decision circuit 620 via the eighth transistor M8. At this time, the first reference voltage Vref1 is transmitted to the switching circuit 140 as the switching signal Sw.

In an embodiment, the seventh transistor M7 is implemented with a P-type transistor, and the eighth transistor M8 is implemented with an N-type transistor. In this case, when the mode decision signal Mo has a high voltage level, the seventh transistor M7 will be turned off and the eighth transistor M8 will be turned on. When the mode decision signal Mo has a low voltage level, the seventh transistor M7 will be turned on and the eighth transistor M8 will be turned off.

In some embodiments that have no special requirements on the thickness of the frame, the aforementioned switching circuits 140-1 to 140n-x may also be omitted. FIG. 12 is a simplified functional block diagram of a display device 1200 according to another embodiment of the present disclosure. The display device 1200 is similar to the display device 100, the difference is that the driving chip 130 of the display device 1200 directly controls whether the multiplexer groups 120-1~120-x are enabled, without the need to pass through the aforementioned switching circuits 140-1~140n- x to control the multiplexer group 120-1~120-x.

Specifically, the driving chip 130 is directed to the multiplexer group Each of 120-1~120-x outputs multiple multiplex signals individually. For example, the driving chip 130 outputs a plurality of first multiplex signals Mu1-1~Mu1-n to the multiplexer group 120-1, and outputs a plurality of second multiplex signals Mu2-1~Mu2-n to the multiplexer group 120 -2, output multiple x-th multiplex signals Mux-1~Mux-n to the multiplexer group 120-x, and so on, which will not be repeated here.

Since the display device 1200 does not need to use the aforementioned switching circuits 140-1 to 140n-x, the display device 1200 has the advantages of simple circuit structure and high operation reliability. The remaining connection methods, components, embodiments, and advantages of the foregoing display device 100 are all applicable to the display device 1200, and for the sake of brevity, they are not repeated here.

In summary, the display device 100, the display device 500, and the display device 1200 can operate the partitions of the active area 150 at different screen update rates, thus having the advantage of being able to adjust power consumption adaptively. If the display device 100, the display device 500, and the display device 1200 are applied to a mobile device with limited power, the use time of the mobile device can be effectively extended.

Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The specification and the scope of patent application do not use the difference in names as a way to distinguish the components, but the difference in the functions of the components as the basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to." In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be electrically connected or not The signal connection methods such as wire transmission and optical transmission are directly connected to the second element, or indirectly electrically or signally connected to the second element through other elements or connection means.

In addition, unless otherwise specified in the description, any singular case also includes the meaning of the plural case.

The above are only the preferred embodiments of the disclosed document, and any changes and modifications made according to the requested items of the disclosed document shall fall within the scope of the disclosed document.

100‧‧‧Display device

110-1~110-y‧‧‧Shift register group

120-1~120-x‧‧‧multiplexer group

130‧‧‧Drive chip

140-1~140-x‧‧‧switch circuit

150‧‧‧ Active area

Ck1‧‧‧First Clock Group

Ck2‧‧‧Second Clock Group

Data‧‧‧Data signal

Sw-1~Sw-x‧‧‧switch signal

Mu-1~Mu-n‧‧‧multiplex signal

A1, A2‧‧‧ Division

1~x‧‧‧ordinate

1~y‧‧‧horizontal coordinate

Claims (18)

A display device includes: a plurality of shift register groups; a plurality of multiplexer groups; a driving chip for controlling the plurality of shift register groups and the plurality of multiplexer groups And a plurality of pixel circuits, wherein one of the shift register groups of the plurality of shift register groups and one of the multiplexer groups of the multiplexer groups jointly drive the multiple Part of the pixel circuits in each pixel circuit; wherein when the one of the shift register groups and the one of the multiplexer groups are enabled in a first period, the plurality of shift register groups The remaining shift register groups of the group and the remaining multiplexer groups of the multiplexer groups are enabled in a second period of the first period, the first period is longer than the second period, In order to make the part of the pixel circuits have a first frame update rate, and make the other part of the pixel circuits have a second frame update rate. The display device of claim 1, wherein the first picture update rate is higher than the second picture update rate. The display device of claim 1 further includes: a plurality of switching circuits, correspondingly coupled to the plurality of multiplexer groups, for receiving a plurality of switching signals and a plurality of multiplex signals from the driving chip; wherein each Switching circuits for receiving the plurality of switching signals A switching signal and the multiplex signals, when one of the switching signals has a first voltage level, the switching circuit outputs the multiplex signals to the multiplexer group coupled to the switching circuit, To enable a multiplexer group coupled to the switching circuit, when one of the switching signals has a second voltage level, the switching circuit does not output the multiplexing signals; wherein the display device includes an active area And a peripheral area, the plurality of pixel circuits are arranged in the active area, the plurality of shift register groups, the plurality of multiplexer groups, the driving chip and the plurality of switching circuits are located in the peripheral area. The display device according to claim 3, wherein the switching circuit includes a plurality of switches, and each switch includes: a control terminal for receiving one of the plurality of switching signals; and a first terminal for receiving the multi-switch One of the multiplex signals; and a second terminal, coupled to the multiplexer group coupled to the switching circuit. The display device according to claim 3 further includes: a plurality of peripheral signal lines, correspondingly coupled to the plurality of switching circuits, for correspondingly transmitting the plurality of switching signals, wherein the plurality of peripheral signal lines are located in the peripheral area Wherein the plurality of peripheral signal lines extend from a first side of the display device toward a second side of the display device, and the first side and the second side are opposite sides of each other. The display device according to claim 3 further includes: a plurality of peripheral signal lines, correspondingly coupled to the plurality of switching circuits, for correspondingly transmitting the plurality of switching signals, wherein the plurality of peripheral signal lines are located in the peripheral area Wherein some of the peripheral signal lines extend from a first side of the display device toward a second side of the display device, and another portion of the peripheral signal lines of the peripheral signal lines extend from the second side It extends toward the first side, and the first side and the second side are opposite sides of each other. The display device according to claim 3, wherein the plurality of pixel circuits are arranged into a pixel matrix having a plurality of rows of pixel circuits and a plurality of columns of pixel circuits, and the display device further includes: a plurality of internal signal lines, from which The peripheral area extends into the active area and is used to transmit the plurality of switching signals to the pixel matrix; wherein when the one of the shift register groups and the one of the multiplexer groups are caused during the first period When enabled, the switching signal received by the partial pixel circuit is maintained at the first voltage level during the first period, and the switching signal received by the other partial pixel circuit is maintained at the first voltage level during the second period The voltage level is maintained at the second voltage level in a third period, and the sum of the lengths of the second period and the third period is equal to the length of the first period. The display device according to claim 7, wherein the plurality of internal The signal lines are alternately arranged with the multiple rows of pixel circuits. The display device according to claim 8, wherein the plurality of internal signal lines are divided into a plurality of groups, the number of the plurality of groups is the same as the number of the multiplexer groups, and the internal signals in each group The wires are coupled to each other. The display device of claim 7, wherein each internal signal line provides the received switching signal to a first row of pixel circuits adjacent to the internal signal line and a second row of pixels adjacent to the internal signal line A pixel circuit, and the internal signal line is located between the first row of pixel circuits and the second row of pixel circuits. The display device of claim 7, wherein each internal signal line transmits the received switching signal to a plurality of rows of pixel circuits adjacent to each other on the side of the internal signal line. The display device according to claim 7, wherein each pixel circuit includes: a capacitor unit; a first transistor including a first terminal, a second terminal, and a control terminal, wherein the first transistor One end is used to receive a data signal, the control end of the first transistor is used to receive a control signal; and a second transistor includes a first end, a second end and a control end, wherein the first The first end of the two transistors is coupled to the In the second end, the second end of the second transistor is coupled to the capacitor unit, and the control end of the second transistor is coupled to one of the plurality of internal signal lines. The display device according to claim 1 further includes: a demultiplexer for outputting a plurality of switching signals according to an input signal output by the driving chip and a plurality of demultiplexing signals; a plurality of switching circuits are correspondingly coupled In the multiplexer group, for receiving the multiple switching signals from the demultiplexer and for receiving multiple multiplexing signals from the driving chip; wherein each switching circuit is used to receive the multiple switching One of the switching signals of the signal and the multiplex signals, when the one of the switching signals has a first voltage level, the switching circuit outputs the multiplex signals to the multiplexer coupled to the switching circuit Group, so that the multiplexer group that can be coupled to the switching circuit does not output the multiplex signals when one of the switching signals has a second voltage level. The display device of claim 13, wherein the demultiplexer is used to receive a mode decision signal from the driver chip, and when the mode select signal has a third voltage level, the demultiplexer uses the multiple switching signals One of them is set to have the first voltage level, and the remaining switching signals of the plurality of switching signals are set to have the second voltage level. When the mode selection signal has a fourth voltage level, the The demultiplexer sets the plurality of switching signals to have the first voltage level. The display device of claim 14, wherein the demultiplexer includes: a plurality of path selection units, wherein each path selection unit is used to receive a first demultiplexing signal and a second demultiplexing signal of the multiple demultiplexing signals Demultiplexing signal, and includes an input terminal, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal, wherein the input terminal of the path selection unit is used to receive the input signal Or one of the plurality of path selection units, the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal are respectively coupled to the plurality of path selections One of the units; and a plurality of mode decision circuits, wherein each mode decision circuit is used to receive the mode decision signal and a first reference voltage, the first reference voltage has the first voltage level, the mode decision circuit It includes an input terminal and a first output terminal, the input terminal of the mode decision circuit is coupled to one of the plurality of path selection units, and the first output terminal of the mode decision circuit is coupled to the plurality of switches One of the circuits; wherein when the mode decision signal has the third voltage level, the mode decision circuit turns on the input terminal of the mode decision circuit and the first output terminal of the mode decision circuit, when the mode When the decision signal has the fourth voltage level, the mode decision circuit outputs the first reference voltage to the first output terminal of the mode decision circuit. The display device of claim 15, wherein each path selection unit further includes: a first selection circuit for receiving the first demultiplexing signal, including an input terminal, a first output terminal and a second output terminal Where the input terminal of the first selection circuit is coupled to the input terminal of the path selection unit; a second selection circuit for receiving the second demultiplexing signal includes an input terminal and a first output And a second output terminal, wherein the input terminal of the second selection circuit is coupled to the first output terminal of the first selection circuit, and the first output terminal of the second selection circuit is coupled to the path selection The first output terminal of the unit, the second output terminal of the second selection circuit is coupled to the second output terminal of the path selection unit; and a third selection circuit for receiving the second demultiplexing signal , Including an input terminal, a first output terminal and a second output terminal, wherein the input terminal of the third selection circuit is coupled to the second output terminal of the first selection circuit, the third selection circuit of the The first output terminal is coupled to the third output terminal of the path selection unit, and the second output terminal of the third selection circuit is coupled to the fourth output terminal of the path selection unit. The display device according to claim 16, wherein the first selection circuit includes: a third transistor including a first terminal, a second terminal, and a control terminal, and the first terminal of the third transistor is coupled to The first output terminal of the first selection circuit, the second terminal of the third transistor is coupled to the input terminal of the first selection circuit, and the control terminal of the third transistor is used to receive the first A demultiplexing signal; a fourth transistor including a first terminal, a second terminal and a control terminal, the first terminal of the fourth transistor is coupled to the second output of the first selection circuit Terminal, the second terminal of the fourth transistor is coupled to the input terminal of the first selection circuit, the control terminal of the fourth transistor is used to receive the first demultiplexing signal; a fifth transistor Including a first end, a second end and a control end, the first end of the fifth transistor is used to receive a second reference voltage, and the second end of the fifth transistor is coupled to the first The first output terminal of a selection circuit, the control terminal of the fifth transistor for receiving the first demultiplexing signal; and a sixth transistor, including a first terminal, a second terminal and a control Terminal, the first terminal of the sixth transistor is used to receive a second reference voltage, the second terminal of the sixth transistor is coupled to the second output terminal of the first selection circuit, the sixth The control terminal of the crystal is used to receive the first demultiplexing signal. The display device according to claim 15, wherein each mode determination circuit includes: a seventh transistor including a first terminal, a second terminal and a control terminal, the first terminal of the seventh transistor is coupled to The input terminal of the mode decision circuit, the second terminal of the seventh transistor is coupled to the first output terminal of the mode decision circuit, and the control terminal of the seventh transistor is used to receive the mode decision signal; as well as An eighth transistor includes a first terminal, a second terminal and a control terminal, the first terminal of the eighth transistor is used to receive the first reference voltage, and the second terminal of the eighth transistor The first output terminal of the mode decision circuit is coupled to the control terminal of the eighth transistor for receiving the mode decision signal.

Images