TWI671873B - Semiconductor package structure - Google Patents

Abstract

An embodiment of the present invention provides a semiconductor package structure. The semiconductor package structure includes a semiconductor die and a redistribution structure. The redistribution structure is disposed on the front side of the semiconductor die. The redistribution structure includes a multilayer package insulation layer and a conductive wall. A multilayer package insulation layer is stacked on the front side of the semiconductor die. The conductive wall runs vertically through multiple layers of the multi-layer package insulation layer. The conductive wall is substantially erected on the front side of the semiconductor die, and is electrically connected to the semiconductor die.

Description

Semiconductor packaging structure

The present invention relates to a semiconductor package structure, and more particularly, to a wafer-level semiconductor package structure.

The wafer-level semiconductor package structure includes a fan-in structure and a fan-out structure. The redistribution structure in the fan-out structure can re-arrange the positions of the die pads to obtain a higher number of I / Os when the size is close to or larger than the die size. In general, a large-area conductor layer can be formed on at least one layer of the redistribution structure to serve as a ground / power plane. In this way, the signal quality and / or power supply quality of the product can be improved.

Because the thermal expansion coefficient of the conductor material is very different from the thermal expansion coefficient of the semiconductor material in the grain. Therefore, if a large-area conductive material is arranged in the redistribution structure, a problem of warpage may occur in the packaging structure. In order to solve the above-mentioned warpage problem, the ground / power plane in the redistribution structure may be formed into a mesh pattern to reduce the area of the conductor material of the ground / power plane. However, the meshed ground / power plane cannot provide a perfect current return path, which in turn causes electromagnetic radiation interference problems, resulting in a reduction in the signal quality of the product and / or the quality of the power supply.

The invention provides a semiconductor package structure, which can effectively improve the signal quality and avoid the problem of warping.

The invention provides a semiconductor package structure, which can effectively improve the signal quality and power supply quality, and can avoid the problem of warping.

The semiconductor package structure of the present invention includes a semiconductor die and a redistribution structure. The redistribution structure is disposed on the front side of the semiconductor die, and includes a multi-layered package insulation layer and a conductive wall. A multilayer package insulation layer is stacked on the front side of the semiconductor die. The conductive wall runs vertically through multiple layers of the multi-layer package insulation layer. The conductive wall is substantially erected on the front side of the semiconductor die, and is electrically connected to the semiconductor die.

In some embodiments of the present invention, the semiconductor package structure may further include at least one signal line. At least one signal line is located in one of the multilayer package insulation layers.

In some embodiments of the present invention, the semiconductor package structure may further include a pair of signal lines. A pair of differential pair signal lines are respectively located in the two layers of the multilayer package insulation layer, and the orthographic projections of the pair of differential pair signal lines on the semiconductor die have regions that can overlap each other.

In some embodiments of the present invention, the redistribution structure may further include an extension trace. The extension trace is disposed in one of the multilayer package insulation layers that is farthest from the semiconductor die, and extends in a direction parallel to the front side of the semiconductor die. The extension trace is electrically connected to the conductive wall.

In some embodiments of the present invention, the semiconductor package structure may further include a package body. The semiconductor die is located in the package, and a part of the package is located between the semiconductor die and the redistribution structure.

In some embodiments of the present invention, the semiconductor package structure may further include a package body and a filling structure. The semiconductor die and the filling structure are located in the package, and the filling structure is located between the semiconductor die and the redistribution structure.

The semiconductor package structure of the present invention includes a semiconductor die and a redistribution structure. The semiconductor die includes a first pad and a second pad. The first pad and the second pad are located on the front side of the semiconductor die. The redistribution structure is disposed on the front side of the semiconductor die, and includes a multilayer package insulation layer, a first conductive wall, and a second conductive wall. A multilayer package insulation layer is stacked on the front side of the semiconductor die. The first conductive wall and the second conductive wall penetrate through a plurality of multilayer insulation layers in the longitudinal direction. The first conductive wall and the second conductive wall are substantially erected on the front side of the semiconductor die, and are electrically connected to the first pad and the second pad of the semiconductor die, respectively.

In an embodiment of the present invention, the redistribution structure may further include a first extension trace and a second extension trace. The first extension trace and the second extension trace are disposed in one of the multilayer package insulation layers that is farthest from the semiconductor die, and extend in a direction parallel to the front side of the semiconductor die. The first extension trace and the second extension trace are electrically connected to the first conductive wall and the second conductive wall, respectively.

In one embodiment of the present invention, the semiconductor package structure may further include at least one signal line. At least one signal line is located in the redistribution structure and is located between the first conductive wall and the second conductive wall.

Based on the foregoing, compared to setting a horizontal ground plane / power plane in the redistribution structure, the embodiment of the present invention provides a vertical conductive wall in the redistribution structure as a vertical ground plane / power plane. The principal plane of the conductive wall is substantially perpendicular to the front side of the semiconductor die. In other words, the main plane of the conductive wall and the front side of the semiconductor die can be prevented from facing each other. In this way, the area of the conductive wall facing the semiconductor die can be reduced. Therefore, the problem of warping of the semiconductor package structure due to the difference in thermal expansion coefficient can be reduced. Furthermore, compared with the meshed ground plane / power plane, the conductive wall of the embodiment of the present invention can provide a perfect current return path, so it can effectively improve the signal quality of the semiconductor package structure and avoid the problem of electromagnetic interference. .

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a semiconductor package structure 10 according to some embodiments of the present invention. FIG. 2 is a schematic perspective view of the signal line 126 and the conductive wall 124 of FIG. 1.

Referring to FIG. 1, a semiconductor package structure 10 according to an embodiment of the present invention includes a semiconductor die 100. The semiconductor die 100 may include a substrate and active and passive components formed in the substrate and / or one side of the substrate. For simplicity, the substrate, active device and passive device of the semiconductor die 100 are not shown in FIG. 1. In some embodiments, the active element may include a diode, a bipolar transistor, a field effect transistor, and the like. Passive components can include resistors, capacitors, inductors, and so on. The substrate may be a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or the semiconductor-on-insulator substrate may include an element semiconductor or a compound semiconductor. For example, the material of the element semiconductor may include Si or Ge. The material of the compound semiconductor may include SiGe, SiC, SiGeC, a group III-V semiconductor material, or a group II-VI semiconductor material. Group III-V semiconductor materials can include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. II-VI semiconductor materials can include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. In addition, the substrate may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be an N-type, and the second conductivity type may be a P-type.

The semiconductor die 100 has a front side FS and a back side RS opposite to each other. The active element and the passive element may be relatively close to the front side FS. In some embodiments, the semiconductor die 100 may be thinned from the backside RS of the semiconductor die 100 to reduce the thickness of the semiconductor die 100. In some embodiments, the semiconductor die 100 may include a pad 102a and a pad 102b. For example, in some embodiments, the pad 102a may be connected to a ground voltage V _SS (or may be referred to as a reference voltage), and may be referred to as a ground pad. The pad 102b can be used to transmit analog signals, digital signals, RF signals, and can be referred to as signal pads. These signals are divided into single-end or differential pairs due to differences in electronic circuits formed by the active or passive components of the semiconductor die 100. The pads 102 a and 102 b are located on the front side FS of the semiconductor die 100. In some embodiments, the pads 102a and 102b may include a conductive layer 104 and a conductive post 106, respectively. The conductive pillar 106 completely or partially covers the conductive layer 104 and is electrically connected to the conductive layer 104. In some embodiments, the semiconductor die 100 may further include an insulating layer 105 covering the conductor layer 104. The insulating layer 105 has an opening to expose a part of the conductive layer 104 so that the conductive post 106 can be electrically connected to the conductive layer 104. In some embodiments, the material of the conductive pillar 106 and the conductive layer 104 may include a metal, a metal alloy, a metal compound, or a combination thereof, respectively. The material of the insulating layer 105 may include silicon oxide, silicon nitride, a polymer material, or a combination thereof.

In some embodiments, the number of pads 102a may be an odd number. In such embodiments, the pad 102b may be adjacent to one pad 102a. In other embodiments, the pads 102 a may be disposed in pairs on the front side FS of the semiconductor die. In such embodiments, the pads 102b may be located between a pair of pads 102a. In addition, the semiconductor die 100 may include one or more pads 102b. However, the number and position of the pads 102a and 102b can be adjusted according to circuit design requirements, and the present invention is not limited thereto.

In some embodiments, the semiconductor package structure 10 may further include a package body 110. The semiconductor die 100 is located in the package body 110. In some embodiments, the backside RS1 of the package body 110 may expose the backside RS of the semiconductor die 100. In some embodiments, the backside RS1 of the package body 110 may be coplanar with the backside RS of the semiconductor die 100. On the other hand, the front side FS1 of the package can expose the pads 102 a and 102 b of the semiconductor die 100. In some embodiments, the material of the package body 110 may include epoxy resin, polyimide, or other suitable resin materials.

The semiconductor package structure 10 further includes a redistribution structure 120. The redistribution structure 120 is disposed on the front side FS of the semiconductor die 100. In some embodiments, a portion of the package body 110 fills a space between the semiconductor die 100 and the redistribution structure 120. The redistribution structure 120 includes a plurality of package insulation layers 122. The multilayer package insulation layer 122 is stacked on the front side FS of the semiconductor die. In some embodiments, the multilayer package insulation layer 122 is sequentially formed on the front side FS1 of the package body 110. For example, the material of the package insulating layer 122 may include polyimide, polybenzoxazole, benzocyclobuten, silicones, acrylates, epoxy Resin (epoxy) or a combination thereof.

Please refer to FIGS. 1 and 2. The redistribution structure 120 further includes a conductive wall 124. The conductive wall 124 penetrates a plurality of the package insulating layers 122 along a normal direction (for example, a direction Z or a stacking direction of the multilayer package insulating layers 122) substantially perpendicular to the surface of the semiconductor die 100. Taking the structure shown in FIG. 1 as an example, the conductive wall 124 penetrates the two insulating layers 122 along the direction Z. In addition, the conductive wall 124 extends on the front side FS1 of the package body 110 in a direction other than the direction Z (for example, the direction Y or the direction X) to form a wall structure. In other words, the conductive wall 124 may extend along the direction Z and the direction Y (or the direction Z and the direction X), and is substantially erected on the front side of the semiconductor die 100. In some embodiments, considering the accuracy of the patterning process used to form the openings accommodating the conductive wall 124, the angle range between the sidewall SW1 of the conductive wall 124 and the normal direction (direction Z) of the surface of the semiconductor die 100 Can be 0 degrees to 45 degrees. In other embodiments, the above patterning process may have better accuracy, and the angle range between the sidewall SW1 of the conductive wall 124 and the normal direction (direction Z) of the surface of the semiconductor die 100 may be 0. Degrees to 20 degrees. The conductive wall 124 is electrically connected to the semiconductor die 100. In some embodiments, the conductive wall 124 is electrically connected to the semiconductor die 100 through the pad 102a, and can be connected to the ground voltage V _SS . In the embodiment shown in FIG. 1 and FIG. 2, the two conductive walls 124 are both connected to the ground voltage V _SS .

In some embodiments, the main plane MS of the conductive wall 124 stands on the front side FS of the semiconductor die 100, and the top surface TS and the bottom surface BS of the conductive wall 124 are parallel to the front side FS of the semiconductor die 100. In other words, the surface of the conductive wall 124 with a smaller area can face the semiconductor die 100, and avoiding that the main plane MS with the largest area of the conductive wall 124 faces the semiconductor die 100. Therefore, the problem of warping of the package structure caused by the difference in thermal expansion coefficient between the semiconductor die 100 and the conductive wall 124 can be reduced. In these embodiments, the width W1 of the conductive wall 124 is relatively smaller than the length (L _PKG ) or width (W _PKG ) of the semiconductor package structure 10. In some embodiments, the width W1 of the conductive wall 124 may range from 1 μm to 750 μm. In other embodiments, the width W1 of the conductive wall 124 may range from 10 μm to 450 μm. In other embodiments, the width W1 of the conductive wall 124 may range from 50 μm to 450 μm. On the other hand, the height H1 of the conductive wall 124 may range from 1 um to 150 um. In other embodiments, the height H1 of the conductive wall 124 may range from 5 um to 100 um. The length L1 of the conductive wall 124 depends on the length of the signal line 126, and its purpose is to provide a perfect current return path for the signal line.

Compared to a horizontal ground plane extending along the direction parallel to the front side FS of the semiconductor die 100 in the redistribution structure, the embodiment of the present invention provides the redistribution structure 120 to be substantially erected on the front side FS of the semiconductor die 100. The conductive wall 124 is used as a vertical ground plane. Specifically, the conductive wall 124 in the embodiment of the present invention has a large-area main plane MS and a top surface TS, a bottom surface BS, and a side surface SS having a relatively small area. The main plane MS having a large area is substantially perpendicular to the surface of the semiconductor die 100. In other words, the main plane MS with a large area does not face the semiconductor die 100, but the top surface TS with a relatively small area faces the semiconductor die 100. In this way, the area of the conductive wall 124 facing the semiconductor die 100 can be reduced. Therefore, the problem of warping of the semiconductor package structure 10 due to the difference in thermal expansion coefficient can be reduced. Moreover, compared with the mesh-shaped ground plane, the conductive wall 124 in the embodiment of the present invention has a complete ground plane. According to this, the conductive wall 124 of the embodiment of the present invention can provide a perfect current return path, so the signal quality of the semiconductor package structure can be effectively improved and the problem of electromagnetic interference can be avoided.

In some embodiments, the redistribution structure 120 may further include an extension trace 124a. The extension trace 124 a is disposed in the package insulation layer 122 farthest from the semiconductor die 100 and extends along a direction (eg, direction X and / or direction Y) parallel to the front side FS of the semiconductor die 100. In addition, the extension trace 124 a is electrically connected to the conductive wall 124. In some embodiments, the materials of the conductive wall 124 and the extension trace 124 a may include a metal, a metal alloy, a metal compound, or a combination thereof, respectively.

In some embodiments, the redistribution structure 120 may further include one or more signal lines 126. One or more signal lines 126 are disposed in the multilayer package insulation layer 122 and can be electrically connected to the pads 102 b of the semiconductor die 100. In some embodiments, the signal line 126 can be used to transmit analog signals, digital signals, or radio frequency signals. In some embodiments, one or more signal lines 126 may include a pair of signal lines 126. The pair of signal lines 126 can be a pair of differential pair signal lines, and can be disposed in both of the multilayer package insulation layer 122. In addition, an orthographic projection of a pair of differential pair signal lines 126 in different package insulating layers 122 on the semiconductor die 100 has regions that can overlap each other. Although the signal line 126 shown in FIG. 2 is a flat plate-shaped structure, the signal line 126 can be patterned to have various shapes, and the embodiment of the present invention is not limited to the shape of the signal line. In some embodiments, the distribution width W2 of each signal line 126 may range from 1 μm to 100 μm. In other embodiments, the distribution width W2 of each signal line 126 may range from 1 μm to 50 μm. The distance D between each signal line 126 and the nearest conductive wall 124 can range from 1 um to 100 um. In other embodiments, the distance D between each signal line 126 and the nearest conductive wall 124 may range from 1 μm to 50 μm. In some embodiments, the redistribution structure 120 may further include an interconnect structure 128. The interconnect structure 128 is disposed in the multilayer package insulation layer 122. The interconnect structure 128 may include conductive vias (not shown) extending in a direction substantially perpendicular to the front side FS of the semiconductor die 100 and traces extending in a direction parallel to the front side FS of the semiconductor die 100. The internal connection structure 128 is electrically connected to the pad 102 b and the signal line 126. In some embodiments, the material of the signal line 126 and the interconnect structure 128 may include a metal, a metal alloy, a metal compound, or a combination thereof, respectively.

In some embodiments, the semiconductor package structure 10 may further include a bump 130. The bump 130 is disposed on a side of the multilayer package insulation layer 122 opposite to the semiconductor die 100 and can extend into the package insulation layer 122 farthest from the semiconductor die 100. Some bumps 130 can be electrically connected to the conductive wall 124 by extending the traces 124a, and can be connected to the ground voltage V _SS . In this way, the conductive wall 124 can provide a ground voltage V _SS to the semiconductor die 100, and can also serve as a ground plane for the signal line 126. In other embodiments, the conductive wall 124 may provide an analog ground voltage (V _{SS_Analog} ), a digital ground voltage (V _{SS_Digital} ), or a radio frequency ground voltage (V _{SS_RF} ) to the semiconductor die 100. In addition, other bumps 130 may be electrically connected to the signal line 126 through the interconnect structure 128 and may be connected to an external signal. In some embodiments, the material of the bump 130 may include gold, copper, nickel, aluminum, tin-lead alloy, conductive polymer material, or a combination thereof. In some embodiments, the width W3 of the bump 130 may range from 100 μm to 500 μm. In some embodiments, the width W3 of the bump 130 may range from 50 μm to 500 μm.

Based on the above, the conductive wall 124 of the embodiment of the present invention stands on the front side FS of the semiconductor die 100. Compared to setting a horizontal ground plane in the redistribution structure 120, in the embodiment of the present invention, a conductive wall 124 is provided in the redistribution structure 120 as a vertical ground plane, and the main plane MS of the conductive wall 124 is substantially perpendicular to the semiconductor die 100 front side FS. In other words, the main plane MS of the conductive wall 124 can be prevented from facing the semiconductor die 100. In this way, the area of the ground plane (ie, the conductive wall 124) facing the semiconductor die 100 can be reduced. Therefore, the problem of warping of the semiconductor package structure 10 due to the difference in thermal expansion coefficient can be reduced. Furthermore, compared to the meshed ground plane, the conductive wall 124 of the embodiment of the present invention has a complete current return path, so the signal quality of the semiconductor package structure 10 can be effectively improved and the problem of electromagnetic interference can be avoided.

FIG. 3 is a schematic perspective view of the signal line 226 and the conductive wall 124 in another embodiment.

Please refer to FIG. 2 and FIG. 3. The pair of signal lines 226 shown in FIG. 3 is similar to the pair of signal lines 126 shown in FIG. 2, but the pair of signal lines 226 shown in FIG. (Omitting drawing). A pair of signal lines 226 are separated from each other. In some embodiments, the distance D1 between the two signal lines 226 may range from 1 μm to 100 μm. In other embodiments, the distance D1 between the two signal lines 226 may range from 1 μm to 50 μm. In addition, the distance D between each signal line 226 and the nearest conductive wall 124 can range from 1 μm to 100 μm. In other embodiments, the distance D between each signal line 126 and the nearest conductive wall 124 may range from 1 μm to 50 μm.

FIG. 4 is a schematic cross-sectional view of a semiconductor package structure 40 according to some embodiments of the present invention.

Please refer to FIGS. 1 and 4. The semiconductor package structure 40 shown in FIG. 4 is similar to the semiconductor package structure 10 shown in FIG. 1, but the redistribution structure 420 of the semiconductor package structure 40 further includes a conductive wall 424. In addition, the semiconductor die 400 includes a pad 402c in addition to the pad 102a and the pad 102b. The pad 402c may be connected to the operating voltage V _DD and may be referred to as a power pad. Similar to the pads 102a and 102b, the pad 402c may also include a conductor layer 104 and a conductor post 106 that are electrically connected to each other. Similar to the conductive wall 124, the conductive wall 424 vertically penetrates a plurality of the multilayer encapsulation and insulation layers 122 and extends along, for example, the X direction or the Y direction, and stands on the front side FS of the semiconductor die 400. The conductive wall 424 is electrically connected to the pad 402 c of the semiconductor die 400. In addition, the conductive wall 424 can be connected to the working voltage V _DD . In other words, in the embodiment shown in FIG. 4, the conductive wall 124 is connected to the ground voltage V _SS , and the conductive wall 424 is connected to the working voltage V _DD . In some embodiments, one or more signal lines 426 may be located between the conductive wall 124 and the conductive wall 424. In addition, one or more signal lines 426 may be electrically connected between the pad 102 b and the bump 130 through the interconnect structure 128. In some embodiments, one or more signal lines 426 may be located in the same package insulation layer 122. In other embodiments, the one or more signal lines 426 include a pair of differential pair signal lines 426. The pair of differential pair signal lines 426 are respectively located in the two packaging insulation layers 122, and the orthographic projections of the two on the semiconductor die 400 have regions that can overlap each other.

In some embodiments, the redistribution structure 420 may further include an extension trace 424a. The extension trace 424 a is disposed in the package insulation layer 122 farthest from the semiconductor die 400, and extends along a direction (eg, direction X or direction Y) parallel to the front side FS of the semiconductor die 400. In addition, the extension trace 424a is electrically connected to the conductive wall 424. Moreover, the bump 130 electrically connected to the conductive wall 424 through the extension wiring 424a is connected to the working voltage V _DD . In this way, the conductive wall 424 can provide the working voltage V _DD to the semiconductor die 400, and can also be used as a longitudinal power plane of the signal line 426. In some embodiments, the conductive wall 124 may provide an analog operating voltage (V _{DD_Analog} ), a digital operating voltage (V _{DD_Digital} ), or a radio frequency operating voltage (V _{DD_RF} ) to the semiconductor die 100.

In other embodiments, both the pad 102a and the pad 402c can be used as a power pad. In these embodiments, both the conductive wall 124 and the conductive wall 424 are connected to the working voltage V _DD , and both of them can be used as a vertical power supply surface. In some embodiments, the conductive wall 124 and the conductive wall 424 can provide an analog operating voltage (V _{DD_Analog} ), a digital operating voltage (V _{DD_Digital} ), or a radio frequency operating voltage (V _{DD_RF} ) to the semiconductor die 100.

FIG. 5 is a schematic cross-sectional view of a semiconductor package structure 50 according to some embodiments of the present invention.

Please refer to FIGS. 4 and 5. The semiconductor package structure 50 shown in FIG. 5 is similar to the semiconductor package structure 40 shown in FIG. 4. The difference between the two is that the redistribution structure 420 of FIG. 4 is formed on the front side FS of the semiconductor die 400, and the embodiment of FIG. 5 provides the redistribution structure 520 in advance, and then the semiconductor die 400 is flip-chip bonded (flip-bonded). chip bonding) is coupled to the redistribution structure 520. In some embodiments, the redistribution structure 520 further includes a plurality of conductive pads CP and an adhesive layer AD. The pads 102a, 102b, and 402c of the semiconductor die 400 may be respectively coupled to the redistribution structure 520 via a plurality of conductor pads CP and an adhesive layer AD. Specifically, the pad 102a, pad 102b, and pad 402c of the semiconductor die 400 may be electrically connected to the conductive wall 124 and the signal line 426 of the redistribution structure 520 via the plurality of conductor pads CP and the bonding layer AD, respectively. And conductive wall 424. In some embodiments, the width W4 of the conductive pad CP may range from 20 μm to 200 μm. In some embodiments, the material of the conductive pad CP may include gold, copper, nickel, aluminum, tin-lead alloy, a conductive polymer material, or a combination thereof. The material of the subsequent layer AD may include gold, copper, nickel, aluminum, tin-lead alloy, conductive polymer materials, or a combination thereof.

In some embodiments, the semiconductor package structure 50 may further include a filling structure UF. The semiconductor die 400 and the filling structure UF are located in the package body 110, and the filling structure UF fills a space between the semiconductor die 400 and the redistribution structure 520. In some embodiments, the material of the filling structure UF may include an epoxy resin, an aromatic amine compound, an inorganic filling material, an organic phosphorus compound, or a combination thereof.

To sum up, compared with setting a horizontal ground plane / power plane in the redistribution structure, the embodiment of the present invention provides a vertical conductive wall in the redistribution structure as a vertical ground plane / power plane. The principal plane of the conductive wall is substantially perpendicular to the front side of the semiconductor die. In other words, the main plane of the conductive wall and the front side of the semiconductor die can be prevented from facing each other. In this way, the area of the conductive wall facing the semiconductor die can be reduced. Therefore, the problem of warping of the semiconductor package structure due to the difference in thermal expansion coefficient can be reduced. Furthermore, compared with the meshed ground plane / power plane, the conductive wall of the embodiment of the present invention can provide a perfect current return path, so it can effectively improve the signal quality of the semiconductor package structure and avoid the problem of electromagnetic interference. .

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 40, 50‧‧‧ semiconductor package structure

100, 400‧‧‧ semiconductor die

102a, 102b, 420c ‧‧‧ pads

104‧‧‧conductor layer

105‧‧‧ Insulation

106‧‧‧conductor post

110‧‧‧ Package

120, 420, 520‧‧‧ heavy wiring structure

122‧‧‧Packaging insulation

124‧‧‧ conductive wall

124a‧‧‧Extended wiring

126, 226‧‧‧ signal line

128‧‧‧Internal connection structure

130‧‧‧ bump

424‧‧‧Conductive wall

424a‧‧‧Extended wiring

426‧‧‧Signal line

AD‧‧‧ Adjacent Layer

BS‧‧‧Underside

CP‧‧‧ pad

D, D1‧‧‧‧pitch

FS, FS1‧‧‧ front

H1‧‧‧ height

L1‧‧‧ length

MS‧‧‧ main plane

RS, RS1‧‧‧ dorsal side

SS‧‧‧ side

SW, SW1‧‧‧ sidewall

TS‧‧‧Top

UF‧‧‧filled structure

V _SS ‧‧‧ Ground voltage

V _DD ‧‧‧ Working voltage

W1, W3, W4‧‧‧Width

W2‧‧‧ distribution width

X, Y, Z‧‧‧ directions

FIG. 1 is a schematic cross-sectional view of a semiconductor package structure according to some embodiments of the present invention. FIG. 2 is a schematic perspective view of the signal line and the conductive wall of FIG. 1. FIG. 3 is a schematic perspective view of a signal line and a conductive wall in another embodiment. 4 and 5 are schematic cross-sectional views of a semiconductor package structure according to other embodiments of the present invention.

Claims (8)

A semiconductor package structure includes: a semiconductor die; and a redistribution structure provided on a front side of the semiconductor die, and including: a multilayer package insulating layer stacked on the front side of the semiconductor die; a conductive wall A plurality of layers of the multi-layer package insulation layer are vertically penetrated, wherein the conductive wall is substantially erected on the front side of the semiconductor die and is electrically connected to the semiconductor die; and an extension wiring is provided at One of the multilayer package insulation layers that is farthest from the semiconductor die and extends in a direction parallel to the front side of the semiconductor die, wherein the extension trace is electrically connected to the conductive wall. The semiconductor package structure according to item 1 of the patent application scope further includes at least one signal line located in one of the multilayer package insulation layers. According to the semiconductor package structure described in item 1 of the scope of patent application, it further includes a pair of differential pair signal lines, which are respectively located in the two layers of the multilayer package insulation layer, and the pair of differential pair signal lines are in the semiconductor crystal. The orthographic projections on the grains have regions that overlap each other. The semiconductor package structure according to item 1 of the patent application scope further includes a package, wherein the semiconductor die is located in the package, and a part of the package is located between the semiconductor die and the rewiring. Between structures. The semiconductor package structure according to item 1 of the patent application scope further includes a package body and a filling structure, wherein the semiconductor die and the filling structure are located in the package body, and the filling structure is located in the semiconductor crystal. Between the particles and the rewiring structure. A semiconductor package structure includes a semiconductor die including a first pad and a second pad, wherein the first pad and the second pad are located on a front side of the semiconductor die; and a rewiring structure, provided On the front side of the semiconductor die, and including: a multilayer package insulating layer stacked on the front side of the semiconductor die; a first conductive wall and a second conductive wall, which vertically penetrate the multilayer package insulation There are multiple layers, wherein the first conductive wall and the second conductive wall are substantially erected on the front side of the semiconductor die, and are respectively electrically connected to the first of the semiconductor die. A pad and the second pad; and a first extension trace and a second extension trace, which are disposed in one of the multilayer package insulation layers that is farthest from the semiconductor die, and are parallel to The front side of the semiconductor die extends in a direction, wherein the first extension trace and the second extension trace are electrically connected to the first conductive wall and the second conductive wall, respectively. The semiconductor package structure according to item 6 of the scope of patent application, further comprising at least one signal line, wherein the at least one signal line is located in the redistribution structure and located between the first conductive wall and the second conductive Between the walls, and wherein the at least one signal line is located in one of the redistribution structures. The semiconductor package structure according to item 6 of the scope of patent application, further comprising at least one signal line, wherein the at least one signal line is located in the redistribution structure and located between the first conductive wall and the second conductive line. Between the two walls, and wherein the at least one signal line includes a pair of differential pair signal lines, the pair of differential pair signal lines are respectively located in two of the multilayer package insulation layer, and the pair of signal lines The orthographic projections on the semiconductor die have regions overlapping each other.