TWI662416B - Efficient peer-to-peer communication support in soc fabrics - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L51/00—User-to-user messaging in packet-switching networks, transmitted according to store-and-forward or real-time protocols, e.g. e-mail
- H04L51/04—Real-time or near real-time messaging, e.g. instant messaging [IM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L51/00—User-to-user messaging in packet-switching networks, transmitted according to store-and-forward or real-time protocols, e.g. e-mail
- H04L51/21—Monitoring or handling of messages
- H04L51/23—Reliability checks, e.g. acknowledgments or fault reporting
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0038—System on Chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
Abstract
用於互連結構中有效率的點對點通訊支援之方法及設備。實施與代理器相關之網路介面而以確保資料存取相應於每一代理器之最新更新的方式促進代理器之間之點對點交易。此係部分經由當從該代理器起始之寫入交易之間之目的地改變時使用從該代理器發送之非後置式(non-posted)「虛擬寫入」而予實施。該虛擬寫入確保相應於先前寫入之資料在後續寫入及讀取交易之前抵達其目的地,因而排序該點對點交易而不需使用集中交易排序實體。 Method and equipment for efficient point-to-point communication support in interconnected structures. Implement an agent-related web interface to facilitate peer-to-peer transactions between agents in a way that ensures data access corresponds to the latest updates for each agent. This is implemented in part by using a non-posted "virtual write" sent from the agent when the destination between write transactions initiated from the agent changes. The virtual write ensures that the data corresponding to the previous write reaches its destination before subsequent write and read transactions, thus ordering the point-to-point transaction without using a centralized transaction ordering entity.
Description
本發明之範疇大體上關於電腦系統中之通訊,更具體但不排他地關於系統晶片(SoC)結構中用於增強點對點通訊之技術。 The scope of the present invention relates generally to communication in computer systems, and more specifically, but not exclusively, to techniques for enhancing point-to-point communication in a system-on-chip (SoC) structure.
電腦系統典型地採用一或多互連以促進系統組件間之通訊,諸如處理器及記憶體之間。互連及/或延伸介面亦可用以支援內建及附加裝置,諸如IO(輸入/輸出)裝置及延伸卡等。在個人電腦導入多年後,互連之主要形式為並列匯流排。並列匯流排結構係用於內部資料轉移及延伸匯流排,諸如產業標準架構(ISA)、微通道架構(MCA)、延伸產業標準架構(EISA)及VESA本機匯流排。在1990年代初期,Intel公司引入週邊組件互連(PCI)電腦匯流排。PCI不僅藉由增加匯流排速度,亦使用共用位址及資料線導入自動組態及以交易為基之資料轉移,而改進早期匯流排技術。 Computer systems typically employ one or more interconnections to facilitate communication between system components, such as processors and memory. The interconnection and / or extension interface can also be used to support built-in and additional devices, such as IO (input / output) devices and extension cards. After the introduction of personal computers for many years, the main form of interconnection was parallel buses. The parallel bus structure is used for internal data transfer and extended buses, such as industry standard architecture (ISA), micro-channel architecture (MCA), extended industry standard architecture (EISA), and VESA native bus. In the early 1990s, Intel introduced the Peripheral Component Interconnect (PCI) computer bus. PCI not only improves the early bus technology by increasing the speed of the bus, but also using a shared address and data line to implement automatic configuration and transaction-based data transfer.
隨著時間的推移,電腦處理器時鐘率以較並 列匯流排時鐘率更快步伐增加。結果,電腦工作量通常受限於互連瓶頸而非處理器速度。儘管並列匯流排支援每一週期大量資料轉移(例如,在PCI-X下32或甚至64位元),其時鐘率受限於時序偏差考量,導致最大匯流排速度之實際限制。為克服此問題,發展高速串列互連。早期串列互連之範例包括串列ATA、USB(通用串列匯流排)、火線(FireWire)路、及RapidIO。廣泛使用之另一標準串列互連為PCI Express(PCIe),其係於2004年在PCIe 1.0標準下導入。 Over time, computer processor clock rates The bus clock rate increases faster. As a result, computer workloads are often limited by interconnect bottlenecks rather than processor speed. Although the parallel bus supports a large amount of data transfer per cycle (for example, 32 or even 64-bit under PCI-X), its clock rate is limited by timing deviation considerations, resulting in a practical limitation of the maximum bus speed. To overcome this problem, high-speed serial interconnects have been developed. Examples of early serial interconnects include serial ATA, USB (Universal Serial Bus), FireWire, and RapidIO. Another widely used standard serial interconnect is PCI Express (PCIe), which was introduced under the PCIe 1.0 standard in 2004.
最近,通常稱為「系統晶片」(SoC)之架構在電腦產業中已成為普遍。並非於分立組件之間具有外部互連,SoC採用內部互連,其促進各式嵌入組件之間之通訊,諸如處理器核心及其他IP(智慧財產權)區塊。該些IP區塊典型地經由一或多互連架構連接,諸如互連網目(例如,橫桿型互連),亦稱為互連結構,或簡單地為「結構」,並與代理器相關,該代理器使用藉由互連實施之可應用通訊協定管理IP核心組件之間之通訊。 Recently, an architecture commonly referred to as a "system-on-chip" (SoC) has become common in the computer industry. Rather than having external interconnections between discrete components, SoCs use internal interconnections, which facilitate communication between various embedded components, such as processor cores and other IP (Intellectual Property) blocks. These IP blocks are typically connected via one or more interconnect architectures, such as interconnect meshes (e.g., crossbar-type interconnects), also known as interconnect structures, or simply "structures" and associated with agents, The agent manages communication between IP core components using an applicable protocol implemented through interconnection.
設計用於SoC之通訊結構可極具挑戰性。隨著SoC上IP區塊數量持續增加,互連結構上流量擁塞同樣地增加。然而,隨著更多IP區塊及相關代理器整合於SoC上,以匯流排為基或以分層樹為基之結構遭遇嚴重線路擁塞及時序收斂問題,侷限了該些互連架構的可擴縮性(scalability)。結果,因其可擴縮性、模組性及易於設計再使用,SoC之晶片上通訊結構現在從匯流排及分層樹 結構移至更複雜的互連結構,諸如網路晶片(NoC)、混合架構等。 Designing communication structures for SoCs can be extremely challenging. As the number of IP blocks on the SoC continues to increase, traffic congestion on the interconnect structure also increases. However, as more IP blocks and related agents are integrated on the SoC, bus-based or hierarchical tree-based structures suffer from severe line congestion and timing convergence issues, limiting the availability of these interconnect architectures Scalability. As a result, because of its scalability, modularity, and ease of design and reuse, the on-chip communication structure of SoCs now moves from buses and hierarchical trees. Structures move to more complex interconnect structures, such as network chips (NoC), hybrid architectures, and more.
200‧‧‧系統晶片平台 200‧‧‧ SoC Platform
202‧‧‧互連結構 202‧‧‧Interconnection Structure
204、612‧‧‧代理器 204, 612‧‧‧ agents
206‧‧‧網路介面 206‧‧‧Interface
300‧‧‧送出佇列 300‧‧‧ Submit queue
308‧‧‧送入佇列 308‧‧‧Sent to the queue
302、310‧‧‧仲裁器 302, 310‧‧‧ Arbiter
304、306、404、406‧‧‧區塊 Blocks 304, 306, 404, 406‧‧‧
312‧‧‧寫入目的地暫存器 312‧‧‧ write destination register
400、402‧‧‧決定區塊 400, 402‧‧‧ decision blocks
500‧‧‧網目網路晶片結構 500‧‧‧net network chip structure
502、606‧‧‧路由器 502, 606‧‧‧ router
600‧‧‧系統 600‧‧‧ system
602‧‧‧系統晶片 602‧‧‧ System Chip
604‧‧‧網路晶片 604‧‧‧Network chip
608‧‧‧互連鏈路 608‧‧‧interconnect link
610‧‧‧智慧財產權區塊 610‧‧‧Intellectual Property Block
614‧‧‧網路介面 614‧‧‧Interface
616、618‧‧‧記憶體控制器 616, 618‧‧‧Memory Controller
620、622‧‧‧記憶體區塊 620, 622‧‧‧Memory Block
624‧‧‧系統介面 624‧‧‧System Interface
藉由參照下列詳細說明,當結合附圖時,上述方面及本發明許多伴隨優點將變得更易於理解,其中,除非特別指名,各圖通篇中相似代號係指相似零件:圖1為示意方塊圖,描繪耦接至互連之三代理器之間發送的一連串信息;圖2為示意方塊圖,描繪連接至互連之複數代理器,其中,每一代理器與網路介面相關,其促使交易排序以確保資料存取不陳舊;圖3為網路介面之一實施例的示意方塊圖;圖4為流程圖,描繪依據一實施例之藉由網路介面實施的邏輯及作業;圖5a-5f為示意方塊圖,用於描繪使用虛擬寫入之演練範例,以確保一連串交易之適當交易排序;以及圖6為採用網路晶片之示範系統晶片的示意方塊圖。 By referring to the following detailed description, the above aspects and many of the accompanying advantages of the present invention will become easier to understand when combined with the drawings, where, unless specifically named, like numbers throughout the drawings refer to similar parts: Figure 1 is a schematic representation Block diagram depicting a series of messages sent between the three agents connected to the interconnect; Figure 2 is a schematic block diagram depicting a plurality of agents connected to the interconnect, where each agent is associated with a network interface and its Promote transaction sequencing to ensure that data access is not stale; Figure 3 is a schematic block diagram of an embodiment of a network interface; Figure 4 is a flowchart depicting logic and operations implemented through a network interface according to an embodiment; 5a-5f are schematic block diagrams, which are used to depict an exercise example using virtual writing to ensure proper transaction sequencing of a series of transactions; and FIG. 6 is a schematic block diagram of an exemplary system chip using a network chip.
文中說明SoC結構中有效率的點對點通訊支援之方法及設備的實施例。在下列說明中,提出許多特定細節,以提供本發明之實施例的徹底理解。然而,孰悉相關技藝之人士將認同無特定細節之一或多項,或使用其他 方法、組件、材料等仍可實現本發明。在其他狀況下,未顯示或詳細說明熟知結構、材料、或作業以避免混淆本發明之態樣。 This article describes the method and equipment for efficient point-to-point communication support in the SoC structure. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. However, those familiar with the relevant art will agree that there are no specific details or use one or more Methods, components, materials, etc. can still implement the invention. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the invention.
本說明書通篇提及「一實施例」或「實施例」表示結合實施例所說明之特徵、結構、或特性係包括於本發明之至少一實施例中。因而,本說明書通篇出現之「在一實施例中」或「在實施例中」用語不一定均指相同實施例。此外,特徵、結構、或特性可以任何適當方式組合於一或多個實施例中。 Reference throughout the specification to "one embodiment" or "an embodiment" means that a feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Therefore, the terms "in an embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, the features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
點對點通訊支援在SoC結構設計中為重要特徵。點對點通訊之重大挑戰為確保正確排序之需求。圖1顯示排序需求之範例。在此範例中,代理器A首先發出寫入至代理器B(步驟1)。代理器A接著發送旗標至代理器C,指出其已寫入資料(步驟2)。當代理器C接收旗標時,便發出讀取至代理器B(步驟3)。需求為代理器C需得到藉由代理器A寫入之最新資料。然而,若未正確設計,藉由代理器C發出之讀取可較藉由代理器A寫入之資料更早抵達代理器B。結果,代理器C可能讀取陳舊資料而非最新資料。 Point-to-point communication support is an important feature in the SoC structure design. A major challenge for peer-to-peer communication is the need to ensure proper sequencing. Figure 1 shows an example of a sorting requirement. In this example, Agent A first issues a write to Agent B (step 1). Agent A then sends a flag to agent C indicating that it has written data (step 2). When Agent C receives the flag, it sends a read to Agent B (step 3). The requirement is that Agent C needs to get the latest data written by Agent A. However, if not properly designed, reads issued by Agent C can reach Agent B earlier than data written by Agent A. As a result, the agent C may read stale data instead of the latest data.
在目前Intel® SoC平台中,藉由支援PCI-e排序之匯流排及分層樹結構支援點對點通訊排序(ordering)。然而,當互連結構從匯流排及分層樹移至更複雜結構架構時,點對點支援便成為重大挑戰,因為在該些先進結構架構中未確保排序。一解決方案為使用互連 結構中之集中排序點,以確保維持正確排序。然而,此途徑增加通訊時間,且集中排序點可成為瓶頸,因為在每一要求行進至其目的地之前必須為排序而首先發送至排序點。設計者亦可使用非後置式(non-posted)寫入取代後置式(posted)點對點通訊的寫入。然而,非後置式寫入途徑增加點對點交易之顯著通訊延遲,因為在發送下一要求之前,需確認每一發出之寫入,因而非後置式寫入無法滿足該等系統中之性能需求。 In current Intel® SoC platforms, point-to-point communication ordering is supported by a bus and hierarchical tree structure that supports PCI-e ordering. However, as interconnected structures move from buses and hierarchical trees to more complex architectures, peer-to-peer support becomes a major challenge because ordering is not ensured in these advanced architectures. One solution is to use interconnects Centralized sorting points in the structure to ensure proper ordering is maintained. However, this approach increases communication time, and centralized sorting points can become a bottleneck, because each request must be sent to the sorting point first for sorting before traveling to its destination. Designers can also use non-posted writes instead of writes for posted point-to-point communications. However, the non-post-write approach increases the significant communication latency of peer-to-peer transactions, as each write that is issued must be confirmed before the next request is sent, so non-post-write cannot meet the performance requirements in these systems.
鑒於上述及其他性能考量,目前呈現低開銷設計以支援直接點對點通訊而無互連結構中之集中排序點。圖2顯示具互連結構202作為通訊結構之SoC平台200的範例。在此架構中,每一代理器204經由網路介面(NI)206連接至互連結構。NI仲裁來自不同佇列支要求並分包勝利要求(如適用)及發送封包至互連結構202上。互連結構接著朝向其目的地(即另一代理器)按路線發送封,且目的地NI解分包信息及將信息轉移至目的地代理器。通常,互連結構202可為任何結構架構,諸如傳統匯流排、分層樹、或更複雜結構,諸如網路晶片(NoC)、混合架構等。再者,技術可用於要求結構中點對點排序支援之任何互連結構。 In view of the above and other performance considerations, a low-overhead design is currently presented to support direct point-to-point communication without a centralized sort point in the interconnect structure. FIG. 2 shows an example of an SoC platform 200 with an interconnect structure 202 as a communication structure. In this architecture, each agent 204 is connected to an interconnect structure via a network interface (NI) 206. NI arbitration comes from different queue support requirements and subcontracts victory requirements (if applicable) and sends packets to interconnect fabric 202. The interconnect structure then sends the packet along its route towards its destination (ie, another agent), and the destination NI decontracts the information and transfers the information to the destination agent. Generally, the interconnect structure 202 may be any structural architecture, such as a traditional bus, a hierarchical tree, or a more complex structure, such as a network chip (NoC), a hybrid architecture, or the like. Furthermore, the technology can be used for any interconnect structure that requires point-to-point ordering support in the structure.
圖3顯示依據一實施例之NI 206的進一步細節。在代理器起始之送出要求被緩衝於送出佇列300中,具仲裁排序之仲裁器302其中要求被發送。回應於仲裁器302從佇列300選擇要求,要求於區塊304中被分包並發 送至結構上。送入要求包含封包,其係從結構接收並預定用於代理器。該些封包首先於區塊306中被解分包,隨之相應要求資料於送入佇列308中緩衝。仲裁器310接著用以仲裁排序,其中佇列之要求被傳送至代理器。應注意的是圖3中所描繪之NI 206僅為支援點對點交易之NI的一範例,因為亦可實施其他NI組態。 FIG. 3 shows further details of the NI 206 according to an embodiment. At the start of the agent, the send request is buffered in the send queue 300, and the arbiter 302 with the arbitration order request is sent. In response to the arbiter 302 selecting request from queue 300, request to be subcontracted and concurrently in block 304 Send to the structure. The incoming request contains a packet that is received from the fabric and is intended for use by the agent. The packets are first unpacked in block 306, and the corresponding data is then requested to be buffered in queue 308. The arbiter 310 is then used to arbitrate the sequencing, where the queued requests are passed to the agent. It should be noted that the NI 206 depicted in Figure 3 is only an example of an NI that supports peer-to-peer transactions, as other NI configurations can also be implemented.
對點對點通訊而言,若自不同來源代理器發送之二信息預定至相同目的地代理器並要求排序,則首先發送之信息必須首先抵達目的地。然而,在結構內,因為來自不同來源代理器之點對點信息可採取不同路徑至相同目的地,極可能在若干點預定用於相同目的地代理器之信息對將以與其插入結構之時間的不同排序抵達目的地。結果,不能確保點對點排序。 For point-to-point communication, if two messages sent from different source agents are scheduled to the same destination agent and require ordering, the first message sent must reach the destination first. However, within the structure, because point-to-point information from agents of different origins can take different paths to the same destination, it is highly likely that the information pair that is intended for the same destination agent at several points will be ordered differently from the time it was inserted into the structure Arrive at the destination. As a result, point-to-point ordering cannot be guaranteed.
主要考量為後置式寫入交易排序。為確保適當點對點後置式寫入交易排序,實施一機構其確保始自相同來源代理器及前往不同目的地代理器的後置式寫入依序抵達其個別目的地。使用以上圖1所呈現之範例,代理器A首先寫入至代理器B(第一後置式寫入)。代理器A接著寫入至代理器C,指出其已寫入至代理器B(另一後置式寫入)。若在代理器C接收來自代理器A之信息時,來自代理器A之後置式寫入已抵達代理器B,代理器C則發送讀取至代理器B,其確保讀取最新資料。結果,可確保排序正確。 The main consideration is post-write transaction ordering. To ensure proper point-to-point post-write transaction ordering, an organization is implemented to ensure that post-writes from the same source agent and to different destination agents arrive sequentially at their individual destinations. Using the example presented in FIG. 1 above, the agent A writes to the agent B first (first write-behind). Agent A then writes to Agent C, indicating that it has written to Agent B (another post-write). If when the agent C receives the information from the agent A, the post-write from the agent A has reached the agent B, the agent C sends a read to the agent B, which ensures that the latest data is read. As a result, it is ensured that the ordering is correct.
為予達成,在一實施例中,如圖3中所示, 在每一NI 206中實施「寫入目的地暫存器」(WDR)312。WDR暫存器用以為其附加代理器發出之最新後置式寫入要求記錄目的地ID。對具N代理器之系統而言,WDR暫存器尺寸僅為logN位元。 To achieve this, in one embodiment, as shown in FIG. 3, A "Write Destination Register" (WDR) 312 is implemented in each NI 206. The WDR register is used to record the destination ID of the latest post-write request issued by its additional agent. For systems with N agents, the WDR register size is only logN bits.
對從代理器發出之每一後置式寫入交易而言,代理器之NI首先為寫入以及其WDR中所記錄之先前(即最近)後置式寫入目的地檢查目的地代理器。 For each post-write transaction issued from the agent, the NI of the agent first checks the destination agent for the write and the previous (ie, most recent) post-write destination recorded in its WDR.
(a)若先前後置式寫入及目前後置式寫入係至相同目的地代理器,NI則直接發送寫入要求至結構上。此邏輯係描繪於圖4之流程圖中,其中,對於決定區塊400及402及是(YES)及否(NO)之個別答案致使流程前進至區塊406,其中要求被發送至結構之上。結構接著按路線發送寫入要求至要求中所識別之目的地代理器。在此狀況下,WDR不需更新,因為目的地代理器與先前後置式寫入的相同。 (a) If the previous post-write and the current post-write are to the same destination agent, NI sends the write request directly to the structure. This logic is depicted in the flowchart of FIG. 4, where the individual answers to the decision blocks 400 and 402 and yes and no cause the process to proceed to block 406, where the request is sent over the structure . The fabric then routes the write request to the destination agent identified in the request. In this case, the WDR does not need to be updated because the destination agent is the same as the previous post-write.
(b)若NI檢測到先前後置式寫入及目前後置式寫入係至不同代理器,則對於決定區塊402之答案為否,且NI將首先發送「虛擬寫入」,諸如非後置式寫入或其他類型交易,如區塊404中所示,其將從目的地NI返回確認至藉由WDR記錄之先前目的地代理器。此「虛擬寫入」首先用以推動所有先前後置式寫入至其目的地。NI接著等候來自先前目的地代理器對於「虛擬寫入」之確認。在接收確認之後,便確保所有先前後置式寫入已推動至目的地。NI接著 發出後置式寫入至結構之上。NI亦更新其WDR以識別新目的地。隨著所有從代理器發送之寫入已依序抵達其目的地,便確保對於此目的地的任何後續讀取要求將存取最新資料更新。 (b) If NI detects that the previous post-write and the current post-write are to different agents, the answer to the decision block 402 is no, and NI will first send a "virtual write" such as a non-post-write A write or other type of transaction, as shown in block 404, will return confirmation from the destination NI to the previous destination agent recorded by the WDR. This "virtual write" is first used to drive all previous post-writes to their destination. NI then waits for confirmation of the "virtual write" from the previous destination agent. After receiving the confirmation, make sure that all previous post-writes have been pushed to their destination. NI goes on Issue a post-write to the structure. National Instruments has also updated its WDR to identify new destinations. As all writes sent from the agent have reached their destination in sequence, it is ensured that any subsequent read requests for this destination will have access to the latest data updates.
對讀取交易而言,NI總是經由結構直接發送要求至目的地(無虛擬交易要求)。如圖4中所描繪,流程從來自決定區塊400之否結果前進至區塊406中發送要求。 For read transactions, NI always sends requests directly to the destination via the structure (no virtual transaction requirements). As depicted in FIG. 4, the process proceeds from the result of the decision block 400 to a request sent in block 406.
圖5a-5f描繪點對點排序方案如何作業以確保要求之適當排序的演練範例。在所描繪之每一圖中,如圖5a中所示多代理器204互連通過網目NoC結構500。每一代理器204操作上耦接至包括WDR 312之NI 206。經由一組操作上耦接至個別NI 206之路由器502,而促進NoC結構中路由。在圖5a-5f中,每一WDR312顯示相應於來自其相應NI之最新寫入目的地的目的地ID。 Figures 5a-5f depict an example of a walkthrough of how a point-to-point sequencing scheme works to ensure the proper sequencing required. In each of the figures depicted, the multi-agent 204 is interconnected through a mesh NoC structure 500 as shown in FIG. 5a. Each agent 204 is operatively coupled to an NI 206 including a WDR 312. A set of routers 502 operatively coupled to individual NI 206 facilitates routing in the NoC structure. In Figures 5a-5f, each WDR312 displays a destination ID corresponding to the latest write destination from its corresponding NI.
在此範例中,代理器C希望從代理器B讀取資料。然而,此資料目前已藉由代理器A寫入至代理器B,所以需要有機構確保代理器C未從代理器B接收陳舊資料。此係經由使用以上討論之虛擬寫入技術予以完成,如下列細節中進一步說明。 In this example, Agent C wants to read data from Agent B. However, this data is currently written to agent B by agent A, so a mechanism is needed to ensure that agent C does not receive stale data from agent B. This is done using the virtual writing techniques discussed above, as further explained in the following details.
(i)對藉由代理器A發出之寫入而言,NI首先檢查WDR。在此範例中,在第一寫入發出時,WDR為「代理器D」,但寫入要求之目的地為「代理器B」,所以NI首先發送「虛擬寫入」至代理器D(如圖5b中作業1所示)。 (i) For writes issued by Agent A, NI first checks the WDR. In this example, when the first write is issued, the WDR is "Agent D", but the destination of the write request is "Agent B", so NI first sends a "virtual write" to Agent D (such as (Shown in Assignment 1 in Figure 5b).
(ii)當代理器D接收此「虛擬寫入」時,便發出「確認」至代理器A(圖5b中作業2)。 (ii) When Agent D receives this "virtual write", it sends an "Acknowledge" to Agent A (Job 2 in Figure 5b).
(iii)一旦接收確認,在代理器A之NI便將其WDR改變至「代理器B」,並發送寫入至代理器B(圖5c中作業3)。 (iii) Once the confirmation is received, the NI at Agent A changes its WDR to "Agent B" and sends a write to Agent B (Job 3 in Figure 5c).
(iv)對於下列至代理器B之寫入要求而言,因為目的地及WDR相同(代理器B),NI便直接發送下列寫入至代理器B。 (iv) For the following write request to Agent B, because the destination and WDR are the same (Agent B), NI sends the following write directly to Agent B.
(i)在代理器A之NI首先檢查WDR。WDR為「代理器B」,但寫入要求之目的地為「代理器C」,所以NI首先發送「虛擬寫入」至代理器B(以推動資料至代理器B,如藉由圖5d中作業1所示)。 (i) The NI of Agent A first checks the WDR. WDR is "Agent B", but the destination of the write request is "Agent C", so NI first sends a "virtual write" to Agent B (to push data to Agent B, as shown in Figure 5d Shown in Assignment 1).
(ii)當代理器B接收此「虛擬寫入」時,便發出「確認」至代理器A(圖5d中作業2)。 (ii) When Agent B receives this "virtual write", it sends an "Acknowledge" to Agent A (Job 2 in Figure 5d).
(iii)一旦接收確認,,在代理器A之NI便將其WDR改變至「代理器C」,並發送寫入旗標至代理器C(圖5e中作業3)。 (iii) Once the confirmation is received, the NI at Agent A changes its WDR to "Agent C" and sends a write flag to Agent C (Job 3 in Figure 5e).
對讀取要求而言,NI總是將其直接發送至目的地節點。在此狀況下,代理器C直接發送所有讀取要求至代理器B(如圖5f中所示)。由於代理器B中資料已為最新,藉由代理器C讀取之資料正確。 For read requests, NI always sends it directly to the destination node. In this case, Agent C sends all read requests directly to Agent B (as shown in Figure 5f). Since the data in Agent B is up to date, the data read by Agent C is correct.
上述描繪藉由各式代理器及相關組件實施之一連串作業的一範例,以確保每一資料要求導致最新資料返回至請求者之方式促進資料交易。儘管係以2D網目結構之上下文說明範例,將理解的是類似途徑可用以確保其他類型互連架構中適當排序作業,包括採用匯流排、層次、混合等互連結構。 The above depicts an example of a series of operations performed by various agents and related components to ensure that each data request causes the latest data to be returned to the requester to facilitate data transactions. Although the examples are illustrated in the context of a 2D mesh structure, it will be understood that similar approaches can be used to ensure proper sequencing in other types of interconnected architectures, including the use of bus, hierarchical, hybrid, and other interconnected structures.
在上述演練範例中,描繪SoC組態具有連接至一代理器之每一NI。文中所揭露之原理及論述亦可實施用於同步連接至多代理器之NI。在此狀況下,NI可具有一藉由所有相關代理器共用之WDR或一用於每一代理器之WDR。前者較簡單但在若干環境下可能產生不必要之虛擬寫入,而後者更有效率但使用稍多邏輯實施。二方法確保點對點通訊之正確排序並具有極低硬體開銷。 In the above walkthrough example, the SoC configuration is depicted with each NI connected to an agent. The principles and discussions disclosed in this article can also be implemented in NI for simultaneous connection to multiple agents. In this case, NI may have a WDR shared by all relevant agents or a WDR for each agent. The former is simpler but may generate unnecessary virtual writes in some environments, while the latter is more efficient but uses slightly more logic to implement. The second method ensures correct sequencing of point-to-point communication and has extremely low hardware overhead.
圖6中顯示在文中所說明之實施例方面,可實施包括具有示範組態之SoC 602的系統600。SoC 602包括包含2D網目互連結構之網路晶片(NoC)604,該 2D網目互連結構具有靠近每一橫桿交叉之路由器606並包含複數互連鏈路608。複數IP區塊610耦接至個別路由器606,形成IP區塊之2D陣列。儘管圖6中顯示16 IP區塊,其僅係描繪,因為IP區塊之數量可改變,從較少數量IP區塊到更多,諸如但不侷限於8、24、32、48、64等,以及任何其間數量。 Shown in FIG. 6 are aspects of the embodiments described herein that a system 600 including an SoC 602 with an exemplary configuration may be implemented. SoC 602 includes a network chip (NoC) 604 including a 2D mesh interconnect structure. The 2D mesh interconnect structure has a router 606 near each crossbar and includes a plurality of interconnect links 608. The plurality of IP blocks 610 are coupled to individual routers 606 to form a 2D array of IP blocks. Although 16 IP blocks are shown in FIG. 6, they are only depicted because the number of IP blocks can be changed from a smaller number of IP blocks to more, such as but not limited to 8, 24, 32, 48, 64, etc. , And any number in between.
每一IP區塊包括代理器612及網路介面614。IP區塊為共同用於SoC中之各式類型IP區塊的描繪,諸如處理器核心、硬體加速器(例如,視訊解碼器、圖形、成像等)、記憶體相關組件(例如,記憶體控制器)、及I/O介面(例如,PCIe、QPI等)。在所描繪之實施例中,描繪一對記憶體控制器616及618分別耦接至記憶體區塊620及622(描繪為DIMM(雙重直列記憶體模組))及耦接至NoC 604中之個別路由器。亦描繪系統介面624,其係SoC 602及未顯示之其他系統組件之間之一或多介面的描繪。如同熟悉本技藝之人士將認同的,實際SoC將包括未顯示之額外組件以避免混淆圖6中所描繪之NoC態樣。 Each IP block includes an agent 612 and a network interface 614. IP blocks are the descriptions of various types of IP blocks commonly used in SoCs, such as processor cores, hardware accelerators (e.g., video decoders, graphics, imaging, etc.), memory-related components (e.g., memory control Device), and I / O interfaces (for example, PCIe, QPI, etc.). In the depicted embodiment, a pair of memory controllers 616 and 618 are depicted coupled to memory blocks 620 and 622 (depicted as DIMMs (dual in-line memory modules)) and coupled to NoC 604, respectively. Individual router. A system interface 624 is also depicted, which is a depiction of one or more interfaces between the SoC 602 and other system components not shown. As those skilled in the art will agree, the actual SoC will include additional components not shown to avoid confusing the NoC aspect depicted in FIG. 6.
在進一步細節中,典型處理器核心IP區塊可能包括耦接至或包括一或多級快取記憶體(例如,L1/L2快取記憶體)之處理器核心。接著,快取記憶體可採用代理器以促進與系統中其他快取記憶體及記憶體代理器之連貫記憶體交易。代理器可用於其他用途,以及諸如非連貫記憶體交易或其他通訊用途。再者,儘管圖6中描繪代理 器為單一區塊,特定IP區塊可具有相關多代理器。 In further details, a typical processor core IP block may include a processor core coupled to or including one or more levels of cache memory (eg, L1 / L2 cache memory). Caches can then use agents to facilitate coherent memory transactions with other caches and memory agents in the system. Agents can be used for other purposes, as well as non-coherent memory transactions or other communication purposes. Again, although the agent is depicted in Figure 6 The server is a single block, and a specific IP block may have an associated multi-agent.
除了以上討論之用於促進交易排序及相關作業之邏輯外,每一網路介面將包括用於與應用互連結構界接之配置。例如,互連結構可包含串列多通道互連結構,諸如Intel之QUICKPATH INTERCONNECT®(QPI)或Intel之KEIZER TECHNOLOGY INTERCONNECT®(KTI)、開放核心協定互連、其他類型標準化或所有權互連,以及未來互連技術及協定。此外,NoC之組態可包括其他類型互連結構組態,諸如但不侷限於環面及3D網目互連(例如,可用於具有以3D陣列組配之IP區塊之未來三維SoC中的互連結構)。 In addition to the logic discussed above to facilitate transaction sequencing and related operations, each network interface will include configurations for interfacing with application interconnect structures. For example, the interconnect structure may include a tandem multi-channel interconnect structure such as Intel's QUICKPATH INTERCONNECT® (QPI) or Intel's KEIZER TECHNOLOGY INTERCONNECT® (KTI), open core protocol interconnects, other types of standardized or proprietary interconnects, and Future interconnection technologies and agreements. In addition, NoC configuration can include other types of interconnect structure configurations, such as, but not limited to, torus and 3D mesh interconnects (e.g., can be used for interworking in future 3D SoCs with IP blocks configured in 3D array Even structure).
所描繪之本發明之實施例的以上說明包括發明摘要中所說明者,不希望窮舉或侷限本發明為所揭露之精確形式。雖然為描繪目的,文中說明本發明之特定實施例及範例,如熟悉相關技藝之人士將認同的,在本發明之範圍內可實施各式等效修改。 The above description of the depicted embodiments of the present invention includes those described in the Abstract of the Invention and is not intended to be exhaustive or to limit the invention to the precise form disclosed. Although for the purpose of illustration, specific embodiments and examples of the present invention are described herein, various equivalent modifications may be implemented within the scope of the present invention, as those skilled in the relevant art will recognize.
鑒於以上詳細說明,本發明可實施該些修改。下列申請專利範圍中所用之用詞不應解譯為侷限本發明於說明書及圖式中所揭露之特定實施例。而是,本發明之範圍完全藉由下列申請專利範圍判定,其係依據申請專利範圍解釋所建立原則來解譯。 In view of the above detailed description, the present invention can implement these modifications. The terms used in the following patent application scope should not be interpreted as limiting the specific embodiments of the present invention disclosed in the description and drawings. Instead, the scope of the present invention is completely determined by the following patent application scope, which is interpreted according to the principles established by the interpretation of the patent application scope.
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Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104081722B (en) | 2012-01-13 | 2018-05-22 | 英特尔公司 | Efficient peer-to-peer communications in SoC constructions are supported |
JP6356624B2 (en) * | 2015-03-23 | 2018-07-11 | 東芝メモリ株式会社 | Memory device and information processing apparatus |
US20170116154A1 (en) * | 2015-10-23 | 2017-04-27 | The Intellisis Corporation | Register communication in a network-on-a-chip architecture |
US20170269959A1 (en) * | 2016-03-15 | 2017-09-21 | Intel Corporation | Method, apparatus and system to send transactions without tracking |
US10324865B2 (en) * | 2016-09-06 | 2019-06-18 | Apple Inc. | Maintaining ordering requirements while converting protocols in a communications fabric |
US11064019B2 (en) * | 2016-09-14 | 2021-07-13 | Advanced Micro Devices, Inc. | Dynamic configuration of inter-chip and on-chip networks in cloud computing system |
KR20200139673A (en) | 2018-03-30 | 2020-12-14 | 프로비노 테크놀로지스, 아이엔씨. | Protocol level control for system-on-chip (SoC) agent reset and power management |
EP3776231B1 (en) | 2018-03-30 | 2023-05-03 | Google LLC | Procedures for implementing source based routing within an interconnect fabric on a system on chip |
US10255218B1 (en) | 2018-06-25 | 2019-04-09 | Apple Inc. | Systems and methods for maintaining specific ordering in bus traffic |
US11580054B2 (en) * | 2018-08-24 | 2023-02-14 | Intel Corporation | Scalable network-on-chip for high-bandwidth memory |
CN112825101B (en) * | 2019-11-21 | 2024-03-08 | 广州希姆半导体科技有限公司 | Chip architecture, data processing method thereof, electronic equipment and storage medium |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6584513B1 (en) * | 2000-03-31 | 2003-06-24 | Emc Corporation | Direct memory access (DMA) transmitter |
US6950438B1 (en) * | 1999-09-17 | 2005-09-27 | Advanced Micro Devices, Inc. | System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system |
US20090274158A1 (en) * | 2008-05-05 | 2009-11-05 | Sentilla Corporation, Inc. | Efficient Broadcast of Data in a Communication Network |
US20090307408A1 (en) * | 2008-06-09 | 2009-12-10 | Rowan Nigel Naylor | Peer-to-Peer Embedded System Communication Method and Apparatus |
US20110296129A1 (en) * | 2010-06-01 | 2011-12-01 | Hitachi, Ltd. | Data transfer device and method of controlling the same |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6636928B1 (en) * | 2000-02-18 | 2003-10-21 | Hewlett-Packard Development Company, L.P. | Write posting with global ordering in multi-path systems |
US6801976B2 (en) | 2001-08-27 | 2004-10-05 | Intel Corporation | Mechanism for preserving producer-consumer ordering across an unordered interface |
US20050091432A1 (en) * | 2003-10-28 | 2005-04-28 | Palmchip Corporation | Flexible matrix fabric design framework for multiple requestors and targets in system-on-chip designs |
US20060050693A1 (en) * | 2004-09-03 | 2006-03-09 | James Bury | Building data packets for an advanced switching fabric |
US8108584B2 (en) | 2008-10-15 | 2012-01-31 | Intel Corporation | Use of completer knowledge of memory region ordering requirements to modify transaction attributes |
US8990633B2 (en) * | 2009-04-21 | 2015-03-24 | Freescale Semiconductor, Inc. | Tracing support for interconnect fabric |
CN102567277A (en) * | 2010-12-30 | 2012-07-11 | 世意法(北京)半导体研发有限责任公司 | Method for reducing power consumption through network-on-chip system |
US8522189B2 (en) * | 2011-03-09 | 2013-08-27 | Intel Corporation | Functional fabric based test access mechanism for SoCs |
US9100348B2 (en) * | 2011-10-03 | 2015-08-04 | Intel Corporation | Managing sideband routers in on-die system fabric |
CN103946824B (en) * | 2011-11-22 | 2016-08-24 | 英特尔公司 | A kind of access control method for nonvolatile random access memory, Apparatus and system |
WO2013081580A1 (en) * | 2011-11-29 | 2013-06-06 | Intel Corporation | Raw memory transaction support |
US8788737B2 (en) * | 2011-12-26 | 2014-07-22 | Qualcomm Technologies, Inc. | Transport of PCI-ordered traffic over independent networks |
CN104081722B (en) * | 2012-01-13 | 2018-05-22 | 英特尔公司 | Efficient peer-to-peer communications in SoC constructions are supported |
US8982734B2 (en) * | 2012-06-26 | 2015-03-17 | Intel Corporation | Methods, apparatus, and systems for routing information flows in networks using spanning trees and network switching element resources |
KR101831550B1 (en) * | 2012-10-22 | 2018-02-22 | 인텔 코포레이션 | Control messaging in multislot link layer flit |
JP6311164B2 (en) * | 2013-12-23 | 2018-04-18 | インテル・コーポレーション | Integration component interconnect |
US9747245B2 (en) * | 2014-12-17 | 2017-08-29 | Intel Corporation | Method, apparatus and system for integrating devices in a root complex |
US9946676B2 (en) * | 2015-03-26 | 2018-04-17 | Intel Corporation | Multichip package link |
US9940287B2 (en) * | 2015-03-27 | 2018-04-10 | Intel Corporation | Pooled memory address translation |
-
2012
- 2012-01-13 CN CN201280066986.1A patent/CN104081722B/en active Active
- 2012-01-13 US US13/810,033 patent/US9755997B2/en active Active
- 2012-01-13 WO PCT/US2012/021187 patent/WO2013105967A1/en active Application Filing
-
2013
- 2013-01-09 TW TW102100694A patent/TWI662416B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6950438B1 (en) * | 1999-09-17 | 2005-09-27 | Advanced Micro Devices, Inc. | System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system |
US6584513B1 (en) * | 2000-03-31 | 2003-06-24 | Emc Corporation | Direct memory access (DMA) transmitter |
US20090274158A1 (en) * | 2008-05-05 | 2009-11-05 | Sentilla Corporation, Inc. | Efficient Broadcast of Data in a Communication Network |
US20090307408A1 (en) * | 2008-06-09 | 2009-12-10 | Rowan Nigel Naylor | Peer-to-Peer Embedded System Communication Method and Apparatus |
US20110296129A1 (en) * | 2010-06-01 | 2011-12-01 | Hitachi, Ltd. | Data transfer device and method of controlling the same |
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WO2013105967A1 (en) | 2013-07-18 |
TW201344447A (en) | 2013-11-01 |
CN104081722A (en) | 2014-10-01 |
CN104081722B (en) | 2018-05-22 |
US20130185370A1 (en) | 2013-07-18 |
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