TWI650945B - Noise cancellation device - Google Patents

Noise cancellation device Download PDF

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TWI650945B
TWI650945B TW106133411A TW106133411A TWI650945B TW I650945 B TWI650945 B TW I650945B TW 106133411 A TW106133411 A TW 106133411A TW 106133411 A TW106133411 A TW 106133411A TW I650945 B TWI650945 B TW I650945B
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module
signal
accumulation operation
accumulation
sampling
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TW106133411A
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TW201916590A (en
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張利達
高晨明
高興波
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北京集創北方科技股份有限公司
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Abstract

一種雜訊消除裝置,包含一取樣模組、一第一相位訊號產生模組、一連接取樣模組及第一相位訊號產生模組的第一乘法運算模組、一連接第一乘法運算模組的第一累加運算模組及一連接第一累加運算模組的第二累加運算模組。取樣模組針對一輸入訊號進行取樣並產生一取樣訊號,第一相位訊號產生模組產生一第一相位訊號,第一乘法運算模組對取樣訊號及第一相位訊號進行乘法運算並產生一第一合成訊號,第一累加運算模組對第一合成訊號進行累加運算並產生一第一累加訊號,第二累加運算模組對第一累加訊號進行累加運算並產生一第一輸出訊號。 A noise canceling device includes a sampling module, a first phase signal generation module, a first multiplication module connected to the sampling module and the first phase signal generation module, and a first multiplication operation module. A first accumulation operation module and a second accumulation operation module connected to the first accumulation operation module. The sampling module samples an input signal and generates a sampling signal. The first phase signal generating module generates a first phase signal. The first multiplication operation module multiplies the sampling signal and the first phase signal and generates a first signal. A composite signal, the first accumulation operation module performs accumulation operation on the first synthesis signal and generates a first accumulation signal, and the second accumulation operation module performs accumulation operation on the first accumulation signal and generates a first output signal.

Description

雜訊消除裝置 Noise Reduction Device

本發明是有關於一種雜訊消除裝置,特別是指一種消除觸控雜訊的雜訊消除裝置。 The present invention relates to a noise cancellation device, in particular to a noise cancellation device for eliminating touch noise.

參閱圖1,在現有的互電容觸控雜訊檢測及消除裝置中,觸控訊號RX經過類比前端電路81的濾波與放大,類比數位轉換器82的取樣,以及解調電路83的解調得到待檢測的觸控資料VO。由於觸控產生的激勵訊號從每個發送端傳輸到每個接收端都會產生不同的相位延遲,導致影響解調的準確度。因此,通常會加入正/餘弦波產生器84來進行正交解調以消除相位影響。 Referring to FIG. 1, in a conventional mutual capacitance touch noise detection and elimination device, the touch signal RX is obtained by filtering and amplifying the analog front-end circuit 81, sampling by the analog digital converter 82, and demodulating by the demodulation circuit 83. Touch data to be detected VO. As the excitation signal generated by the touch is transmitted from each transmitting end to each receiving end, a different phase delay will occur, which will affect the accuracy of demodulation. Therefore, a sine / cosine wave generator 84 is usually added to perform quadrature demodulation to eliminate phase effects.

一般來說,正/餘弦波產生器84為數位電路,初始相位若設定為0,則為正弦波產生器;若相位為90度,則為餘弦波產生器;初始相位為任意值就是一個任意初始相位正弦產生器。若類比數位轉換器82對觸控訊號RX接收到的正弦波進行採樣,得到的正弦波序列為x(n),解調序列為sin(ωn)及cos(ωn),則解調運算表示如下: ((Σx(n)sin(ωn))2+(Σx(n)cos(ωn))2)1/2 Generally speaking, the sine / cosine wave generator 84 is a digital circuit. If the initial phase is set to 0, it is a sine wave generator. If the phase is 90 degrees, it is a cosine wave generator. The initial phase is an arbitrary value. Initial phase sine generator. If the analog-to-digital converter 82 samples the sine wave received by the touch signal RX, the obtained sine wave sequence is x (n), and the demodulation sequence is sin (ωn) and cos (ωn), then the demodulation operation is expressed as follows : ((Σ x ( n ) sin (ω n )) 2 + (Σ x ( n ) cos (ω n )) 2 ) 1/2

然而,上述解調過程雖然可以消除與訊號頻率不相同的連續存在的雜訊干擾,但是對於在取樣序列中疊加了由外部干擾引起的不連續的間斷性時域突變,就會對解調運算的結果帶來極大的影響,例如,若雜訊疊加到類比數位轉換器82所取樣的正弦訊號上,就會導致解調結果出現偏差,進一步造成觸控檢測的偏差甚至失效。 However, although the above-mentioned demodulation process can eliminate continuous noise interference that is not the same as the signal frequency, the demodulation operation will be performed for discontinuous discontinuous time domain mutations caused by external interference in the sampling sequence. The result of this method has a great impact. For example, if noise is superimposed on the sine signal sampled by the analog-to-digital converter 82, it will cause deviations in the demodulation results, further causing deviations in touch detection and even failure.

因此,本發明之目的,即在提供一種可有效解決不連續時域突變雜訊對解調的影響的雜訊消除裝置。 Therefore, an object of the present invention is to provide a noise cancellation device that can effectively solve the influence of discontinuous time-domain abrupt noise on demodulation.

於是,本發明雜訊消除裝置,包含一取樣模組、一第一相位訊號產生模組、一連接取樣模組及第一相位訊號產生模組的第一乘法運算模組、一連接第一乘法運算模組的第一累加運算模組及一連接第一累加運算模組的第二累加運算模組,其中,取樣模組針對一輸入訊號進行取樣並產生一取樣訊號,第一相位訊號產生模組產生一第一相位訊號,第一乘法運算模組對取樣訊號及第一相位訊號進行乘法運算並產生一第一合成訊號,第一累加運算模組對第一合成訊號進行累加運算並產生一第一累加訊號,第二累加運算模組對第一累加訊號進行累加運算並產生一第一輸出訊號。 Therefore, the noise cancellation device of the present invention includes a sampling module, a first phase signal generating module, a first multiplication operation module connected to the sampling module and the first phase signal generating module, and a first multiplication A first accumulation operation module of the operation module and a second accumulation operation module connected to the first accumulation operation module, wherein the sampling module samples an input signal and generates a sampling signal, and the first phase signal generation module The group generates a first phase signal. The first multiplication operation module multiplies the sampling signal and the first phase signal and generates a first composite signal. The first accumulation operation module performs an accumulation operation on the first composite signal and generates a The first accumulation signal and the second accumulation operation module accumulate the first accumulation signal and generate a first output signal.

在一實施例中,雜訊消除裝置還包含一第二相位訊號產生模組、一連接取樣模組及第二相位訊號產生模組的第二乘法運算模組、一連接第二乘法運算模組的第三累加運算模組及一連接第三累加運算模組的第四累加運算模組,其中,第二相位訊號產生模組產生一第二相位訊號,第二乘法運算模組對取樣訊號及第二相位訊號進行乘法運算並產生一第二合成訊號,第三累加運算模組對第二合成訊號進行累加運算並產生一第二累加訊號,第四累加運算模組對第二累加訊號進行累加運算並產生一第二輸出訊號。 In an embodiment, the noise cancellation device further includes a second phase signal generating module, a second multiplication operation module connected to the sampling module and the second phase signal generation module, and a second multiplication operation module. A third accumulation operation module and a fourth accumulation operation module connected to the third accumulation operation module, wherein the second phase signal generation module generates a second phase signal, and the second multiplication operation module performs sampling on the sampling signal and The second phase signal is multiplied to generate a second synthesized signal. The third accumulation operation module is used to accumulate the second synthesized signal and generate a second accumulation signal. The fourth accumulation operation module is used to accumulate the second accumulated signal. Calculate and generate a second output signal.

進一步地,第一相位訊號為正弦波訊號,第二相位訊號為餘弦波訊號。 Further, the first phase signal is a sine wave signal, and the second phase signal is a cosine wave signal.

在一實施例中,雜訊消除裝置還包含一連接第一累加運算模組的第一計數模組、一連接第二累加運算模組的第二計數模組、一連接第三累加運算模組的第三計數模組及一連接第四累加運算模組的第四計數模組,其中,第一計數模組用以計數第一累加運算模組的累加次數,第二計數模組用以計數第二累加運算模組的累加次數,第三計數模組用以計數第三累加運算模組的累加次數,第四計數模組用以計數第四累加運算模組的累加次數。 In one embodiment, the noise cancellation device further includes a first counting module connected to the first accumulation operation module, a second counting module connected to the second accumulation operation module, and a third accumulation operation module. A third counting module and a fourth counting module connected to the fourth accumulation operation module, wherein the first counting module is used to count the accumulation times of the first accumulation operation module, and the second counting module is used to count The accumulation number of the second accumulation operation module, the third counting module is used to count the accumulation times of the third accumulation operation module, and the fourth counting module is used to count the accumulation times of the fourth accumulation operation module.

在一實施例中,取樣模組的取樣頻率為第一相位訊號之頻率與第二相位訊號之頻率的整數倍。 In one embodiment, the sampling frequency of the sampling module is an integer multiple of the frequency of the first phase signal and the frequency of the second phase signal.

在一實施例中,第一累加運算模組的累加次數為N1, 第二累加運算模組的累加次數為N2,且N1×N2為取樣模組的取樣點數。進一步地,N1為第一相位訊號的半週期的整數倍,且N1×N2包含整數個第一相位訊號之週期。 In one embodiment, the accumulation number of the first accumulation operation module is N1, The accumulation number of the second accumulation operation module is N2, and N1 × N2 is the number of sampling points of the sampling module. Further, N1 is an integer multiple of a half period of the first phase signal, and N1 × N2 includes an integer number of periods of the first phase signal.

在一實施例中,第三累加運算模組的累加次數為N3,第四累加運算模組的累加次數為N4,且N3×N4為取樣模組的取樣點數。進一步地,N3為第二相位訊號的半週期的整數倍,且N3×N4包含整數個第二相位訊號之週期。 In one embodiment, the accumulation number of the third accumulation operation module is N3, the accumulation number of the fourth accumulation operation module is N4, and N3 × N4 is the number of sampling points of the sampling module. Further, N3 is an integer multiple of a half period of the second phase signal, and N3 × N4 includes an integer number of periods of the second phase signal.

在一實施例中,雜訊消除裝置還包含一第一檢測單元,該第一檢測單元包括一連接第一累加運算模組的第一檢測模組及一連接第一檢測模組的第五計數模組,第一檢測模組用以檢測第一累加運算模組每累加N1個取樣點時的訊號雜訊,第五計數模組計數通過第一檢測模組檢測的次數。 In one embodiment, the noise cancellation device further includes a first detection unit, the first detection unit includes a first detection module connected to the first accumulation operation module and a fifth count connected to the first detection module. Module, the first detection module is used to detect the signal noise when the first accumulation operation module accumulates N1 sampling points, and the fifth counting module counts the number of times passed by the first detection module.

在一實施例中,雜訊消除裝置還包含一第二檢測單元,該第二檢測單元包括一連接第三累加運算模組的第二檢測模組及一連接第二檢測模組的第六計數模組,第二檢測模組用以檢測第三累加運算模組每累加N3個取樣點時的訊號雜訊,第六計數模組計數通過第二檢測模組檢測的次數。 In an embodiment, the noise cancellation device further includes a second detection unit, the second detection unit includes a second detection module connected to the third accumulation operation module and a sixth count connected to the second detection module. Module, the second detection module is used to detect the signal noise when the third accumulation operation module accumulates N3 sampling points, and the sixth counting module counts the number of times passed by the second detection module.

本發明之功效在於:可以有效消除雜訊且解決不連續時域突變雜訊對解調的影響。 The effect of the present invention is that it can effectively eliminate noise and solve the effect of discontinuous time domain abrupt noise on demodulation.

100‧‧‧雜訊消除裝置 100‧‧‧Noise Cancellation Device

10‧‧‧類比前端模組 10‧‧‧ analog front-end module

20‧‧‧取樣模組 20‧‧‧Sampling module

31‧‧‧第一乘法運算模組 31‧‧‧The first multiplication module

32‧‧‧第二乘法運算模組 32‧‧‧Second Multiplication Module

41‧‧‧第一相位訊號產生模組 41‧‧‧First Phase Signal Generation Module

42‧‧‧第二相位訊號產生模組 42‧‧‧Second Phase Signal Generation Module

51‧‧‧第一累加運算模組 51‧‧‧The first accumulation operation module

52‧‧‧第二累加運算模組 52‧‧‧Second accumulation module

53‧‧‧第三累加運算模組 53‧‧‧Third accumulation module

54‧‧‧第二累加運算模組 54‧‧‧Second accumulation module

61‧‧‧第一計數模組 61‧‧‧First counting module

62‧‧‧第二計數模組 62‧‧‧Second counting module

63‧‧‧第三計數模組 63‧‧‧Third counting module

64‧‧‧第四計數模組 64‧‧‧Fourth counting module

71‧‧‧第一檢測單元 71‧‧‧first detection unit

711‧‧‧第一檢測模組 711‧‧‧The first detection module

712‧‧‧第五計數模組 712‧‧‧Fifth counting module

72‧‧‧第二檢測單元 72‧‧‧Second detection unit

721‧‧‧第二檢測模組 721‧‧‧Second detection module

722‧‧‧第六計數模組 722‧‧‧Sixth counting module

RX‧‧‧觸控訊號 RX‧‧‧touch signal

VA1‧‧‧第一累加訊號 VA1‧‧‧The first cumulative signal

VA2‧‧‧第二累加訊號 VA2‧‧‧Second cumulative signal

VD1‧‧‧第一合成訊號 VD1‧‧‧First composite signal

VD2‧‧‧第二合成訊號 VD2‧‧‧Second composite signal

VI‧‧‧輸入訊號 VI‧‧‧Input signal

VO1‧‧‧第一輸出訊號 VO1‧‧‧First output signal

VO2‧‧‧第二輸出訊號 VO2‧‧‧Second output signal

VP1‧‧‧第一相位訊號 VP1‧‧‧First Phase Signal

VP2‧‧‧第二相位訊號 VP2‧‧‧Second Phase Signal

VS‧‧‧取樣訊號 VS‧‧‧Sampling signal

S11~S15‧‧‧步驟 S11 ~ S15‧‧‧step

S21~S27‧‧‧步驟 S21 ~ S27‧‧‧ steps

本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中:圖1是習知雜訊消除電路的電路方塊圖;圖2是本發明雜訊消除裝置的第一實施例的電路方塊示意圖;圖3是本發明雜訊消除裝置在取樣訊號的相位偏移穩定且可準確測量的實施態樣下的電路方塊示意圖;圖4是第一實施例之第一合成訊號的累加運作流程圖;圖5是第一實施例之取樣訊號的波形圖;圖6是第一實施例之第一合成訊號的波形圖;圖7是第一實施例之第一累加訊號的波形圖;圖8是第一實施例之第一輸出訊號的波形圖;圖9是本發明雜訊消除裝置的第二實施例的電路方塊示意圖;及圖10是第二實施例之第一合成訊號的累加運作流程圖。 Other features and effects of the present invention will be clearly presented in the embodiment with reference to the drawings, wherein: FIG. 1 is a circuit block diagram of a conventional noise canceling circuit; FIG. 2 is a first example of the noise canceling device of the present invention. A schematic circuit block diagram of the embodiment; FIG. 3 is a schematic circuit block diagram of the noise cancellation device of the present invention in a phase in which the phase shift of the sampling signal is stable and can be accurately measured; FIG. 4 is a first composite signal of the first embodiment 5 is a waveform diagram of the sampling signal of the first embodiment; FIG. 6 is a waveform diagram of the first composite signal of the first embodiment; and FIG. 7 is a waveform of the first accumulation signal of the first embodiment FIG. 8 is a waveform diagram of a first output signal of the first embodiment; FIG. 9 is a schematic circuit block diagram of a second embodiment of a noise canceling device of the present invention; and FIG. 10 is a first composite signal of the second embodiment Cumulative operation flowchart.

在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。 Before the present invention is described in detail, it should be noted that in the following description, similar elements are represented by the same numbers.

參閱圖2,為本發明雜訊消除裝置100之第一實施例,本雜訊消除裝置100應用於觸控顯示裝置中,用以檢測與消除觸控 時所產生的雜訊(noise)。在本實施例中,雜訊消除裝置100包含一類比前端模組10、一連接類比前端模組10的取樣模組20、一連接取樣模組20的第一乘法運算模組31、一連接取樣模組20的第二乘法運算模組32、一連接第一乘法運算模組31的第一相位訊號產生模組41、一連接第二乘法運算模組32的第二相位訊號產生模組42、一連接第一乘法運算模組31的第一累加運算模組51、一連接第一累加運算模組51的第二累加運算模組52、一連接第二乘法運算模組32的第三累加運算模組53、一連接第三累加運算模組53的第二累加運算模組54、一連接第一累加運算模組51的第一計數模組61、一連接第二累加運算模組52的第二計數模組62、一連接第三累加運算模組53的第三計數模組63及一連接第四累加運算模組54的第四計數模組64。 Referring to FIG. 2, a first embodiment of a noise cancellation device 100 according to the present invention. The noise cancellation device 100 is applied to a touch display device to detect and eliminate touch. Noise generated from time to time. In this embodiment, the noise cancellation device 100 includes an analog front-end module 10, a sampling module 20 connected to the analog front-end module 10, a first multiplication module 31 connected to the sampling module 20, and a connection sampling A second multiplication module 32 of the module 20, a first phase signal generation module 41 connected to the first multiplication module 31, a second phase signal generation module 42 connected to the second multiplication module 32, A first accumulation operation module 51 connected to the first multiplication operation module 31, a second accumulation operation module 52 connected to the first accumulation operation module 51, and a third accumulation operation connected to the second multiplication operation module 32 Module 53, a second accumulation operation module 54 connected to the third accumulation operation module 53, a first count module 61 connected to the first accumulation operation module 51, and a first accumulation operation module 52 connected to the second accumulation operation module 52 Two counting modules 62, a third counting module 63 connected to the third accumulation operation module 53 and a fourth counting module 64 connected to the fourth accumulation operation module 54.

類比前端模組10為一類比前端(Analog Front-End,AFE)電路,其接收觸控顯示裝置中感應電極(圖未示)所產生的觸控訊號RX,並針對觸控訊號RX進行濾波及訊號放大,以產生一輸入訊號VI。取樣模組20為一類比數位轉換器(ADC),用以針對輸入訊號VI進行取樣,並產生一取樣訊號VS。 The analog front-end module 10 is an analog front-end (AFE) circuit, which receives a touch signal RX generated by a sensing electrode (not shown) in a touch display device, and performs filtering and filtering on the touch signal RX. The signal is amplified to generate an input signal VI. The sampling module 20 is an analog-to-digital converter (ADC) for sampling the input signal VI and generating a sampling signal VS.

第一相位訊號產生模組41為一正弦波/餘弦波訊號產生器,用以產生一第一相位訊號VP1。第一乘法運算模組31對取樣訊號VS及第一相位訊號VP1進行乘法運算,並產生一第一合成訊 號VD1。第二相位訊號產生模組42為一正弦波/餘弦波訊號產生器,用以產生一第二相位訊號VP2。第二乘法運算模組32對取樣訊號VS及第二相位訊號VP2進行乘法運算,並產生一第二合成訊號VD2。 The first phase signal generating module 41 is a sine wave / cosine wave signal generator, and is used for generating a first phase signal VP1. The first multiplication module 31 multiplies the sampling signal VS and the first phase signal VP1 and generates a first composite signal. No. VD1. The second phase signal generating module 42 is a sine wave / cosine wave signal generator for generating a second phase signal VP2. The second multiplication operation module 32 multiplies the sampling signal VS and the second phase signal VP2 and generates a second composite signal VD2.

在本實施例中,第一相位訊號產生模組41為正弦波訊號產生器,即第一相位訊號VP1為正弦波訊號;第二相位訊號產生模組42為餘弦波訊號產生器,即第二相位訊號VP2為餘弦波訊號,且第一相位訊號VP1與第二相位訊號VP2的相位相差90度。 In this embodiment, the first phase signal generating module 41 is a sine wave signal generator, that is, the first phase signal VP1 is a sine wave signal; the second phase signal generating module 42 is a cosine wave signal generator, that is, the second The phase signal VP2 is a cosine wave signal, and the phase of the first phase signal VP1 and the second phase signal VP2 are 90 degrees out of phase.

特別說明的是,第一相位訊號產生模組41與第二相位訊號產生模組42所產生的相位訊號可互換,也就是第一相位訊號產生模組41為餘弦波訊號產生器,第二相位訊號產生模組42為正弦波訊號產生器,並不以本實施例為限。 In particular, the phase signals generated by the first phase signal generating module 41 and the second phase signal generating module 42 are interchangeable, that is, the first phase signal generating module 41 is a cosine wave signal generator, and the second phase The signal generating module 42 is a sine wave signal generator, and is not limited to this embodiment.

此外,取樣模組20的取樣頻率為第一相位訊號VP1之頻率與第二相位訊號VP2之頻率的整數倍,使得每個週期的第一相位訊號VP1與第二相位訊號VP2分別包含整數個取樣點,舉例來說,若取樣模組20的取樣頻率為2MHz,第一相位訊號VP1(正弦波訊號)與第二相位訊號VP2(餘弦波訊號)的頻率為100KHz,則每個週期的第一相位訊號VP1與第二相位訊號VP2分別包含20個取樣點。 In addition, the sampling frequency of the sampling module 20 is an integer multiple of the frequency of the first phase signal VP1 and the frequency of the second phase signal VP2, so that the first phase signal VP1 and the second phase signal VP2 each include an integer number of samples in each cycle. For example, if the sampling frequency of the sampling module 20 is 2MHz, and the frequency of the first phase signal VP1 (sine wave signal) and the second phase signal VP2 (cosine wave signal) is 100KHz, then the first of each cycle The phase signal VP1 and the second phase signal VP2 each include 20 sampling points.

第一累加運算模組51及第二累加運算模組52分別為一 累加器,第一累加運算模組51對第一合成訊號VD1進行累加運算,並產生一第一累加訊號VA1,第二累加運算模組52則再對該第一累加訊號VA1進行累加運算,並產生一第一輸出訊號VO1。第一計數模組61及第二計數模組62分別為一計數器,用以分別計數第一累加運算模組51及第二累加運算模組52所累加的次數。需說明的是,第一累加運算模組51預設的累加次數為N1,第二累加運算模組52預設的累加次數則為N2,N1×N2為取樣模組20的取樣點數,也就是總累加次數。 The first accumulation operation module 51 and the second accumulation operation module 52 are respectively Accumulator, the first accumulation operation module 51 performs accumulation operation on the first composite signal VD1 and generates a first accumulation signal VA1, and the second accumulation operation module 52 performs accumulation operation on the first accumulation signal VA1, and A first output signal VO1 is generated. The first counting module 61 and the second counting module 62 are counters, respectively, for counting the times accumulated by the first accumulation operation module 51 and the second accumulation operation module 52, respectively. It should be noted that the number of accumulations preset by the first accumulation operation module 51 is N1, the number of accumulations preset by the second accumulation operation module 52 is N2, and N1 × N2 is the number of sampling points of the sampling module 20. Is the total number of accumulations.

此外,N1的設置原則為第一相位訊號VP1的半週期的整數倍,以上述舉例來說,第一相位訊號VP1在單一週期中係包含20個取樣點,則N1可設置為10、20、30、40等。N2的設置原則為N1×N2必須包含整數個第一相位訊號VP1之週期,以上述舉例來說,N1×N2必須是20的整數倍,N2越大,則消除雜訊的效果越好,但相對消耗的時間較長,故N1及N2之設置會配合不同需求與效能而定。 In addition, the setting principle of N1 is an integer multiple of the half period of the first phase signal VP1. Taking the above example, for example, the first phase signal VP1 includes 20 sampling points in a single cycle, then N1 can be set to 10, 20, 30, 40 and so on. The setting principle of N2 is that N1 × N2 must include an integer number of periods of the first phase signal VP1. Taking the above example, N1 × N2 must be an integer multiple of 20, and the larger N2, the better the noise removal effect, but The relative time consumption is longer, so the settings of N1 and N2 will depend on different needs and performance.

第三累加運算模組53及第四累加運算模組54分別為一累加器,第三累加運算模組53對第二合成訊號VD2進行累加運算,並產生一第二累加訊號VA2,第四累加運算模組54則再對該第二累加訊號VA2進行累加運算,並產生一第二輸出訊號VO2。第三計數模組63及第四計數模組64分別為一計數器,用以分別計數第三累 加運算模組53及第四累加運算模組54所累加的次數。類似於第一累加運算模組51及第二累加運算模組52,第三累加運算模組53預設的累加次數為N3,第四累加運算模組54預設的累加次數則為N4,N3×N4為取樣模組20的取樣點數(總累加次數),且N3及N4的設置原則分別與N1及N2相同,故不多加贅述。 The third accumulation operation module 53 and the fourth accumulation operation module 54 are respectively an accumulator. The third accumulation operation module 53 performs accumulation operation on the second composite signal VD2, and generates a second accumulation signal VA2, and the fourth accumulation operation. The operation module 54 then performs an accumulation operation on the second accumulation signal VA2 and generates a second output signal VO2. The third counting module 63 and the fourth counting module 64 are respectively a counter for counting the third tiredness. The number of times accumulated by the addition module 53 and the fourth accumulation module 54. Similar to the first accumulation operation module 51 and the second accumulation operation module 52, the preset accumulation number of the third accumulation operation module 53 is N3, and the preset accumulation number of the fourth accumulation operation module 54 is N4, N3. × N4 is the number of sampling points (total accumulation times) of the sampling module 20, and the setting principles of N3 and N4 are the same as N1 and N2, respectively, so it will not be repeated.

另外,取樣模組20所輸出的取樣訊號VS分別與第一相位訊號VP1(正弦波訊號)及第二相位訊號VP2(餘弦波訊號)進行乘法與累加運算,是為了對取樣訊號VS進行正交解調,以消除取樣訊號VS的相位不確定性導致的解調偏差。若在取樣訊號VS的相位偏移穩定且可準確測量的實施態樣下,可以只用單一正弦波訊號或餘弦波訊號進行解調,雜訊消除裝置100的內部電路可如圖3所示,此時正弦波訊號的初始相位需與取樣訊號VS的相位偏移調整成一致。 In addition, the sampling signal VS output by the sampling module 20 is multiplied and accumulated with the first phase signal VP1 (sine wave signal) and the second phase signal VP2 (cosine wave signal) to orthogonalize the sampling signal VS. Demodulation to eliminate demodulation deviation caused by the phase uncertainty of the sampled signal VS. If the phase shift of the sampling signal VS is stable and can be accurately measured, demodulation can be performed using only a single sine wave signal or a cosine wave signal. The internal circuit of the noise cancellation device 100 can be shown in FIG. 3, At this time, the initial phase of the sine wave signal needs to be adjusted to match the phase offset of the sampling signal VS.

再者,第一計數模組61、第二計數模組62、第三計數模組63及第四計數模組64可分別為單一獨立的計數器,或是整合成同一計數器或計算裝置中,亦或是分別內建於第一累加運算模組51、第二累加運算模組52、第三累加運算模組53及第四累加運算模組54中,並不以本實施例為限。 In addition, the first counting module 61, the second counting module 62, the third counting module 63, and the fourth counting module 64 may be single independent counters, or integrated into the same counter or computing device. Or they are respectively built in the first accumulation operation module 51, the second accumulation operation module 52, the third accumulation operation module 53 and the fourth accumulation operation module 54, which are not limited to this embodiment.

參閱圖2及圖4,圖4為第一合成訊號VD1的累加運作流程。由於本實施例之第二合成訊號VD2的累加運作流程與第一合成 訊號VD1的累加運作流程相同,故僅以第一合成訊號VD1說明。 Referring to FIG. 2 and FIG. 4, FIG. 4 is an accumulation operation flow of the first composite signal VD1. Due to the accumulation operation flow of the second composite signal VD2 in this embodiment and the first composite signal The accumulation operation process of the signal VD1 is the same, so only the first composite signal VD1 is used for explanation.

當類比前端模組10接收觸控訊號RX並針對其進行濾波及訊號放大後,取樣模組20會針對類比前端模組10的輸出進行取樣,以產生取樣訊號VS,其波形如圖5所示。接著,第一乘法運算模組31會對取樣訊號VS及第一相位訊號VP1進行乘法運算,以產生第一合成訊號VD1,其波形則如圖6所示,之後進入累加運算流程。 After the analog front-end module 10 receives the touch signal RX and filters and amplifies the signal, the sampling module 20 samples the output of the analog front-end module 10 to generate a sampling signal VS, and its waveform is shown in FIG. 5 . Next, the first multiplication module 31 multiplies the sampling signal VS and the first phase signal VP1 to generate a first composite signal VD1. The waveform of the first composite signal VD1 is shown in FIG.

步驟S11,將第一累加運算模組51及第二累加運算模組52的累加次數及結果歸零,且將第一計數模組61及第二計數模組62的計數次數歸零。 In step S11, the accumulation times and results of the first accumulation operation module 51 and the second accumulation operation module 52 are reset to zero, and the count times of the first count module 61 and the second count module 62 are reset to zero.

步驟S12,第一累加運算模組51接收取樣模組20的取樣點,且第一計數模組61的計數次數加一。 In step S12, the first accumulation operation module 51 receives the sampling points of the sampling module 20, and the number of counts of the first counting module 61 is increased by one.

步驟S13,判斷第一計數模組61所計數的次數是否為N1(第一累加運算模組51預設的累加次數),若是,則進入步驟S14;若否,則返回執行步驟S12。 In step S13, it is determined whether the number of times counted by the first counting module 61 is N1 (the number of accumulations preset by the first accumulation operation module 51). If yes, the process proceeds to step S14;

步驟S14,第一累加運算模組51將累加運算後產生的第一累加訊號VA1傳送至第二累加運算模組52,且第二計數模組62的計數次數加一,並將第一累加運算模組51的累加次數與結果及第一計數模組61的計數次數歸零。 In step S14, the first accumulation operation module 51 transmits the first accumulation signal VA1 generated after the accumulation operation to the second accumulation operation module 52, and the count number of the second counting module 62 is increased by one, and the first accumulation operation is performed. The accumulation times and results of the module 51 and the count times of the first counting module 61 are reset to zero.

步驟S15,判斷第二計數模組62所計數的次數是否為 N2(第二累加運算模組52預設的累加次數),若是,則累加結束並輸出第一輸出訊號VO1;若否,則返回執行步驟S12。 Step S15, determining whether the number of times counted by the second counting module 62 is N2 (the number of accumulations preset by the second accumulation operation module 52). If yes, the accumulation ends and the first output signal VO1 is output; if not, the process returns to step S12.

舉例來說,若取樣模組20的取樣點數為60,並定義序列為a1、a2、a3…a60,且N1為10,N2為6,則第一累加運算模組51每次會累加10個取樣點(即a1~a10、a11~a20以此類推),再分段進入第二累加運算模組52中進行累加。 For example, if the number of sampling points of the sampling module 20 is 60, and the sequence is defined as a1, a2, a3 ... a60, and N1 is 10, N2 is 6, the first accumulation operation module 51 will accumulate 10 each time Sampling points (ie, a1 ~ a10, a11 ~ a20, and so on), and then segmented into the second accumulation operation module 52 for accumulation.

因此,透過第一累加運算模組51及第二累加運算模組52的雙重累加,並以平均值作為解調輸出,如此可有效消除觸控時所產生的雜訊,而第一累加運算模組51的輸出(第一累加訊號VA1)波形及第二累加運算模組52的輸出(第一輸出訊號VO1)波形分別如圖7及圖8所示。由圖7及圖8中清楚可知,經過兩次累加運算後,第一輸出訊號VO1為一其斜率與取樣模組20相位相關的理想直線。 Therefore, through the double accumulation of the first accumulation operation module 51 and the second accumulation operation module 52, and using the average value as the demodulation output, the noise generated during touch can be effectively eliminated, and the first accumulation operation mode The waveform of the output (first accumulation signal VA1) of the group 51 and the waveform of the output (first output signal VO1) of the second accumulation operation module 52 are shown in Figs. 7 and 8, respectively. As is clear from FIG. 7 and FIG. 8, after two accumulation operations, the first output signal VO1 is an ideal straight line whose slope is related to the phase of the sampling module 20.

參閱圖9,為本發明雜訊消除裝置100之第二實施例,其大致與第一實施例相同,不同的是,雜訊消除裝置100還包含一連接第一累加運算模組51的第一檢測單元71及一連接第三累加運算模組53的第二檢測單元72。 Referring to FIG. 9, a second embodiment of a noise cancellation device 100 according to the present invention is substantially the same as the first embodiment. The difference is that the noise cancellation device 100 further includes a first connection module 51 connected to the first accumulation operation module 51. The detection unit 71 and a second detection unit 72 connected to the third accumulation operation module 53.

第一檢測單元71包括一連接第一累加運算模組51的第一檢測模組711及一連接第一檢測模組711的第五計數模組712,第一檢測模組711用以檢測第一累加運算模組51每累加N1個取樣點 時的訊號雜訊,第五計數模組712則計數通過第一檢測模組711檢測的次數。 The first detection unit 71 includes a first detection module 711 connected to the first accumulation operation module 51 and a fifth counting module 712 connected to the first detection module 711. The first detection module 711 is used to detect the first Accumulation module 51 accumulates N1 sampling points The fifth signal module 712 counts the number of times detected by the first detection module 711.

第二檢測單元72包括一連接第三累加運算模組53的第二檢測模組721及一連接第二檢測模組721的第六計數模組722,第二檢測模組721用以檢測第三累加運算模組53每累加N3個取樣點時的訊號雜訊,第六計數模組722則計數通過第二檢測模組721檢測的次數。特別說明的是,雜訊消除裝置100中其他模組的運算及功能皆與第一實施例相同,故不多加敘述。 The second detection unit 72 includes a second detection module 721 connected to the third accumulation operation module 53 and a sixth counting module 722 connected to the second detection module 721. The second detection module 721 is used to detect the third The accumulation operation module 53 accumulates signal noise every N3 sampling points, and the sixth counting module 722 counts the number of times detected by the second detection module 721. It is specifically noted that the operations and functions of the other modules in the noise cancellation device 100 are the same as those of the first embodiment, and therefore will not be described further.

配合參閱圖10,圖10為第二實施例之第一合成訊號VD1的累加運作流程。同樣地,由於本實施例之第二合成訊號VD2的累加運作流程與第一合成訊號VD1的累加運作流程相同,故僅以第一合成訊號VD1說明。 With reference to FIG. 10, FIG. 10 is an accumulation operation flow of the first composite signal VD1 of the second embodiment. Similarly, since the accumulation operation flow of the second composite signal VD2 in this embodiment is the same as the accumulation operation flow of the first composite signal VD1, only the first composite signal VD1 will be described.

當類比前端模組10接收觸控訊號RX並針對其進行濾波及訊號放大後,取樣模組20會針對類比前端模組10的輸出進行取樣,以產生取樣訊號VS,接著,第一乘法運算模組31會對取樣訊號VS及第一相位訊號VP1進行乘法運算,以產生第一合成訊號VD1,之後進入累加運算流程。 After the analog front-end module 10 receives the touch signal RX and filters and amplifies the signal, the sampling module 20 samples the output of the analog front-end module 10 to generate a sampling signal VS. Then, the first multiplication mode The group 31 performs a multiplication operation on the sampling signal VS and the first phase signal VP1 to generate a first composite signal VD1, and then enters the accumulation operation flow.

步驟S21,將第一累加運算模組51及第二累加運算模組52的累加次數及結果歸零,且將第一計數模組61、第二計數模組62及第五計數模組712的計數次數歸零。 In step S21, the accumulation times and results of the first accumulation operation module 51 and the second accumulation operation module 52 are reset to zero, and the values of the first counting module 61, the second counting module 62, and the fifth counting module 712 are reset to zero. The count is reset to zero.

步驟S22,接收取樣模組20的取樣點,且第一計數模組61的計數次數加一。 In step S22, the sampling points of the sampling module 20 are received, and the number of counts of the first counting module 61 is increased by one.

步驟S23,判斷第一計數模組61所計數的次數是否為N1(第一累加運算模組51預設的累加次數),若是,則進入步驟S24;若否,則返回執行步驟S22。 In step S23, it is determined whether the number of times counted by the first counting module 61 is N1 (the number of accumulations preset by the first accumulation operation module 51). If yes, the process proceeds to step S24; if not, the process returns to step S22.

步驟S24,第一檢測模組711檢測第一累加運算模組51中該N1個取樣點時的訊號雜訊是否過大(例如:超過一預定範圍),若是,則進入步驟S26;若否,則進入步驟S25。 In step S24, the first detection module 711 detects whether the signal noise at the N1 sampling points in the first accumulation operation module 51 is too large (for example, exceeds a predetermined range). If yes, go to step S26; if not, then Go to step S25.

步驟S25,第一累加運算模組51將累加運算後產生的第一累加訊號VA1傳送至第二累加運算模組52,且第五計數模組712的計數次數加一。 In step S25, the first accumulation operation module 51 transmits the first accumulation signal VA1 generated after the accumulation operation to the second accumulation operation module 52, and the number of counts of the fifth counting module 712 is incremented by one.

步驟S26,將第一累加運算模組51的累加次數與結果及第一計數模組61的計數次數歸零,且第二計數模組62的計數次數加一。 In step S26, the accumulation times and results of the first accumulation operation module 51 and the count times of the first counting module 61 are reset to zero, and the count times of the second counting module 62 are incremented by one.

步驟S27,判斷第二計數模組62所計數的次數是否為N2(第二累加運算模組52預設的累加次數),若是,則累加結束並輸出第一輸出訊號VO1;若否,則返回執行步驟S22。 In step S27, it is determined whether the number of times counted by the second counting module 62 is N2 (the number of accumulations preset by the second accumulation operation module 52). If yes, the accumulation ends and the first output signal VO1 is output; if not, it returns Go to step S22.

以上述相同舉例來說,若取樣模組20的取樣點數為60,並定義序列為a1、a2、a3…a60,且N1為10,N2為6,則第一累加運算模組51每次會累加10個取樣點(即a1~a10、a11~a20 以此類推),再分次進入第二累加運算模組52中進行累加。其中,若第一檢測模組711檢測出例如a1~a10的雜訊過大,則會將a1~a10的累加結果丟棄,也就是不會進入步驟S25而將第一累加運算模組51的累加結果傳送至第二累加運算模組52,所以第五計數模組712的計數結果會小於或等於第二計數模組62的計數結果(即N2),如此可將雜訊過大的局部數據排除在第二累加運算模組52之外,以完成去除時域上的突變雜訊。 Taking the same example as above, if the number of sampling points of the sampling module 20 is 60, and the sequence is defined as a1, a2, a3 ... a60, and N1 is 10, N2 is 6, the first accumulation operation module 51 Will accumulate 10 sampling points (i.e. a1 ~ a10, a11 ~ a20 And so on), and then stepwise enter the second accumulation operation module 52 for accumulation. Among them, if the first detection module 711 detects that the noise such as a1 to a10 is too large, the accumulated results of a1 to a10 are discarded, that is, the accumulated results of the first accumulation operation module 51 are not entered in step S25. Sent to the second accumulation operation module 52, so the counting result of the fifth counting module 712 will be less than or equal to the counting result of the second counting module 62 (ie, N2), so that the local data with excessive noise can be excluded from the first The two accumulation operation modules 52 are used to remove abrupt noise in the time domain.

補充說明的是,在特殊的情況中,若第五計數模組712的計數結果為0,則表示本次觸控訊號RX的雜訊干擾極強,無法獲得有效的觸控資料,此時雜訊消除裝置100可以向系統的微處理器(MCU,圖未示)發送一個中斷或者狀態標誌,說明此時干擾很強,由微處理器作進一步處理。 It is added that, in a special case, if the counting result of the fifth counting module 712 is 0, it means that the noise interference of the touch signal RX is extremely strong, and effective touch data cannot be obtained. The signal cancellation device 100 may send an interrupt or status flag to the microprocessor (MCU, not shown) of the system, indicating that the interference is very strong at this time, and the microprocessor will further process it.

綜上所述,本發明雜訊消除裝置100藉由正弦波/餘弦波訊號的解調,以及雙重累加運算,可以有效消除雜訊且解決不連續時域突變雜訊對解調的影響,故確實能達成本發明之目的。 In summary, the noise cancellation device 100 of the present invention can effectively eliminate noise and solve the impact of discontinuous time-domain sudden noise on demodulation by demodulating sine / cosine wave signals and double accumulation operation. It can really achieve the purpose of the invention.

惟以上所述者,僅為本發明之實施例而已,當不能以此限定本發明實施之範圍,凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。 However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited in this way, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the content of the patent specification of the present invention are still Within the scope of the invention patent.

Claims (11)

一種雜訊消除裝置,包含:一取樣模組,針對一輸入訊號進行取樣,並產生一取樣訊號;一第一相位訊號產生模組,產生一第一相位訊號;一第一乘法運算模組,直接連接該取樣模組及該第一相位訊號產生模組,該第一乘法運算模組對該取樣訊號及該第一相位訊號進行乘法運算,並產生一第一合成訊號;一第一累加運算模組,直接連接該第一乘法運算模組,該第一累加運算模組對該第一合成訊號進行累加運算,並產生一第一累加訊號;及一第二累加運算模組,直接連接該第一累加運算模組,該第二累加運算模組對該第一累加訊號進行累加運算,並產生一第一輸出訊號。A noise canceling device includes: a sampling module for sampling an input signal and generating a sampling signal; a first phase signal generating module for generating a first phase signal; a first multiplication module, Directly connected to the sampling module and the first phase signal generating module, the first multiplication operation module multiplies the sampling signal and the first phase signal, and generates a first composite signal; a first accumulation operation A module that is directly connected to the first multiplication module, the first accumulation operation module that accumulates the first composite signal and generates a first accumulation signal; and a second accumulation operation module that is directly connected to the A first accumulation operation module, which performs an accumulation operation on the first accumulation signal and generates a first output signal. 如請求項1所述的雜訊消除裝置,還包含一第二相位訊號產生模組,產生一第二相位訊號;一第二乘法運算模組,連接該取樣模組及該第二相位訊號產生模組,該第二乘法運算模組對該取樣訊號及該第二相位訊號進行乘法運算,並產生一第二合成訊號;一第三累加運算模組,連接該第二乘法運算模組,該第三累加運算模組對該第二合成訊號進行累加運算,並產生一第二累加訊號;及一第四累加運算模組,連接該第三累加運算模組,該第四累加運算模組對該第二累加訊號進行累加運算,並產生一第二輸出訊號。The noise cancellation device according to claim 1, further comprising a second phase signal generation module to generate a second phase signal; a second multiplication module connected to the sampling module and the second phase signal generation Module, the second multiplication operation module multiplies the sampling signal and the second phase signal to generate a second composite signal; a third accumulation operation module connected to the second multiplication operation module, the The third accumulation operation module performs accumulation operation on the second composite signal and generates a second accumulation signal; and a fourth accumulation operation module connected to the third accumulation operation module, and the fourth accumulation operation module pairs The second accumulation signal is accumulated and generates a second output signal. 如請求項2所述的雜訊消除裝置,其中,該第一相位訊號為正弦波訊號,該第二相位訊號為餘弦波訊號。The noise cancellation device according to claim 2, wherein the first phase signal is a sine wave signal and the second phase signal is a cosine wave signal. 如請求項1所述的雜訊消除裝置,還包含一第一計數模組,連接該第一累加運算模組,用以計數該第一累加運算模組的累加次數;一第二計數模組,連接該第二累加運算模組,用以計數該第二累加運算模組的累加次數;一第三計數模組,連接該第三累加運算模組,用以計數該第三累加運算模組的累加次數;及一第四計數模組,連接該第四累加運算模組,用以計數該第四累加運算模組的累加次數。The noise cancellation device according to claim 1, further comprising a first counting module connected to the first accumulation operation module for counting the accumulation times of the first accumulation operation module; a second counting module Connected to the second accumulation operation module to count the accumulation times of the second accumulation operation module; a third counting module connected to the third accumulation operation module to count the third accumulation operation module And a fourth counting module connected to the fourth accumulation operation module for counting the accumulation times of the fourth accumulation operation module. 如請求項2所述的雜訊消除裝置,其中,該第三累加運算模組的累加次數為N3,該第四累加運算模組的累加次數為N4,且N3×N4為該取樣模組的取樣點數。The noise cancellation device according to claim 2, wherein the number of accumulations of the third accumulation operation module is N3, the number of accumulations of the fourth accumulation operation module is N4, and N3 × N4 is the number of accumulations of the sampling module. Number of sampling points. 如請求項5所述的雜訊消除裝置,其中,N3為該第二相位訊號的半週期的整數倍,且N3×N4包含整數個該第二相位訊號之週期。The noise cancellation device according to claim 5, wherein N3 is an integer multiple of a half period of the second phase signal, and N3 × N4 includes an integer number of periods of the second phase signal. 如請求項1、2或5所述的雜訊消除裝置,其中,該第一累加運算模組的累加次數為N1,該第二累加運算模組的累加次數為N2,且N1×N2為該取樣模組的取樣點數。The noise cancellation device according to claim 1, 2, or 5, wherein the number of accumulations of the first accumulation operation module is N1, the number of accumulations of the second accumulation operation module is N2, and N1 × N2 is the Number of sampling points of the sampling module. 如請求項7所述的雜訊消除裝置,其中,N1為該第一相位訊號的半週期的整數倍,且N1×N2包含整數個該第一相位訊號之週期。The noise cancellation device according to claim 7, wherein N1 is an integer multiple of a half period of the first phase signal, and N1 × N2 includes an integer number of periods of the first phase signal. 如請求項2所述的雜訊消除裝置,其中,該取樣模組的取樣頻率為該第一相位訊號之頻率與該第二相位訊號之頻率的整數倍。The noise cancellation device according to claim 2, wherein the sampling frequency of the sampling module is an integer multiple of the frequency of the first phase signal and the frequency of the second phase signal. 如請求項7所述的雜訊消除裝置,還包含一第一檢測單元,該第一檢測單元包括一連接該第一累加運算模組的第一檢測模組及一連接該第一檢測模組的第五計數模組,該第一檢測模組用以檢測該第一累加運算模組每累加N1個取樣點時的訊號雜訊,該第五計數模組計數通過該第一檢測模組檢測的次數。The noise cancellation device according to claim 7, further comprising a first detection unit. The first detection unit includes a first detection module connected to the first accumulation operation module and a first detection module connected to the first detection module. The fifth counting module, the first detecting module is configured to detect signal noise when the first accumulation operation module accumulates N1 sampling points, and the fifth counting module counts through the first detecting module Times. 如請求項5所述的雜訊消除裝置,還包含一第二檢測單元,該第二檢測單元包括一連接該第三累加運算模組的第二檢測模組及一連接該第二檢測模組的第六計數模組,該第二檢測模組用以檢測該第三累加運算模組每累加N3個取樣點時的訊號雜訊,該第六計數模組計數通過該第二檢測模組檢測的次數。The noise cancellation device according to claim 5, further comprising a second detection unit. The second detection unit includes a second detection module connected to the third accumulation operation module and a second detection module connected to the second detection module. The sixth counting module, the second detection module is used to detect the signal noise when the third accumulation operation module accumulates N3 sampling points, and the sixth counting module counts through the second detection module to detect Times.
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