TWI637511B - Enhanced-mode high electron mobility transistor and method for forming the same - Google Patents

Abstract

Embodiments of the present invention relate to an enhanced high electron mobility transistor (HEMT) including a substrate, a first III-V semiconductor layer disposed on the substrate, and a first III-V semiconductor layer disposed on the first III-V semiconductor layer a second III-V semiconductor layer, a third III-V semiconductor layer disposed on the second III-V semiconductor layer, and extending from the third III-V semiconductor layer into the second III-V The group semiconductor layer and the first III-V semiconductor layer have an amorphous region as an isolation region and a gate electrode disposed in the amorphous region. The second III-V semiconductor layer and the third III-V semiconductor layer include a different material to form a heterojunction.

Description

Enhanced high electron mobility transistor and method of forming same

Embodiments of the present invention relate to a semiconductor component, and more particularly to an enhanced high electron mobility transistor.

Semiconductor devices have been widely used in various electronic products such as, for example, high power devices, personal computers, mobile phones, and digital cameras. The semiconductor device is usually fabricated by sequentially depositing an insulating layer or a dielectric layer material, a conductive layer material, and a semiconductor layer material on a semiconductor substrate, and then patterning the various material layers formed by using a lithography process, whereby the semiconductor substrate is formed thereon. Circuit parts and components are formed on top.

Among them, high electron mobility transistors (for example, enhanced high electron mobility transistors) are widely used in high power devices due to their advantages of high output voltage and high breakdown voltage.

However, existing enhanced high electron mobility transistors still have some disadvantages and are not satisfactory in all respects.

An embodiment of the present invention provides an enhanced high electron mobility transistor, comprising: a substrate; a first III-V semiconductor layer disposed on the substrate; and a second III-V semiconductor layer disposed on the first III- On the V-group semiconductor layer; a third III-V semiconductor layer disposed on the second III-V semiconductor layer, wherein the second III-V semiconductor layer and the third III-V semiconductor layer comprise different materials to form a heterogeneity a junction region extending from the third III-V semiconductor layer into the second III-V semiconductor layer and the first III-V semiconductor layer as an isolation region; and a gate electrode , disposed in the above amorphous region.

The embodiment of the present invention also provides a method for forming an enhanced high electron mobility transistor, comprising: providing a substrate; forming a first III-V semiconductor layer on the substrate; forming a second III-V semiconductor layer in the above a III-V semiconductor layer; forming a third III-V semiconductor layer on the second III-V semiconductor layer, wherein the second III-V semiconductor layer and the third III-V semiconductor layer Including a dissimilar material to form a heterojunction; forming an amorphous region extending from the third III-V semiconductor layer into the second III-V semiconductor layer and the first III-V semiconductor layer as isolation a region; and forming a gate electrode in the amorphous region.

100‧‧‧Substrate

200‧‧‧First III-V semiconductor layer

300‧‧‧Second III-V semiconductor layer

400‧‧‧ Third III-V semiconductor layer

402‧‧‧ Heterojunction

404‧‧‧Two-dimensional electronic cloud (2DEG)

500‧‧‧Amorphous area

602‧‧‧ source ohmic contact

604‧‧‧Bungan ohmic contact

702‧‧‧ gate electrode

800‧‧‧ gate dielectric layer

900‧‧‧ Passivation layer

10, 10', 10"‧‧‧ high electron mobility transistor

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It is noted that the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

1-7 are a series of cross-sectional views for explaining a method of forming an enhanced high electron mobility transistor according to an embodiment of the present invention.

Figure 8 depicts an enhanced high electron mobility transistor of some embodiments of the invention.

Figure 9 illustrates an enhanced high electron mobility transistor of some embodiments of the present invention.

The following disclosure provides many different embodiments or examples to implement various features of the present invention. The following disclosure sets forth specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes that a first feature is formed on or above a second feature, that is, it may include an embodiment in which the first feature is in direct contact with the second feature, and may also include Additional features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact with each other. In addition, the different examples disclosed below may reuse the same reference symbols and/or labels. These repetitions are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

Various variations of the embodiments are described below. For ease of explanation, similar component numbers may be used to identify similar components. It will be appreciated that additional operational steps may be performed before, during or after the method, and that in other embodiments of the method, portions of the operational steps may be substituted or omitted.

The method for forming an enhanced high electron mobility transistor according to an embodiment of the present invention converts a portion of a III-V semiconductor layer into an amorphous region by an ion implantation process, and forms a gate electrode in the amorphous region. It can avoid or reduce gate leakage.

[First Embodiment]

Figure 1 illustrates the initial steps of this embodiment. First, provide the base Board 100. For example, substrate 100 can include a germanium substrate, a tantalum carbide (SiC) substrate, a sapphire substrate, a multilayer substrate, a graded substrate, other suitable substrates, or a combination thereof. In some embodiments, the substrate 100 may further include a semiconductor on insulator (SOI) substrate (eg, an insulating layer upper germanium substrate or an insulating layer upper germanium substrate), and the insulating layer upper semiconductor substrate may include a bottom plate and a set a buried oxide layer on the bottom plate and a semiconductor layer disposed on the buried oxide layer.

Next, as shown in FIG. 2, the first III-V semiconductor layer 200 is formed on the substrate 100. In some embodiments, the first III-V semiconductor layer 200 can include an N-type III-V semiconductor, which can include germanium, oxygen, other suitable dopants, or a combination thereof. In some embodiments, the N-type III-V semiconductor described above may include an N-type binary III-V semiconductor (eg, N-GaN). In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) can be used. And other suitable methods or combinations thereof to form the first III-V semiconductor layer 200 over the substrate 100.

In some embodiments, prior to the step of forming the first III-V semiconductor layer 200 over the substrate 100, it may be desirable (eg, to avoid or reduce the relationship between the substrate 100 and the first III-V semiconductor layer 200). A defect generated by lattice mismatch is formed by forming a buffer layer (not shown) on the substrate 100, and forming a first III-V semiconductor layer 200 on the buffer layer. For example, when the first III-V semiconductor layer 200 is N-GaN, the buffer layer may include AlN, AlGaN, other suitable materials, or a combination thereof.

Next, as shown in FIG. 3, a second III-V semiconductor layer 300 is formed over the first III-V semiconductor layer 200. In some embodiments, the second III-V semiconductor layer 300 can include a P-type III-V semiconductor, which can include magnesium, other suitable dopants, or a combination thereof. In some embodiments, the P-type III-V semiconductor described above may include a P-type binary III-V semiconductor (eg, P-GaN). In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) can be used. And other suitable methods or combinations thereof to form the second III-V semiconductor layer 300 over the first III-V semiconductor layer 200.

Next, as shown in FIG. 4, a third III-V semiconductor layer 400 is formed over the second III-V semiconductor layer 300. In some embodiments, the third III-V semiconductor layer 400 can include an undoped III-V semiconductor. In some embodiments, the undoped III-V semiconductor described above may include an undoped ternary III-V semiconductor (eg, undoped AlGaN). In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) can be used. And other suitable methods or combinations thereof to form the third III-V semiconductor layer 400 over the second III-V semiconductor layer 300.

As shown in FIG. 4, the third III-V semiconductor layer 400 includes a material different from the second III-V semiconductor layer 300 to form a heterojunction 402 (for example, forming a heterostructure with the AlGaN layer 400/GaN layer 300). Joint). In some embodiments, the heterojunction 402 causes a two-dimensional electron gas ( 2DEG) 404 is formed in the second III-V semiconductor layer 300 and extends along the interface between the second III-V semiconductor layer 300 and the third III-V semiconductor layer 400.

Next, as shown in FIG. 5, an amorphous region 500 extending from the third III-V semiconductor layer 400 into the second III-V semiconductor layer 300 and the first III-V semiconductor layer 200 is formed. For example, the amorphous region 500 can serve as an isolation region that can be used to avoid or reduce gate leakage, as will be described later. Further, as shown in FIG. 5, the amorphous region 500 may extend into the first III-V semiconductor layer 200 but does not extend to the bottom surface of the first III-V semiconductor layer 200.

For example, the amorphous region 500 may include an amorphized III-V semiconductor (eg, in the present embodiment, the amorphous region 500 includes amorphized GaN and AlGaN). In some embodiments, heavy ions (eg, oxygen ions, other suitable ions, or combinations thereof) can be implanted into one portion of the first III-V semiconductor layer 200, the second III-V, using an ion implantation process. a portion of the group semiconductor layer 300 and a portion of the third III-V semiconductor layer 400 such that a portion of the first III-V semiconductor layer 200, a portion of the second III-V semiconductor layer 300, and a third III- A portion of the group V semiconductor layer 400 is converted from crystalline to amorphous to form an amorphous region 500.

Next, as shown in FIG. 6, a source ohmic contact 602 and a drain ohmic contact 604 are formed. For example, source ohmic contact 602 and drain ohmic contact 604 can each comprise Ti, Al, Au, Pd, other suitable metallic materials, alloys thereof, or combinations thereof. In some embodiments, source ohmic contact 602 is in direct contact with third III-V semiconductor layer 400, while drain ohmic contact 604 is in direct contact with first III-V semiconductor layer 200. For example, one or more etching processes may be performed to the first III-V semiconductor layer 200 and the second III-V semiconductor layer 300. And forming a trench (not shown) corresponding to the source ohmic contact 602 and the drain ohmic contact 604 in the third III-V semiconductor layer 400, followed by physical vapor deposition (eg, evaporation or sputtering), Electroplating, atomic layer deposition, other suitable methods, or a combination thereof, filling the conductive material in the trench and removing excess conductive material via a suitable patterning process (eg, lithography process, etching process, or a combination thereof) A source ohmic contact 602 and a drain ohmic contact 604 are formed.

Next, as shown in FIG. 7, the gate electrode 702 is formed in the amorphous region 500 to form the high electron mobility transistor 10. For example, the gate electrode 702 can comprise a metallic material, a polysilicon, other suitable electrically conductive materials, or a combination thereof. For example, one or more etching processes may be performed to form a gate trench (not shown) corresponding to the gate electrode 702 in the amorphous region 500, followed by physical vapor deposition (eg, evaporation or sputtering). Plating, plating, atomic layer deposition, other suitable methods, or a combination thereof, filling the conductive material in the gate trench and via a suitable patterning process (eg, lithography process, etching process, or a combination thereof) Excess conductive material is removed to form gate electrode 702.

As shown in FIG. 7, in the present embodiment, the high electron mobility transistor 10 is an enhanced high electron mobility transistor (ie, normally-off) in which a P-type second III-V semiconductor is used. Layer 300 (eg, P-type GaN) can serve as a channel region for high electron mobility transistor 10. As shown in Fig. 7, the gate electrode 702 of the high electron mobility transistor 10 is formed in the amorphous region 500, and since the amorphous region 500 can serve as an isolation region, gate leakage can be avoided or reduced.

It should be noted that in the embodiment of the present invention, the channel length L of the high electron mobility transistor 10 can be substantially equivalent to the thickness of the P-type second III-V semiconductor layer 300, and thus can be controlled by the P-type. Second III-V semiconductor layer The epitaxial thickness of 300 precisely controls the channel length L of the high electron mobility transistor 10. In contrast, in the prior art, the channel length of the high electron mobility transistor is affected by the etching process, so that the channel length L cannot be precisely controlled by adjusting the deposition conditions as in the embodiment of the present invention.

In summary, the gate electrode of the high electron mobility transistor of the embodiment of the present invention is formed in an amorphous region (for example, an amorphized III-V semiconductor) to avoid or reduce gate leakage to improve its performance. .

[Second embodiment]

Fig. 8 is a view showing a high electron mobility transistor 10' of a second embodiment of the present invention. As shown in FIG. 8, a gate dielectric layer 800 is further disposed between the gate electrode 702 of the high electron mobility transistor 10' and the amorphous region 500, and the gate leakage current can be further reduced. For example, the gate dielectric layer 800 can surround the gate electrode 702 (eg, partially surrounding). In some embodiments, the gate dielectric layer 800 may include hafnium oxide, hafnium oxide (HfO ₂ ), hafnium oxide (HfSiO), hafnium oxynitride (HfSiON), hafnium oxide (HfTaO), niobium oxide ( HfTiO), hafnium zirconium oxide (HfZrO), tantalum nitride, niobium oxynitride, zirconia, titania, alumina, ceria-alumina (HfO ₂ -Al ₂ O ₃ ), other suitable dielectric materials or Combination of the above. In some embodiments, chemical vapor deposition, atomic layer deposition, high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), A gate dielectric layer 800 is formed by plasma enhanced CVD (PECVD), other suitable methods, or a combination thereof. For example, a gate dielectric can be formed in the gate trench after the step of forming a gate trench corresponding to the gate electrode 702 and before the step of filling the conductive material in the gate trench Floor.

[Third embodiment]

Fig. 9 is a view showing a high electron mobility transistor 10" of the third embodiment of the present invention. As shown in Fig. 9, the third III-V semiconductor layer 400 of the high electron mobility transistor 10" is further disposed. There is a passivation layer 900 that can be used to protect the underlying film layer. For example, passivation layer 900 can comprise SiN, AlN, other suitable materials, or a combination thereof. For example, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), The passivation layer 900 is formed by other suitable methods or combinations thereof. In some embodiments, heavy ions may also be implanted into a portion of the passivation layer 900 using the ion implantation process described above such that a portion of the passivation layer 900 described above is converted to a portion of the amorphous region 500. It should be noted that the gate dielectric layer 702 of the high electron mobility transistor 10" and the amorphous region 500 may also be provided with the aforementioned gate dielectric layer.

In summary, the gate electrode of the high electron mobility transistor of the embodiment of the present invention is formed in an amorphous region (for example, an amorphized III-V semiconductor) to avoid or reduce gate leakage to improve its performance. .

The foregoing summary of the various embodiments of the invention may be Those skilled in the art will understand that other processes and structures can be readily designed or modified based on the embodiments of the present invention to achieve the same objectives and/or to achieve the embodiments described herein. The same advantages. Those of ordinary skill in the art should also understand that these equal structures are not backed up. The spirit and scope of the invention are derived from the embodiments of the invention. Various changes, permutations, or modifications may be made to the embodiments of the invention without departing from the spirit and scope of the invention.

Claims (15)

An enhanced mode high electron mobility transistor (HEMT) comprising: a substrate; a first III-V semiconductor layer disposed on the substrate; and a second III-V semiconductor layer disposed on the substrate On the first III-V semiconductor layer; a third III-V semiconductor layer disposed on the second III-V semiconductor layer, wherein the second III-V semiconductor layer and the third III- The group V semiconductor layer includes a different material to form a heterojunction; an amorphous region extending from the third III-V semiconductor layer into the second III-V semiconductor layer and the first a III-V semiconductor layer serves as an isolation region; a gate electrode is disposed in the amorphous region; a source ohmic contact, wherein the source ohmic contact directly contacts the third III-V semiconductor layer; And a drain ohmic contact, wherein the drain ohmic contact directly contacts the first III-V semiconductor layer. The enhanced high electron mobility transistor of claim 1, wherein the amorphous region comprises an amorphized III-V semiconductor. The enhanced high electron mobility transistor according to claim 1, wherein the first III-V semiconductor layer comprises an N-type binary III-V semiconductor, and the second III-V semiconductor layer Including a P-type binary III-V semiconductor, the third III-V semiconductor layer includes an undoped ternary III-V half conductor. The enhanced high electron mobility transistor according to claim 3, wherein the first III-V semiconductor layer comprises N-type GaN, and the second III-V semiconductor layer comprises P-type GaN, The third III-V semiconductor layer includes undoped AlGaN. The enhanced high electron mobility transistor according to claim 1, wherein the amorphous region is formed by an ion implantation process. The enhanced high electron mobility transistor according to claim 1, wherein the second III-V semiconductor layer comprises a channel region, and one channel length of the channel region is substantially the same as the second III One of the thicknesses of the -V semiconductor layer. The enhanced high electron mobility transistor according to claim 1, further comprising: a gate dielectric layer disposed in the amorphous region, wherein the gate dielectric layer surrounds the gate electrode. The reinforced high electron mobility transistor according to claim 1, wherein the amorphous region does not extend to a bottom surface of the first III-V semiconductor layer. A method for forming an enhanced high electron mobility transistor, comprising: providing a substrate; forming a first III-V semiconductor layer on the substrate; forming a second III-V semiconductor layer on the first III- Forming a third III-V semiconductor layer on the second III-V semiconductor layer, Wherein the second III-V semiconductor layer and the third III-V semiconductor layer comprise a different material to form a heterojunction; forming a third III-V semiconductor layer extending into the second III-V An amorphous region of the group semiconductor layer and the first III-V semiconductor layer serves as an isolation region; and a gate electrode is formed in the amorphous region. The method for forming an enhanced high electron mobility transistor according to claim 9, wherein the forming the amorphous region comprises: performing an amorphization process to make a portion of the first III-V semiconductor layer And converting a portion of the second III-V semiconductor layer and one of the third III-V semiconductor layer into the amorphous region. The method for forming an enhanced high electron mobility transistor according to claim 10, wherein the portion of the first III-V semiconductor layer does not extend to one of the first III-V semiconductor layers surface. The method for forming an enhanced high electron mobility transistor according to claim 10, wherein the amorphization process comprises an ion implantation process. The method for forming an enhanced high electron mobility transistor according to claim 12, wherein the ion implantation process comprises implanting oxygen ions to the portion of the first III-V semiconductor layer, the second The portion of the III-V semiconductor layer and the portion of the third III-V semiconductor layer. The method for forming an enhanced high electron mobility transistor according to claim 9, wherein the step of forming the gate electrode in the amorphous region comprises: performing an etching process to form a gate trench in the non-etching In the crystal zone; A conductive material is filled in the gate trench to form the gate electrode. The method for forming an enhanced high electron mobility transistor according to claim 14, further comprising: forming a gate dielectric layer before the step of filling the conductive material in the gate trench In the pole groove.