TWI613493B - Sensing and pixel array structure on display panel - Google Patents
Sensing and pixel array structure on display panel Download PDFInfo
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- TWI613493B TWI613493B TW105142124A TW105142124A TWI613493B TW I613493 B TWI613493 B TW I613493B TW 105142124 A TW105142124 A TW 105142124A TW 105142124 A TW105142124 A TW 105142124A TW I613493 B TWI613493 B TW I613493B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
Abstract
一種具感測之顯示畫素陣列結構包括底承載板、第一線 路層、第一平坦層、第二線路層、第二平坦層、第一傳導結構、第二傳導結構以及畫素單元層。第一線路層配置於底承載板上。第一平坦層覆蓋第一線路層，且第二平坦層之遠離第二線路層的一側具有一平坦面。畫素單元層配置於第二平坦層的平坦面上且畫素單元層包一畫素單元。畫素單元至少包括一驅動電路。第一及第二傳導結構貫穿第一平坦層、第二線路層及第二平坦層並且連接於畫素單元層結構與第一及第二線路層之間。其中第一線路層包括一第一感測電極，第二線路層包括一第二感測電極。 A sensing pixel array structure includes a bottom carrier plate and a first line The circuit layer, the first flat layer, the second circuit layer, the second flat layer, the first conductive structure, the second conductive structure, and the pixel unit layer. The first circuit layer is disposed on the bottom carrier board. The first flat layer covers the first circuit layer, and a side of the second flat layer remote from the second circuit layer has a flat surface. The pixel unit layer is disposed on a flat surface of the second flat layer, and the pixel unit layer includes a pixel unit. The pixel unit includes at least a driving circuit. The first and second conductive structures penetrate the first flat layer, the second wiring layer, and the second flat layer and are connected between the pixel unit layer structure and the first and second wiring layers. The first circuit layer includes a first sensing electrode, and the second circuit layer includes a second sensing electrode.
Description
本申請是有關於一種具感測之顯示畫素陣列結構。 The present application relates to a sensing pixel array structure.
平面顯示面板已經是現行顯示產品的主流。隨著各種需求的增加與提升，例如示解析度或畫質方面的需求提升，會使得平面顯示面板中各畫素單元的驅動電路結構可能變得複雜。舉例來說，若採用有機發光材料當作顯示介質，各畫素單元的驅動電路結構可能包括不只一個電晶體以及一個或多個的電容結構，抑或是將現有面板當中的電路再結合其他的功能，將再增加其他線路之設計於面板上。另外，平面顯示面板中本身就還需要設置多種訊號線，例如掃描線、資料線以及電源線或是其他線路等。如此一來，在有限的面積中需要設置各種線路、主動元件、電容結構或其他功能所需的構件，這使得驅動電路結構的布局設計受到侷限。 Flat display panels have become the mainstream of current display products. With the increase and improvement of various requirements, such as the improvement in display resolution or image quality, the driving circuit structure of each pixel unit in the flat display panel may become complicated. For example, if an organic light-emitting material is used as a display medium, the driving circuit structure of each pixel unit may include more than one transistor and one or more capacitor structures, or the circuits in the existing panel may be combined with other functions. , Will add other circuit designs on the panel. In addition, the flat display panel itself needs to be provided with various signal lines, such as scanning lines, data lines, power lines, or other lines. In this way, various circuits, active components, capacitor structures, or other components required for functions need to be provided in a limited area, which limits the layout design of the driving circuit structure.
本申請提供一種具感測之顯示畫素陣列結構，有助於提升驅動電路結構的布局彈性。 The present application provides a sensing pixel array structure, which helps to improve the layout flexibility of the driving circuit structure.
本申請提供一種具感測之顯示畫素陣列結構，將訊號線的線路與感應電路結構製作於不同層位，以增加顯示面板電路結構的布局面積。 The present application provides a display pixel array structure with sensing. The circuit of the signal line and the sensing circuit structure are made at different levels to increase the layout area of the display panel circuit structure.
本申請之一實施例提供一種具感測之顯示畫素陣列結構，其包括一畫面顯示區及一周邊線路區，周邊線路區位於畫面顯示區外側，其中畫面顯示區包括一底承載板、一第一線路層、一第一平坦層、一第二線路層、一第二平坦層、一畫素單元層、一第一傳導結構、一第二傳導結構以及一第三傳導結構。線路層配置於底承載板上。第一平坦層覆蓋第一線路層，第二線路層，配置於該第一平坦層上，第二平坦層，覆蓋該第二線路層，且該第二平坦層之遠離該第二線路層的一側具有一平坦面。畫素單元層配置於平坦層的平坦面上且畫素單元層包括一畫素單元。第一傳導結構，配置於畫面顯示區，貫穿該第二平坦層、該第二線路層及第一平坦層並且連接於該畫素單元層與該第一線路層之間，第二傳導結構，配置於畫面顯示區，貫穿該第二平坦層並且連接於該畫素單元層與該第二線路層之間。在周邊線路區包括第三傳導結構，配置於周邊線路區，貫穿該第一平坦層並且連接於該第一線路層該第二線路層之間。 An embodiment of the present application provides a display pixel array structure with sensing, which includes a picture display area and a peripheral circuit area. The peripheral circuit area is located outside the picture display area. The picture display area includes a bottom carrier board, a The first circuit layer, a first planar layer, a second circuit layer, a second planar layer, a pixel unit layer, a first conductive structure, a second conductive structure, and a third conductive structure. The circuit layer is arranged on the bottom carrier board. The first planar layer covers the first circuit layer, the second circuit layer is disposed on the first planar layer, the second planar layer covers the second circuit layer, and the second planar layer is far from the second circuit layer. One side has a flat surface. The pixel unit layer is disposed on a flat surface of the flat layer, and the pixel unit layer includes a pixel unit. The first conductive structure is disposed in the screen display area, penetrates the second flat layer, the second wiring layer and the first flat layer and is connected between the pixel unit layer and the first wiring layer. The second conductive structure, It is arranged in the screen display area, penetrates the second flat layer and is connected between the pixel unit layer and the second circuit layer. The peripheral circuit area includes a third conductive structure, which is disposed in the peripheral circuit area, penetrates the first flat layer and is connected between the first circuit layer and the second circuit layer.
根據本申請之一實施例，所述具感測之顯示畫素陣列結 構中第一線路層包括一第一感測電極，第二線路層包括一第二感測電極。 According to an embodiment of the present application, the sensing display pixel array node In the structure, the first circuit layer includes a first sensing electrode, and the second circuit layer includes a second sensing electrode.
根據本申請之一實施例，所述第一平坦層級第二平坦層的材質包括有機絕緣材料、無機絕緣材料或其組合。 According to an embodiment of the present application, a material of the first flat layer and the second flat layer includes an organic insulating material, an inorganic insulating material, or a combination thereof.
根據本申請之一實施例，所述該有機絕緣材料包括聚亞醯胺、有機光阻材料、或其組合。 According to an embodiment of the present application, the organic insulating material includes polyimide, an organic photoresist material, or a combination thereof.
根據本申請之一實施例，所述該無機絕緣材料包括氧化矽、氮化矽、氮氧化矽或其組合。 According to an embodiment of the present application, the inorganic insulating material includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
根據本申請之一實施例，所述具感測之顯示面板包括上述的具感測之顯示畫素陣列結構以及顯示介質層，其中顯示介質層配置於畫素單元層上並連接畫素單元層。 According to an embodiment of the present application, the display panel with sensing includes the above-mentioned display pixel array structure with sensing and a display medium layer, wherein the display medium layer is disposed on the pixel unit layer and connected to the pixel unit layer. .
為讓本申請的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above features and advantages of this application more comprehensible, embodiments are described below in detail with the accompanying drawings as follows.
100、200、300、400、500、600、700、800、900、1000、2000‧‧‧顯示面板 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 2000‧‧‧ display panels
110、210、310、410、510、610、710、810、910、1010、2010‧‧‧底承載板 110, 210, 310, 410, 510, 610, 710, 810, 910, 1010, 2010‧‧‧ bottom load plate
120、220、320、420、520、620、720、820、920、1020、1120、1220、1320、1420、1520、1620、1720、1820、1920、2020‧‧‧第一線路層 120, 220, 320, 420, 520, 620, 720, 820, 920, 1020, 1120, 1220, 1320, 1420, 1520, 1620, 1720, 1820, 1920, 2020
120.1、220.1、320.1、420.1、520.1、620.1、720.1、820.1、920.1、1020.1、1120.1、1220.1、1320.1、1420.1、1520.1、1620.1、1720.1、1820.1、1920.1、2020.1‧‧‧第二線路層 120.1, 220.1, 320.1, 420.1, 520.1, 620.1, 720.1, 820.1, 920.1, 1020.1, 1120.1, 1220.1, 1320.1, 1420.1, 1520.1, 1620.1, 1720.1, 1820.1, 1920.1, 2020.1‧‧‧ Second circuit layer
130、230、330、330、430、530、630、730、830、930、1030、1130、1230、1330、1420、1520、1620、1720、1820、1920、2020‧‧‧ 第一平坦層 130, 230, 330, 330, 430, 530, 630, 730, 830, 930, 1030, 1130, 1230, 1330, 1420, 1520, 1620, 1720, 1820, 1920, 2020 First flat layer
130.1、230.1、330.1、430.1、530.1、630.1.、730.1、830.1、930.1、1030.1、1130.1、2030.1‧‧‧第二平坦層 130.1, 230.1, 330.1, 430.1, 530.1, 630.1., 730.1, 830.1, 930.1, 1030.1, 1130.1, 2030.1‧‧‧ Second flat layer
132、232、332、332、432、532、632、732、832、932、1032、2032‧‧‧平坦面 132, 232, 332, 332, 432, 532, 632, 732, 832, 932, 1032, 2032‧‧‧ flat surface
140、240、340、440、540、640、740、840、940、1040、2040‧‧‧畫素單元層 140, 240, 340, 440, 540, 640, 740, 840, 940, 1040, 2040‧‧‧ pixel unit layer
150、250、350、450、550、650、750、850、950、1050、2050‧‧‧第一傳導結構 150, 250, 350, 450, 550, 650, 750, 850, 950, 1050, 2050‧‧‧ first conductive structure
150.1、250.1、350.1、450.1、550.1、650.1、750.1、850.1、950.1、1050.1、2050.1‧‧‧第二傳導結構 150.1, 250.1, 350.1, 450.1, 550.1, 650.1, 750.1, 850.1, 950.1, 1050.1, 205.1
160‧‧‧顯示介質層 160‧‧‧Display media layer
170、370、570、770、870、970、1070、1770、1870、1970、2070‧‧‧閘極線 170, 370, 570, 770, 870, 970, 1070, 1770, 1870, 1970, 2070
171、271、371、471、571、671、771、871、971、1071、1171、1271、1371、1471、1571、1671、1771、1871、1971、2071‧‧‧第一感測電極 171, 271, 371, 471, 571, 671, 771, 871, 971, 1071, 1171, 1371, 1371, 1471, 1671, 1671, 1771, 1771, 1871, 1971, 2071
172、272、372、472、572、672、772、872、972、1072、1172、1272、1372、1472、1572、1672、1772、1872、1972、2072‧‧‧第二感測電極 172, 272, 372, 472, 572, 672, 772, 872, 972, 1072, 1172, 1272, 1372, 1472, 1572, 1672, 1772, 1872, 1972, 2072
173、273、573、673、973、1173、1373、1973、2073‧‧‧電源線 173, 273, 573, 673, 973, 1173, 1373, 1973, 2073‧‧‧ power cord
180、280、380、480、780、880、1280、1480、2080‧‧‧訊號線 180, 280, 380, 480, 780, 880, 1280, 1480, 2080‧‧‧ signal lines
1151、1251、1351、1451、1551、1651、1751、1851、1951、2051‧‧‧第三傳導結構 1151, 1251, 1351, 1451, 1551, 1651, 1751, 1851, 1951, 2051‧‧‧ third conductive structure
1152、1252、1352、1452、1752、1852、1952‧‧‧第四傳導結構 1152, 1252, 1352, 1452, 1752, 1852, 1952 ‧‧‧ fourth conductive structure
1153、1953‧‧‧第五傳導結構 1153, 1953‧‧‧ fifth conductive structure
I-I’‧‧‧剖線 I-I’‧‧‧ hatched
圖1為本申請第一實施例之一具感測之顯示面板之局部上視示意圖。 FIG. 1 is a schematic partial top view of a display panel with sensing according to a first embodiment of the present application.
圖2為本申請第一實施例之一具感測之顯示面板之剖面示意圖。 FIG. 2 is a schematic cross-sectional view of a sensing display panel according to a first embodiment of the present application.
圖3為本申請第二實施例之一具感測之顯示面板之剖面示意圖。 3 is a schematic cross-sectional view of a display panel with sensing according to a second embodiment of the present application.
圖4為本申請第三實施例之一具感測之顯示面板之剖面示意圖。 4 is a schematic cross-sectional view of a sensing display panel according to a third embodiment of the present application.
圖5為本申請第四實施例之一具感測之顯示面板之剖面示意圖。 FIG. 5 is a schematic cross-sectional view of a display panel with sensing according to a fourth embodiment of the present application.
圖6為本申請第五實施例之一具感測之顯示面板之剖面示意圖。 FIG. 6 is a schematic cross-sectional view of a display panel with sensing according to a fifth embodiment of the present application.
圖7為本申請第六實施例之一具感測之顯示面板之剖面示意圖。 FIG. 7 is a schematic cross-sectional view of a display panel with sensing according to a sixth embodiment of the present application.
圖8為本申請第七實施例之一具感測之顯示面板之剖面示意圖。 FIG. 8 is a schematic cross-sectional view of a sensing display panel according to a seventh embodiment of the present application.
圖9為本申請第八實施例之一具感測之顯示面板之剖面示意圖。 FIG. 9 is a schematic cross-sectional view of a sensing display panel according to an eighth embodiment of the present application.
圖10為本申請第九實施例之一具感測之顯示面板之剖面示意圖。 FIG. 10 is a schematic cross-sectional view of a sensing display panel according to a ninth embodiment of the present application.
圖11為本申請第十實施例之一具感測之顯示面板之剖面示意圖。 FIG. 11 is a schematic cross-sectional view of a display panel with sensing according to a tenth embodiment of the present application.
圖12為本申請第十一實施例之一具感測之顯示面板之周邊線路剖面示意圖。 FIG. 12 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to an eleventh embodiment of the present application.
圖13為本申請第十二實施例之一具感測之顯示面板之周邊線路剖面示意圖。 13 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a twelfth embodiment of the present application.
圖14為本申請第十三實施例之一具感測之顯示面板之周邊線路剖面示意圖。 14 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a thirteenth embodiment of the present application.
圖15為本申請第十四實施例之一具感測之顯示面板之周邊線路剖面示意圖。 15 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a fourteenth embodiment of the present application.
圖16為本申請第十五實施例之一具感測之顯示面板之周邊線路剖面示意圖。 16 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a fifteenth embodiment of the present application.
圖17為本申請第十六實施例之一具感測之顯示面板之周邊線路剖面示意圖。 17 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a sixteenth embodiment of the present application.
圖18為本申請第十七實施例之一具感測之顯示面板之周邊線路剖面示意圖。 18 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a seventeenth embodiment of the present application.
圖19為本申請第十八實施例之一具感測之顯示面板之周邊線路剖面示意圖。 19 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to an eighteenth embodiment of the present application.
圖20為本申請第十九實施例之一具感測之顯示面板之周邊線路剖面示意圖。 20 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a nineteenth embodiment of the present application.
圖21為本申請第二十實施例之一具感測之顯示面板之剖面示意圖。 FIG. 21 is a schematic cross-sectional view of a sensing display panel according to a twentieth embodiment of the present application.
為了驅動顯示面板或感測訊號，需要提供不只一種訊號，例如複數條掃描訊號、複數條資料訊號、複數條電源訊號或是其他複數條感測訊號等，因此不論是傳遞訊號用的線路在整個顯示面板中估有一定比例的面積，或是增加感測功能的結構於面板中。在本申請的實施方式說明中，上述線路的至少一種可以分別設置於第一線路層或是第二線路層中，並可以第一平坦層或第 二平坦層來區隔第一線路層與第二線路層或第二線路層與畫素單元層之間，使得第一線路層、第二線路層與畫素單元層在垂直方向上彼此分離(位於不同層位)，另外，畫素單元層包括多個畫素單元，且這些畫素單元為一陣列排列，其中單一畫素單元包括驅動電路結構以及連接於驅動電路結構的畫素電極。驅動電路結構則至少包括第一主動元件、第二主動元件。如此一來，一方面畫素單元層中單一畫素單元的驅動電路結構能夠具有增大的布局面積，可提升驅動電路結構的設計彈性，另一方面，可以藉由第一線路層及第二線路層中的相對感測電極產生電容形成感測訊號。 In order to drive a display panel or a sensing signal, more than one signal needs to be provided, such as a plurality of scanning signals, a plurality of data signals, a plurality of power signals, or other plurality of sensing signals. A certain percentage of the area is estimated in the display panel, or a structure that adds a sensing function to the panel. In the description of the embodiment of the present application, at least one of the above circuits may be respectively disposed in the first circuit layer or the second circuit layer, and may be the first flat layer or the first layer. Two flat layers separate the first circuit layer from the second circuit layer or between the second circuit layer and the pixel unit layer, so that the first circuit layer, the second circuit layer, and the pixel unit layer are vertically separated from each other ( (Located in different layers). In addition, the pixel unit layer includes a plurality of pixel units, and the pixel units are arranged in an array. A single pixel unit includes a driving circuit structure and a pixel electrode connected to the driving circuit structure. The driving circuit structure includes at least a first active element and a second active element. In this way, on the one hand, the driving circuit structure of a single pixel unit in the pixel unit layer can have an increased layout area, which can improve the design flexibility of the driving circuit structure, and on the other hand, the first circuit layer and the second circuit layer can be used. The opposite sensing electrodes in the circuit layer generate capacitance to form a sensing signal.
圖1為本申請第一實施例的第一實施例之一具感測之顯示面板之局部上視示意圖。圖1中省略了具感測之顯示面板的部分構件，只顯示了顯示面板100的部分構件，包括複數條訊號線、複數條閘極線、複數條電源線以及複數條第一感測電極、第二感測電極、第一傳導結構及第二傳導結構。換言之，複數條訊號線、複數條閘極線、複數條電源線以及複數條第一感測電極及複數條第二感測電極是以不同層的結構交疊在畫素單元層下方。本申請後述之實施例中關於複數條訊號線、複數條閘極線、複數條電源線以及複數條第一感測電極及複數條第二感測電極都簡述為訊號線、閘極線、電源線以及第一感測電極及第二感測電極。 FIG. 1 is a schematic partial top view of a sensing display panel according to a first embodiment of the first embodiment of the present application. Some components of the display panel with sensing are omitted in FIG. 1, and only some components of the display panel 100 are shown, including a plurality of signal lines, a plurality of gate lines, a plurality of power lines, and a plurality of first sensing electrodes, The second sensing electrode, the first conductive structure, and the second conductive structure. In other words, the plurality of signal lines, the plurality of gate lines, the plurality of power lines, and the plurality of first sensing electrodes and the plurality of second sensing electrodes are overlapped under the pixel unit layer in different layers. In the embodiments described later in this application, the plurality of signal lines, the plurality of gate lines, the plurality of power lines, and the plurality of first sensing electrodes and the plurality of second sensing electrodes are briefly described as signal lines, gate lines, The power line, the first sensing electrode and the second sensing electrode.
圖2為本申請第一實施例之一具感測之顯示面板之剖面示意圖。請參照圖1剖線I-I’及圖2，在圖2中顯示面板100包括底承載板110、第一線路層120、第一平坦層130、第二線路層 120.1、第二平坦層130.1、畫素單元層140、第一傳導結構150、第二傳導結構150.1以及顯示介質層160，其中底承載板110、第一線路層120、第一平坦層130、第二線路層120.1、第二平坦層130.1、畫素單元層140、第一傳導結構150、第二傳導結構150.1所構成的結構可以稱為畫素陣列結構。第一線路層120配置於底承載板110上。第一平坦層130覆蓋第一線路層120，第二線路層120.1配置於第一平坦層130上，第二平坦層130.1覆蓋第二線路層120.1，且第二平坦層130.1之遠離第二線路層120.1的一側具有一平坦面132。畫素單元層140配置於第二平坦層130.1的平坦面132上且畫素單元層140包括畫素單元。畫素單元包括電性連接驅動電路結構的畫素電極。第一傳導結構150貫穿第一平坦層130、第二線路層120.1及第二平坦層130.1並且連接於驅動電路結構與第一線路層120之間，第一傳導結構150更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線170，另外，第一線路層中更包括第一感測電極171，其中閘極線170與第一感測電極171電性上分離。顯示介質層160配置於畫素單元層140上並連接畫素單元層。第二傳導結構150.1貫穿第二平坦層130.1並且連接於畫素單元層的驅動電路結構與第二線路層120.1之間，第二傳導結構150.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線180，另外，第二線路層中更包括第二感測電極172與電源線173，其中訊號線180與第二感測電極172及電源線173電性上分離。第一感測電極171與第二感測電極172 兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。第一線路層120中的訊號線180電性連接至畫素單元層130透過第一傳導結構150。如此一來，畫素單元層130可以接收到來自訊號線180所提供的訊號而驅動顯示介質層160。在本實施例中，顯示介質層160的材質包括有機發光材料，不過其他實施例也可以採用液晶材料、電泳顯示材料、發光半導體材料等其他材料作為顯示介質層160。 FIG. 2 is a schematic cross-sectional view of a sensing display panel according to a first embodiment of the present application. Please refer to the section line I-I 'of FIG. 1 and FIG. 2. In FIG. 2, the display panel 100 includes a bottom carrier board 110, a first circuit layer 120, a first flat layer 130, and a second circuit layer. 120.1, the second flat layer 130.1, the pixel unit layer 140, the first conductive structure 150, the second conductive structure 150.1, and the display medium layer 160, wherein the bottom carrier board 110, the first wiring layer 120, the first flat layer 130, the first The structure composed of the two circuit layers 120.1, the second flat layer 130.1, the pixel unit layer 140, the first conductive structure 150, and the second conductive structure 150.1 may be referred to as a pixel array structure. The first circuit layer 120 is disposed on the bottom carrier board 110. The first planar layer 130 covers the first circuit layer 120, the second circuit layer 120.1 is disposed on the first planar layer 130, the second planar layer 130.1 covers the second circuit layer 120.1, and the second planar layer 130.1 is far from the second circuit layer 120.1 has a flat surface 132 on one side. The pixel unit layer 140 is disposed on the flat surface 132 of the second flat layer 130.1, and the pixel unit layer 140 includes a pixel unit. The pixel unit includes a pixel electrode electrically connected to the driving circuit structure. The first conductive structure 150 penetrates the first flat layer 130, the second circuit layer 120.1, and the second flat layer 130.1 and is connected between the driving circuit structure and the first circuit layer 120. The first conductive structure 150 is further connected to the pixel unit. The driving circuit structure of the layer and the gate line 170 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 171, wherein the gate line 170 is electrically separated from the first sensing electrode 171. The display medium layer 160 is disposed on the pixel unit layer 140 and is connected to the pixel unit layer. The second conductive structure 150.1 penetrates the second flat layer 130.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 120.1. The second conductive structure 150.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal line 180 in the second circuit layer. In addition, the second circuit layer further includes a second sensing electrode 172 and a power line 173, wherein the signal line 180 is electrically separated from the second sensing electrode 172 and the power line 173. First sensing electrode 171 and second sensing electrode 172 Opposite each other to generate a capacitor C, and generate a sensing signal through the change of the capacitor C. The signal line 180 in the first circuit layer 120 is electrically connected to the pixel unit layer 130 and passes through the first conductive structure 150. In this way, the pixel unit layer 130 can receive the signal provided by the signal line 180 to drive the display medium layer 160. In this embodiment, the material of the display medium layer 160 includes an organic light emitting material, but other materials such as a liquid crystal material, an electrophoretic display material, and a light emitting semiconductor material may be used as the display medium layer 160 in other embodiments.
在本實施例中，其中閘極線、第一感測電極設置於第一線路層，而訊號線與電源線及第二感測電極都設置於第二線路層中，而且第一線路層、第二線路層與畫素單元層彼此上下疊置。因此，使得畫素單元層中各畫素單元的布局空間不需受到上述線路或是其他畫素單元的構件所局限，因而更富有彈性，在後續的其他實施例中，也是依此方式實施。 In this embodiment, the gate line and the first sensing electrode are disposed on the first circuit layer, and the signal line, the power line, and the second sensing electrode are disposed on the second circuit layer, and the first circuit layer, The second circuit layer and the pixel unit layer are stacked on top of each other. Therefore, the layout space of each pixel unit in the pixel unit layer does not need to be limited by the above-mentioned circuit or other pixel unit components, so it is more flexible. In other subsequent embodiments, it is also implemented in this way.
此外，在本實施例中第一平坦層設於第一線路層及第二線路層之間，而設置於第二線路層與畫素單元層之間的第二平坦層具有平坦表面。可以將畫素單元中主動元件製作於該平坦表面，以確保主動元件品質；另外，在底承載板及第一線路層之間也可多一層水氣阻障層(未繪示)以保護及延長內部元件壽命。在此實施例中，主動元件可設置為頂閘型薄膜電晶體結構或底閘型薄膜電晶體結構。在後續的其他實施例中，也可依此方式實施。 In addition, in this embodiment, the first flat layer is disposed between the first circuit layer and the second circuit layer, and the second flat layer disposed between the second circuit layer and the pixel unit layer has a flat surface. The active element in the pixel unit can be made on the flat surface to ensure the quality of the active element. In addition, an additional water vapor barrier layer (not shown) can be added between the bottom carrier board and the first circuit layer to protect and Extend the life of internal components. In this embodiment, the active element may be configured as a top-gate thin film transistor structure or a bottom-gate thin film transistor structure. In other subsequent embodiments, it can also be implemented in this manner.
此外，第一平坦層或第二平坦層的材質包括有機絕緣材料、無機絕緣材料或其組合，並且第二平坦層的溫度耐受性可以 容忍驅動電路結構的製程溫度。舉例而言，作為第一平坦層或第二平坦層的有機絕緣材料包括聚亞醯胺、有機光阻材料、或其組合，而無機絕緣材料包括氧化矽、氮化矽、氮氧化矽或其組合。在一實施例中，第一平坦層或第二平坦層可以是沉積層或塗佈層，以沉積或塗佈方式形成。而平坦層之平坦面的表面起伏程度可以依照不同製程需求而決定。在一實施例中，只要第二平坦面的表面起伏程度(或是粗糙度)不致降低驅動電路結構的製作良率，即可採用。在後續的其他實施例中，也是依此方式實施。 In addition, the material of the first flat layer or the second flat layer includes an organic insulating material, an inorganic insulating material, or a combination thereof, and the temperature resistance of the second flat layer may be Tolerate the process temperature of the drive circuit structure. For example, the organic insulating material as the first flat layer or the second flat layer includes polyimide, an organic photoresist material, or a combination thereof, and the inorganic insulating material includes silicon oxide, silicon nitride, silicon oxynitride, or the like. combination. In an embodiment, the first flat layer or the second flat layer may be a deposited layer or a coating layer, and is formed in a deposition or coating manner. The degree of undulation of the flat surface of the flat layer can be determined according to different process requirements. In one embodiment, as long as the surface undulation (or roughness) of the second flat surface does not reduce the manufacturing yield of the driving circuit structure, it can be adopted. In other subsequent embodiments, this is also implemented.
此外，關於本實施例之第一或第二傳導結構的形成方法，可包括先在第一平坦層、第二線路層或第二平坦層上形成暴露出第一線路層120或第二線路層的貫孔(未繪示)，並且在貫孔中填入導電材料。在後續的其他實施例中，也是依此方式實施。 In addition, the method for forming the first or second conductive structure in this embodiment may include first forming a first circuit layer 120 or a second circuit layer on the first planar layer, the second circuit layer, or the second planar layer to expose the first circuit layer 120 or the second circuit layer. Through holes (not shown), and conductive materials are filled in the through holes. In other subsequent embodiments, this is also implemented.
圖3為本申請第二實施例之一具感測之顯示面板之剖面示意圖。請參照圖3，顯示面板200包括底承載板220、第一線路層220、第一平坦層230、第二線路層220.1、第二平坦層230.1、畫素單元層240、第一傳導結構250、第二傳導結構250.1，其中底承載板210、第一線路層220、第一平坦層230、第二線路層220.1、第二平坦層230.1、畫素單元層240、第一傳導結構250、第二傳導結構250.1所構成的結構可以稱為畫素陣列結構。第一線路層220配置於底承載板210上。第一平坦層230覆蓋第一線路層220，第二線路層220.1配置於第一平坦層230上，第二平坦層230.1覆蓋第二線路層220.1，且第二平坦層230.1之遠離第二線路 層220.1的一側具有一平坦面232。畫素單元層240配置於第二平坦層230.1的平坦面232上且畫素單元層240包括畫素單元。畫素單元包括電性連接驅動電路結構的畫素電極。第一傳導結構250貫穿第一平坦層230、第二線路層220.1及第二平坦層230.1並且連接於畫素單元層的驅動電路結構與第一線路層220之間，第一傳導結構250更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線，本實施例中，第一線路層中第一感測電極271之至少一與閘極線之至少一為共同電極。顯示介質層(未繪示)配置於畫素單元層240上並連接畫素單元層。第二傳導結構250.1貫穿第二平坦層230.1並且連接於畫素單元層的驅動電路結構與第二線路層220.1之間，第二傳導結構250.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線280，另外，第二線路層中更包括第二感測電極272與電源線273，其中訊號線280與第二感測電極272及電源線273電性上分離。共同電極(含第一感測電極271)與第二感測電極272兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 3 is a schematic cross-sectional view of a display panel with sensing according to a second embodiment of the present application. 3, the display panel 200 includes a bottom carrier board 220, a first circuit layer 220, a first planar layer 230, a second circuit layer 220.1, a second planar layer 230.1, a pixel unit layer 240, a first conductive structure 250, The second conductive structure 250.1 includes the bottom carrier board 210, the first circuit layer 220, the first flat layer 230, the second circuit layer 220.1, the second flat layer 230.1, the pixel unit layer 240, the first conductive structure 250, and the second The structure formed by the conductive structure 250.1 may be referred to as a pixel array structure. The first circuit layer 220 is disposed on the bottom carrier plate 210. The first planar layer 230 covers the first circuit layer 220, the second circuit layer 220.1 is disposed on the first planar layer 230, the second planar layer 230.1 covers the second circuit layer 220.1, and the second planar layer 230.1 is far from the second circuit. The layer 220.1 has a flat surface 232 on one side. The pixel unit layer 240 is disposed on the flat surface 232 of the second flat layer 230.1, and the pixel unit layer 240 includes a pixel unit. The pixel unit includes a pixel electrode electrically connected to the driving circuit structure. The first conductive structure 250 penetrates the first flat layer 230, the second circuit layer 220.1, and the second flat layer 230.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 220. The first conductive structure 250 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate lines in the first circuit layer. In this embodiment, at least one of the first sensing electrodes 271 and at least one of the gate lines in the first circuit layer are common electrodes. . The display medium layer (not shown) is disposed on the pixel unit layer 240 and is connected to the pixel unit layer. The second conductive structure 250.1 penetrates the second flat layer 230.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 220.1. The second conductive structure 250.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal lines 280 in the second circuit layer, and in addition, the second circuit layer further includes a second sensing electrode 272 and a power line 273, wherein the signal line 280 is electrically separated from the second sensing electrode 272 and the power line 273. The common electrode (including the first sensing electrode 271) and the second sensing electrode 272 are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖4為本申請第三實施例之一具感測之顯示面板之剖面示意圖。請參照圖4，顯示面板300包括底承載板310、第一線路層320、第一平坦層330、第二線路層320.1、第二平坦層330.1、畫素單元層340、第一傳導結構350以及第二傳導結構350.1，其中底承載板310、第一線路層320、第一平坦層330、第二線路層320.1、第二平坦層330.1、畫素單元層340、第一傳導結構350、 第二傳導結構350.1所構成的結構可以稱為畫素陣列結構。第一線路層320配置於底承載板310上。第一平坦層330覆蓋第一線路層320，第二線路層320.1配置於第一平坦層330上，第二平坦層330.1覆蓋第二線路層320.1，且第二平坦層330.1之遠離第二線路層320.1的一側具有一平坦面332。畫素單元層340配置於第二平坦層330.1的平坦面332上且畫素單元層340包括畫素單元。畫素單元包括電性連接驅動電路結構的畫素電極。第一傳導結構350貫穿第一平坦層330、第二線路層320.1及第二平坦層330.1並且連接於畫素單元層的驅動電路結構與第一線路層320之間，第一傳導結構350更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線370，另外，第一線路層中更包括第一感測電極371，其中閘極線370與第一感測電極171電性上分離。顯示介質層(未繪示)配置於畫素單元層340上並連接畫素單元層。第二傳導結構350.1貫穿第二平坦層330.1並且連接於畫素單元層的驅動電路結構與第二線路層320.1之間，第二傳導結構350.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線380，另外，第二線路層中更包括第二感測電極與電源線，其中第二感測電極372之至少一及電源線之至少一為共同電極並與訊號線380電性上分離。第一感測電極371與共同電極(含第二感測電極372)兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 4 is a schematic cross-sectional view of a sensing display panel according to a third embodiment of the present application. Referring to FIG. 4, the display panel 300 includes a bottom carrier board 310, a first circuit layer 320, a first planar layer 330, a second circuit layer 320.1, a second planar layer 330.1, a pixel unit layer 340, a first conductive structure 350, and The second conductive structure 350.1 includes the bottom carrier plate 310, the first circuit layer 320, the first planar layer 330, the second circuit layer 320.1, the second planar layer 330.1, the pixel unit layer 340, the first conductive structure 350, The structure formed by the second conductive structure 350.1 may be referred to as a pixel array structure. The first circuit layer 320 is disposed on the bottom carrier plate 310. The first planar layer 330 covers the first circuit layer 320, the second circuit layer 320.1 is disposed on the first planar layer 330, the second planar layer 330.1 covers the second circuit layer 320.1, and the second planar layer 330.1 is far from the second circuit layer 320.1 has a flat surface 332 on one side. The pixel unit layer 340 is disposed on the flat surface 332 of the second flat layer 330.1, and the pixel unit layer 340 includes a pixel unit. The pixel unit includes a pixel electrode electrically connected to the driving circuit structure. The first conductive structure 350 penetrates the first flat layer 330, the second circuit layer 320.1, and the second flat layer 330.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 320. The first conductive structure 350 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate line 370 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 371, wherein the gate line 370 and the first sensing electrode 171 Electrically separated. The display medium layer (not shown) is disposed on the pixel unit layer 340 and is connected to the pixel unit layer. The second conductive structure 350.1 penetrates the second flat layer 330.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 320.1. The second conductive structure 350.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal line 380 in the two circuit layer. In addition, the second circuit layer further includes a second sensing electrode and a power line, wherein at least one of the second sensing electrode 372 and at least one of the power line are a common electrode and communicate with the signal line. 380 is electrically separated. The first sensing electrode 371 and the common electrode (including the second sensing electrode 372) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖5為本申請第四實施例之一具感測之顯示面板之剖面示意圖。請參照圖5，顯示面板400包括底承載板420、第一線路 層420、第一平坦層430、第二線路層420.1、第二平坦層430.1、畫素單元層440、第一傳導結構450、第二傳導結構450.1，其中底承載板410、第一線路層420、第一平坦層430、第二線路層420.1、第二平坦層430.1、畫素單元層440、第一傳導結構450、第二傳導結構450.1所構成的結構可以稱為畫素陣列結構。第一線路層420配置於底承載板410上。第一平坦層430覆蓋第一線路層420，第二線路層420.1配置於第一平坦層430上，第二平坦層430.1覆蓋第二線路層420.1，且第二平坦層430.1之遠離第二線路層420.1的一側具有一平坦面432。畫素單元層440配置於第二平坦層430.1的平坦面432上且畫素單元層440包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極。第一傳導結構450貫穿第一平坦層430、第二線路層420.1及第二平坦層430.1並且連接於畫素單元層的驅動電路結構與第一線路層420之間，第一傳導結構450更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線，其中第一感測電極471之至少一與閘極線之至少一為第一共同電極。另外，第二線路層包括第二感測電極472之至少一及電源線之至少一為第二共同電極並與訊號線480電性上分離，其中，第二傳導結構450.1連接於畫素單元層的驅動電路結構與第二線路層中的訊號線480。第一共同電極(含第一感測電極471)與第二共同電極(含第二感測電極472)兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 FIG. 5 is a schematic cross-sectional view of a display panel with sensing according to a fourth embodiment of the present application. 5, the display panel 400 includes a bottom carrier plate 420 and a first circuit. Layer 420, first flat layer 430, second circuit layer 420.1, second flat layer 430.1, pixel unit layer 440, first conductive structure 450, second conductive structure 450.1, of which the bottom carrier plate 410 and the first circuit layer 420 The structure formed by the first flat layer 430, the second circuit layer 420.1, the second flat layer 430.1, the pixel unit layer 440, the first conductive structure 450, and the second conductive structure 450.1 may be referred to as a pixel array structure. The first circuit layer 420 is disposed on the bottom carrier plate 410. The first planar layer 430 covers the first circuit layer 420, the second circuit layer 420.1 is disposed on the first planar layer 430, the second planar layer 430.1 covers the second circuit layer 420.1, and the second planar layer 430.1 is far from the second circuit layer 420.1 has a flat surface 432 on one side. The pixel unit layer 440 is disposed on the flat surface 432 of the second flat layer 430.1, and the pixel unit layer 440 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 450 penetrates the first flat layer 430, the second circuit layer 420.1, and the second flat layer 430.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 420. The first conductive structure 450 goes further. The driving circuit structure connected to the pixel unit layer and the gate lines in the first circuit layer, wherein at least one of the first sensing electrodes 471 and at least one of the gate lines are first common electrodes. In addition, the second circuit layer includes at least one of the second sensing electrodes 472 and at least one of the power lines as a second common electrode and is electrically separated from the signal line 480. The second conductive structure 450.1 is connected to the pixel unit layer. The driving circuit structure and the signal line 480 in the second circuit layer. The first common electrode (including the first sensing electrode 471) and the second common electrode (including the second sensing electrode 472) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖6為本申請第五實施例之一具感測之顯示面板之剖面 示意圖。請參照圖6，顯示面板500包括底承載板510、第一線路層520、第一平坦層530、第二線路層520.1、第二平坦層530.1、畫素單元層540、第一傳導結構550、第二傳導結構550.1，其中底承載板510、第一線路層520、第一平坦層530、第二線路層520.1、第二平坦層530.1、畫素單元層540、第一傳導結構550、第二傳導結構550.1所構成的結構可以稱為畫素陣列結構。第一線路層520配置於底承載板510上。第一平坦層530覆蓋第一線路層520，第二線路層520.1配置於第一平坦層530上，第二平坦層530.1覆蓋第二線路層520.1，且第二平坦層530.1之遠離第二線路層520.1的一側具有一平坦面532。畫素單元層540配置於第二平坦層530.1的平坦面532上且畫素單元層540包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極。第一傳導結構550貫穿第一平坦層530、第二線路層520.1及第二平坦層530.1並且連接於畫素單元層的驅動電路結構與第一線路層520之間，第一傳導結構550更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線570，另外，第一線路層中更包括第一感測電極571，其中閘極線570與第一感測電極571電性上分離。顯示介質層(未繪示)配置於畫素單元層540上並連接畫素單元層。第二傳導結構550.1貫穿第二平坦層530.1並且連接於畫素單元層的驅動電路結構與第二線路層520.1之間，第二傳導結構550.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線，另外，第二線路層中更包括第二感測電極572與電 源線573，其中第二感測電極572之至少一及訊號線之至少一為共同電極並與電源線573電性上分離。第一感測電極571與共同電極(含第二感測電極572)兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 FIG. 6 is a cross-section of a display panel with sensing according to a fifth embodiment of the present application. schematic diagram. Referring to FIG. 6, the display panel 500 includes a bottom carrier board 510, a first circuit layer 520, a first planar layer 530, a second circuit layer 520.1, a second planar layer 530.1, a pixel unit layer 540, a first conductive structure 550, The second conductive structure 550.1, wherein the bottom carrier plate 510, the first circuit layer 520, the first flat layer 530, the second circuit layer 520.1, the second flat layer 530.1, the pixel unit layer 540, the first conductive structure 550, and the second The structure formed by the conductive structure 550.1 may be referred to as a pixel array structure. The first circuit layer 520 is disposed on the bottom carrier plate 510. The first planar layer 530 covers the first circuit layer 520, the second circuit layer 520.1 is disposed on the first planar layer 530, the second planar layer 530.1 covers the second circuit layer 520.1, and the second planar layer 530.1 is far from the second circuit layer 520.1 has a flat surface 532 on one side. The pixel unit layer 540 is disposed on the flat surface 532 of the second flat layer 530.1, and the pixel unit layer 540 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 550 penetrates the first flat layer 530, the second wiring layer 520.1, and the second flat layer 530.1 and is connected between the driving circuit structure of the pixel unit layer and the first wiring layer 520. The first conductive structure 550 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate line 570 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 571, wherein the gate line 570 and the first sensing electrode 571 Electrically separated. The display medium layer (not shown) is disposed on the pixel unit layer 540 and is connected to the pixel unit layer. The second conductive structure 550.1 penetrates the second flat layer 530.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 520.1. The second conductive structure 550.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal lines in the second circuit layer. In addition, the second circuit layer further includes a second sensing electrode 572 and an electrical circuit. The source line 573, wherein at least one of the second sensing electrode 572 and at least one of the signal lines are common electrodes and are electrically separated from the power line 573. The first sensing electrode 571 and the common electrode (including the second sensing electrode 572) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖7為本申請實施例之一具感測之顯示面板之剖面示意圖。請參照圖7，顯示面板600包括底承載板620、第一線路層620、第一平坦層630、第二線路層620.1、第二平坦層630.1、畫素單元層640、第一傳導結構650、第二傳導結構650.1，其中底承載板610、第一線路層620、第一平坦層630、第二線路層620.1、第二平坦層630.1、畫素單元層640、第一傳導結構650、第二傳導結構650.1所構成的結構可以稱為畫素陣列結構。第一線路層620配置於底承載板610上。第一平坦層630覆蓋第一線路層620，第二線路層620.1配置於第一平坦層630上，第二平坦層630.1覆蓋第二線路層620.1，且第二平坦層630.1之遠離第二線路層620.1的一側具有一平坦面632。畫素單元層640配置於第二平坦層630.1的平坦面632上且畫素單元層640包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極。第一傳導結構650貫穿第一平坦層630、第二線路層620.1及第二平坦層630.1並且連接於畫素單元層的驅動電路結構與第一線路層620之間，第一傳導結構650更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線，其中第一感測電極671之至少一與閘極線之至少一為第一共同電極。另外，第二線路層包括第二感測電 極672之至少一及訊號線之至少一為第二共同電極並與電源線673電性上分離，其中，第二傳導結構550.1貫穿第二平坦層630.1並且連接於畫素單元層的驅動電路結構與第二線路層620.1之間，第二傳導結構550.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線。第一共同電極(含第一感測電極671)與第二共同電極(含第二感測電極672)兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 FIG. 7 is a schematic cross-sectional view of a display panel with sensing according to an embodiment of the present application. Referring to FIG. 7, the display panel 600 includes a bottom carrier board 620, a first circuit layer 620, a first flat layer 630, a second circuit layer 620.1, a second flat layer 630.1, a pixel unit layer 640, a first conductive structure 650, The second conductive structure 650.1, wherein the bottom carrier plate 610, the first circuit layer 620, the first flat layer 630, the second circuit layer 620.1, the second flat layer 630.1, the pixel unit layer 640, the first conductive structure 650, and the second The structure formed by the conductive structure 650.1 can be referred to as a pixel array structure. The first circuit layer 620 is disposed on the bottom carrier plate 610. The first planar layer 630 covers the first circuit layer 620, the second circuit layer 620.1 is disposed on the first planar layer 630, the second planar layer 630.1 covers the second circuit layer 620.1, and the second planar layer 630.1 is far from the second circuit layer 620.1 has a flat surface 632 on one side. The pixel unit layer 640 is disposed on the flat surface 632 of the second flat layer 630.1, and the pixel unit layer 640 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 650 penetrates the first flat layer 630, the second circuit layer 620.1, and the second flat layer 630.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 620. The first conductive structure 650 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate lines in the first circuit layer, wherein at least one of the first sensing electrodes 671 and at least one of the gate lines are first common electrodes. In addition, the second circuit layer includes a second sensing circuit. At least one of the electrodes 672 and at least one of the signal lines are the second common electrode and are electrically separated from the power line 673. The second conductive structure 550.1 penetrates the second flat layer 630.1 and is connected to the driving circuit structure of the pixel unit layer. Between the second circuit layer 620.1 and the second conductive structure 550.1, the driving circuit structure of the pixel unit layer and the signal line in the second circuit layer are further connected. The first common electrode (including the first sensing electrode 671) and the second common electrode (including the second sensing electrode 672) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖8為本申請第七實施例之一具感測之顯示面板之剖面示意圖。請參照圖8，顯示面板700包括底承載板710、第一線路層720、第一平坦層730、第二線路層720.1、第二平坦層730.1、畫素單元層740、第一傳導結構750以及第二傳導結構750.1，其中底承載板710、第一線路層720、第一平坦層730、第二線路層720.1、第二平坦層730.1、畫素單元層740、第一傳導結構750、第二傳導結構750.1所構成的結構可以稱為畫素陣列結構。第一線路層720配置於底承載板710上。第一平坦層730覆蓋第一線路層720，第二線路層720.1配置於第一平坦層730上，第二平坦層730.1覆蓋第二線路層720.1，且第二平坦層730.1之遠離第二線路層720.1的一側具有一平坦面732。畫素單元層740配置於第二平坦層730.1的平坦面732上且畫素單元層740包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極。第一傳導結構750貫穿第一平坦層730、第二線路層720.1及第二平坦層730.1並且連接於畫素單元層的驅動電路結構與第一線路層720 之間，第一傳導結構750更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線770，另外，第一線路層中更包括第一感測電極771及電源線773，其中閘極線770、電源線773與第一感測電極771電性上分離。顯示介質層(未繪示)配置於畫素單元層740上並連接畫素單元層。第二傳導結構750.1貫穿第二平坦層730.1並且連接於畫素單元層的驅動電路結構與第二線路層720.1之間，第二傳導結構750.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線780，另外，第二線路層中更包括第二感測電極772，其中第二感測電極772及訊號線780電性上分離。第一感測電極771與第二感測電極772兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 FIG. 8 is a schematic cross-sectional view of a sensing display panel according to a seventh embodiment of the present application. Referring to FIG. 8, the display panel 700 includes a bottom carrier board 710, a first circuit layer 720, a first flat layer 730, a second circuit layer 720.1, a second flat layer 730.1, a pixel unit layer 740, a first conductive structure 750, and The second conductive structure 750.1, wherein the bottom carrier plate 710, the first circuit layer 720, the first flat layer 730, the second circuit layer 720.1, the second flat layer 730.1, the pixel unit layer 740, the first conductive structure 750, and the second The structure formed by the conductive structure 750.1 may be referred to as a pixel array structure. The first circuit layer 720 is disposed on the bottom carrier plate 710. The first planar layer 730 covers the first circuit layer 720, the second circuit layer 720.1 is disposed on the first planar layer 730, the second planar layer 730.1 covers the second circuit layer 720.1, and the second planar layer 730.1 is far from the second circuit layer 720.1 has a flat surface 732 on one side. The pixel unit layer 740 is disposed on the flat surface 732 of the second flat layer 730.1, and the pixel unit layer 740 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 750 penetrates the first flat layer 730, the second wiring layer 720.1, and the second flat layer 730.1 and is connected to the driving circuit structure of the pixel unit layer and the first wiring layer 720. In between, the first conductive structure 750 is further connected to the driving circuit structure of the pixel unit layer and the gate line 770 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 771 and a power line. 773, wherein the gate line 770 and the power line 773 are electrically separated from the first sensing electrode 771. The display medium layer (not shown) is disposed on the pixel unit layer 740 and is connected to the pixel unit layer. The second conductive structure 750.1 penetrates the second flat layer 730.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 720.1. The second conductive structure 750.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal line 780 in the second circuit layer, and in addition, the second circuit layer further includes a second sensing electrode 772, wherein the second sensing electrode 772 and the signal line 780 are electrically separated. The first sensing electrode 771 and the second sensing electrode 772 face each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖9為本申請第八實施例之一具感測之顯示面板之剖面示意圖。請參照圖9，顯示面板800包括底承載板820、第一線路層820、第一平坦層830、第二線路層820.1、第二平坦層830.1、畫素單元層840、第一傳導結構850、第二傳導結構850.1，其中底承載板810、第一線路層820、第一平坦層830、第二線路層820.1、第二平坦層830.1、畫素單元層840、第一傳導結構850、第二傳導結構850.1所構成的結構可以稱為畫素陣列結構。第一線路層820配置於底承載板810上。第一平坦層830覆蓋第一線路層820，第二線路層820.1配置於第一平坦層830上，第二平坦層830.1覆蓋第二線路層820.1，且第二平坦層830.1之遠離第二線路層820.1的一側具有一平坦面832。畫素單元層840配置於第二平 坦層830.1的平坦面832上且畫素單元層840包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極。第一傳導結構850貫穿第一平坦層830、第二線路層820.1及第二平坦層830.1並且連接於畫素單元層的驅動電路結構與第一線路層820之間，第一傳導結構850更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線870，第一線路層更包括第一感測電極871及電源線，其中第一感測電極871之至少一及電源線之至少一為共同電極，並且與閘極線870電性上分離。另外，第二傳導結構850.1貫穿第二平坦層830.1並且連接於畫素單元層的驅動電路結構與第二線路層820.1之間，第二傳導結構850.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線880，第二線路層中更包括第二感測電極872與訊號線880電性上分離。共同電極(含第一感測電極871)與第二感測電極872兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 FIG. 9 is a schematic cross-sectional view of a sensing display panel according to an eighth embodiment of the present application. Referring to FIG. 9, the display panel 800 includes a bottom carrier board 820, a first circuit layer 820, a first flat layer 830, a second circuit layer 820.1, a second flat layer 830.1, a pixel unit layer 840, a first conductive structure 850, The second conductive structure 850.1 includes a bottom carrier plate 810, a first circuit layer 820, a first flat layer 830, a second circuit layer 820.1, a second flat layer 830.1, a pixel unit layer 840, a first conductive structure 850, and a second The structure formed by the conductive structure 850.1 may be referred to as a pixel array structure. The first circuit layer 820 is disposed on the bottom carrier plate 810. The first planar layer 830 covers the first circuit layer 820, the second circuit layer 820.1 is disposed on the first planar layer 830, the second planar layer 830.1 covers the second circuit layer 820.1, and the second planar layer 830.1 is far from the second circuit layer 820.1 has a flat surface 832 on one side. The pixel unit layer 840 is arranged on the second flat The Tan layer 830.1 is on a flat surface 832 and the pixel unit layer 840 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 850 penetrates the first flat layer 830, the second circuit layer 820.1, and the second flat layer 830.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 820. The first conductive structure 850 goes further The driving circuit structure connected to the pixel unit layer and the gate line 870 in the first circuit layer, the first circuit layer further includes a first sensing electrode 871 and a power line, wherein at least one of the first sensing electrode 871 and a power source At least one of the lines is a common electrode and is electrically separated from the gate line 870. In addition, the second conductive structure 850.1 penetrates the second flat layer 830.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 820.1. The second conductive structure 850.1 is further connected to the driving circuit structure of the pixel unit layer. It is electrically separated from the signal line 880 in the second circuit layer, and the second circuit layer further includes a second sensing electrode 872 and the signal line 880. The common electrode (including the first sensing electrode 871) and the second sensing electrode 872 are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖10為本申請第九實施例之一具感測之顯示面板之剖面示意圖。請參照圖10，顯示面板900包括底承載板910、第一線路層920、第一平坦層930、第二線路層920.1、第二平坦層930.1、畫素單元層940、第一傳導結構950以及第二傳導結構950.1，其中底承載板910、第一線路層920、第一平坦層930、第二線路層920.1、第二平坦層930.1、畫素單元層940、第一傳導結構950、第二傳導結構950.1所構成的結構可以稱為畫素陣列結構。第一線路層920配置於底承載板910上。第一平坦層930覆蓋第一線路 層920，第二線路層920.1配置於第一平坦層930上，第二平坦層930.1覆蓋第二線路層920.1，且第二平坦層930.1之遠離第二線路層920.1的一側具有一平坦面932。畫素單元層940配置於第二平坦層930.1的平坦面932上且畫素單元層940包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極。第一傳導結構950貫穿第一平坦層930、第二線路層920.1及第二平坦層930.1並且連接於畫素單元層的驅動電路結構與第一線路層920之間，第一傳導結構950更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線970，另外，第一線路層中更包括第一感測電極971及電源線973，其中閘極線970、電源線973與第一感測電極971電性上分離。顯示介質層(未繪示)配置於畫素單元層940上並連接畫素單元層。第二傳導結構950.1貫穿第二平坦層930.1並且連接於畫素單元層的驅動電路結構與第二線路層920.1之間，第二傳導結構950.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線，另外，第二線路層中更包括第二感測電極972，其中第二感測電極972之至少一及訊號線之至少一為共同電極。第一感測電極971與共同電極(含第二感測電極972)兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 FIG. 10 is a schematic cross-sectional view of a sensing display panel according to a ninth embodiment of the present application. 10, the display panel 900 includes a bottom carrier board 910, a first circuit layer 920, a first planar layer 930, a second circuit layer 920.1, a second planar layer 930.1, a pixel unit layer 940, a first conductive structure 950, and The second conductive structure 950.1, wherein the bottom carrier plate 910, the first circuit layer 920, the first flat layer 930, the second circuit layer 920.1, the second flat layer 930.1, the pixel unit layer 940, the first conductive structure 950, and the second The structure formed by the conductive structure 950.1 can be referred to as a pixel array structure. The first circuit layer 920 is disposed on the bottom carrier board 910. The first flat layer 930 covers the first circuit Layer 920, the second circuit layer 920.1 is disposed on the first planar layer 930, the second planar layer 930.1 covers the second circuit layer 920.1, and a side of the second planar layer 930.1 away from the second circuit layer 920.1 has a planar surface 932 . The pixel unit layer 940 is disposed on the flat surface 932 of the second flat layer 930.1, and the pixel unit layer 940 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 950 penetrates the first flat layer 930, the second circuit layer 920.1, and the second flat layer 930.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 920. The first conductive structure 950 goes further. The driving circuit structure connected to the pixel unit layer and the gate line 970 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 971 and a power line 973, among which the gate line 970 and the power line 973 is electrically separated from the first sensing electrode 971. The display medium layer (not shown) is disposed on the pixel unit layer 940 and is connected to the pixel unit layer. The second conductive structure 950.1 penetrates the second flat layer 930.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 920.1. The second conductive structure 950.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer 920.1. The signal lines in the two circuit layers. In addition, the second circuit layer further includes a second sensing electrode 972. At least one of the second sensing electrodes 972 and at least one of the signal lines are common electrodes. The first sensing electrode 971 and the common electrode (including the second sensing electrode 972) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
圖11為本申請第十實施例之一具感測之顯示面板之剖面示意圖。請參照圖11，顯示面板1000包括底承載板1020、第一線路層1020、第一平坦層1030、第二線路層1020.1、第二平坦層1030.1、畫素單元層1040、第一傳導結構1050、第二傳導結構 1050.1，其中底承載板1010、第一線路層1020、第一平坦層1030、第二線路層1020.1、第二平坦層1030.1、畫素單元層1040、第一傳導結構1050、第二傳導結構1050.1所構成的結構可以稱為畫素陣列結構。第一線路層1020配置於底承載板1010上。第一平坦層1030覆蓋第一線路層1020，第二線路層1020.1配置於第一平坦層1030上，第二平坦層1030.1覆蓋第二線路層1020.1，且第二平坦層1030.1之遠離第二線路層1020.1的一側具有一平坦面1032。畫素單元層1040配置於第二平坦層1030.1的平坦面1032上且畫素單元層1040包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極。第一傳導結構1050貫穿第一平坦層1030、第二線路層1020.1及第二平坦層1030.1並且連接於畫素單元層的驅動電路結構與第一線路層1020之間，第一傳導結構1050更進一步連接於畫素單元層的驅動電路結構與第一線路層中的閘極線1070，第一線路層更包括第一感測電極1071及電源線，其中第一感測電極1071之至少一及電源線之至少一為第一共同電極，並且與閘極線1070電性上分離。另外，第二傳導結構1050.1貫穿第二平坦層1030.1並且連接於畫素單元層的驅動電路結構與第二線路層1020之間，第二傳導結構1050.1更進一步連接於畫素單元層的驅動電路結構與第二線路層中的訊號線，第二線路層更包括第二感測電極1072，第二感測電極1072之至少一與訊號線之至少一為第二共同電極。第一共同電極(含第一感測電極1071)與第二共同電極(含第二感測電極1072)兩兩相對以產生一電 容C，並透過該電容C的變化產生感應訊號。 FIG. 11 is a schematic cross-sectional view of a display panel with sensing according to a tenth embodiment of the present application. Referring to FIG. 11, the display panel 1000 includes a bottom carrier board 1020, a first circuit layer 1020, a first flat layer 1030, a second circuit layer 1020.1, a second flat layer 1030.1, a pixel unit layer 1040, a first conductive structure 1050, Second conductive structure 1050.1, including the bottom carrier board 1010, the first circuit layer 1020, the first flat layer 1030, the second circuit layer 1020.1, the second flat layer 1030.1, the pixel unit layer 1040, the first conductive structure 1050, and the second conductive structure 1050.1 The structure formed may be referred to as a pixel array structure. The first circuit layer 1020 is disposed on the bottom carrier board 1010. The first planar layer 1030 covers the first circuit layer 1020, the second circuit layer 1020.1 is disposed on the first planar layer 1030, the second planar layer 1030.1 covers the second circuit layer 1020.1, and the second planar layer 1030.1 is far from the second circuit layer 1020.1 has a flat surface 1032 on one side. The pixel unit layer 1040 is disposed on the flat surface 1032 of the second flat layer 1030.1, and the pixel unit layer 1040 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 1050 penetrates the first planar layer 1030, the second circuit layer 1020.1, and the second planar layer 1030.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 1020. The first conductive structure 1050 goes further. The driving circuit structure connected to the pixel unit layer and the gate line 1070 in the first circuit layer. The first circuit layer further includes a first sensing electrode 1071 and a power line, wherein at least one of the first sensing electrode 1071 and a power source. At least one of the lines is a first common electrode, and is electrically separated from the gate line 1070. In addition, the second conductive structure 1050.1 penetrates the second flat layer 1030.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 1020. The second conductive structure 1050.1 is further connected to the driving circuit structure of the pixel unit layer. And the signal line in the second circuit layer, the second circuit layer further includes a second sensing electrode 1072, at least one of the second sensing electrode 1072 and at least one of the signal lines are a second common electrode. The first common electrode (including the first sensing electrode 1071) and the second common electrode (including the second sensing electrode 1072) are opposed to each other to generate an electricity The capacitance C is generated by a change in the capacitance C.
上述本申請的實施例中，第一線路層或第二線路層都可能包含複數條訊號線、電源線、閘極線、第一感測電極以及第二感測電極，若當顯示面板的承載板做為面板周邊線路的延伸電路區時，上述複數的訊號線、電源線、閘極線、第一感測電極或是第二感測電極，都必須在面板周邊區往外輸送訊號或是送入訊號，在本申請之第十一實施例中，同時參照圖12，其面板顯示區的結構參照圖2及圖3，在此不贅述，在面板周邊線路區須增加一第三傳導結構1151、一第四傳導結構1152及一第五傳導結構1153，分別向下貫穿第一平坦層1130將第二線路層1120.1之電源線1173、第二感測電極1172及訊號線1180的線路分別傳導至面板周邊區域的第一線路層上1120。 In the above embodiments of the present application, the first circuit layer or the second circuit layer may include a plurality of signal lines, power lines, gate lines, first sensing electrodes, and second sensing electrodes. When the board is used as the extended circuit area of the peripheral circuit of the panel, the above-mentioned plural signal lines, power lines, gate lines, first sensing electrodes or second sensing electrodes must all transmit signals or send signals outside the peripheral area of the panel. For the input signal, in the eleventh embodiment of the present application, referring to FIG. 12 at the same time, the structure of the panel display area is shown in FIG. 2 and FIG. 3, which will not be repeated here. A fourth conductive structure 1152 and a fifth conductive structure 1153 respectively penetrate the first flat layer 1130 downward to conduct the lines of the power line 1173, the second sensing electrode 1172, and the signal line 1180 of the second circuit layer 1120.1 to 1120 on the first circuit layer in the peripheral area of the panel.
在本申請之第十二實施例中，同時參照圖13，其面板顯示區的結構參照圖4及圖5，在此不贅述，在面板周邊線路區增加一第三傳導結構1251及一第四傳導結構1252，分別向下貫穿第一平坦層1230將第二線路層1220.1之電源線之至少一與第二感測電極1272之至少一之共同電極與訊號線1280的線路分別傳導至面板周邊區域的第一線路層1220上。 In the twelfth embodiment of the present application, referring to FIG. 13 at the same time, the structure of the panel display area is shown in FIG. 4 and FIG. 5, which will not be repeated here. A third conductive structure 1251 and a fourth are added to the peripheral circuit area of the panel. The conductive structure 1252 penetrates the first flat layer 1230 downwardly, respectively, and conducts at least one common electrode of the second circuit layer 1220.1 and at least one common electrode of the second sensing electrode 1272 and the signal line 1280 to the panel peripheral area, respectively. On the first circuit layer 1220.
在本申請之第十三實施例中，同時參照圖14，其面板顯示區的結構參照圖6及圖7，在此不贅述，在周邊線路區增加一第三傳導結構1351及一第四傳導結構1352，分別向下貫穿第一平坦層1330將第二線路層1320.1之訊號線之至少一與第二感測電極 1372之至少一之共同電極與電源線1373的線路分別傳導至面板周邊區域的第一線路層1320上。 In the thirteenth embodiment of the present application, referring to FIG. 14 at the same time, the structure of the panel display area is referred to FIG. 6 and FIG. 7, which are not described in detail here. A third conductive structure 1351 and a fourth conductive are added to the peripheral circuit area. Structure 1352, penetrating through the first flat layer 1330 and at least one of the signal lines of the second circuit layer 1320.1 and the second sensing electrode, respectively. At least one of the common electrodes of 1372 and the lines of the power line 1373 are respectively conducted to the first circuit layer 1320 in the peripheral area of the panel.
在本申請之第十四實施例中，同時參照圖15，其面板顯示區的結構參照圖8及圖9，在此不贅述，在面板周邊線路區增加一第三傳導結1451構及一第四傳導結構1452，分別向下貫穿第一平坦層1430將第二線路層1420.1之訊號線1480與第二感測電極1472的線路分別傳導至面板周邊區域的第一線路層1420上。 In the fourteenth embodiment of the present application, referring to FIG. 15 at the same time, the structure of the panel display area is shown in FIG. 8 and FIG. 9, which will not be repeated here. A third conductive junction 1451 structure and a first The four conductive structures 1452 penetrate the first flat layer 1430 downwardly and respectively conduct the signal lines 1480 of the second circuit layer 1420.1 and the lines of the second sensing electrode 1472 to the first circuit layer 1420 in the peripheral area of the panel.
在本申請之第十五實施例中，同時參照圖16，其面板顯示區的結構參照圖10及圖11，在此不贅述，在面板周邊線路區增加一第三傳導結構1551，向下貫穿第一平坦層1530將第二線路層1520.1之訊號線之至少一及第二感測電極1572之至少一之共同電極的線路傳導至面板周邊區域的第一線路層1520上。 In the fifteenth embodiment of the present application, referring to FIG. 16 at the same time, the structure of the panel display area is shown in FIG. 10 and FIG. 11, which will not be described in detail here. A third conductive structure 1551 is added to the peripheral circuit area of the panel and penetrates downward. The first flat layer 1530 conducts lines of the common electrode of at least one of the signal lines of the second circuit layer 1520.1 and at least one of the second sensing electrodes 1572 to the first circuit layer 1520 in the peripheral area of the panel.
在本申請之第十六實施例中，同時參照圖17，其面板顯示區的結構參照圖3、圖5及圖7，在此不贅述，在面板周邊線路區增加一第三傳導結構1651，向上貫穿第一平坦層1630將第一線路層1620中閘極線之至少一及第一感測電極1671之至少一之共同電極的線路傳導至面板周邊區域的第二線路層1620.1上。 In the sixteenth embodiment of the present application, referring to FIG. 17 at the same time, the structure of the panel display area is referred to FIG. 3, FIG. 5, and FIG. 7, which is not repeated here, and a third conductive structure 1651 is added to the peripheral circuit area of the panel. Through the first flat layer 1630 upward, the lines of the common electrode of at least one of the gate lines and at least one of the first sensing electrodes 1671 in the first circuit layer 1620 are conducted to the second circuit layer 1620.1 in the peripheral area of the panel.
在本申請之第十七實施例中，同時參照圖18，其面板顯示區的結構參照圖2、圖4及圖6，在此不贅述，在面板周邊線路區增加一第三傳導結構1751及一第四傳導結構1752，分別向上貫穿第一平坦層1730將第一線路層1720之閘極線1770與第一感測電極1171的線路分別傳導至面板周邊區域的第二線路層1720.1 上。 In the seventeenth embodiment of the present application, referring to FIG. 18 at the same time, the structure of the panel display area is shown in FIG. 2, FIG. 4, and FIG. 6, and details are not described herein. A third conductive structure 1751 and A fourth conductive structure 1752 penetrates the first flat layer 1730 upward to conduct the gate lines 1770 of the first circuit layer 1720 and the lines of the first sensing electrode 1171 to the second circuit layer 1720.1 in the peripheral area of the panel, respectively. on.
在本申請之第十八實施例中，同時參照圖19，其面板顯示區的結構參照圖9及圖11，在此不贅述，在面板周邊線路區須增加一第三傳導結構1851及一第四傳導結構1852，分別向上貫穿第一平坦層1830將第一線路層1820之電源線之至少一與第一感測電極1871之至少一之共同電極與閘極線1870的線路分別傳導至面板周邊區域的第二線路層1820.1上。 In the eighteenth embodiment of the present application, referring to FIG. 19 at the same time, the structure of the panel display area is referred to FIG. 9 and FIG. 11, which will not be repeated here. A four-conducting structure 1852 penetrates the first flat layer 1830 upwards and conducts at least one common line of the first wiring layer 1820 and at least one common electrode of the first sensing electrode 1871 and the gate line 1870 to the panel periphery respectively. Area on the second circuit layer 1820.1.
在本申請之第十九實施例中，同時參照圖20，其面板顯示區的結構參照圖8及圖10，在此不贅述，在面板周邊線路區增加一第三傳導結構1951、一第四傳導結構1952及一第五傳導結構1953，分別貫穿第一平坦層1930將第一線路層1920之閘極線1970、第一感測電極1971及電源線1973的線路分別傳導至面板周邊區域的第二線路層1920.1上。 In the nineteenth embodiment of the present application, referring to FIG. 20 at the same time, the structure of the panel display area is shown in FIG. 8 and FIG. 10, which will not be repeated here. A third conductive structure 1951, a fourth is added to the peripheral circuit area of the panel. The conductive structure 1952 and a fifth conductive structure 1953 penetrate the first flat layer 1930 to conduct the lines of the gate line 1970, the first sensing electrode 1971, and the power line 1973 of the first circuit layer 1920 to the first of the peripheral regions of the panel, respectively. The second line layer is on 1920.1.
圖21為本申請第二十實施例之一具感測之顯示面板之剖面示意圖。請參照圖21，顯示面板2000包括底承載板2010、第一線路層2020、第一平坦層2030、第二線路層2020.1、第二平坦層2030.1、畫素單元層2040、第一傳導結構2050、第二傳導結構2050.1，其中底承載板2010、第一線路層2020、第一平坦層2030、第二線路層2020.1、第二平坦層2030.1、畫素單元層2040、第一傳導結構2050、第二傳導結構2050.1所構成的結構可以稱為畫素陣列結構2002。第一線路層2020配置於底承載板2010上。第一平坦層2030覆蓋第一線路層2020，第二線路層2020.1配置於第 一平坦層2030上，第二平坦層2030.1覆蓋第二線路層2020.1，且第二平坦層2030.1之遠離第二線路層2020.1的一側具有一平坦面2032。畫素單元層2040配置於第二平坦層2030.1的平坦面2032上且畫素單元層2040包括畫素單元。畫素單元包括電性連接畫素單元層的驅動電路結構的畫素電極、閘極線2070、電源線2073及訊號線2080。第一傳導結構2050貫穿第一平坦層2030、第二線路層2020.1及第二平坦層2030.1並且連接於畫素單元層的驅動電路結構與第一線路層2020之間，第一傳導結構2050更進一步連接於畫素單元層的驅動電路結構第一線路層中的第一感測電極2071，另外，第二線路層包括第二感測電極2072。第一感測電極2071與第二感測電極2072兩兩相對以產生一電容C，並透過該電容C的變化產生感應訊號。 FIG. 21 is a schematic cross-sectional view of a sensing display panel according to a twentieth embodiment of the present application. Referring to FIG. 21, the display panel 2000 includes a bottom carrier board 2010, a first circuit layer 2020, a first flat layer 2030, a second circuit layer 202.1, a second flat layer 2030.1, a pixel unit layer 2040, a first conductive structure 2050, The second conductive structure 2050.1, wherein the bottom carrier board 2010, the first circuit layer 2020, the first flat layer 2030, the second circuit layer 202.1, the second flat layer 2030.1, the pixel unit layer 2040, the first conductive structure 2050, and the second The structure formed by the conductive structure 2050.1 may be referred to as a pixel array structure 2002. The first circuit layer 2020 is disposed on the bottom carrier board 2010. The first flat layer 2030 covers the first circuit layer 2020, and the second circuit layer 2020.1 is disposed at the first On a flat layer 2030, the second flat layer 2030.1 covers the second circuit layer 2020.1, and a side of the second flat layer 2030.1 far from the second circuit layer 2020.1 has a flat surface 2032. The pixel unit layer 2040 is disposed on the flat surface 2032 of the second flat layer 2030.1, and the pixel unit layer 2040 includes a pixel unit. The pixel unit includes a pixel electrode, a gate line 2070, a power line 2073, and a signal line 2080 electrically connected to a driving circuit structure of the pixel unit layer. The first conductive structure 2050 penetrates the first planar layer 2030, the second circuit layer 2020.1, and the second planar layer 2030.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 2020. The first conductive structure 2050 goes one step further. The driving circuit structure connected to the pixel unit layer has a first sensing electrode 2071 in a first wiring layer, and the second wiring layer includes a second sensing electrode 2072. The first sensing electrode 2071 and the second sensing electrode 2072 are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.
在上述揭露的第二十實施例中，第一線路層或第二線路層都包含複數條第一感測電極以及第二感測電極，若當具感測之顯示面板的承載板做為面板周邊線路的延伸電路區時，上述複數的第一感測電極或是第二感測電極，都必須在面板周邊區往外輸送感應訊號，在面板周邊線路區增加一第三傳導結構2051，向下或向上貫穿第一平坦層，使的第一感測電極訊號往上至第二線路層中，或是第二感測電極訊號往下至第一線路層中。 In the twentieth embodiment disclosed above, either the first circuit layer or the second circuit layer includes a plurality of first sensing electrodes and a second sensing electrode, and if the carrier board with the sensing display panel is used as the panel When extending the circuit area of the peripheral circuit, the above-mentioned plurality of first sensing electrodes or second sensing electrodes must transmit the sensing signal outward in the peripheral area of the panel, and a third conductive structure 2051 is added in the peripheral area of the panel, downward. Or the first flat layer is penetrated upward, so that the signal of the first sensing electrode goes up to the second circuit layer, or the signal of the second sensing electrode goes down to the first circuit layer.
綜上所述，本申請實施例的具感測之顯示面板及具感測之顯示畫素陣列結構將畫素單元中的驅動電路結構、感應電路結構與傳遞訊號的線路可分開設置於不同層位中，一方面可以增加 畫素單元中驅動電路結構的布局面積並使得驅動電路結構的布局更富有彈性，另一方面更可以在顯示面板中增加感應的功能。因此，根據本申請實施例設計，顯示面板具有更多功能的設計空間。 In summary, the sensing display panel and the sensing pixel array structure of the embodiment of the present application can separate the driving circuit structure, the sensing circuit structure and the signal transmission line in the pixel unit in different layers. Bit, on the one hand can increase The layout area of the driving circuit structure in the pixel unit makes the layout of the driving circuit structure more flexible. On the other hand, the sensing function can be added to the display panel. Therefore, according to the design of the embodiment of the present application, the display panel has a design space with more functions.
雖然本申請已以實施例揭露如上，然其並非用以限定本申請，任何所屬技術領域中具有通常知識者，在不脫離本申請的精神和範圍內，當可作些許的更動與潤飾，故本申請的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present application has been disclosed as above by way of example, it is not intended to limit the present application. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present application. The scope of protection of this application shall be determined by the scope of the attached patent application.
110‧‧‧底承載板 110‧‧‧Bottom load plate
120‧‧‧第一線路層 120‧‧‧First circuit layer
130‧‧‧第一平坦層 130‧‧‧ the first flat layer
120.1‧‧‧第二線路層 120.1‧‧‧Second circuit layer
130.1‧‧‧第二平坦面 130.1‧‧‧ second flat surface
132‧‧‧平坦面 132‧‧‧ flat surface
140‧‧‧畫素單元層 140‧‧‧ pixel unit layer
160‧‧‧顯示介質層 160‧‧‧Display media layer
150‧‧‧第一傳導結構 150‧‧‧first conductive structure
150.1‧‧‧第二傳導結構 150.1‧‧‧Second conductive structure
170‧‧‧閘極線 170‧‧‧Gate line
171‧‧‧第一感測電極 171‧‧‧first sensing electrode
172‧‧‧第二感測電極 172‧‧‧Second sensing electrode
173‧‧‧電源線 173‧‧‧Power cord
180‧‧‧訊號線 180‧‧‧ signal line
Claims (20)
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| CN201611236068.5A CN108206197A (en) | 2016-12-20 | 2016-12-28 | display pixel array structure with sensing function |
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| US20100149117A1 (en) * | 2008-12-11 | 2010-06-17 | Au Optronics Corporation | Color filter touch sensing substrate and display panel and manufacturing methods of the same |
| TW201303659A (en) * | 2011-07-07 | 2013-01-16 | Wintek Corp | Touch-sensitive display panel |
| TW201643642A (en) * | 2015-06-05 | 2016-12-16 | 群創光電股份有限公司 | Display device |
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| CN103713792B (en) * | 2013-12-23 | 2016-06-01 | 京东方科技集团股份有限公司 | Array substrate and manufacture method thereof and touch display unit |
| CN104536636B (en) * | 2015-01-27 | 2017-12-08 | 京东方科技集团股份有限公司 | A kind of preparation method of array base palte, contact panel and array base palte |
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| CN105932029A (en) * | 2016-06-08 | 2016-09-07 | 京东方科技集团股份有限公司 | Array substrate, production method thereof, touch display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100149117A1 (en) * | 2008-12-11 | 2010-06-17 | Au Optronics Corporation | Color filter touch sensing substrate and display panel and manufacturing methods of the same |
| TW201303659A (en) * | 2011-07-07 | 2013-01-16 | Wintek Corp | Touch-sensitive display panel |
| TW201643642A (en) * | 2015-06-05 | 2016-12-16 | 群創光電股份有限公司 | Display device |
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