TWI613493B - Sensing and pixel array structure on display panel - Google Patents

Sensing and pixel array structure on display panel Download PDF

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Publication number
TWI613493B
TWI613493B TW105142124A TW105142124A TWI613493B TW I613493 B TWI613493 B TW I613493B TW 105142124 A TW105142124 A TW 105142124A TW 105142124 A TW105142124 A TW 105142124A TW I613493 B TWI613493 B TW I613493B
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Taiwan
Prior art keywords
layer
circuit
sensing
circuit layer
flat
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TW105142124A
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Chinese (zh)
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TW201823825A (en
Inventor
鍾育華
張志嘉
張祖強
張凱銘
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財團法人工業技術研究院
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Priority to TW105142124A priority Critical patent/TWI613493B/en
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Publication of TW201823825A publication Critical patent/TW201823825A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3225OLED integrated with another component
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/326Active matrix displays special geometry or disposition of pixel-elements

Abstract

A sensing pixel array structure includes a bottom carrier plate and a first line The circuit layer, the first flat layer, the second circuit layer, the second flat layer, the first conductive structure, the second conductive structure, and the pixel unit layer. The first circuit layer is disposed on the bottom carrier board. The first flat layer covers the first circuit layer, and a side of the second flat layer remote from the second circuit layer has a flat surface. The pixel unit layer is disposed on a flat surface of the second flat layer, and the pixel unit layer includes a pixel unit. The pixel unit includes at least a driving circuit. The first and second conductive structures penetrate the first flat layer, the second wiring layer, and the second flat layer and are connected between the pixel unit layer structure and the first and second wiring layers. The first circuit layer includes a first sensing electrode, and the second circuit layer includes a second sensing electrode.

Description

Pixel array structure with display

The present application relates to a sensing pixel array structure.

Flat display panels have become the mainstream of current display products. With the increase and improvement of various requirements, such as the improvement in display resolution or image quality, the driving circuit structure of each pixel unit in the flat display panel may become complicated. For example, if an organic light-emitting material is used as a display medium, the driving circuit structure of each pixel unit may include more than one transistor and one or more capacitor structures, or the circuits in the existing panel may be combined with other functions. , Will add other circuit designs on the panel. In addition, the flat display panel itself needs to be provided with various signal lines, such as scanning lines, data lines, power lines, or other lines. In this way, various circuits, active components, capacitor structures, or other components required for functions need to be provided in a limited area, which limits the layout design of the driving circuit structure.

The present application provides a sensing pixel array structure, which helps to improve the layout flexibility of the driving circuit structure.

The present application provides a display pixel array structure with sensing. The circuit of the signal line and the sensing circuit structure are made at different levels to increase the layout area of the display panel circuit structure.

An embodiment of the present application provides a display pixel array structure with sensing, which includes a picture display area and a peripheral circuit area. The peripheral circuit area is located outside the picture display area. The picture display area includes a bottom carrier board, a The first circuit layer, a first planar layer, a second circuit layer, a second planar layer, a pixel unit layer, a first conductive structure, a second conductive structure, and a third conductive structure. The circuit layer is arranged on the bottom carrier board. The first planar layer covers the first circuit layer, the second circuit layer is disposed on the first planar layer, the second planar layer covers the second circuit layer, and the second planar layer is far from the second circuit layer. One side has a flat surface. The pixel unit layer is disposed on a flat surface of the flat layer, and the pixel unit layer includes a pixel unit. The first conductive structure is disposed in the screen display area, penetrates the second flat layer, the second wiring layer and the first flat layer and is connected between the pixel unit layer and the first wiring layer. The second conductive structure, It is arranged in the screen display area, penetrates the second flat layer and is connected between the pixel unit layer and the second circuit layer. The peripheral circuit area includes a third conductive structure, which is disposed in the peripheral circuit area, penetrates the first flat layer and is connected between the first circuit layer and the second circuit layer.

According to an embodiment of the present application, the sensing display pixel array node In the structure, the first circuit layer includes a first sensing electrode, and the second circuit layer includes a second sensing electrode.

According to an embodiment of the present application, a material of the first flat layer and the second flat layer includes an organic insulating material, an inorganic insulating material, or a combination thereof.

According to an embodiment of the present application, the organic insulating material includes polyimide, an organic photoresist material, or a combination thereof.

According to an embodiment of the present application, the inorganic insulating material includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

According to an embodiment of the present application, the display panel with sensing includes the above-mentioned display pixel array structure with sensing and a display medium layer, wherein the display medium layer is disposed on the pixel unit layer and connected to the pixel unit layer. .

In order to make the above features and advantages of this application more comprehensible, embodiments are described below in detail with the accompanying drawings as follows.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 2000‧‧‧ display panels

110, 210, 310, 410, 510, 610, 710, 810, 910, 1010, 2010‧‧‧ bottom load plate

120, 220, 320, 420, 520, 620, 720, 820, 920, 1020, 1120, 1220, 1320, 1420, 1520, 1620, 1720, 1820, 1920, 2020

120.1, 220.1, 320.1, 420.1, 520.1, 620.1, 720.1, 820.1, 920.1, 1020.1, 1120.1, 1220.1, 1320.1, 1420.1, 1520.1, 1620.1, 1720.1, 1820.1, 1920.1, 2020.1‧‧‧ Second circuit layer

130, 230, 330, 330, 430, 530, 630, 730, 830, 930, 1030, 1130, 1230, 1330, 1420, 1520, 1620, 1720, 1820, 1920, 2020 First flat layer

130.1, 230.1, 330.1, 430.1, 530.1, 630.1., 730.1, 830.1, 930.1, 1030.1, 1130.1, 2030.1‧‧‧ Second flat layer

132, 232, 332, 332, 432, 532, 632, 732, 832, 932, 1032, 2032‧‧‧ flat surface

140, 240, 340, 440, 540, 640, 740, 840, 940, 1040, 2040‧‧‧ pixel unit layer

150, 250, 350, 450, 550, 650, 750, 850, 950, 1050, 2050‧‧‧ first conductive structure

150.1, 250.1, 350.1, 450.1, 550.1, 650.1, 750.1, 850.1, 950.1, 1050.1, 205.1

160‧‧‧Display media layer

170, 370, 570, 770, 870, 970, 1070, 1770, 1870, 1970, 2070

171, 271, 371, 471, 571, 671, 771, 871, 971, 1071, 1171, 1371, 1371, 1471, 1671, 1671, 1771, 1771, 1871, 1971, 2071

172, 272, 372, 472, 572, 672, 772, 872, 972, 1072, 1172, 1272, 1372, 1472, 1572, 1672, 1772, 1872, 1972, 2072

173, 273, 573, 673, 973, 1173, 1373, 1973, 2073‧‧‧ power cord

180, 280, 380, 480, 780, 880, 1280, 1480, 2080‧‧‧ signal lines

1151, 1251, 1351, 1451, 1551, 1651, 1751, 1851, 1951, 2051‧‧‧ third conductive structure

1152, 1252, 1352, 1452, 1752, 1852, 1952 ‧‧‧ fourth conductive structure

1153, 1953‧‧‧ fifth conductive structure

I-I’‧‧‧ hatched

FIG. 1 is a schematic partial top view of a display panel with sensing according to a first embodiment of the present application.

FIG. 2 is a schematic cross-sectional view of a sensing display panel according to a first embodiment of the present application.

3 is a schematic cross-sectional view of a display panel with sensing according to a second embodiment of the present application.

4 is a schematic cross-sectional view of a sensing display panel according to a third embodiment of the present application.

FIG. 5 is a schematic cross-sectional view of a display panel with sensing according to a fourth embodiment of the present application.

FIG. 6 is a schematic cross-sectional view of a display panel with sensing according to a fifth embodiment of the present application.

FIG. 7 is a schematic cross-sectional view of a display panel with sensing according to a sixth embodiment of the present application.

FIG. 8 is a schematic cross-sectional view of a sensing display panel according to a seventh embodiment of the present application.

FIG. 9 is a schematic cross-sectional view of a sensing display panel according to an eighth embodiment of the present application.

FIG. 10 is a schematic cross-sectional view of a sensing display panel according to a ninth embodiment of the present application.

FIG. 11 is a schematic cross-sectional view of a display panel with sensing according to a tenth embodiment of the present application.

FIG. 12 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to an eleventh embodiment of the present application.

13 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a twelfth embodiment of the present application.

14 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a thirteenth embodiment of the present application.

15 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a fourteenth embodiment of the present application.

16 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a fifteenth embodiment of the present application.

17 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a sixteenth embodiment of the present application.

18 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a seventeenth embodiment of the present application.

19 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to an eighteenth embodiment of the present application.

20 is a schematic cross-sectional view of a peripheral circuit of a display panel with sensing according to a nineteenth embodiment of the present application.

FIG. 21 is a schematic cross-sectional view of a sensing display panel according to a twentieth embodiment of the present application.

In order to drive a display panel or a sensing signal, more than one signal needs to be provided, such as a plurality of scanning signals, a plurality of data signals, a plurality of power signals, or other plurality of sensing signals. A certain percentage of the area is estimated in the display panel, or a structure that adds a sensing function to the panel. In the description of the embodiment of the present application, at least one of the above circuits may be respectively disposed in the first circuit layer or the second circuit layer, and may be the first flat layer or the first layer. Two flat layers separate the first circuit layer from the second circuit layer or between the second circuit layer and the pixel unit layer, so that the first circuit layer, the second circuit layer, and the pixel unit layer are vertically separated from each other ( (Located in different layers). In addition, the pixel unit layer includes a plurality of pixel units, and the pixel units are arranged in an array. A single pixel unit includes a driving circuit structure and a pixel electrode connected to the driving circuit structure. The driving circuit structure includes at least a first active element and a second active element. In this way, on the one hand, the driving circuit structure of a single pixel unit in the pixel unit layer can have an increased layout area, which can improve the design flexibility of the driving circuit structure, and on the other hand, the first circuit layer and the second circuit layer can be used. The opposite sensing electrodes in the circuit layer generate capacitance to form a sensing signal.

FIG. 1 is a schematic partial top view of a sensing display panel according to a first embodiment of the first embodiment of the present application. Some components of the display panel with sensing are omitted in FIG. 1, and only some components of the display panel 100 are shown, including a plurality of signal lines, a plurality of gate lines, a plurality of power lines, and a plurality of first sensing electrodes, The second sensing electrode, the first conductive structure, and the second conductive structure. In other words, the plurality of signal lines, the plurality of gate lines, the plurality of power lines, and the plurality of first sensing electrodes and the plurality of second sensing electrodes are overlapped under the pixel unit layer in different layers. In the embodiments described later in this application, the plurality of signal lines, the plurality of gate lines, the plurality of power lines, and the plurality of first sensing electrodes and the plurality of second sensing electrodes are briefly described as signal lines, gate lines, The power line, the first sensing electrode and the second sensing electrode.

FIG. 2 is a schematic cross-sectional view of a sensing display panel according to a first embodiment of the present application. Please refer to the section line I-I 'of FIG. 1 and FIG. 2. In FIG. 2, the display panel 100 includes a bottom carrier board 110, a first circuit layer 120, a first flat layer 130, and a second circuit layer. 120.1, the second flat layer 130.1, the pixel unit layer 140, the first conductive structure 150, the second conductive structure 150.1, and the display medium layer 160, wherein the bottom carrier board 110, the first wiring layer 120, the first flat layer 130, the first The structure composed of the two circuit layers 120.1, the second flat layer 130.1, the pixel unit layer 140, the first conductive structure 150, and the second conductive structure 150.1 may be referred to as a pixel array structure. The first circuit layer 120 is disposed on the bottom carrier board 110. The first planar layer 130 covers the first circuit layer 120, the second circuit layer 120.1 is disposed on the first planar layer 130, the second planar layer 130.1 covers the second circuit layer 120.1, and the second planar layer 130.1 is far from the second circuit layer 120.1 has a flat surface 132 on one side. The pixel unit layer 140 is disposed on the flat surface 132 of the second flat layer 130.1, and the pixel unit layer 140 includes a pixel unit. The pixel unit includes a pixel electrode electrically connected to the driving circuit structure. The first conductive structure 150 penetrates the first flat layer 130, the second circuit layer 120.1, and the second flat layer 130.1 and is connected between the driving circuit structure and the first circuit layer 120. The first conductive structure 150 is further connected to the pixel unit. The driving circuit structure of the layer and the gate line 170 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 171, wherein the gate line 170 is electrically separated from the first sensing electrode 171. The display medium layer 160 is disposed on the pixel unit layer 140 and is connected to the pixel unit layer. The second conductive structure 150.1 penetrates the second flat layer 130.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 120.1. The second conductive structure 150.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal line 180 in the second circuit layer. In addition, the second circuit layer further includes a second sensing electrode 172 and a power line 173, wherein the signal line 180 is electrically separated from the second sensing electrode 172 and the power line 173. First sensing electrode 171 and second sensing electrode 172 Opposite each other to generate a capacitor C, and generate a sensing signal through the change of the capacitor C. The signal line 180 in the first circuit layer 120 is electrically connected to the pixel unit layer 130 and passes through the first conductive structure 150. In this way, the pixel unit layer 130 can receive the signal provided by the signal line 180 to drive the display medium layer 160. In this embodiment, the material of the display medium layer 160 includes an organic light emitting material, but other materials such as a liquid crystal material, an electrophoretic display material, and a light emitting semiconductor material may be used as the display medium layer 160 in other embodiments.

In this embodiment, the gate line and the first sensing electrode are disposed on the first circuit layer, and the signal line, the power line, and the second sensing electrode are disposed on the second circuit layer, and the first circuit layer, The second circuit layer and the pixel unit layer are stacked on top of each other. Therefore, the layout space of each pixel unit in the pixel unit layer does not need to be limited by the above-mentioned circuit or other pixel unit components, so it is more flexible. In other subsequent embodiments, it is also implemented in this way.

In addition, in this embodiment, the first flat layer is disposed between the first circuit layer and the second circuit layer, and the second flat layer disposed between the second circuit layer and the pixel unit layer has a flat surface. The active element in the pixel unit can be made on the flat surface to ensure the quality of the active element. In addition, an additional water vapor barrier layer (not shown) can be added between the bottom carrier board and the first circuit layer to protect and Extend the life of internal components. In this embodiment, the active element may be configured as a top-gate thin film transistor structure or a bottom-gate thin film transistor structure. In other subsequent embodiments, it can also be implemented in this manner.

In addition, the material of the first flat layer or the second flat layer includes an organic insulating material, an inorganic insulating material, or a combination thereof, and the temperature resistance of the second flat layer may be Tolerate the process temperature of the drive circuit structure. For example, the organic insulating material as the first flat layer or the second flat layer includes polyimide, an organic photoresist material, or a combination thereof, and the inorganic insulating material includes silicon oxide, silicon nitride, silicon oxynitride, or the like. combination. In an embodiment, the first flat layer or the second flat layer may be a deposited layer or a coating layer, and is formed in a deposition or coating manner. The degree of undulation of the flat surface of the flat layer can be determined according to different process requirements. In one embodiment, as long as the surface undulation (or roughness) of the second flat surface does not reduce the manufacturing yield of the driving circuit structure, it can be adopted. In other subsequent embodiments, this is also implemented.

In addition, the method for forming the first or second conductive structure in this embodiment may include first forming a first circuit layer 120 or a second circuit layer on the first planar layer, the second circuit layer, or the second planar layer to expose the first circuit layer 120 or the second circuit layer. Through holes (not shown), and conductive materials are filled in the through holes. In other subsequent embodiments, this is also implemented.

3 is a schematic cross-sectional view of a display panel with sensing according to a second embodiment of the present application. 3, the display panel 200 includes a bottom carrier board 220, a first circuit layer 220, a first planar layer 230, a second circuit layer 220.1, a second planar layer 230.1, a pixel unit layer 240, a first conductive structure 250, The second conductive structure 250.1 includes the bottom carrier board 210, the first circuit layer 220, the first flat layer 230, the second circuit layer 220.1, the second flat layer 230.1, the pixel unit layer 240, the first conductive structure 250, and the second The structure formed by the conductive structure 250.1 may be referred to as a pixel array structure. The first circuit layer 220 is disposed on the bottom carrier plate 210. The first planar layer 230 covers the first circuit layer 220, the second circuit layer 220.1 is disposed on the first planar layer 230, the second planar layer 230.1 covers the second circuit layer 220.1, and the second planar layer 230.1 is far from the second circuit. The layer 220.1 has a flat surface 232 on one side. The pixel unit layer 240 is disposed on the flat surface 232 of the second flat layer 230.1, and the pixel unit layer 240 includes a pixel unit. The pixel unit includes a pixel electrode electrically connected to the driving circuit structure. The first conductive structure 250 penetrates the first flat layer 230, the second circuit layer 220.1, and the second flat layer 230.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 220. The first conductive structure 250 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate lines in the first circuit layer. In this embodiment, at least one of the first sensing electrodes 271 and at least one of the gate lines in the first circuit layer are common electrodes. . The display medium layer (not shown) is disposed on the pixel unit layer 240 and is connected to the pixel unit layer. The second conductive structure 250.1 penetrates the second flat layer 230.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 220.1. The second conductive structure 250.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal lines 280 in the second circuit layer, and in addition, the second circuit layer further includes a second sensing electrode 272 and a power line 273, wherein the signal line 280 is electrically separated from the second sensing electrode 272 and the power line 273. The common electrode (including the first sensing electrode 271) and the second sensing electrode 272 are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

4 is a schematic cross-sectional view of a sensing display panel according to a third embodiment of the present application. Referring to FIG. 4, the display panel 300 includes a bottom carrier board 310, a first circuit layer 320, a first planar layer 330, a second circuit layer 320.1, a second planar layer 330.1, a pixel unit layer 340, a first conductive structure 350, and The second conductive structure 350.1 includes the bottom carrier plate 310, the first circuit layer 320, the first planar layer 330, the second circuit layer 320.1, the second planar layer 330.1, the pixel unit layer 340, the first conductive structure 350, The structure formed by the second conductive structure 350.1 may be referred to as a pixel array structure. The first circuit layer 320 is disposed on the bottom carrier plate 310. The first planar layer 330 covers the first circuit layer 320, the second circuit layer 320.1 is disposed on the first planar layer 330, the second planar layer 330.1 covers the second circuit layer 320.1, and the second planar layer 330.1 is far from the second circuit layer 320.1 has a flat surface 332 on one side. The pixel unit layer 340 is disposed on the flat surface 332 of the second flat layer 330.1, and the pixel unit layer 340 includes a pixel unit. The pixel unit includes a pixel electrode electrically connected to the driving circuit structure. The first conductive structure 350 penetrates the first flat layer 330, the second circuit layer 320.1, and the second flat layer 330.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 320. The first conductive structure 350 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate line 370 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 371, wherein the gate line 370 and the first sensing electrode 171 Electrically separated. The display medium layer (not shown) is disposed on the pixel unit layer 340 and is connected to the pixel unit layer. The second conductive structure 350.1 penetrates the second flat layer 330.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 320.1. The second conductive structure 350.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal line 380 in the two circuit layer. In addition, the second circuit layer further includes a second sensing electrode and a power line, wherein at least one of the second sensing electrode 372 and at least one of the power line are a common electrode and communicate with the signal line. 380 is electrically separated. The first sensing electrode 371 and the common electrode (including the second sensing electrode 372) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

FIG. 5 is a schematic cross-sectional view of a display panel with sensing according to a fourth embodiment of the present application. 5, the display panel 400 includes a bottom carrier plate 420 and a first circuit. Layer 420, first flat layer 430, second circuit layer 420.1, second flat layer 430.1, pixel unit layer 440, first conductive structure 450, second conductive structure 450.1, of which the bottom carrier plate 410 and the first circuit layer 420 The structure formed by the first flat layer 430, the second circuit layer 420.1, the second flat layer 430.1, the pixel unit layer 440, the first conductive structure 450, and the second conductive structure 450.1 may be referred to as a pixel array structure. The first circuit layer 420 is disposed on the bottom carrier plate 410. The first planar layer 430 covers the first circuit layer 420, the second circuit layer 420.1 is disposed on the first planar layer 430, the second planar layer 430.1 covers the second circuit layer 420.1, and the second planar layer 430.1 is far from the second circuit layer 420.1 has a flat surface 432 on one side. The pixel unit layer 440 is disposed on the flat surface 432 of the second flat layer 430.1, and the pixel unit layer 440 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 450 penetrates the first flat layer 430, the second circuit layer 420.1, and the second flat layer 430.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 420. The first conductive structure 450 goes further. The driving circuit structure connected to the pixel unit layer and the gate lines in the first circuit layer, wherein at least one of the first sensing electrodes 471 and at least one of the gate lines are first common electrodes. In addition, the second circuit layer includes at least one of the second sensing electrodes 472 and at least one of the power lines as a second common electrode and is electrically separated from the signal line 480. The second conductive structure 450.1 is connected to the pixel unit layer. The driving circuit structure and the signal line 480 in the second circuit layer. The first common electrode (including the first sensing electrode 471) and the second common electrode (including the second sensing electrode 472) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

FIG. 6 is a cross-section of a display panel with sensing according to a fifth embodiment of the present application. schematic diagram. Referring to FIG. 6, the display panel 500 includes a bottom carrier board 510, a first circuit layer 520, a first planar layer 530, a second circuit layer 520.1, a second planar layer 530.1, a pixel unit layer 540, a first conductive structure 550, The second conductive structure 550.1, wherein the bottom carrier plate 510, the first circuit layer 520, the first flat layer 530, the second circuit layer 520.1, the second flat layer 530.1, the pixel unit layer 540, the first conductive structure 550, and the second The structure formed by the conductive structure 550.1 may be referred to as a pixel array structure. The first circuit layer 520 is disposed on the bottom carrier plate 510. The first planar layer 530 covers the first circuit layer 520, the second circuit layer 520.1 is disposed on the first planar layer 530, the second planar layer 530.1 covers the second circuit layer 520.1, and the second planar layer 530.1 is far from the second circuit layer 520.1 has a flat surface 532 on one side. The pixel unit layer 540 is disposed on the flat surface 532 of the second flat layer 530.1, and the pixel unit layer 540 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 550 penetrates the first flat layer 530, the second wiring layer 520.1, and the second flat layer 530.1 and is connected between the driving circuit structure of the pixel unit layer and the first wiring layer 520. The first conductive structure 550 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate line 570 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 571, wherein the gate line 570 and the first sensing electrode 571 Electrically separated. The display medium layer (not shown) is disposed on the pixel unit layer 540 and is connected to the pixel unit layer. The second conductive structure 550.1 penetrates the second flat layer 530.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 520.1. The second conductive structure 550.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal lines in the second circuit layer. In addition, the second circuit layer further includes a second sensing electrode 572 and an electrical circuit. The source line 573, wherein at least one of the second sensing electrode 572 and at least one of the signal lines are common electrodes and are electrically separated from the power line 573. The first sensing electrode 571 and the common electrode (including the second sensing electrode 572) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

FIG. 7 is a schematic cross-sectional view of a display panel with sensing according to an embodiment of the present application. Referring to FIG. 7, the display panel 600 includes a bottom carrier board 620, a first circuit layer 620, a first flat layer 630, a second circuit layer 620.1, a second flat layer 630.1, a pixel unit layer 640, a first conductive structure 650, The second conductive structure 650.1, wherein the bottom carrier plate 610, the first circuit layer 620, the first flat layer 630, the second circuit layer 620.1, the second flat layer 630.1, the pixel unit layer 640, the first conductive structure 650, and the second The structure formed by the conductive structure 650.1 can be referred to as a pixel array structure. The first circuit layer 620 is disposed on the bottom carrier plate 610. The first planar layer 630 covers the first circuit layer 620, the second circuit layer 620.1 is disposed on the first planar layer 630, the second planar layer 630.1 covers the second circuit layer 620.1, and the second planar layer 630.1 is far from the second circuit layer 620.1 has a flat surface 632 on one side. The pixel unit layer 640 is disposed on the flat surface 632 of the second flat layer 630.1, and the pixel unit layer 640 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 650 penetrates the first flat layer 630, the second circuit layer 620.1, and the second flat layer 630.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 620. The first conductive structure 650 goes one step further. The driving circuit structure connected to the pixel unit layer and the gate lines in the first circuit layer, wherein at least one of the first sensing electrodes 671 and at least one of the gate lines are first common electrodes. In addition, the second circuit layer includes a second sensing circuit. At least one of the electrodes 672 and at least one of the signal lines are the second common electrode and are electrically separated from the power line 673. The second conductive structure 550.1 penetrates the second flat layer 630.1 and is connected to the driving circuit structure of the pixel unit layer. Between the second circuit layer 620.1 and the second conductive structure 550.1, the driving circuit structure of the pixel unit layer and the signal line in the second circuit layer are further connected. The first common electrode (including the first sensing electrode 671) and the second common electrode (including the second sensing electrode 672) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

FIG. 8 is a schematic cross-sectional view of a sensing display panel according to a seventh embodiment of the present application. Referring to FIG. 8, the display panel 700 includes a bottom carrier board 710, a first circuit layer 720, a first flat layer 730, a second circuit layer 720.1, a second flat layer 730.1, a pixel unit layer 740, a first conductive structure 750, and The second conductive structure 750.1, wherein the bottom carrier plate 710, the first circuit layer 720, the first flat layer 730, the second circuit layer 720.1, the second flat layer 730.1, the pixel unit layer 740, the first conductive structure 750, and the second The structure formed by the conductive structure 750.1 may be referred to as a pixel array structure. The first circuit layer 720 is disposed on the bottom carrier plate 710. The first planar layer 730 covers the first circuit layer 720, the second circuit layer 720.1 is disposed on the first planar layer 730, the second planar layer 730.1 covers the second circuit layer 720.1, and the second planar layer 730.1 is far from the second circuit layer 720.1 has a flat surface 732 on one side. The pixel unit layer 740 is disposed on the flat surface 732 of the second flat layer 730.1, and the pixel unit layer 740 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 750 penetrates the first flat layer 730, the second wiring layer 720.1, and the second flat layer 730.1 and is connected to the driving circuit structure of the pixel unit layer and the first wiring layer 720. In between, the first conductive structure 750 is further connected to the driving circuit structure of the pixel unit layer and the gate line 770 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 771 and a power line. 773, wherein the gate line 770 and the power line 773 are electrically separated from the first sensing electrode 771. The display medium layer (not shown) is disposed on the pixel unit layer 740 and is connected to the pixel unit layer. The second conductive structure 750.1 penetrates the second flat layer 730.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 720.1. The second conductive structure 750.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer. The signal line 780 in the second circuit layer, and in addition, the second circuit layer further includes a second sensing electrode 772, wherein the second sensing electrode 772 and the signal line 780 are electrically separated. The first sensing electrode 771 and the second sensing electrode 772 face each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

FIG. 9 is a schematic cross-sectional view of a sensing display panel according to an eighth embodiment of the present application. Referring to FIG. 9, the display panel 800 includes a bottom carrier board 820, a first circuit layer 820, a first flat layer 830, a second circuit layer 820.1, a second flat layer 830.1, a pixel unit layer 840, a first conductive structure 850, The second conductive structure 850.1 includes a bottom carrier plate 810, a first circuit layer 820, a first flat layer 830, a second circuit layer 820.1, a second flat layer 830.1, a pixel unit layer 840, a first conductive structure 850, and a second The structure formed by the conductive structure 850.1 may be referred to as a pixel array structure. The first circuit layer 820 is disposed on the bottom carrier plate 810. The first planar layer 830 covers the first circuit layer 820, the second circuit layer 820.1 is disposed on the first planar layer 830, the second planar layer 830.1 covers the second circuit layer 820.1, and the second planar layer 830.1 is far from the second circuit layer 820.1 has a flat surface 832 on one side. The pixel unit layer 840 is arranged on the second flat The Tan layer 830.1 is on a flat surface 832 and the pixel unit layer 840 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 850 penetrates the first flat layer 830, the second circuit layer 820.1, and the second flat layer 830.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 820. The first conductive structure 850 goes further The driving circuit structure connected to the pixel unit layer and the gate line 870 in the first circuit layer, the first circuit layer further includes a first sensing electrode 871 and a power line, wherein at least one of the first sensing electrode 871 and a power source At least one of the lines is a common electrode and is electrically separated from the gate line 870. In addition, the second conductive structure 850.1 penetrates the second flat layer 830.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 820.1. The second conductive structure 850.1 is further connected to the driving circuit structure of the pixel unit layer. It is electrically separated from the signal line 880 in the second circuit layer, and the second circuit layer further includes a second sensing electrode 872 and the signal line 880. The common electrode (including the first sensing electrode 871) and the second sensing electrode 872 are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

FIG. 10 is a schematic cross-sectional view of a sensing display panel according to a ninth embodiment of the present application. 10, the display panel 900 includes a bottom carrier board 910, a first circuit layer 920, a first planar layer 930, a second circuit layer 920.1, a second planar layer 930.1, a pixel unit layer 940, a first conductive structure 950, and The second conductive structure 950.1, wherein the bottom carrier plate 910, the first circuit layer 920, the first flat layer 930, the second circuit layer 920.1, the second flat layer 930.1, the pixel unit layer 940, the first conductive structure 950, and the second The structure formed by the conductive structure 950.1 can be referred to as a pixel array structure. The first circuit layer 920 is disposed on the bottom carrier board 910. The first flat layer 930 covers the first circuit Layer 920, the second circuit layer 920.1 is disposed on the first planar layer 930, the second planar layer 930.1 covers the second circuit layer 920.1, and a side of the second planar layer 930.1 away from the second circuit layer 920.1 has a planar surface 932 . The pixel unit layer 940 is disposed on the flat surface 932 of the second flat layer 930.1, and the pixel unit layer 940 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 950 penetrates the first flat layer 930, the second circuit layer 920.1, and the second flat layer 930.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 920. The first conductive structure 950 goes further. The driving circuit structure connected to the pixel unit layer and the gate line 970 in the first circuit layer. In addition, the first circuit layer further includes a first sensing electrode 971 and a power line 973, among which the gate line 970 and the power line 973 is electrically separated from the first sensing electrode 971. The display medium layer (not shown) is disposed on the pixel unit layer 940 and is connected to the pixel unit layer. The second conductive structure 950.1 penetrates the second flat layer 930.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 920.1. The second conductive structure 950.1 is further connected to the driving circuit structure of the pixel unit layer and the first circuit layer 920.1. The signal lines in the two circuit layers. In addition, the second circuit layer further includes a second sensing electrode 972. At least one of the second sensing electrodes 972 and at least one of the signal lines are common electrodes. The first sensing electrode 971 and the common electrode (including the second sensing electrode 972) are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

FIG. 11 is a schematic cross-sectional view of a display panel with sensing according to a tenth embodiment of the present application. Referring to FIG. 11, the display panel 1000 includes a bottom carrier board 1020, a first circuit layer 1020, a first flat layer 1030, a second circuit layer 1020.1, a second flat layer 1030.1, a pixel unit layer 1040, a first conductive structure 1050, Second conductive structure 1050.1, including the bottom carrier board 1010, the first circuit layer 1020, the first flat layer 1030, the second circuit layer 1020.1, the second flat layer 1030.1, the pixel unit layer 1040, the first conductive structure 1050, and the second conductive structure 1050.1 The structure formed may be referred to as a pixel array structure. The first circuit layer 1020 is disposed on the bottom carrier board 1010. The first planar layer 1030 covers the first circuit layer 1020, the second circuit layer 1020.1 is disposed on the first planar layer 1030, the second planar layer 1030.1 covers the second circuit layer 1020.1, and the second planar layer 1030.1 is far from the second circuit layer 1020.1 has a flat surface 1032 on one side. The pixel unit layer 1040 is disposed on the flat surface 1032 of the second flat layer 1030.1, and the pixel unit layer 1040 includes a pixel unit. The pixel unit includes a pixel electrode of a driving circuit structure electrically connected to the pixel unit layer. The first conductive structure 1050 penetrates the first planar layer 1030, the second circuit layer 1020.1, and the second planar layer 1030.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 1020. The first conductive structure 1050 goes further. The driving circuit structure connected to the pixel unit layer and the gate line 1070 in the first circuit layer. The first circuit layer further includes a first sensing electrode 1071 and a power line, wherein at least one of the first sensing electrode 1071 and a power source. At least one of the lines is a first common electrode, and is electrically separated from the gate line 1070. In addition, the second conductive structure 1050.1 penetrates the second flat layer 1030.1 and is connected between the driving circuit structure of the pixel unit layer and the second circuit layer 1020. The second conductive structure 1050.1 is further connected to the driving circuit structure of the pixel unit layer. And the signal line in the second circuit layer, the second circuit layer further includes a second sensing electrode 1072, at least one of the second sensing electrode 1072 and at least one of the signal lines are a second common electrode. The first common electrode (including the first sensing electrode 1071) and the second common electrode (including the second sensing electrode 1072) are opposed to each other to generate an electricity The capacitance C is generated by a change in the capacitance C.

In the above embodiments of the present application, the first circuit layer or the second circuit layer may include a plurality of signal lines, power lines, gate lines, first sensing electrodes, and second sensing electrodes. When the board is used as the extended circuit area of the peripheral circuit of the panel, the above-mentioned plural signal lines, power lines, gate lines, first sensing electrodes or second sensing electrodes must all transmit signals or send signals outside the peripheral area of the panel. For the input signal, in the eleventh embodiment of the present application, referring to FIG. 12 at the same time, the structure of the panel display area is shown in FIG. 2 and FIG. 3, which will not be repeated here. A fourth conductive structure 1152 and a fifth conductive structure 1153 respectively penetrate the first flat layer 1130 downward to conduct the lines of the power line 1173, the second sensing electrode 1172, and the signal line 1180 of the second circuit layer 1120.1 to 1120 on the first circuit layer in the peripheral area of the panel.

In the twelfth embodiment of the present application, referring to FIG. 13 at the same time, the structure of the panel display area is shown in FIG. 4 and FIG. 5, which will not be repeated here. A third conductive structure 1251 and a fourth are added to the peripheral circuit area of the panel. The conductive structure 1252 penetrates the first flat layer 1230 downwardly, respectively, and conducts at least one common electrode of the second circuit layer 1220.1 and at least one common electrode of the second sensing electrode 1272 and the signal line 1280 to the panel peripheral area, respectively. On the first circuit layer 1220.

In the thirteenth embodiment of the present application, referring to FIG. 14 at the same time, the structure of the panel display area is referred to FIG. 6 and FIG. 7, which are not described in detail here. A third conductive structure 1351 and a fourth conductive are added to the peripheral circuit area. Structure 1352, penetrating through the first flat layer 1330 and at least one of the signal lines of the second circuit layer 1320.1 and the second sensing electrode, respectively. At least one of the common electrodes of 1372 and the lines of the power line 1373 are respectively conducted to the first circuit layer 1320 in the peripheral area of the panel.

In the fourteenth embodiment of the present application, referring to FIG. 15 at the same time, the structure of the panel display area is shown in FIG. 8 and FIG. 9, which will not be repeated here. A third conductive junction 1451 structure and a first The four conductive structures 1452 penetrate the first flat layer 1430 downwardly and respectively conduct the signal lines 1480 of the second circuit layer 1420.1 and the lines of the second sensing electrode 1472 to the first circuit layer 1420 in the peripheral area of the panel.

In the fifteenth embodiment of the present application, referring to FIG. 16 at the same time, the structure of the panel display area is shown in FIG. 10 and FIG. 11, which will not be described in detail here. A third conductive structure 1551 is added to the peripheral circuit area of the panel and penetrates downward. The first flat layer 1530 conducts lines of the common electrode of at least one of the signal lines of the second circuit layer 1520.1 and at least one of the second sensing electrodes 1572 to the first circuit layer 1520 in the peripheral area of the panel.

In the sixteenth embodiment of the present application, referring to FIG. 17 at the same time, the structure of the panel display area is referred to FIG. 3, FIG. 5, and FIG. 7, which is not repeated here, and a third conductive structure 1651 is added to the peripheral circuit area of the panel. Through the first flat layer 1630 upward, the lines of the common electrode of at least one of the gate lines and at least one of the first sensing electrodes 1671 in the first circuit layer 1620 are conducted to the second circuit layer 1620.1 in the peripheral area of the panel.

In the seventeenth embodiment of the present application, referring to FIG. 18 at the same time, the structure of the panel display area is shown in FIG. 2, FIG. 4, and FIG. 6, and details are not described herein. A third conductive structure 1751 and A fourth conductive structure 1752 penetrates the first flat layer 1730 upward to conduct the gate lines 1770 of the first circuit layer 1720 and the lines of the first sensing electrode 1171 to the second circuit layer 1720.1 in the peripheral area of the panel, respectively. on.

In the eighteenth embodiment of the present application, referring to FIG. 19 at the same time, the structure of the panel display area is referred to FIG. 9 and FIG. 11, which will not be repeated here. A four-conducting structure 1852 penetrates the first flat layer 1830 upwards and conducts at least one common line of the first wiring layer 1820 and at least one common electrode of the first sensing electrode 1871 and the gate line 1870 to the panel periphery respectively. Area on the second circuit layer 1820.1.

In the nineteenth embodiment of the present application, referring to FIG. 20 at the same time, the structure of the panel display area is shown in FIG. 8 and FIG. 10, which will not be repeated here. A third conductive structure 1951, a fourth is added to the peripheral circuit area of the panel. The conductive structure 1952 and a fifth conductive structure 1953 penetrate the first flat layer 1930 to conduct the lines of the gate line 1970, the first sensing electrode 1971, and the power line 1973 of the first circuit layer 1920 to the first of the peripheral regions of the panel, respectively. The second line layer is on 1920.1.

FIG. 21 is a schematic cross-sectional view of a sensing display panel according to a twentieth embodiment of the present application. Referring to FIG. 21, the display panel 2000 includes a bottom carrier board 2010, a first circuit layer 2020, a first flat layer 2030, a second circuit layer 202.1, a second flat layer 2030.1, a pixel unit layer 2040, a first conductive structure 2050, The second conductive structure 2050.1, wherein the bottom carrier board 2010, the first circuit layer 2020, the first flat layer 2030, the second circuit layer 202.1, the second flat layer 2030.1, the pixel unit layer 2040, the first conductive structure 2050, and the second The structure formed by the conductive structure 2050.1 may be referred to as a pixel array structure 2002. The first circuit layer 2020 is disposed on the bottom carrier board 2010. The first flat layer 2030 covers the first circuit layer 2020, and the second circuit layer 2020.1 is disposed at the first On a flat layer 2030, the second flat layer 2030.1 covers the second circuit layer 2020.1, and a side of the second flat layer 2030.1 far from the second circuit layer 2020.1 has a flat surface 2032. The pixel unit layer 2040 is disposed on the flat surface 2032 of the second flat layer 2030.1, and the pixel unit layer 2040 includes a pixel unit. The pixel unit includes a pixel electrode, a gate line 2070, a power line 2073, and a signal line 2080 electrically connected to a driving circuit structure of the pixel unit layer. The first conductive structure 2050 penetrates the first planar layer 2030, the second circuit layer 2020.1, and the second planar layer 2030.1 and is connected between the driving circuit structure of the pixel unit layer and the first circuit layer 2020. The first conductive structure 2050 goes one step further. The driving circuit structure connected to the pixel unit layer has a first sensing electrode 2071 in a first wiring layer, and the second wiring layer includes a second sensing electrode 2072. The first sensing electrode 2071 and the second sensing electrode 2072 are opposed to each other to generate a capacitor C, and a sensing signal is generated by the change of the capacitor C.

In the twentieth embodiment disclosed above, either the first circuit layer or the second circuit layer includes a plurality of first sensing electrodes and a second sensing electrode, and if the carrier board with the sensing display panel is used as the panel When extending the circuit area of the peripheral circuit, the above-mentioned plurality of first sensing electrodes or second sensing electrodes must transmit the sensing signal outward in the peripheral area of the panel, and a third conductive structure 2051 is added in the peripheral area of the panel, downward. Or the first flat layer is penetrated upward, so that the signal of the first sensing electrode goes up to the second circuit layer, or the signal of the second sensing electrode goes down to the first circuit layer.

In summary, the sensing display panel and the sensing pixel array structure of the embodiment of the present application can separate the driving circuit structure, the sensing circuit structure and the signal transmission line in the pixel unit in different layers. Bit, on the one hand can increase The layout area of the driving circuit structure in the pixel unit makes the layout of the driving circuit structure more flexible. On the other hand, the sensing function can be added to the display panel. Therefore, according to the design of the embodiment of the present application, the display panel has a design space with more functions.

Although the present application has been disclosed as above by way of example, it is not intended to limit the present application. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present application. The scope of protection of this application shall be determined by the scope of the attached patent application.

110‧‧‧Bottom load plate

120‧‧‧First circuit layer

130‧‧‧ the first flat layer

120.1‧‧‧Second circuit layer

130.1‧‧‧ second flat surface

132‧‧‧ flat surface

140‧‧‧ pixel unit layer

160‧‧‧Display media layer

150‧‧‧first conductive structure

150.1‧‧‧Second conductive structure

170‧‧‧Gate line

171‧‧‧first sensing electrode

172‧‧‧Second sensing electrode

173‧‧‧Power cord

180‧‧‧ signal line

Claims (20)

  1. A sensing pixel array structure includes: a bottom carrier board including a screen display area and a peripheral circuit area, the peripheral circuit area is located outside the screen display area, wherein the screen display area includes a first circuit layer Is disposed on the bottom carrier board, the first circuit layer includes a plurality of first sensing electrodes; a first planar layer covering the first circuit layer; and a second circuit layer disposed on the first planar layer The second circuit layer includes a plurality of second sensing electrodes, a second flat layer covers the second circuit layer, and a side of the second flat layer remote from the second circuit layer has a flat surface; A pixel unit layer is disposed on the flat surface; a first conductive structure is disposed on the screen display area, penetrates the second flat layer, the second circuit layer, and the first flat layer and is connected to the pixel Between the unit layer and the first circuit layer; a second conductive structure disposed in the screen display area, penetrating the second flat layer and connected between the pixel unit layer and the second circuit layer; and the periphery The circuit area includes: Conductive structure disposed in the peripheral circuit region, through the first planar layer and connected to the first circuit layer between the second circuit layer.
  2. The display pixel array structure with sensing according to item 1 of the scope of the patent application, wherein the first circuit layer further includes a plurality of gate lines, wherein the first sensing electrodes and the plurality of gates are extremely independent of each other. The electrode.
  3. The sensing pixel array structure according to item 2 of the scope of the patent application, wherein the second circuit layer further includes a plurality of signal lines and a plurality of power lines, wherein the second sensing electrodes, the signals The wires and the power lines are independent electrodes.
  4. The sensing pixel array structure according to item 2 of the scope of patent application, wherein the second circuit layer further includes a plurality of signal lines and a plurality of power lines, wherein at least one of the second sensing electrodes and At least one of the power lines is a common electrode, and the signal lines are independent electrodes.
  5. The sensing pixel array structure according to item 2 of the scope of patent application, wherein the second circuit layer further includes a plurality of signal lines and a plurality of power lines, wherein at least one of the second sensing electrodes and At least one of the signal lines is a common electrode, and the power lines are independent electrodes.
  6. The sensing pixel array structure according to item 1 of the patent application scope, wherein the first circuit layer further includes a plurality of gate lines, wherein at least one of the first sensing electrodes and the plurality of gates At least one of the polar lines is a common electrode.
  7. The sensing pixel array structure according to item 6 of the patent application scope, wherein the second circuit layer further includes a plurality of signal lines and a plurality of power lines, wherein the second sensing electrodes, the signals The wires and the power lines are independent electrodes.
  8. The sensing pixel array structure according to item 6 of the patent application scope, wherein the second circuit layer further includes a plurality of signal lines and a plurality of power lines, wherein at least one of the second sensing electrodes and At least one of the power lines is a common electrode, and the signal lines are independent electrodes.
  9. The sensing pixel array structure according to item 6 of the patent application scope, wherein the second circuit layer further includes a plurality of signal lines and a plurality of power lines, wherein at least one of the second sensing electrodes and At least one of the signal lines is a common electrode, and the power lines are independent electrodes.
  10. The display pixel array structure with sensing as described in item 1 of the patent application scope, wherein the first circuit layer further includes a plurality of gate lines and a plurality of power lines, wherein the first sensing electrodes and the gates The epipolar lines and the source lines are independent electrodes.
  11. The display pixel array structure with sensing according to item 10 of the scope of patent application, wherein the second circuit layer further includes a plurality of signal lines, wherein the second sensing electrodes and the signal lines are independent of each other. electrode.
  12. The sensing pixel array structure as described in claim 10 of the patent application scope, wherein the second circuit layer further includes a plurality of signal lines, wherein at least one of the second sensing electrodes and one of the signal lines At least one is a common electrode.
  13. The sensing pixel array structure according to item 1 of the patent application scope, wherein the first circuit layer further includes a plurality of gate lines and a plurality of power lines, wherein at least one of the first sensing electrodes At least one of the plurality of power lines is a common electrode, and the gate lines are independent electrodes.
  14. The display pixel array structure with sensing as described in item 13 of the scope of the patent application, wherein the second circuit layer further includes a plurality of signal lines, wherein the second sensing electrodes and the signal lines are independent of each other. electrode.
  15. The display pixel array structure with sensing according to item 13 of the scope of the patent application, wherein the second circuit layer further includes a plurality of signal lines, wherein at least one of the second sensing electrodes and at least one of the signal lines At least one is a common electrode.
  16. The sensing pixel array structure according to item 1 of the patent application scope further includes a fourth conductive structure disposed in the peripheral circuit area, penetrating the first flat layer and connected to the first circuit layer. Between the second circuit layers.
  17. The sensing pixel array structure according to item 1 of the patent application scope further includes a fifth conductive structure disposed in the peripheral circuit area, penetrating the first flat layer and connected to the first circuit layer. Between the second circuit layers.
  18. The sensing pixel array structure according to item 1 of the scope of the patent application, wherein the pixel unit layer includes a plurality of gate lines and a plurality of data lines.
  19. The sensing pixel array structure according to item 18 of the scope of patent application, wherein the pixel unit layer further includes a plurality of power lines.
  20. The sensing pixel array structure according to item 1 of the patent application scope, wherein the material of the first flat layer and the second flat layer includes an organic insulating material, an inorganic insulating material, or a combination thereof, wherein the organic The insulating material includes polyimide, an organic photoresist material, or a combination thereof, and the inorganic insulating material includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
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US20100149117A1 (en) * 2008-12-11 2010-06-17 Au Optronics Corporation Color filter touch sensing substrate and display panel and manufacturing methods of the same
TW201303659A (en) * 2011-07-07 2013-01-16 Wintek Corp Touch-sensitive display panel
TW201643642A (en) * 2015-06-05 2016-12-16 群創光電股份有限公司 Display device

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KR101273239B1 (en) * 2010-09-20 2013-06-11 엘지디스플레이 주식회사 Liquid crystal display device with a built-in touch screen and method for manufacturing the same
CN103713792B (en) * 2013-12-23 2016-06-01 京东方科技集团股份有限公司 Array substrate and manufacture method thereof and touch display unit
CN104536636B (en) * 2015-01-27 2017-12-08 京东方科技集团股份有限公司 A kind of preparation method of array base palte, contact panel and array base palte
CN104571715B (en) * 2015-02-02 2018-01-02 京东方科技集团股份有限公司 Array base palte and preparation method thereof and driving method, display device
CN105932029A (en) * 2016-06-08 2016-09-07 京东方科技集团股份有限公司 Array substrate, production method thereof, touch display panel and display device

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US20100149117A1 (en) * 2008-12-11 2010-06-17 Au Optronics Corporation Color filter touch sensing substrate and display panel and manufacturing methods of the same
TW201303659A (en) * 2011-07-07 2013-01-16 Wintek Corp Touch-sensitive display panel
TW201643642A (en) * 2015-06-05 2016-12-16 群創光電股份有限公司 Display device

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