TWI598880B - Non-volatile semiconductor memory device and erasure method thereof - Google Patents

Description

Non-volatile semiconductor memory device and its erasing method

The present invention relates to a non-volatile memory device such as a flash memory and an erase method thereof.

In recent non-volatile memory devices such as flash memory, double patterning technology is employed for large-capacity and high-density semiconductor lithography. The double patterning technique is used as a lithography technique having a resolution of, for example, 42 nm or less, and it is known that, for example, a pattern is exposed by a pitch of 2 times and then shifted from a pitch of only 1/2 thereof. A method of exposing the same, and a method of removing an unnecessary pattern after using a process trick such as a spacer process. [Prior Art Document] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-250186 [Patent Document 2] US Patent Application Publication No. 2008/0165585 [Patent Document 3] US Patent Application Publication No. 2013/0163359 (Patent Document 4) Patent Application Publication No. 2011/0069543 [Patent Document 5] US Patent Application Publication No. 2012/0008412 [Problem to be Solved by the Invention]

Due to the large capacity and high density of the flash memory as described above, the interval between the word lines and the interval between the bit lines become very narrow, so that data between adjacent word lines or adjacent bit lines The characteristics of the data program (write) or erase have a large impact. For this reason, for example, in a conventional technique such as Patent Document 1 to Patent Document 5, a method for optimizing data erasing characteristics has been proposed.

1 is a longitudinal cross-sectional view showing an applied voltage of each electrode at the time of erasing data of a flash memory of a conventional example.

In FIG. 1, an N well 2 is formed by, for example, implanting phosphorus on a P-type semiconductor substrate 1, and a P well 3 is formed by, for example, implanting boron on the upper portion of the N well 2. Next, by forming the following electrodes on the P well 3, the respective electrodes, the N well 2, and the P well 3 are applied with a predetermined voltage (voltage in each bracket in FIG. 1) as shown in FIG. Furthermore, FL is in a floating state. (1) source line SL; (2) select gate line SGS, select gate line SGD; (3) virtual word line DWLS, virtual word line DWLD; (4) word line WL0 to word line WL31 (5) Bit line GBL.

Here, VDWL is a voltage applied to the virtual word line DWLS and the virtual word line DWLD, and is adjacent to each of the virtual word line DWLS and the virtual word line DWLD, for example, two edge area side character lines WL0 and edges. The area side word line WL1, the edge area side word line WL30, and the edge area side word line WL31 are respectively applied with a voltage Vea, a voltage Veb, a voltage Veb, and a voltage Vea. Further, a voltage Vee is applied to the word line WL2 to the word line WL29 at the center portion other than the edge region, and a voltage VERS is applied to the N well 2 and the P well 3. An example of such applied voltages is as follows.

Vea=Veb≒0 V Vee=0.3 V～0.5 V VERS=15 V～25 V

According to the erasing method of the conventional example of Fig. 1, the edge region is a region that is specific because it is not periodic in the manufacturing process. Usually, the word line of the edge area is erased by the erasing speed of the word line slower than the other area, so the word line of the edge area is usually applied with 0 V, and on the other hand, the character outside the edge area is applied. The line applies a voltage greater than 0 V. The adjustment is performed in such a manner as to reduce the erasing speed of the word line with a fast erasing speed, so that the erasing speeds of all the word lines are identical, so that the threshold distribution of the erased memory cells is narrowed. However, in the double patterning technique, a uniform line width or space cannot be ensured on the word line at the center portion, and therefore there is a problem that the erasing operation on the word line other than the edge area cannot be optimized.

It is an object of the present invention to provide a non-volatile semiconductor memory device and an erase method thereof that can optimize the erasing operation of a non-volatile semiconductor memory device as compared with the prior art. [Means for solving the problem]

A nonvolatile semiconductor memory device according to a first aspect of the invention includes a control circuit that is configured by a memory cell array including memory cells disposed at respective intersections of a plurality of word lines and a plurality of bit lines The predetermined area is applied with a prescribed erase voltage to erase the data, and the non-volatile semiconductor memory device is characterized in that: the control circuit has an even number of words other than the edge end of the memory cell array The meta-line and the odd-numbered word line apply mutually different word line voltages, and a voltage different from the word line voltage is applied to the edge end of the memory cell array, and the erase voltage is applied to the memory. The cell is used to erase the data.

In the non-volatile semiconductor memory device, a word line voltage for an odd number of word lines other than an edge end portion of the memory cell array is set higher or lower than the memory cell The word line voltage of an even number of word lines other than the edge of the element array.

Further, in the nonvolatile semiconductor memory device, the word line at the edge of the memory cell array is at least one adjacent to a selected gate line or a virtual word line at both ends. The word line.

Furthermore, in the non-volatile semiconductor memory device, the control circuit has different verifying conditions for memory cells of even bit lines and memory cells of odd bit lines. The verification of the data erasure is performed.

Further, in the nonvolatile semiconductor memory device, the verification condition is set such that memory cells for even bit lines and memory cells of odd bit lines are among the following conditions At least one difference: (1) word line voltage; (2) discharge time of the bit line when the bit line is precharged and the data of the read data is read; (3) charging from the source line The data reads the charging time of the bit line when the opposite data is read; (4) the pre-charging time of the bit line when the bit line is precharged and the data of the read data is read; and (5) The sense voltage of the bit line when the bit line is precharged to read the data of the read data.

Further, in the nonvolatile semiconductor memory device, the word line voltages different from each other are based on data erased in a wafer test of the nonvolatile semiconductor memory device. The threshold voltage is determined.

Further, in the non-volatile semiconductor memory device, the word line voltages different from each other are based on data erased in a wafer test given to the non-volatile semiconductor memory device. The same threshold voltage is used to erase the voltage to determine.

Further, in the nonvolatile semiconductor memory device, the threshold voltage at the time of erasing the data measured in the wafer test is measured in the following four cases: (1) Examples of even-numbered word lines and even-numbered bit lines; (2) examples of even-numbered word lines and odd-numbered bit lines; (3) examples of odd-numbered word lines and even-numbered bit lines; (4) Examples of odd-numbered word lines and odd-numbered bit lines.

Further, in the nonvolatile semiconductor memory device, the erase voltage is a well applied to the memory cell array.

Furthermore, in the non-volatile semiconductor memory device, the determined word line voltage data different from each other is stored to a portion of the memory cell array, and the non- The power of the volatile semiconductor memory device is read from the memory cell array when turned on and used during erasing of the data.

Further, in the nonvolatile semiconductor memory device, all of the memory cells of the predetermined area are written before the erasing sequence is performed.

The erasing method of the nonvolatile semiconductor memory device according to the second aspect of the present invention is an erasing method of a nonvolatile semiconductor memory device including a control circuit, the control circuit being disposed by being included in a plurality of Data is erased by applying a predetermined erase voltage to a predetermined area of the memory cell array of the memory cells at each intersection of the plurality of bit lines, the non-volatile semiconductor memory device The erasing method is characterized in that: the control circuit applies mutually different word line voltages to even-numbered word lines and odd-numbered word lines other than the edge end portion of the memory cell array, A word line at the edge of the memory cell array applies a voltage different from the word line voltage, and the erase voltage is applied to the memory cell to erase the data.

In the erasing method of the non-volatile semiconductor memory device, the word line voltage for an odd number of word lines other than the edge end portion of the memory cell array is set to be higher or lower than A word line voltage of an even number of word lines other than the edge of the memory cell array. [Effects of the Invention]

Accordingly, it is possible to provide a nonvolatile semiconductor memory device and an erase method thereof that can optimize the erasing operation of a nonvolatile semiconductor memory device as compared with the prior art of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals.

The findings obtained by the measurement of the present invention. Fig. 2 is a view showing the measurement result of the (NAND) type flash memory of the present invention, that is, the threshold voltage Vth with respect to the page number. 3 is a graph showing the measurement results of the NAND flash memory of the present invention, that is, the distribution of the threshold values of the memory cells with respect to odd-numbered word lines and even-numbered word lines.

In FIG. 2, the memory cells of the page P0 and the page P1 of the NAND type flash memory are located on the even word line WL0, and the memory cells of the page P2 and the page P3 are located on the odd word line WL1. Further, the page P0, the page P2, the page P4, and the like are located on the even bit line GBL, and the page P1, the page P3, the page P5, and the like are located on the odd bit line GBL. That is, the relationship between the number of pages, the word line number, and the bit line number is as follows.

[Table 1]         <TABLE border="1" borderColor="#000000" width="_0001"><TBODY><tr><td> page</td><td> character line</td><td> bit line< /td></tr><tr><td> P0 </td><td> WL0 </td><td> Even </td></tr><tr><td> P1 </td>< Td> WL0 </td><td> odd number</td></tr><tr><td> P2 </td><td> WL1 </td><td> even number</td></tr> <tr><td> P3 </td><td> WL1 </td><td> odd </td></tr><tr><td> P4 </td><td> WL2 </td> <td> Even </td></tr><tr><td> P5 </td><td> WL2 </td><td> Odd </td></tr><tr><td> ... ... </td><td> ...... </td><td> ...... </td></tr></TBODY></TABLE>

As shown in the figures of Fig. 2 and Fig. 3, the following matters are known.

(1) The threshold voltages Vth have substantially the same value with respect to even-numbered word lines or odd-numbered word lines, but are slightly different due to differences in semiconductor wafer fabrication. (2) With respect to the bit line GBL, the threshold voltage Vth periodically changes with respect to the even or odd bit lines adjacent to each other. (3) The threshold voltage Vth periodically changes with respect to the page number. Based on these findings, the present invention proposes an erasing method of the present embodiment as follows.

4 is a block diagram showing an example of the configuration of a NAND flash memory according to an embodiment of the present invention. In FIG. 4, the NAND type flash memory of the present embodiment includes a memory cell array 10, a control circuit 11 for controlling the operation of the memory cell array 10, a row decoder 12, and a high voltage. Generating circuit 13, page buffer circuit (PB) 14, column decoder 15, memory register 16, command register 17, address register 18. The operation logic controller 19, the data input/output buffer 50, the data input/output terminal 51, and the control signal input terminal 53. Furthermore, 52 is the data line.

The page buffer circuit 14 includes a sense amplifier circuit (SA) and a data latch circuit (data latch) provided for each group (GBLe, GBLo) of the bit line GBL in order to perform data writing and reading in a predetermined page unit. Circuit). Furthermore, the sense amplification circuit (SA) includes a number of components including a latch circuit (L2).

Each memory cell string of the memory cell array 10 is connected to each intersection of the selection gate line SGD and the bit line GBL, and each memory cell of the memory cell string MC is connected to the plurality of word lines WL. In order to select the word line WL and the bit line GBL of the memory cell array 10, a column decoder 12 and a row decoder 15 are provided, respectively. The control circuit 11 performs program control of data writing, erasing, and reading. The memory register 16 is connected to the control circuit 11, and pre-stores parameters (mode set data) required for the operations of reading, writing, and erasing, and is self-memory by the control circuit 11 when the power is turned on. The fuse data storage area in the element array is read and set. The high voltage generating circuit 13 controlled by the control circuit 11 generates a boosted high voltage or intermediate voltage for data rewriting, erasing, and reading.

The data input/output buffer 50 is used for input and output of data and input of commands and address signals. That is, data is transferred between the input/output terminal 51 and the page buffer circuit 14 via the input/output buffer 50, the data line 52, and the latch circuit (L2) 14b. The address signal input from the input/output terminal 51 is held in the address register 18 and sent to the column decoder 12 and the row decoder 15 for decoding. A command for operation control is also input from the input/output terminal 51. The input command is decoded and held in the command register 17, thereby controlling the control circuit 11. An external control signal such as the wafer enable signal CEB, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEB, and the read enable signal REB is extracted to the control signal input terminal 53 via the control signal input terminal 53 to The logic controller 19 is actuated and generates an internal control signal in accordance with the action mode. The internal control signal is control for data latching, transfer, and the like in the input/output buffer 50, and is sent to the control circuit 11 to perform operation control.

Fig. 5 is a vertical cross-sectional view showing an applied voltage of each electrode when the data of the flash memory of Fig. 4 is erased. In FIG. 5, the P-type semiconductor substrate 1, the N well 2, the P well 3, and the respective electrodes are formed in the same manner as in FIG. 1, but are different in the following points. (1) A voltage VDWL1 is applied to the dummy word line DWLS instead of the voltage VDWL. (2) A voltage VDWL2 is applied to the dummy word line DWLD instead of the voltage VDWL. (3) The voltage Vea and the voltage Veb are applied to the word line WL0 and the word line WL1 in the edge region, and the voltage Vec and the voltage Ved are applied to the word line WL30 and the word line WL31 in the edge region. (4) A voltage Vee is applied to the even-numbered word line WL2, the word line WL4, ..., the word line WL28 other than the edge region. (5) A voltage Veo is applied to the odd word line WL1, the word line WL3, ..., the word line WL29 other than the edge region.

Here, an example of the applied voltage is as follows.

Vea=Ved=0 V～0.5 V Veb=Vec=0 V～0.5 V Vee=0.3 V～0.5 V Veo=0.3 V～0.5 V VERS=15 V～25 V

Therefore, in view of the findings of FIGS. 2 and 3, the odd-numbered word line applied voltage Veo is preferably set such that the even-numbered word line is applied with a voltage Vee of, for example, 0.1 V to 0.5 V. In the conventional example of FIG. 1, the voltage Vea is the two word line WL0 and the word line WL31 for the outermost edge in the edge region, and the applied voltage of the word line other than the edge region is not on the even or odd number. The voltage Vee is applied to the voltage difference. However, in the present embodiment, considering the effects of the findings of FIGS. 2 and 3, the voltage applied to the word line in the central region other than the edge region is dependent on the even or odd number. A voltage Vee and a voltage Veo are applied to the voltage difference.

Further, in the present embodiment, each of the two word lines WL0, the word line WL1, the word line WL30, and the word line WL31 in the both edge regions of the edge portion of the memory array are respectively used and the central region. The applied voltage Vee of the word line and the applied voltage Veo are different applied voltages. Here, the two word lines WL0, the word line WL1, the word lines WL30, and WL31 in the both edge regions of the edge portion of the memory array are used, but the present invention is not limited thereto, and may be Each of the two ends uses an applied voltage different from the applied voltage Vee and the applied voltage Veo of the word line of the central region on one or three word lines. In the present embodiment, the case where 32 memory cells are connected to the memory cell string MC has been disclosed. However, the present invention is not limited thereto, and may be a larger number of series cells such as 64 memory cells, and the edge region is also enlarged. . Further, as shown in FIG. 5, the word line WL0 is provided adjacent to the selection gate line SGS via the dummy word line DWLS, and the word line WL31 is set adjacent to the selection gate line SGD via the dummy word line DWLD. . Further, the word line at the edge end portion may include the word line WL1 and the word line WL30 in addition to WL0 and WL31 as in the present embodiment.

Fig. 6 is a circuit diagram showing a verification operation when the data erase program of the flash memory of Fig. 4 is used. In FIG. 6, MC is a NAND type memory cell string, BLSe is a selection signal of an even bit line GBL0, bit line GBL2, ..., BLSo is an odd bit line GBL1, a bit line GBL3, ... Selection signal.

Here, the width of the active layer region of the memory cell string MC and the width of the floating gate exist as described above, and there is a difference in the dependence of even and odd numbers due to double patterning, and this difference also occurs when erasing The limit voltage Vth has an effect. The data in the graph of Figure 2, although small in difference, is heavily dependent on the wafer and/or wafer lot of the flash memory wafer. Since the difference is common to the word line WL, it cannot be compensated by the word line voltage VWL at the time of erasing. The difference can be compensated by changing the condition setting of the verification. For example, the word line voltage VWL at the time of verification is preferably changed between an even page and an odd page. As another method, it is possible to use the discharge time of the bit line GBL at the time of normal data reading (grounding the source line and pre-charging the bit line from the page buffer circuit 14) or reverse reading. The charging time of the bit line GBL (which charges the bit line from the source line SL when GBL = 0 V) substantially compensates for the difference. Alternatively, the pre-charging time of the bit line at the time of reading the data of the read data by pre-charging the bit line or the bit reading the data of the read data by pre-charging the bit line may be used. The sense voltage of the line is used to compensate for the difference.

That is, in the present embodiment, the verification condition at the time of erasing the data program can be set as follows, that is, the memory cell for the even-numbered bit line and the memory cell of the odd bit line make the following conditions At least one of the differences is: (1) the word line voltage VWL; (2) the discharge time of the bit line when the bit line is precharged and the data of the read data is read; (3) the reverse data reading The charging time of the bit line when the data is read from the source line; (4) the pre-charging time of the bit line when the bit line is precharged and the data of the read data is read; (5) The sensing voltage of the bit line when the bit line is precharged and the data of the read data is read.

Fig. 6 shows the verification of the odd-numbered pages by the reverse reading, and the verification at the time of erasing (confirmation when the data has been erased) is two actions of verifying the odd-numbered pages and verifying the even-numbered pages. For example, a word line voltage VWL is set to 0 V for verification of even pages, and is set to, for example, 0.2 V for verification of odd pages. That is, the reason is that the erasure of odd pages is slower than the erasure of even pages according to the characteristics of the graph of FIG.

FIG. 7 is a flow chart showing a wafer test process for the flash memory of FIG. 4. Hereinafter, an example of voltage setting will be described with reference to FIG. 7, and the wafer test processing will be described.

In step S1 of Fig. 7, the write time is measured by programming all the memory cell strings MC as data "0". This step also serves to determine the pre-processing of the erase characteristic in the next step, but the write time data is a parameter for determining the write condition setting, regardless of the erased parameter.

Specifically, using the Incremental Step Pulse Program (ISPP) method, the following items are determined for all pages of a plurality of blocks in the memory cell array 10 to calculate the actual use of the write start. Voltage Vstart. Here, the threshold value of the initial 10-bit of the memory cell is exceeded by the word line voltage Vpn when the verification voltage PV is exceeded, and the start voltage Vstart is determined by, for example, the start voltage Vstart=the average value of the voltage Vpn−2 V. Furthermore, in this example, the average value of the voltages Vpn of all the pages is used, but the present invention is not limited thereto, and the minimum value of the voltage Vpn of all the pages may be used.

The data of the memory cell string MC of a plurality of blocks (Vth < 0 V) is erased in step S2, and the threshold voltage Vth is measured for the four examples A to D. Here, four examples are as follows. (Example A) Even number of word lines, even number of bit lines. (Example B) Even number of word lines, odd number of bit lines. (Example C) Odd number of word lines, even number of bit lines. (Example D) Odd number of word lines, odd number of bit lines.

Specifically, the following items are measured for a plurality of blocks and the average value of the offset used is calculated using the average value thereof. First, use the Incremental Step Pulse Erase (ISPE) method, for example, using the starting voltage Vstart=14 V, the step voltage Vstep=0.2 V, and erasing the verification voltage EV=0 V to eliminate the data until The threshold voltage Vth of the 50% bit of the page 32 (the WL line at the center of the memory string) reaches 0 V or less. Then, the threshold voltage Vth of the bit is measured for the four examples, and the bit has the 10th largest threshold voltage Vth. The specific order is as follows.

(1) The data of page 0 is read, and the average value of the 10th largest threshold voltage Vth is measured as Vth0. Here, the data of the page 0 of several blocks can be obtained, so the operation of averaging is added. (Same as the following) (2) The data of the page 1 is read, and the average value of the 10th largest threshold voltage Vth is measured as Vth1. (3) The data of the page 2 is read, and the average value of the tenth largest threshold voltage Vth is measured as Vth2. (4) The data of page 3 is read, and the average value of the 10th largest threshold voltage Vth is measured as vth3. (5) The data of page 4, page 8, page 12, ..., page 56 is read, and the average value of the 10th largest threshold voltage Vth is measured as the threshold voltage Vthee of the example A. (6) The data of page 5, page 9, page 13, ..., page 57 is read, and the average value of the 10th largest threshold voltage Vth is measured as the threshold voltage Vtheo of the example B. (7) The data of page 6, page 10, page 14, ..., page 58 is read, and the average value of the 10th largest threshold voltage Vth is measured as the threshold voltage Vthoe of the example C. (8) The data of page 7, page 11, page 15, ..., page 59 is read, and the average value of the 10th largest threshold voltage Vth is measured as the threshold voltage Vthoo of the example D. (9) The data of the page 60 is read, and the average value of the 10th largest threshold voltage Vth is measured as Vth60. (10) The data of the page 61 is read, and the average value of the 10th largest threshold voltage Vth is measured as Vth61. (11) The data of the page 62 is read, and the average value of the 10th largest threshold voltage Vth is measured as Vth62. (12) The data of the page 63 is read, and the average value of the 10th largest threshold voltage Vth is measured as Vth63.

Next, the offset value is determined based on the threshold voltage Vth measured in step S3, and the determined offset value is stored as a part of the model data such as the erase voltage in the memory register 16 in step S4, and the end is ended. Said processing. Then, after all the operation parameters (model data) written, erased, and read are gathered, the data of the memory register 16 is written to the fuse data storage area of the memory cell array.

Specifically, for example, when the measured data is Vth1=Vth63=0.5 V, Vth0=Vth62=0.6 V, Vth2=Vth3=Vth60=Vth61=1.2 V, Vthee=0.8 V, Vtheo=0.9 V, Vthoe=1.1 V, When Vthoo=0.95 V, the bias value can be obtained by Vea=0.6 V, Veb=0.0 V, Vee=0.3 V, Veo=0.1 V, Vec=0.0 V, Ved=0.6 V, if these voltages are applied By erasing, the threshold voltage Vth can be equalized after the substantially erasing, thereby suppressing the unevenness to approximately 0.1 V. (The deviation of the threshold in Figure 3 can be removed.)

This means that the slowest erase is Vth2, Vth3, Vth60, Vth61=1.2 V, and the erase speed of Vthee=0.8 V is 0.4 V faster, so instead 0.3 V is applied to the voltage Vee to make the erase slower. The reason why it is not 0.4 V is that the erase of the memory cell of the threshold voltage Vtheo of the same word line becomes shallow, so it is compatible with this aspect.

Here, for example, when Vth0 and Vth1 on the same word line are considered, when the setting is Vea=0.6 V, the threshold voltage Vth1 (word line WL0, odd bit line, page 1) is deepened after erasing. 0.1 V, but if you compensate for this, just set the verification voltage of page 1 to 0.1 V instead of 0 V.

Then, data erasing is performed by substituting these conditions, and the erasing voltage Vep for erasing the verification voltage EV for a plurality of blocks is measured, and the erasing start voltage Vstart is set to, for example, Vep-4 V. Then, the offset value and the erase start voltage Vstart are stored in the memory register, thereby ending the characteristic measurement and parameter setting of the erase.

Here, the erasing characteristic measurement is based on the point at which the threshold value Vth of 50% of the page 32 reaches 0 V or less, and the threshold value of the bit of each page is measured, and the bit has the 10th largest. The present invention is not limited thereto, and for example, it is also possible to erase the 99% of the fastest page to a point such as a threshold of 0 V or less, or to measure the equivalent for each page. The 3σ bit is used to reach the erase voltage below the threshold of 0 V. Further, the step voltage is set to 0.2 V, but the following method is also preferable, that is, starting with 0.5 V first, and becoming 0.1 V after approaching the target value to improve the accuracy.

Fig. 8 is a flow chart showing the processing when the power supply for the flash memory of Fig. 4 is turned on. In step S11 of FIG. 8, when the power is turned on, the control circuit 11 reads the model data from the fuse data storage area of the memory cell array and transfers it to the memory register 16 for storage. Then, in step S12, the model data such as the erase voltage is read from the memory register 16, and the read model data is set as the operating condition to cause the memory to operate.

As described above, according to the present embodiment, data is erased by using different word line voltages on even-numbered word lines and odd-numbered word lines, so that data erasing can be performed based on the threshold voltage characteristics of data erasing. Therefore, it is possible to optimally erase data with high precision compared to conventional techniques.

Here, the conventional erasing is to apply an erase voltage to a block in which data has been written, that is, a memory cell is a cell in which the data is 1 (erased state) and a cell whose data is 0 (write state). An erase voltage is applied in a state in which the element mixture exists. In the FN tunneling effect, although the threshold after erasing is not determined by the initial threshold, the effect of the coupling between the floating gates remains, so it is not perfect. Therefore, as shown in the pre-erase write processing of FIG. 9, writing is performed before erasing (S21), and the erase voltage is applied and verification is repeated (S22). Thereby, the threshold value before the application of the erasing voltage is approximately coincident, whereby the uniformity of the threshold distribution after erasing can be further improved. The pre-erase write does not require verification, and all word lines are selected for processing, so that it can be completed in about 100 microseconds, and the erasure is about 2 milliseconds, so it is not a problem.

In the above embodiments, the NAND flash memory has been described. However, the present invention is not limited thereto, and can be applied to a non-no or non-no flash type using a double patterning technique. In various non-volatile semiconductor memory devices such as memory.

In the above embodiment, the control circuit 10 erases the data by applying a predetermined erase voltage to a predetermined block of the memory cell array. However, the present invention is not limited thereto, and for example, a NOR flash is used. In various nonvolatile semiconductor memory devices such as a memory, data can be erased by applying a predetermined erase voltage to a predetermined area of the memory cell array.

In the above embodiment, an even number of bit lines may be an even number of global bit lines and an odd number of bit lines may be an odd number of global bit lines for the applied voltage of the bit lines at the time of erasing. .

The present invention is different from Patent Document 1 to Patent Document 5. The present invention is characterized in that data is erased by using different word line voltages on even-numbered word lines and odd-numbered word lines, but in the patent document 1 to 5, the features described in the patent document 5 are neither disclosed nor implied. [Industrial availability]

As described in detail above, the erasing action of the non-volatile semiconductor memory device to which the double patterning technique is applied can be optimized as compared with the prior art of the present invention.

1‧‧‧Semiconductor substrate

2‧‧‧N well

3‧‧‧P trap

10‧‧‧Memory cell array

11‧‧‧Control circuit

12‧‧‧ column decoder

13‧‧‧High voltage generating circuit

14‧‧‧Page Buffer Circuit (PB)

14b‧‧‧Latch Circuit (L2)

15‧‧‧ line decoder

16‧‧‧Memory Register

17‧‧‧Command register

18‧‧‧ address register

19‧‧‧Action Logic Controller

50‧‧‧ Data input and output buffer

51‧‧‧ Data input and output terminals

52‧‧‧Information line

53‧‧‧Control signal input terminal

BLSe, GBL0, GBL2, GBL4‧‧‧ even bit lines

BLSo, GBL1, GBL3, GBL5‧‧‧ odd bit lines

DWLD, DWLS‧‧‧ virtual character line

FL‧‧‧Floating state

GBL‧‧‧ bit line

MC‧‧‧NAND type memory cell string

P0, P1, Pn, Pn+1, P62, P63‧‧‧ pages

S1~S4, S11, S12, S21, S22‧‧‧ steps

SGD, SGS‧‧‧ select gate line

SL‧‧‧ source line

VDWL, VDWL1, VDWL2, Vea, Veb, Vec, Ved, Vee, Veo, VERS‧‧ ‧ voltage

WL, WL0~WL31‧‧‧ character line

1 is a longitudinal cross-sectional view showing an applied voltage of each electrode at the time of erasing data of a flash memory of a conventional example. Fig. 2 is a view showing the erasing characteristic of the flash memory by double patterning, that is, the threshold voltage Vth with respect to the page number. 3 is a graph showing a distribution characteristic of a memory cell by double patterning, that is, a threshold value of a memory cell with respect to an odd number of word lines and an even number of word lines. 4 is a block diagram showing an example of the configuration of a flash memory according to an embodiment of the present invention. Fig. 5 is a vertical cross-sectional view showing an applied voltage of each electrode when the data of the flash memory of Fig. 4 is erased. Fig. 6 is a circuit diagram showing a verification operation at the time of erasing data of the flash memory of Fig. 4; FIG. 7 is a flow chart showing a wafer test process for the flash memory of FIG. 4. Fig. 8 is a flow chart showing the processing when the power supply for the flash memory of Fig. 4 is turned on. Fig. 9 is a flow chart showing the pre-erase write processing for the flash memory of Fig. 4.

1‧‧‧Semiconductor substrate

2‧‧‧N well

3‧‧‧P trap

DWLD, DWLS‧‧‧ virtual character line

FL‧‧‧Floating state

GBL‧‧‧ bit line

SGD, SGS‧‧‧ select gate line

SL‧‧‧ source line

VDWL1, VDWL2, Vea, Veb, Vec, Ved, Vee, Veo, VERS‧‧‧ voltage

WL0~WL31‧‧‧ character line

Claims (13)

A non-volatile semiconductor memory device includes a control circuit for defining a region of a memory cell array including memory cells disposed at respective intersections of a plurality of word lines and a plurality of bit lines Applying a prescribed erase voltage to erase the data, and the non-volatile semiconductor memory device is characterized in that the control circuit has an even number of word lines other than the edge end of the memory cell array Applying mutually different word line voltages to the odd word lines, applying a voltage different from the word line voltage to the word lines at the edge of the memory cell array, and applying the voltage to the memory cell array The voltage applied to the word line at the edge of both ends is the same, and the erase voltage is applied to the memory cell to erase the data. The non-volatile semiconductor memory device according to claim 1, wherein a word line voltage for an odd number of word lines other than an edge end portion of the memory cell array is set higher or lower than The word line voltage of an even number of word lines other than the edge of the memory cell array. The non-volatile semiconductor memory device of claim 1, wherein the word lines of the edge portions of the memory cell array are at least one adjacent to a selected gate line or a virtual word line at both ends. The root of the word line. The non-volatile semiconductor memory device of claim 1, wherein the control circuit performs the memory cells of the even-numbered bit lines and the memory cells of the odd-numbered bit lines under different verification conditions. Verification of the data erasure. The non-volatile semiconductor memory device of claim 4, wherein The verification condition is set such that memory cells for even bit lines and memory cells of odd bit lines make at least one of the following conditions different: (1) word line voltage; (2) bit bit The discharge time of the bit line when the line is precharged to read the data of the read data; (3) the charging time of the bit line for reading the data when the source line is charged during the reverse data reading; (4) pre-charging time of the bit line when the bit line is precharged to read the data of the read data; and (5) the bit at the time of reading the data of the read data by precharging the bit line The sense voltage of the line. The non-volatile semiconductor memory device according to claim 1, wherein the word line voltages different from each other are based on data erased in a wafer test of the non-volatile semiconductor memory device. The threshold voltage is determined. The non-volatile semiconductor memory device of claim 1, wherein the word line voltages different from each other are based on data measured in a wafer test applied to the non-volatile semiconductor memory device. The erase voltage of the same threshold voltage is determined in addition to the time. The non-volatile semiconductor memory device according to claim 6, wherein the threshold voltage at the time of erasing the data measured in the wafer test is determined by the following four examples: (1) Examples of even-numbered word lines and even-numbered bit lines; (2) Examples of even-numbered word lines and odd-numbered bit lines; (3) Examples of odd-numbered word lines and even-numbered bit lines And (4) examples of odd-numbered word lines and odd-numbered bit lines. The non-volatile semiconductor memory device of claim 1, wherein the erase voltage is a well applied to the array of memory cells. The non-volatile semiconductor memory device of claim 6, wherein the determined mutually different word line voltages are after being stored in a portion of the memory cell array, the non- The power of the volatile semiconductor memory device is read from the memory cell array when turned on and used during erasing of the data. The non-volatile semiconductor memory device according to claim 1, wherein all memory cells of the predetermined area are written before the erasing process is performed. A method for erasing a non-volatile semiconductor memory device, the non-volatile semiconductor memory device comprising a control circuit, the control circuit comprising a plurality of word lines and a plurality of bit lines at each intersection a prescribed area of the memory cell array of the memory cell applies a prescribed erase voltage to erase the data, and the erase method of the non-volatile semiconductor memory device is characterized in that the control circuit is Even-numbered word lines and odd-numbered word lines other than the edge end portion of the memory cell array are applied with mutually different word line voltages, and the word lines of the edge portions of the memory cell array are applied to The voltage of the word line voltage is different And the voltage applied to the word line at the edge of the edge of the memory cell array is the same, and the erase voltage is applied to the memory cell to erase the data. The erasing method of the nonvolatile semiconductor memory device according to claim 12, wherein a word line voltage of an odd number of word lines other than an edge end portion of the memory cell array is set to be higher than or A word line voltage lower than an even number of word lines other than the edge end of the memory cell array.