TWI586171B - Image sensor with shared column readout circuis - Google Patents

Description

Image sensor for shared line read circuit

The present invention relates to an image sensor and refers to an image sensor having a shared line read circuit architecture.

Complementary Metal-Oxide-Semiconductor (CMOS) image sensors are read in a column-by-column manner when reading pixel data. When reading a column of pixels, each pixel is connected to a corresponding column readout circuit, wherein the row read circuit mainly includes an analog to digital conversion module (Analog-to-digital) The converter (ADC) is used to convert the signal on the pixel into an analog form for processing by the back end image signal processor. Taking a pixel array having M x N pixels as an example, the pixel array requires N row read circuits to process signals on N pixels. Since the row read circuit occupies a considerable area on the CMOS image sensor, the architecture of the shared row read circuit is employed in some designs. That is, several pixels in each column of pixels share the same row read circuit. Please refer to the example shown in Figure 1. In part (a) of Fig. 1, in which two adjacent pixels in each column of pixels share one row reading circuit, a pixel array having M x N pixels P requires N/2 row reading circuits. Further, in part (b) of Fig. 1, each row of pixels in each column shares one row reading circuit, and a pixel array having M x N pixels requires only N/4 row reading circuits. Through this architecture, the number of row read circuits can be effectively reduced. However, due to the shared row read circuit, it is necessary to control the transfer gate in each pixel through the transfer gate control signals having different timings, staggering the timing of the connection to the row read circuit. In the example of part (a), each column of pixels requires two different timing transmission gate control signals (TG_i_1 and TG_i_2); in the example of part (b), each column of pixels requires four different timing transmission gates. Control signal (TG_i_1~TG_i_4). However, today's CMOS image sensors have increasingly higher pixel densities, making the spacing between pixels and pixels quite small, and it is quite difficult to place more signal lines between pixel columns. On the other hand, when more different timing signals are needed, it means that the related signal generating circuits are more complicated and larger in area, which is quite unfavorable for the overall design.

In order to solve the above problems, the present invention provides an innovative shared line read circuit architecture, which can effectively reduce the need for transmission gate control signals required for each column of pixels. In addition, combined with the architecture of the present invention and the special control signal timing, the capacity of the buffer memory required in the row read circuit can also be reduced.

An embodiment of the present invention provides an image sensor, the image sensor includes: a pixel array having M columns of pixels, each column of pixels further comprising N pixels, each pixel including a transmission gate; a signal generation For generating M sets of transmission gate control signals, each group having a first transmission gate control signal and a second transmission gate control signal having different timings, respectively, for controlling the transmission gates in each column of pixels, wherein the a transmission gate control signal and the second transmission gate control signal respectively cause a transmission gate of a different N/2 pixels in each column of pixels to be turned on; a plurality of bit lines, each of which is selectively coupled to each column a transfer gate of one of the two pixels in the pixel; and a plurality of row read circuits, each of which is selectively coupled to one of the two bit lines of the plurality of bit lines, and the read is coupled The signal on the bit line obtains an integral data of one pixel, wherein each row reading circuit continuously reads the N/ after the first transmission gate control signal turns on the transmission gate of the N/2 pixels. Two of the 2 pixels Integration of pixel data.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

2 is a schematic diagram of an embodiment of an image sensor of the present invention, which illustrates how the present invention uses only two different timing transmission gate control signals, thereby allowing four pixels per column in the pixel array. The pixels share the architecture of a row read circuit. Please refer to the timing diagram shown in Figure 3. When the pixels 120_i_0~120_i_3 of the i-th column are read, the selection signal SEL_0 is first pulled up, so that the common terminal A of the pixels 120_i_0 and 120_i_1 is connected to the upper bit line BL0 through the source follower 130_0, and the pixels 120_i_2 and 120_i_3 are made. The common terminal B is connected to the upper bit line BL1 through the source follower 130_1. At the time point T1, the reset signal RST_0 is raised, turning on the reset switch 140_0, and at this time, the terminal A and the end point B are respectively charged to the reference voltage VDD. After a period of time, the charging is completed and the reset signal RST_0 is lowered. The switching signal SW0 then turns on the bit line switch 160_0, causing the row read circuit 150_0 to read the reset data associated with the pixel 120_i_0 from the bit line BL0. Then, the switching signal SW1 turns on the bit line switch 160_1, and causes the row read circuit 150_0 to read the reset data from the bit line BL1 to the pixel 120_i_2. After the reset data of the pixels 120_i_0 and 120_i_2 are read, the transfer gate control signal TG_i_0 is pulled up, and the transfer gates 170_i_0 and 170_i_2 are turned on. The integrated charge is transferred from the pixels 120_i_0 and 120_i_2 to the endpoint A and the endpoint B. When the transfer gate control signal TG_i_0 is lowered, the transfer gates 170_i_0 and 170_i_2 are turned off, and the charge transfer of the pixels 120_i_0 and 120_i_2 is ended. The signals on the endpoints A and B are transmitted to the bit lines BL0 and BL1 through the source followers 130_0 and 130_1, respectively. Then, the switching signal SW0 is turned on to turn on the bit line switch 160_0, and the switching signal SW1 is turned on to the bit line switch 160_1. Then, the integrated data of the pixels 120_i_0 and 120_i_2 can be read out by the line reading circuit 150_0 to complete the pixel 120_i_0. Read with 120_i_2.

At time T7, the reset signal RST_0 is again raised, turning on the reset switch 140_0 and the reset switch 140_1 again, charging the terminals A and B to the reference voltage VDD. Then, the reset signal RST_0 is lowered. The switching signal SW0 then turns on the bit line switch 160_0, causing the row read circuit 150_0 to read the reset data of the pixel 120_i_1. Then, the switching signal SW1 turns on the bit line switch 160_1, and causes the line read circuit 150_0 to read the reset data of the pixel 120_i_3. After the reset data of the pixels 120_i_1 and 120_i_3 are read, the transfer gate control signal TG_i_1 is raised, and the transfer gates 170_i_1 and 170_i_3 are turned on, so that the pixels 120_i_1 and 120_i_3 start to perform charge transfer. When the transfer gate control signal TG_i_1 is lowered, the charge transfer ends. The integration results on Endpoint A and Endpoint B are transferred to bit lines BL0 and BL1 through source followers 130_0 and 130_1, respectively. Then, the switching signal SW0 is turned on by the bit line switch 160_0 and the switching signal SW1 is turned on by the bit line switch 160_1, so that the integrated data of the pixels 120_i_1 and 120_i_3 can be read by the line reading circuit 150_0, thereby completing the pixel. Reading of 120_i_1 and 120_i_3.

In the above manner, the pixels of each column need only pass through two different timing transmission gate control signals, for example, the signals TG_i_0 and TG_i_1 control the pixels of the ith column, or the signals TG_i+1_0 and TG_i+1_1 control the i+th A column of pixels allows four pixels in each column of pixels to share a row read circuit. In this way, the layout area of the signal line for transmitting the gate control signal can be reduced. It should be noted that since the pixels 120_i_0 and 120_i_1 and the pixels 120_i+1_0 and 120_i+1_1 are connected to the bit line BL0 through the same source follower 130_0. Therefore, although the pixels 120_i_0 and 120_i_1 and the pixels 120_i+1_0 and 120_i+1_1 belong to different columns, respectively, the timings of the transmission gate control signals TG_i_0 and TG_i_1 need to be different from the timings of the transmission gate control signals TG_i+1_0 and TG_i+1_1. Avoid conflicts on signal reading. In addition, due to the reduction in the number of transmission gate control signals required for each column of pixels, the circuit area and power consumption of the signal generation circuit 190 which generates the transmission gate control signal is only half that of the conventional signal generation circuit. It should be understood from the above description that if the number of pixels of a column of pixels in the pixel array is N, the number of row read circuits required for the entire pixel array is N/4, and the number of required bit lines is N. /2.

In addition, although the above description is only for the four pixels of the i-th column in the pixel array, the integration operation and the result reading of the other pixels in the i-th column can be controlled by the same transmission gate control signals TG_i_0 and TG_i_1. In addition, the reset signal RST_0 can also control the remaining pixels of the i-th column to be reset, and the selection signal SEL_0 can also allow the pixels of the i-th column and the i+1th column to be connected to corresponding corresponding sources through their respective source followers. Bit line. Those skilled in the art should be able to understand the same operation mode of other column pixels through the above description, so as to understand the overall view of the present invention.

In the above description, it is assumed that the reading of the pixel data is performed based on a digital correlation double sampling sampling architecture. This architecture will sample the signal of each pixel twice, after relevant calculations, and finally get the sensitivity value of the pixel, which can effectively eliminate the noise. In this architecture, the row read circuit reads the reset switch to charge the endpoint, the signal on the endpoint as the reset data, and the signal generated by the pixel at the endpoint during the integration period as the integral data. After that, the two data are processed through the image sensor to obtain the sensitivity value of the pixel. When the pixel array of the present invention is applied under such a sampling architecture, the capacity of the buffer memory can be reduced compared to the conventional architecture. For details, please refer to the pixel array of FIG. 2, the timing chart of FIG. 3, and the architectural diagram of the embodiment of the row read circuit shown in FIG.

At the time point T1, the reset signal RST_0 is raised to charge the terminals A and B to the reference voltage VDD, respectively. After the reset signal RST_0 is lowered, signals corresponding to the reset data of the pixels 120_i_0 and 120_i_2 are respectively obtained on the bit lines BL0 and BL1. Next, at time point T2, the switching signal SW0 turns on the bit line switch 160_0, and connects the bit line BL0 to the row read circuit 150_0. The row read circuit 150_0 converts the signal on the bit line BL0 into a digital form through the internal analog to digital conversion processing module 150_0_1. Thereby, the reset data corresponding to the pixel 120_i_0 is obtained and stored in the buffer memory 150_0_2. At the time point T21, the scan signal hscan is raised, thereby reading the reset data of the pixel 120_i_0 in the buffer memory 150_0_2 into the image signal processor 200. Similarly, at time T3, after the switching signal SW1 turns on the turn-on bit line switch 160_1, the analog-to-digital conversion processing module 150_0_1 can obtain the reset data about the pixel 120_i_2, and store it in the buffer memory 150_0_2, etc. After the signal hscan is once again raised, the reset data of the pixel 120_i_2 is read to the image signal processor 200.

At the time point T4, the transmission gate control signal TG_i_0 is raised. At this time, the pixels 120_i_0 and 120_i_2 start to perform charge transfer on the terminal A and the end point B. When the transmission gate control signal TG0 is lowered, the charge transfer ends, respectively. Signals relating to the integrated data of the pixels 120_i_0 and 120_i_2 are obtained on the bit lines BL0 and BL1. Then at time point T5, the switching signal SW0 turns on the bit line switch 160_0, and the analog-to-digital conversion processing module 150_0_1 converts the signal on the bit line BL0 into a digital signal. The integral data corresponding to the pixel 120_i_0 is obtained and stored in the buffer memory 150_0_2. When the scan signal hscan is raised, the integral data of the pixel 120_i_0 in the buffer memory 150_0_2 is read into the image signal processor 200. Similarly, at time T6, after the switching signal SW1 turns on the turn-on bit line switch 160_1, the row read circuit 150_0 can obtain the integral data about the pixel 120_i_2, and store it in the buffer memory 150_0_2, and the scan signal hscan is boosted. After that, the credit data of 120_i_2 is read into the video signal processor 200. In this way, the reading of the pixels 120_i_0 and 120_i_2 can be completed, and the respective reset data and integral data are obtained. Thereafter, the image signal processor 200 performs correlation calculation to obtain the photosensitive values of the pixels 120_i_0 and 120_i_2. It should be noted here that the above description is explained by the viewpoint of the row reading circuit 150_0, but the entire image sensor actually includes other row reading circuits 150_1~150_(N-1)/4 ( Assuming that each column has N pixels, each time the scan signal hscan is raised, the data stored in the buffer memory in each row read circuit is read into the image signal processor 200. Therefore, the rise of the scan signal hscan causes the reset data or credit data of N/2 pixels in each column of pixels to be read into the image signal processor 200.

In addition, in order to maintain signal stability at the input of the line read circuit, it is ensured that the settling time of the signal on the input can be in a desired range. Therefore, in an embodiment, the present invention additionally designs a level maintaining circuit, please refer to the timing diagram of FIG. 3 and the architecture diagram of FIG. When the signals SW0 and SW1 are lowered, the signal SW_dmy will turn on the switch 212 in the level maintaining circuit 210, so that the level of the input terminal IN of the line reading circuit 150_0 can maintain a certain value. The switch 212 in the level maintaining circuit 210 is connected to the reference voltage VREF through the resistor 214, so that the level of the input terminal IN is maintained. In addition, when the level is maintained, the level of the input terminal IN may trigger the analog to digital conversion processing module 150_0_1 to perform signal conversion, and the result is written into the buffer memory 150_0_2, causing the buffered data in the buffer memory 150_0_2 to be buffered. Destruction, therefore, the isolation signal dis_trig is pulled up while maintaining the level, and the switch 150_0_3 between the analog to digital conversion processing module 150_0_1 and the buffer memory 150_0_2 is disconnected to protect the buffered data.

In the present invention, the capacity of the buffer memory 150_0_2 of the row read circuit 150_0 only needs to coincide with the amount of data outputted each time by the analog to digital conversion module 150_0_1. Please refer to FIG. 5A, which illustrates the timing relationship between the output of the analog-to-digital conversion module 150_0_1 and the scan signal hscan. As can be seen from the relationship shown in the figure, every time a reset data or integral data (RST#1, RST#2, SIG#1, SIG#2) of one pixel is obtained, the scan signal hscan rises immediately and will be buffered. The buffered data of the memory 150_0_2 is read into the image processing circuit 200. Therefore, the buffer memory 150_0_2 only needs to sequentially store 120_i_0 reset data (RST#1), 120_i_2 reset data (RST#2), 120_i_0 integral data (SIG#1), and 120_i_2 credit data (SIG). #2). If the analog to digital conversion module 150_0_1 has a resolution of 12 bits, the buffer memory 150_0_2 only needs 12 bits wide.

In the architecture of the conventional shared line read circuit, since a plurality of pixels share a bit line connected to the row read circuit, each time the shared line read circuit reads the signal on the bit line, it will be destroyed. The signal on the bit line, therefore, the reset of different pixels or the integration of different pixels must be performed at different times, resulting in the inability to continuously read the reset data and integral data of different pixels as in the present invention (please refer to the time in Figure 3). Points T1 and T4 share the pixels 120_i_0 to 120_i_03 of the same row read circuit 150_0, and two pixels respectively start to be reset and integrated. Figure 5B illustrates the timing relationship between the analog-to-digital conversion module output and the scan signal under the conventional shared architecture. In Figure 5B, the analog-to-digital conversion module outputs one pixel of reset data (RST#1), followed by the integral data (SIG#1), and then another pixel's reset data (RST#2). ) and the point data (SIG#1) are different from the timing of the present invention. The reason why the present invention can continuously read the reset data and the integral data of the pixel is that the reset data of different pixels (eg, 120_i_0 and 120_i_2) are respectively placed on different bit lines (BL0 and BL1), so There is no need to reset again between successive reads, and the credit data is placed on different bit lines, so there is no need to integrate again between consecutive reads. In the conventional architecture, the buffer memory requires four memory slots (BANK0~3), which store the reset data and integral data of the first pixel and the reset data and integral data of the second pixel, respectively. After the scan signal hscan rises, the reset data and the integral data of the first pixel are read to the image signal processor, and the reset data and the integral data of the second pixel are moved to the weight of the first pixel stored. Set the data slot of the data and integral data (BANK2~3), and continue to write the reset data and integral data of the third pixel in the buffer memory (BANK0~1), and then repeat. It can be seen that the buffer memory capacity of this case is only 1/4 of the conventional architecture.

In the above description, although the description is based on the digital correlation double sampling sampling architecture, this is not a limitation of the application of the present invention. In other embodiments of the present invention, the row reading circuit may also skip the read reset. The steps of the data, only the point data is read.

In summary, the present invention effectively controls the number of transmission gate control signals required for each column of pixels in the architecture of the shared row read circuit, and also reduces the buffer memory capacity required in the row read circuit. These architectural simplifications also effectively reduce the overall power consumption of the image sensor.

The "an embodiment" referred to above means that a particular feature, structure or characteristic described for the embodiment is included in at least one embodiment of the invention. Furthermore, "an embodiment" as used in the different paragraphs herein does not represent the same embodiment. Therefore, while the various structural features or methodological acts are described above, respectively, for the various embodiments, it should be noted that these various features can be implemented in the same particular embodiment. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

120_i_0, 120_i_1, 120_i_2, 120_i_3, 120_i+1_0, 120_i+1_1, 120_i+1_2, 120_i+1_3‧‧ ‧ pixels
110_i_0, 110_i_1, 110_i_2, 110_i_3, 110_i+1_0, 110_i+1_1, 110_i+1_2, 110_i+1_3‧‧‧ photosensitive element
130_0, 130_1‧‧‧ source follower
BL0, BL1‧‧‧ bit line
140_0, 140_1‧‧‧Reset switch
150_0, 150_1‧‧‧ lines read circuit
150_0_1‧‧‧ Analog to Digital Conversion Processing Module
150_0_2‧‧‧Buffered memory
150_0_3, 180_0, 180_1‧‧ switch
160_0, 160_1‧‧‧ bit line switch
170_i_0, 170_i_1, 170_i_2, 170_i_3‧‧‧ transmission gate
190‧‧‧Signal Generator
200‧‧‧Image Signal Processor
210‧‧‧Standing Stabilization Circuit
212‧‧‧ switch
214‧‧‧resistance

Figure 1 illustrates a conventional pixel array having a shared row read circuit architecture. 2 is a block diagram of an image sensor according to an embodiment of the present invention. Figure 3 is a timing diagram corresponding to each control signal in Figure 2. Figure 4 is a block diagram of a row read circuit in accordance with one embodiment of the present invention. The 5A and 5B diagrams respectively show the buffer memory configuration mode and the data output timing of the architecture of the present invention and the conventional architecture.

120_i_0, 120_i_1, 120_i_2, 120_i_3, 120_i+1_0, 120_i+1_1, 120_i+1_2, 120_i+1_3‧‧ ‧ pixels

110_i_0, 110_i_1, 110_i_2, 110_i_3, 110_i+1_0, 110_i+1_1, 110_i+1_2, 110_i+1_3‧‧‧ photosensitive element

130_0, 130_1‧‧‧ source follower

BL0, BL1‧‧‧ bit line

140_0, 140_1‧‧‧Reset switch

150_0‧‧‧ line read circuit

160_0, 160_1‧‧‧ bit line switch

170_i_0, 170_i_1, 170_i_2, 170_i_3‧‧‧ transmission gate

190‧‧‧Signal Generator

Claims (10)

An image sensor comprising: a pixel array having M columns of pixels, each column of pixels further comprising N pixels, each pixel comprising a transmission gate; a signal generator for generating M sets of transmission gate control signals, Each of the first transmission gate control signal and the second transmission gate control signal having different timings are respectively used to control the transmission gates in each column of pixels, wherein the first transmission gate control signal and the second transmission gate control The signals respectively cause the transmission gates of different N/2 pixels in each column of pixels to be turned on; the plurality of bit lines, each of the bit lines being selectively coupled to the transmission gate of one of the two pixels in each column of pixels; And a plurality of row read circuits, each of which is selectively coupled to one of the two bit lines of the plurality of bit lines, and reads signals of the coupled bit lines to obtain at least one pixel An integral data, wherein each row reading circuit continuously reads out the integral data of two pixels of the N/2 pixels after the first transmission gate control signal turns on the transmission gate of the N/2 pixels . The image sensor of claim 1, further comprising: a plurality of reset switches, each coupled to two pixels in each column of pixels and two pixels in each column of pixels, the reset switch When turned on, a common endpoint of the four connected pixels is charged. The image sensor of claim 2, wherein each row reading circuit is after the reset switch is turned on, and before the first transmission gate control signal turns on the transmission gate of the N/2 pixels in a column of pixels And resetting the reset data of two of the N/2 pixels in succession. The image sensor of claim 1, further comprising: a plurality of bit line switches, each of the bit line switches being coupled to one of the plurality of bit lines, and each of the two bit line switches Connected to a row read circuit, the row read circuit can select one of the two bit lines coupled, and read the signal on the bit line. The image sensor of claim 4, wherein each row of the read circuit comprises: an analog to digital conversion module coupled to the different one of the plurality of bit line switches, each group of bit line switches, each group The bit line switch includes a first bit line switch and a second bit line switch, wherein the first bit line switch and the second bit line switch are turned on at different times, so that the analog to digital conversion module Connecting to different bit lines in the plurality of bit lines at different times, and generating a conversion output according to the signal on the connected bit line, the conversion output includes the integral data of the pixel; and a buffer memory The analog output to the digital conversion module is configured to temporarily store the converted output, wherein the buffer memory has the same capacity as the converted output data. The image sensor of claim 5, further comprising: an image signal processor coupled to the plurality of row read circuits, each time the analog input to the digital conversion module in the row of the read circuit generates the conversion After outputting, the image signal processor reads the temporarily stored conversion output from the buffer memory. The image sensor of claim 1, wherein the number of the plurality of row read circuits is N/4. The image sensor of claim 1, wherein the number of the plurality of bit lines is N/2. The image sensor of claim 1, further comprising: a plurality of level maintaining circuits, each of the level maintaining circuits being selectively coupled to one of the plurality of line reading circuits, respectively When the row read circuit is not connected to any bit line, the signal level of one of the input circuits of the row is maintained. The image sensor of claim 1, further comprising: a plurality of source followers, each coupled to two pixels in each column of pixels and two pixels in each column of pixels Transmitting a signal on one of the common endpoints coupled to the four pixels to one of the plurality of bitlines.