TWI584287B - Device and method for improved threshold voltage distribution for non-volatile memory - Google Patents

Description

Apparatus and method for improving valve voltage distribution of non-volatile memory

Embodiments of the present invention relate to semiconductor devices, and more particularly to methods for improving the distribution of programmed valve voltage (Vt) and operation of semiconductor memory devices.

Semiconductor devices are typically classified as volatile semiconductor devices (which require a power supply to maintain the storage of data) or non-volatile semiconductor devices (which retain data even when the power supply is removed). Non-volatile semiconductor devices are, for example, flash memory devices, which are generally classified into NOR or NAND flash memory devices. Such flash memory devices can stack memory cells or layers on top of each other in the form of a 3D architecture. When faster programming and erasing speeds are required, 3D NAND flash memory is typically used, in large part because its serialized serialized structure allows programmatic and erase operations to be performed on A whole string of memory cells. In vertical NAND strings, the layers have different diameters because of the non-standard etch angle.

As for the 3D NAND flash memory associated with circular memory cells, the difference in diameter includes different stylized performance, which traditionally results in a wider stylized valve voltage (Vt) distribution. When the diameter of the memory cell is larger, the corresponding stylized time is also The longer it is. In this regard, the challenges presented by large diameters are, for example, insufficiently stylized in stylized time. In addition, when a string of memory cells of different diameters is included, the stylized time of the string will be difficult to control. Therefore, how to improve the programmed valve voltage distribution of 3D NAND devices and improve (for example, reduce) the programming time is one of the current topics in the industry.

Embodiments of the present invention provide improved semiconductor device operation, and in particular, a method for controlling a programmed valve voltage distribution corresponding to a non-volatile memory device, such as a 3D NAND flash memory.

In one aspect of the invention, a method for controlling a voltage distribution of a programmed valve corresponding to a non-volatile memory device is presented. In an embodiment, the method includes providing a non-volatile memory device. The non-volatile memory device includes one or more strings, each string including a plurality of memory cells, the memory cells including a first memory cell and a second memory cell. The method further includes performing a function of the non-volatile memory device by applying a first functional voltage to the first memory cell and applying a second functional voltage to the second memory cell. The first functional voltage is different from the second functional voltage.

In another aspect of the invention, a non-volatile memory device in which a programmed valve voltage distribution is controlled is provided. The non-volatile memory device includes a plurality of memory cells along a string. The string includes a channel area. Each memory cell includes a word line located at the string. The memory cells include a first memory cell having a first word line and a second memory cell having a second word line. Applying a first functional voltage to the first memory cell via the first word line and via the second word line pair The second memory cell applies a second functional voltage to which the first memory cell and the second memory cell perform a function. The first functional voltage is different from the second functional voltage.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100, 200‧‧‧ string

10a, 10b, 10c, 10d, WL1~WLN‧‧‧ character lines

Θ‧‧‧outer corner

R _TOP ‧‧‧ top radius

R _BOT ‧‧‧ bottom radius

D _A , D _B , D _C , D _D ‧‧‧ channel width

50‧‧‧Channel area

40‧‧‧Through tunnel

30‧‧‧ Capture layer

20‧‧‧Barrier or dielectric layer

210, 220, 230‧‧‧ memory cells

PV‧‧‧program verify threshold

EV‧‧‧erase verify threshold

V _{WL_1} ~V _{WL_n ‧‧‧} WL1~WLN word line corresponding to the applied voltage

V _g ‧‧‧stylized voltage

△V _g ‧‧‧stylized voltage change

5, 6‧‧‧ valve voltage variation

P‧‧‧ points

400‧‧‧Program

410, 420, 430, 440, 450 ‧ ‧ steps

FIG. 1A is a perspective view showing an example of a non-volatile memory device according to an embodiment of the present invention.

Fig. 1B is a cross-sectional view of the string shown in Fig. 1A.

Figures 2A and 2B illustrate the operation of one of the conventional strings and the wide valve voltage variation that results in memory cells along the string.

3A and 3B are diagrams showing an exemplary operation of a portion of a string in accordance with an embodiment of the present invention, and a corresponding improvement (decrease) in valve voltage variation along the memory cells of the string.

4A and 4B illustrate examples of stylized algorithms in accordance with various embodiments of the present invention.

FIG. 5 is a diagram showing an example of an improved post-programmed valve voltage distribution based on a group according to an embodiment of the present invention.

Figure 6 is a flow chart showing a procedure for controlling voltage distribution in accordance with an embodiment of the present invention.

In the present description, some embodiments of the invention are described in detail with reference to the drawings, but not all embodiments are illustrated in the drawings. In fact, these inventions may use a variety of different variations and are not limited to the embodiments herein. relatively, The disclosure provides these embodiments to meet the statutory requirements of the application. The same reference symbols are used in the drawings to refer to the same or similar elements.

Although specific terms are employed herein, they are used in a generic and descriptive sense and not for the purpose of limitation. Unless the terms have been defined in other ways, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art. It will be further understood that those terms, such as those defined in commonly used dictionaries, should be interpreted as having the meaning commonly understood by those skilled in the art to which the invention pertains. It will be further understood that those terms, such as those defined in commonly used dictionaries, should be interpreted as having an explanation consistent with the meaning of the related art and the disclosure. Unless generally stated so in this disclosure, these commonly used terms are not to be interpreted in an idealized or overly formal sense.

As used herein, "gate structure" refers to an element in a semiconductor device, such as a memory device. Non-limiting examples of memory devices include flash memory devices (e.g., NAND flash memory devices). Undefined Erasable Programmable Read-Only Memory (EPROM) and Electrically Erasable Programmable Read-Only Memory (EEPROM) flash memory devices example. The gate structure of the present invention can be a collection of gate structures that can operate in a memory device or a subset of one or more components of the gate structure.

The term "non-volatile memory device" as used herein refers to a semiconductor device that can store information even after the power is removed. Non-volatile memory devices include But not limited to, Mask Read-Only Memory, Programmable Read-Only Memory, Erasable Programmable ROM Electrically Erasable Programmable Read-Only Memory, and flash memory, such as NAND and NOR flash memory.

A "substrate" as used herein may include any underlying material on which devices, circuits, epitaxial layers or semiconductors may be formed. In general, the substrate can be used to define a layer underlying the semiconductor device or to form a base layer of the semiconductor device. The substrate can comprise one or any combination of germanium, doped silicon, germanium, silicon germanium, semiconductor compound, or other semiconductor materials.

The gate structure (e.g., non-volatile memory device) and method of the present invention improves the programmed valve voltage distribution of a non-volatile memory device, such as a 3D NAND flash memory, for random access. To this end, the stylized speed of the non-volatile memory device will increase based on the non-uniformly programmed voltage.

The present invention is directed to a variety of functions, including stylization (e.g., PGM), erasure (e.g., ERS), reading (e.g., READ), or any other function that applies voltage to multiple cells on the same string. The invention can be implemented in different types of devices and/or memory cells, including 3D NAND flash memory, other non-volatile memory devices (such as 3D NOR, 3D ROM, 2D NAND or 2D NOR), under regular configuration MOS memory cells or any other device for voltage control in a regular configuration. For illustrative purposes, this article provides an example of stylized 3D NAND flash memory. this Those of ordinary skill in the art will understand how to apply other functions to other types of devices based on the disclosure provided herein.

Figures 1A and 1B illustrate a portion of a non-volatile memory device, such as a 3D NAND flash memory. 1B is a cross-sectional view drawn along line 1A of the AA" line, and the portion of the non-volatile memory device shown includes a vertical string 100 comprising a plurality of memory cells. 100 includes four memory cells, however in various embodiments, string 100 can include more than four or less than four memory cells, depending on the application. In general, string 100 typically includes word lines 10a, 10b, 10c and 10d (e.g., word lines corresponding to respective memory cells) envelop the cylindrical portion around them. Note that although the string 100 is generally cylindrical, it is actually a slightly conical shape. The process causes the string to deviate slightly from the standard. Therefore, the outer angle θ is less than 90. This causes the radius R _{TOP of the} string top to be larger than the radius R _BOT at the bottom of the string. Therefore, the channel width of each memory cell in the string 100 is It is different from the adjacent memory cell width (for example, D _A > D _B > D _C > D _D ).

In general, NAND string 100 includes a tunneling layer 40 surrounding the channel region 50, a capture layer 30, and a barrier layer or dielectric layer 20. In various embodiments, tunneling layer 40 can be composed of an oxide and have a thickness of about 5 nm. In some embodiments. The barrier or dielectric layer 20 can be composed of an oxide and have a thickness of about 7 nm. Channel region 50 may comprise a polysilicon material or other suitable material. The word lines (e.g., 10a, 10b, 10c, and 10d) surround the barrier or dielectric layer 20 such that each memory cell has a word line. The word lines (e.g., 10a, 10b, 10c, and 10d) may be comprised of a polycrystalline germanium material, metal, or other suitable material.

2A and 2B illustrate the normal operation of NAND string 200 having three memory cells 210, 220, and 230. In this example, the channel diameter or width W1 of the memory cell 210 is 100 nm, the channel diameter or width W2 of the memory cell 220 is 90 nm, and the channel diameter or width W3 of the memory cell 230 is 80 nm. During the execution of the stylized function, a uniform voltage V _g = 20 V is applied to each memory cell via the respective word line of each memory cell. When the stylized function is executed, the stylized valve voltage distribution is broadened due to the difference in memory cell velocity, which is caused by the difference in channel diameter or width of the memory cell. Therefore, according to the present example, when a uniform voltage of 20 V is applied, because of the difference in width of the three memory cells 210, 220, 230, it is noted that although the memory cell string 200 is generally cylindrical, it is actually slightly conical. The process of etching the string of layers causes the string to deviate slightly from the standard. Therefore, the external angle α is less than 90°. The stylized voltage causes a wide stylized valve voltage variation over time5. As shown, the larger the channel width of a memory cell, the longer the stylization time for that memory cell. Conversely, when the channel width of a memory cell is smaller, the programming time for the memory cell is shorter. As shown in Fig. 2B, at a time of 1 x 10 ^-5 seconds, the stylized valve voltage variation 5 of the three memory cells is approximately 1 to 1.5V. Due to the difference in the width of the three memory channels, the variation between the three memory cells is approximately 20% of the voltage of each memory cell.

The present invention proposes a method of reducing valve voltage variation along a memory cell of a string whereby the valve voltage distribution is made tight. Figures 3A and 3B illustrate an example of the method. FIG. 3A illustrates an example in which the string 200 includes memory cells 210, 220, and 230. In this example, the channel diameter or width of the memory cell 210 is 100 nm, and the channel diameter or width of the memory cell 220 is 90 nm. The memory cell 230 The channel diameter or width is 80 nm. A non-uniform voltage is applied instead of applying a uniform voltage of 20V to the respective memory cells via the corresponding word line. Therefore, the word line of the memory cell 210 applies a stylized voltage V _g = 20 V to the memory cell 210, and the word line of the memory cell 220 applies a stylized voltage V _g = 19.5 V to the memory cell 220, while the memory cell 230 stylized character line is applied a voltage V _g = 19V to the memory cell 230. Thus, the stylized voltage applied to a memory cell having a smaller channel diameter or width is smaller than a programmed voltage applied to a memory cell having a larger channel diameter or width. Figure 3B illustrates the valve voltage variation of the three memory cells as a function of time when operating at a non-uniformly programmed voltage. In particular, the valve voltage variation 6 of the three memory cells is minimal at a time of 1 x 10 ^-5 seconds. For this reason, applying a non-uniform voltage reduces the stylized valve voltage variation between memory cells and reduces the stylization time.

In various embodiments, the stylized voltage applied to each of the cells in a string via the corresponding word line can be used to minimize the valve voltage variation of the memory cells on the string. For example, the voltage of each memory cell programmable string, V _g, may not be the same. In other embodiments, the string can be divided into two segments or groups, wherein the first stylized voltage is applied to a memory cell having a channel diameter or width equal to or greater than a threshold, and a second stylized voltage system A memory cell applied to a channel diameter or width that is less than the threshold. In this example, the first stylized voltage can be greater than the second stylized voltage. In various embodiments, the string can be divided into a plurality of segments or groups using a plurality of threshold widths, wherein the memory cells in each segment or group are provided with a particular stylized voltage.

In various embodiments, the stylized voltage difference applied to the two memory cells may be based on a difference in channel width between the two memory cells. In other embodiments, the stylized voltage difference between two adjacent memory cells may be predetermined rather than based on the difference in channel width between the two adjacent memory cells. For example, in some embodiments, the stylized voltage differences between any two pairs of adjacent memory cells are the same. This refers to a regular stylized voltage distribution. Therefore, in the above example, the difference between the stylized voltages applied to the memory cells 210, 220 is the same as the difference between the stylized voltages applied to the memory cells 220, 230. In other embodiments, the stylized voltages between the first pair of adjacent memory cells and the second pair of adjacent memory cells may be different. This refers to an irregular stylized voltage distribution. For example, the difference between the stylized voltages applied to the memory cells 210, 220 is different from the difference between the stylized voltages applied to the memory cells 220, 230.

Those skilled in the art will appreciate that the programmed voltage distribution applied to a particular string of memory cells can be used to minimize valve voltage variations of the string of memory cells, taking into account other operational constraints. For example, the same stylized voltage distribution can be applied to each of the strings including the semiconductor device. In another example, the device can be limited to provide k (k is a positive integer) different stylized voltages along the strings, but the string can include n (n is a positive integer) different memory cells.

Figures 4A and 4B depict two programmed voltage distributions applied to n memory cells in a string, where ΔV _g is a stylized voltage change. For example, in the examples shown in FIGS. 3A and 3B, the difference between the stylized voltages applied to the memory cells 210 and 220 and the difference ΔV _g between the stylized voltages applied to the memory cells 220 and 230 are 0.5V. As indicated above, in various embodiments, the stylized voltage distribution may be regular (eg, ΔV _g between any two adjacent memory cells or groups may be constant), or the stylized voltage distribution may be irregular (For example, ΔV _g between adjacent memory cells or groups may be different).

Fig. 5 is a diagram showing an example of a string including N (N is a positive integer) memory cells. Each memory cell corresponds to a word line, such as the marks WL1, WL2, WL3, ..., WLN. The N memory cells are divided into n (n is a positive integer less than or equal to N) groups. In some embodiments, multiple memory cells in each group are identical. In other embodiments, some groups may include different numbers of memory cells. However, each group includes at least one memory cell. Each group is applied with a specific stylized voltage. For example, group 1 can include 5 memory cells having the largest channel width among all of the memory cells of the string, and group 2 can include 4 memory cells having the smallest channel width among all of the memory cells along the string. The first stylized voltage can be applied to the memory cells of the group 1 via the corresponding word lines of the memory cells of the group 1, and the second stylized voltage can be corresponding to the word lines corresponding to the memory cells of the group 2. And applied to the memory cells of group 2. In this example, the first stylized voltage is greater than the second stylized voltage.

The right side of Figure 5 shows the effect of the number of groups of n groups of memory cells along the string on the valve voltage distribution, where each group is applied with a specific stylized voltage and each group is applied a different specific Stylized voltage. For example, all of the memory cells in group 1 are applied with a first stylized voltage, and all of the memory cells in group 2 are applied with a second stylized voltage, the first stylized voltage being unequal to the second stylized voltage. When the number of groups of memory cells along the n-group of the string is small, compared to The memory cells of the string are divided into n groups, and dividing the memory cells along the string into n+1 groups can significantly reduce the width of the valve voltage distribution. However, after point P, increasing the number of groups only gently reduces the width of the valve voltage distribution. Thus, in one embodiment, the number of groups used will coincide with point P such that the valve voltage distribution is reduced and the effect of applying a non-uniform stylized voltage on other performance characteristics of the memory device is minimized.

FIG. 6 is a flow chart showing a routine 400 for controlling a programmed valve voltage distribution corresponding to a non-volatile memory device in accordance with an embodiment of the present invention. The process 400 begins at step 410 by providing a memory device (e.g., a 3D NAND flash memory device). The memory device can include one or more strings, each string including a plurality of memory cells, such as shown in Figures 1A and 1B. Each memory cell corresponds to a portion of the channel region of the string. This portion of the channel region has a particular channel width associated with it. At step 420, the number of groups used in each string is determined. For example, in one embodiment, an analysis similar to that shown in Figure 5 can be performed to determine the optimal number of groups for each group. In other embodiments, operational limits or other restrictions may be used to determine the number of groups in each string. At step 430, the memory cells in the string are assigned to the groups. For example, the first five memory cells in a string can be assigned to group 1, the next five memory cells along the string can be assigned to group 2, and so on.

At step 440, the stylized voltage distribution applied to each group is determined. In various embodiments, this step can include analyzing the channel width of the memory cells in the group (eg, comparing the average channel width of the group 1 memory cells with the average channel width of the group 2 memory cells to determine the program between group 1 and group 2) Voltage difference). In various embodiments, the memory cells of the string are not grouped, and the stylized voltage system for each memory cell is determined. In some embodiments, the distribution of stylized voltages may be determined based on operational constraints and/or other limitations.

At step 450, a stylized function is implemented. For example, a stylized voltage can be applied to each memory cell via a corresponding word line to program the memory cells of the string. The stylized voltage applied to each memory cell can be a predetermined distribution based on the stylized voltage. In effect, the stylized voltage distribution is applied to the memory cells along the string such that the stylized voltage applied to one of the memory cells on the string is different from the programmed voltage applied to one of the second memory cells on the string. This reduces the valve voltage variation along the memory cells of the string. It will be appreciated by those of ordinary skill in the art that, as indicated above, the method can be used for a variety of functions, including stylization, erasing, reading, and the application of other voltage systems to the same string of memory cells. In addition, it should be understood that the present invention can be applied to various types of semiconductor devices, including non-volatile memory devices such as 3D NOR, 3D ROM, 2D NAND, 3D NAND, 2D NOR, MOS memory cells in a regular configuration, or Any other device used for voltage control in a regular configuration.

In various embodiments, steps 420-440 may be performed once for the device. Next, at various times during which functions (e.g., PGM, ERS, Read, etc.) are performed, a predetermined voltage distribution is applied as described herein to control valve voltage variations along the memory cells of the strings. For example, a predetermined voltage distribution can be accessed and applied, rather than completing steps 420-440 to determine the voltage distribution each time a function is to be performed.

One aspect of the present invention provides a non-volatile memory device that is planned in accordance with one of the methods of the present invention.

Numerous modifications and other embodiments of the inventions set forth herein will be apparent to those skilled in the <RTIgt; Therefore, it is to be understood that the invention is not intended to be In addition, although the above description and related drawings are described in the context of some illustrative combinations of elements and/or functions, it should be understood that different combinations of elements and/or functions may be made without departing from the following claims. The scope of the scope is provided by alternative embodiments. Here, for example, combinations of elements and/or functions that are different from those detailed above are also considered to be possible in certain of the following claims. Although specific terms are employed herein, they are used in a generic and descriptive sense and are not limiting.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

400‧‧‧Program

410, 420, 430, 440, 450 ‧ ‧ steps

Claims (8)

A method of controlling a valve voltage distribution corresponding to a non-volatile memory device, comprising: providing the non-volatile memory device, the non-volatile memory device comprising a string, the string comprising a first group and a second group, The first group and the second group each include a plurality of memory cells sequentially arranged along the single string; and a function of executing the non-volatile memory device, wherein execution of the function includes the first group All of the memory cells of the group apply the same first functional voltage, and apply the same second functional voltage to all of the memory cells of the second group, the first functional voltage and the second functional voltage different. The method of claim 1, wherein the memory cells of the first group comprise a first memory cell, and the memory cells of the second group comprise a second memory cell, the first The memory cell includes a channel region defined by a first width, the second memory cell including a channel region defined by a second width, the first width being different from the second width. The method of claim 2, wherein the first width is greater than the second width, and the first functional voltage is greater than the second functional voltage. The method of claim 1, wherein the first functional voltage is applied to the memories of the first group through a plurality of first word lines associated with the memory cells of the first group The second functional voltage is applied to the memory cells of the second group through a plurality of second word lines associated with the memory cells of the second group. The method of claim 1, wherein the first functional voltage and the second functional voltage are consistent with a predetermined functional voltage distribution. A non-volatile memory device includes: a string comprising a first group and a second group, the first group and the second group each being arranged along a single string a plurality of memory cells, the memory cells of the first group comprise a plurality of first word lines, and the memory cells of the second group comprise a plurality of second word lines, the same first functional voltage All of the memory cells applied to the first group via the first word lines, and the same second function voltage is applied to all of the memories of the second group via the second word lines And performing a function on the non-volatile memory device, and the first functional voltage is different from the second functional voltage. The non-volatile memory device of claim 6, wherein the string comprises a channel region, the memory cells of the first group comprise a first memory cell, and the memory of the second group The cell includes a second memory cell, the channel region corresponding to a portion of the first memory cell being defined by a first channel width, the channel region corresponding to a portion of the second memory cell being defined by a second channel width, the first The width of one channel is greater than the width of the second channel, and the first functional voltage is greater than the second functional voltage. The non-volatile memory device of claim 6, wherein the string comprises a channel region, the channel region is semi-tapered, and the string further comprises: a tunneling layer disposed at the channel region, A capture layer disposed at the tunneling layer and a barrier layer disposed at the capture layer, the first word lines and the second word lines being disposed at a portion of the barrier layer.