TWI582832B - Method of fabricating an epitaxial layer - Google Patents

Description

Method for manufacturing epitaxial layer

The invention relates to a method for fabricating an epitaxial layer, in particular to a method for fabricating an epitaxial layer which is subjected to an epitaxial process without hydrogen and less than 800 ° C, which can have a square angle of the interface between the epitaxial layer and the substrate .

As the semiconductor process enters the deep micron era, the line width of the semiconductor process has developed to the bottleneck. How to increase the carrier mobility to increase the speed of the MOS transistor and increase the drive current of the transistor component has become more important. . In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, for example, using germanium (SiGe) or germanium carbon. The lattice constant of (SiC) is different from that of single crystal Si, so that the gate channel is subjected to the tension or pressure generated by the lattice strain on both sides, and thus the moving force of the carrier when passing through the gate channel Increase, and make PMOS or NMOS transistors work faster.

One of the methods for straining the germanium lattice of the gate channel is to combine the selective epitaxial growth (SEG) technique, which forms a groove in the substrate on both sides of the gate structure, and then uses an epitaxial process in the groove. An epitaxial layer having the same crystal lattice as the substrate, such as a germanium (SiGe) layer or a germanium carbon (SiC) layer, is formed to stress the gate channel.

Fig. 1 is a schematic cross-sectional view showing a conventional MOS transistor using epitaxial technology. As shown in FIG. 1, the MOS transistor 100 is formed in such a manner that a gate structure 120 is formed on the substrate 110. The gate structure 120 can include a gate dielectric layer 122, a gate electrode 124, and a cap layer 126. Then, a spacer 130 is formed on the side of the gate structure 120, wherein the spacer 130 is, for example, a single layer or a multilayer composite structure such as a hafnium oxide layer or a tantalum nitride layer. Next, the spacers 140 are automatically aligned and etched using the spacers 130 and the gate structures 120 as masks. Thereafter, an 800 ° C epitaxial pre-baking process is introduced to further clean the surface of the recess 140. Finally, an epitaxial layer 150 is formed in the recess 140 by, for example, a germanium seed deposition process, a tantalum epitaxial process, and a capping process. In addition, the periphery of the MOS transistor 100 is generally formed with a trench isolation structure 10 to electrically insulate the MOS transistors from each other.

In the present process, the MOS transistor 100, when forming the spacers 130, introduces a chlorine-containing gas such as hexachlorosilane (HCD) into the precursor, which will adhere to the chlorine during the process. The surfaces of the spacers 130 and the recesses 140 cause the interface between the epitaxial layer 150 and the substrate 110 formed after the 800° C epitaxial prebaking process to pass hydrogen to be passivated into an arc shape. Passivation causes the gate channel 160 to be reduced to increase the stress applied by the epitaxial layer 150 thereto. In practice, it is difficult for us to control the degree of passivation, resulting in no stable reproducibility of the electrical quality of the MOS transistor 100.

The object of the present invention is to provide a method for fabricating an epitaxial layer to form an epitaxial layer having a square angle with the substrate interface.

According to a preferred embodiment of the present invention, the present invention provides a method for fabricating an epitaxial layer, comprising: first, providing a substrate. Next, the substrate is etched to form at least one recess in the substrate. Successively, the grooves are surface treated to form a Si-OH containing surface. Further, an in-situ epitaxial process is performed in which the epitaxial process is performed without hydrogen and less than 800 ° C to form an epitaxial layer in the recess.

Based on the above, the present invention provides a method for fabricating an epitaxial layer by first processing a recess to form a surface containing Si—OH, and then performing an in-situ epitaxial process to form an epitaxial layer in the recess, wherein The in-situ epitaxial process must be carried out without hydrogen and at less than 800 °C. The epitaxial layer formed in this way may have an angular shape with the interface of the substrate. In this way, the problem that the interface between the conventional epitaxial layer and the substrate is passivated into an arc shape after the epitaxial process can be solved.

2-4 illustrate a method of fabricating an epitaxial layer in accordance with a preferred embodiment of the present invention. Referring to Figures 2-4, a substrate 210 is first provided. The substrate 210 is, for example, a germanium substrate, a germanium-containing substrate, or a semiconductor substrate such as a silicon-on-insulator (SOI) substrate. Next, a patterned mask 220 is formed on the substrate 210 (as shown in FIG. 2). In this embodiment, the mask 220 may be a tantalum nitride layer, and particularly a tantalum nitride layer formed by using hexachlorodecane (HCD) as a precursor, and the mask 220 is made of, for example, etched lithography. The pattern is patterned, but the invention is not limited thereto. In other embodiments, the mask 220 may be of other materials, and the mask 220 may be formed of a chlorine-containing material as a precursor or a chlorine atom in the process. As a result, the surface of the substrate 210 is adhered with a chlorine component to form a chlorine-containing substrate. Next, the mask 220 is automatically aligned to define and etch the recess 230 in the substrate 210. The groove 230 is formed, for example, by dry etching. Next, a surface treatment P is performed in the recess 230 to form a Si-OH-containing surface, and is a Si-OH rich surface (as shown in Fig. 3). In the present embodiment, the surface treatment P includes a cleaning process for removing chlorine, native oxide or impurities, etc. in the substrate 210, and forming a Si-OH-containing surface. Then, an in-situ epitaxial process is performed to form an epitaxial layer 240 in the recess 230 (as shown in FIG. 4 ), wherein the epitaxial process may include an epitaxial process, an epitaxial process, or a矽 Carbon epitaxial process.

It is emphasized herein that the in-situ epitaxial process of the present invention is carried out in the absence of hydrogen and less than 800 ° C, so that even if the recess 230 is a Si-OH surface, the interface between the epitaxial layer 240 and the substrate 210 can be maintained. It is horny. In other words, the in-situ epitaxial process of the present invention can prevent the interface between the epitaxial layer 240 and the substrate 210 from being passivated into an arc shape.

It should be noted that in the present embodiment, the in-situ epitaxial process specifically excludes the conventional epitaxial pre-baking process to achieve the above object. Because the current epitaxial baking process of 800 ° C and simultaneous hydrogen introduction is a necessary step for forming the epitaxial layer 240, as a further cleaning of the groove 230, but the epitaxial pre-baking process will make the The interface between the epitaxial layer 240 and the substrate 210 is formed into an arc shape and affects the electrical quality. In this embodiment, the pre-ebending pre-baking process is specifically excluded. Further, Fig. 9 is a view showing experimental data of a MOS transistor of a preferred embodiment of the present invention. It can be seen from Fig. 9 that the MOS transistor formed by the pre-epitaxial baking process is excluded, which has a lower threshold voltage (Vt) than the conventional (pre-epitaxial baking process), and thus has a high opening. Current, so it has good electrical quality.

The above-described method for fabricating the epitaxial layer can be applied to a process of various semiconductor elements having an epitaxial structure. For example, a PMOS transistor or an NMOS transistor is formed, but the invention is not limited thereto.

5-7 illustrate a preferred embodiment of the method of fabricating the epitaxial layer of the present invention for fabricating a MOS transistor. Referring to FIGS. 5-7, a method of fabricating the MOS transistor 300 in one of the preferred embodiments, first, as shown in FIG. 5, a substrate 310 is provided, which is, for example, a semiconductor substrate such as a germanium substrate. Then, a gate structure 320 is formed on the substrate 310, which may include a gate dielectric layer 322, a gate electrode 324 and a cap layer 326. The detailed formation method and material are well known in the art, so This statement.

In the embodiment, a sidewall spacer 330 is selectively formed on the sidewall of the gate structure 320, and then a lightly doped ion implantation is performed by using the gate structure 320 and the sidewall spacer 330 as a hard mask. The lightly doped source/drain regions 340 are automatically aligned and defined in the substrate 310 on both sides of the gate structure 320, wherein the sidewall spacers 330 are, for example, a single layer or a multilayer composite layer such as a tantalum nitride layer or a hafnium oxide layer. Next, a spacer 350 is formed on the sidewall of the gate structure 320. In the present embodiment, the spacer 350 is a tantalum nitride layer, especially formed of hexachlorodecane (HCD) as a precursor, but in other embodiments, the spacer 350 may be other materials and spacers. 350 may be formed by a chlorine-containing material as a precursor or a chlorine atom in the process, such that chlorine is attached to the substrate 310 to form a chlorine-containing substrate.

Continuing, as shown in FIG. 6, the gate 360 is automatically aligned with the spacer 350 and the spacer 350 as a hard mask in the substrate 310 on the side of the gate structure 320, wherein the recess 360 can be etched, for example, by etching. Process formation. Then, a surface treatment P is performed to form a Si-OH-containing surface on the surface of the groove 360, and is a surface rich in Si-OH (Si-OH rich). In the present embodiment, the surface treatment P may include a cleaning process to simultaneously form Si-OH bonds on the surface of the substrate 310 in the process of removing impurities such as native oxide.

Subsequently, as shown in FIG. 7, an in-situ epitaxial process is performed to form an epitaxial layer 370 in the recess 360, wherein the epitaxial layer 370 may comprise a germanium epitaxial layer depending on the characteristics of the MOS transistor. , or a carbon epitaxial layer. For example, the in-situ epitaxial process may include a germanium seed deposition process, a germanium epitaxial process, and a capping process. However, it must be emphasized that the in-situ epitaxial process of the present invention is carried out in the absence of hydrogen and less than 800 ° C, so that even if the substrate 310 still contains chlorine, the interface of the epitaxial layer 370 and the substrate 310 can be maintained at one angle. shape. In other words, the interface between the epitaxial layer 370 and the substrate 310 is not passivated into an arc shape after the epitaxial process. In this way, the epitaxial pre-baking process of the chlorine-containing surface and the high temperature of 800 ° C in the prior art can be solved, and the interface of the epitaxial layer 370 and the substrate 310 is passivated into an arc shape, thereby avoiding the epitaxial layer 150. The increase in pitch causes the stress applied by the epitaxial layer 150 to the gate channel under the gate structure 320 to be reduced, so that the transfer speed of the crystal carrier is slowed down, affecting the electrical quality of the MOS transistor 300. In other words, this embodiment eliminates a necessary step of the conventional epitaxial process in which hydrogen is introduced and an epitaxial pre-baking process at 800 ° C is applied so that the epitaxial layer 370 can be free of hydrogen and less than 800 ° C. It is formed under the environment, but the invention is not limited thereto.

Finally, the spacers 350 can be removed to complete the fabrication of the MOS transistor 300. Of course, the epitaxial layer 370 may be formed in the doped source/drain region or simultaneously with the source/drain conductive dopant, or may be doped after forming the epitaxial layer 370 to form Source / bungee. Moreover, after the epitaxial layer 370 is formed, a metal germanide may be formed on the epitaxial layer 370, or a contact hole etch stop layer (CESL) having stress may be formed, which should be covered by the embodiment of the present invention. range.

In the above, the 5-7 diagram is described by taking a method of fabricating a single MOS transistor as an example. Therefore, the spacer 350 formed by using hexachlorodecane (HCD) as a precursor is the main gap of the MOS transistor 300. Wall, but in the general CMOS transistor process, the hard mask formed by using hexachlorodecane (HCD) as a precursor can be used simultaneously to protect a first conductivity type MOS transistor from etching. The hard mask and the spacer of another second conductivity type MOS transistor are used to etch the grooves required for the enamel epitaxy.

Fig. 8 is a schematic cross-sectional view showing a CMOS transistor according to a preferred embodiment of the present invention, which employs a method of fabricating an epitaxial layer of the present invention. As shown in FIG. 8, a deposition process of a hexachlorodecane (HCD) as a precursor and a patterning process are performed to conformally cover a mask layer 422 on the second conductivity type MOS transistor 420, and At the same time, a mask layer (not shown) covered on the first conductivity type MOS transistor 410 is etched to form a spacer 412. Thus, a mask 422 can be formed by using the mask layer 422 and the spacer 412 as a hard mask. In one embodiment, the MOS transistor 420 of the second conductivity type may be an N-type transistor, and the MOS transistor 410 of the first conductivity type may be a P-type transistor, so the epitaxial layer may be a 矽锗(SiGe) layer; but in other embodiments, the MOS transistor 420 can also be a P-type transistor and the MOS transistor 410 is an N-type transistor, and the epitaxial layer can be a silicon-on-silicon (SiC) layer. . In addition, the mask layer 422 and the spacer 412 may include a tantalum nitride layer formed of hexachlorodecane (HCD) as a precursor, but other materials may be used in other embodiments, and the mask layer 422 and the spacers 412 may be formed by a chlorine-containing gas as a precursor or a chlorine atom in the process.

In summary, the present invention provides a method for fabricating an epitaxial layer that can be applied to various semiconductor processes such as MOS transistor processes. The epitaxial layer is formed by surface treating the recess to form a Si-OH-rich surface, and then performing an in-situ epitaxial process to form an epitaxial layer in the recess, wherein the in-situ epitaxial process must be performed. It is carried out without hydrogen and at less than 800 °C. The epitaxial layer formed in this way may have an angular shape with the interface of the substrate. In this way, the problem that the interface between the conventional epitaxial layer and the substrate is passivated into an arc shape after the epitaxial process can be solved. Furthermore, an embodiment of the present invention eliminates the conventional 800 ° C epitaxial pre-baking process for introducing hydrogen to effectively maintain the interface between the epitaxial layer and the substrate at an angle.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Ditch isolation structure

100, 300, 410, 420. . . MOS transistor

110, 210, 310. . . Base

120, 320. . . Gate structure

122, 322. . . Gate dielectric layer

124, 324. . . Gate electrode

126, 326. . . Cover

130, 350, 412. . . Clearance wall

140, 230, 360, 414. . . Groove

150, 240, 370. . . Epitaxial layer

160. . . Gate channel

220. . . Mask

330. . . Side wall

340. . . Lightly doped source/drain region

422. . . Mask layer

P. . . Surface treatment

Fig. 1 is a schematic cross-sectional view showing a conventional MOS transistor using epitaxial technology.

2-4 illustrate a method of fabricating an epitaxial layer in accordance with a preferred embodiment of the present invention.

5-7 illustrate a method of fabricating a MOS transistor according to a preferred embodiment of the present invention, which employs a method of fabricating an epitaxial layer of the present invention.

Fig. 8 is a cross-sectional view showing a CMOS transistor according to a preferred embodiment of the present invention, which employs a method of fabricating an epitaxial layer of the present invention.

Fig. 9 is a view showing experimental data of a MOS transistor of a preferred embodiment of the present invention.

210. . . Base

220. . . Mask

240. . . Epitaxial layer

Claims (13)

A method for fabricating an epitaxial layer, comprising: providing a substrate as a chlorine-containing substrate; etching the substrate to form at least one groove in the substrate; surface treating the groove, wherein the cleaning process comprises a cleaning process to remove a chlorine, a primary oxide or an impurity in the substrate, and forming a surface containing Si—OH; after the cleaning process, performing an in-situ epitaxial process, wherein the in-situ epitaxial process comprises an epitaxial process or A carbon epitaxial process is performed and is carried out in the absence of hydrogen and less than 800 ° C to form an epitaxial layer in the recess. The method for fabricating an epitaxial layer according to the first aspect of the invention, wherein the epitaxial layer formed by the method for fabricating the epitaxial layer is formed in a PMOS transistor or an NMOS transistor. The method for fabricating an epitaxial layer according to claim 1, wherein the substrate comprises a patterned mask. The method for fabricating an epitaxial layer according to claim 3, wherein the mask comprises a precursor of hexachlorodecane (HCD). The method for fabricating an epitaxial layer according to claim 3, wherein the mask comprises a precursor containing a chlorine-containing material. The method for fabricating an epitaxial layer according to claim 3, wherein the mask comprises a tantalum nitride layer. The method for fabricating an epitaxial layer according to claim 1, wherein the in-situ epitaxial process does not include an epitaxial pre-baking process. The method for fabricating an epitaxial layer according to claim 1, wherein the substrate comprises a gate structure. The method for fabricating an epitaxial layer according to claim 8, wherein the gate structure comprises a gate dielectric layer, a gate electrode layer, a cap layer, and a spacer. The method for fabricating an epitaxial layer according to claim 9, wherein the spacer comprises a precursor of hexachlorodecane (HCD). The method for fabricating an epitaxial layer according to claim 9, wherein the spacer comprises a precursor containing a chlorine-containing material. The method for fabricating an epitaxial layer according to claim 9, wherein the spacer comprises a tantalum nitride layer. The method for fabricating an epitaxial layer according to claim 1, wherein the method The epitaxial layer and the interface of the substrate have an angular shape.