TWI575662B - 半導體裝置結構與其形成方法 - Google Patents
半導體裝置結構與其形成方法 Download PDFInfo
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- TWI575662B TWI575662B TW104136966A TW104136966A TWI575662B TW I575662 B TWI575662 B TW I575662B TW 104136966 A TW104136966 A TW 104136966A TW 104136966 A TW104136966 A TW 104136966A TW I575662 B TWI575662 B TW I575662B
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- Prior art keywords
- protection unit
- gate stack
- semiconductor device
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- 238000000034 method Methods 0.000 title claims description 111
- 239000004065 semiconductor Substances 0.000 title claims description 84
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 125000006850 spacer group Chemical group 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 36
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- 230000001681 protective effect Effects 0.000 description 10
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- 239000007789 gas Substances 0.000 description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
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- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 6
- 229910052735 hafnium Inorganic materials 0.000 description 5
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
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- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-O phosphonium Chemical compound [PH4+] XYFCBTPGUUZFHI-UHFFFAOYSA-O 0.000 description 2
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- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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- 239000000126 substance Substances 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- SITVSCPRJNYAGV-UHFFFAOYSA-L tellurite Chemical compound [O-][Te]([O-])=O SITVSCPRJNYAGV-UHFFFAOYSA-L 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
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- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
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- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QWDUNBOWGVRUCG-UHFFFAOYSA-N n-(4-chloro-2-nitrophenyl)acetamide Chemical compound CC(=O)NC1=CC=C(Cl)C=C1[N+]([O-])=O QWDUNBOWGVRUCG-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/41783—Raised source or drain electrodes self aligned with the gate
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H01L29/66409—Unipolar field-effect transistors
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Description
本發明係關於半導體裝置結構,更特別關於其保護單元之結構與形狀。
半導體積體電路(IC)產業已快速成長一段時日。IC材料與設計的技術進步,使每一代的IC都比前一代的IC更小更複雜。
在IC進化時,功能密度(單位晶片面積所具有的內連線裝置數目)增加,而裝置尺寸(製程技術所能達到的最小構件或線路)減少。上述縮小裝置的製程有利於增加產能並降低相關成本。
然而上述進展將增加IC製程的複雜度。由於結構尺寸持續縮小,製程也變得越來越複雜。如此一來,形成尺寸越來越小且可信的半導體裝置將面臨挑戰。
本發明一實施例提供之半導體裝置結構,包括:閘極堆疊,位於半導體基板上;保護單元,位於閘極堆疊上,其中保護單元的頂部比保護單元的底部寬;間隔物單元,位於保護單元的側表面與閘極堆疊的側壁上;以及導電接點,電性連接至半導體基板上的導電結構。
本發明一實施例提供之半導體裝置結構,包括:
鰭狀結構,位於半導體基板上;閘極堆疊,位於鰭狀結構上;保護單元,位於閘極堆疊上,其中保護單元的頂部比保護單元的底部寬;間隔物單元,位於保護單元的側表面與閘極堆疊的側壁上;以及導電接點,電性連接至鰭狀結構上的源極/汲極結構。
本發明一實施例提供之半導體裝置結構的形成方
法,包括:形成虛置閘極堆疊於半導體基板上;形成多個間隔物單元於虛置閘極堆疊的側壁上;移除虛置閘極堆疊以形成凹陷於間隔物單元之間;移除部份間隔物單元,使凹陷的較上部份變寬;形成金屬閘極堆疊於凹陷中;以及形成保護單元於凹陷中,以覆蓋金屬閘極堆疊。
θ‧‧‧夾角
H‧‧‧總高度
P‧‧‧想像平面
T‧‧‧厚度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
100‧‧‧半導體基板
101‧‧‧鰭狀結構
104‧‧‧閘極介電層
105‧‧‧閘極
106、108‧‧‧間隔物單元
109‧‧‧閘極堆疊
112‧‧‧源極/汲極結構
114‧‧‧介電層
116、124‧‧‧凹陷
118‧‧‧閘極介電層
118t、120t、122t‧‧‧上表面
120‧‧‧功函數層
122‧‧‧導電填充層
122’‧‧‧導電電極
123‧‧‧金屬閘極堆疊
125‧‧‧保護材料層
126‧‧‧保護單元
126b‧‧‧底部
126s‧‧‧側表面
126t‧‧‧頂部
128‧‧‧介電層
130‧‧‧導電接點
第1A至1I圖係某些實施例中,半導體裝置結構在其形成製程中多種階段的剖視圖。
第2圖係某些實施例中,半導體裝置結構的剖視圖。
第3A圖係某些實施例中,半導體裝置結構的剖視圖。
第3B圖係某些實施例中,半導體裝置結構的剖視圖。
第3C圖係某些實施例中,半導體裝置結構的剖視圖。
第3D圖係某些實施例中,半導體裝置結構的剖視圖。
下述內容提供的不同實施例可實施本揭露的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本
揭露。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。此外,本揭露之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。標號重複僅為了簡化並清楚說明,並不代表不同實施例及/或排列中具有相同標號的元件具有類似的相對關係。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。
本揭露的某些實施例將說明如下。第1A至1I圖係某些實施例中,半導體裝置結構於形成製程的多種階段之剖視圖。在第1A至1I圖的階段之前、之中、或之後可進行額外步驟。在不同實施例中,可將某些下述階段置換為其他方式,或省略某些下述階段。另一方面,半導體裝置結構可具有額外結構。在不同實施例中,可將某些下述結構置換為其他結構,或省略某些下述結構。
如第1A圖所示,提供半導體基板100。在某些實施例中,半導體基板100為基體半導體基板如半導體晶圓。舉例來說,半導體基板100為矽晶圓。半導體基板100可包含矽或其他半導體元素材料如鍺。在某些實施例中,半導體基板100包
含半導體化合物。半導體化合物可包含砷化鎵、碳化矽、砷化銦、磷化銦、另一合適的半導體化合物、或上述之組合。
在某些實施例中,半導體基板100包含絕緣層上半
導體(SOI)基板。SOI基板之製作方法可為佈植氧隔離(SIMOX)製程、晶圓接合製程、其他可行方法、或上述之組合。
在某些實施例中,形成一或多個鰭狀結構。如第
1A圖所示,為鰭狀結構之一者(鰭狀結構101)的圖式。在某些實施例中,多個凹陷或溝槽(未圖示)係形成於半導體基板100中。如此一來,多個鰭狀結構(如鰭狀結構101)係形成於凹陷之間。在某些實施例中,可採用一或多道光微影與蝕刻製程形成凹陷。
如第1A圖所示,某些實施例之隔離結構(未圖示)
係形成於凹陷中以圍繞鰭狀結構101的較下部份。隔離結構係用以定義與電性隔離形成於半導體基板100之中及/或之上的多種裝置單元。在某些實施例中,隔離結構包含淺溝槽隔離(STI)結構、局部氧化矽(LOCOS)結構、其他合適的隔離結構、或上述之組合。
在某些實施例中,每一隔離結構為多層結構。在
某些實施例中,隔離結構之組成為介電材料,其可包含氧化矽、氮化矽、氮氧化矽、掺雜氟的矽酸鹽玻璃(FSG)、低介電常數介電材料、其他合適材料、或上述之組合。在某些實施例中,可形成STI襯墊(未圖示)以降低半導體基板100與隔離結構之間的界面之結晶缺陷。同樣地,STI襯墊亦可降低鰭狀結構與隔離結構之間的界面之結晶缺陷。
在某些實施例中,介電材料層係沉積於半導體基
板100上。介電材料覆蓋鰭狀結構(如鰭狀結構101)並填入鰭狀結構之間的凹陷。在某些實施例中,介電材料層的沉積方法為化學氣相沉積(CVD)製程、旋轉塗佈製程、其他可行製程、或上述之組合。在某些實施例中,進行平坦化製程以薄化介電材料層,直到露出鰭狀結構101。平坦化製程可為化學機械拋光(CMP)製程、研磨製程、蝕刻製程、其他可行製程、或上述之組合。之後可回蝕刻介電材料層,使其低於鰭狀結構101的頂部。如此一來可形成隔離結構。在某些實施例中,鰭狀結構(如鰭狀結構101)自隔離結構凸起。
如第1A圖所示之某些實施例中,閘極介電層104係
沉積於隔離結構與鰭狀結構101上。在某些實施例中,閘極介電層104之組成為氧化矽、氮化矽、氮氧化矽、高介電常數之介電材料、其他合適的介電材料、或上述之組合。高介電常數之介電材料包含氧化鉿、氧化鋯、氧化鋁、氧化鉿-氧化鋁合金、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、其他合適的高介電常數材料、或上述之組合。在某些實施例中,閘極介電層104為虛置閘極介電層,其將移除於後續製程中。在某些實施例中,可省略閘極介電層104。
在某些實施例中,閘極介電層104的沉積方法為化學氣相沉積(CVD)製程、原子層沉積(ALD)製程、熱氧化製程、物理氣相沉積(PVD)製程、其他可行製程、或上述之組合。
如第1A圖所示之某些實施例中,之後形成閘極105於閘極介電層104上,以覆蓋部份鰭狀結構101。在某些實施例
中,閘極105為虛置閘極,之後將置換為金屬閘極。在某些實施例中,閘極105之組成為多晶矽。在某些實施例中,位於閘極15下的部份鰭狀結構101作為通道區。
在某些實施例中,沉積閘極層於閘極介電層104上
的方法為CVD製程或其他可行製程。在某些實施例中,閘極層之組成為多晶矽。在某些實施例中,之後可形成圖案化硬遮罩層(未圖示)於閘極層上。圖案化硬遮罩層可用於將閘極層圖案化成一或多個閘極(如第1A圖所示之閘極105)。在某些實施例中,亦可圖案化閘極介電層104如第1A圖所示。閘極105與閘極介電層104可組成閘極堆疊109。在某些實施例中,閘極堆疊109為虛置閘極堆疊,之後將置換為金屬閘極堆疊。在某些實施例中,閘極堆疊109圍繞鰭狀結構101的側壁表面與上表面,並延伸至半導體基板100上。
在某些實施例中,圖案化硬遮罩層包含第一硬遮
罩層與第二硬遮罩層。第一硬遮罩層係位於閘極層與第二硬遮罩層之間。在某些實施例中,第一硬遮罩層之組成為氮化矽。
在某些實施例中,第二硬遮罩層之組成為氧化矽。在某些實施例中,第二硬遮罩層比第一硬遮罩層厚。
在某些實施例中,形成封裝單元(未圖示)於閘極堆
疊109的側壁上。封裝單元可用以保護閘極堆疊109,並有助於形成輕掺雜源極/汲極(LDS/D)區的後續製程。在某些實施例中,可採用離子佈植製程以形成LDS/D區。在某些其他實施例中,並未形成封裝單元。在某些其他實施例中,並未形成LDS/D區。
如第1A圖所示的某些實施例中,接著形成間隔物
單元108於閘極堆疊109的側壁上。間隔物單元108可用以保護閘極堆疊109,並有助於形成源極/汲極結構的後續製程。在某些實施例中,間隔物單元108之組成為介電材料,可包含氮化矽、氮氧化矽、氧化矽、其他合適材料、或上述之組合。
在某些實施例中,可沉積介電材料層於半導體基
板100與閘極堆疊109上。介電材料層之沉積方法可為CVD製程、ALD製程、旋轉塗佈製程、其他可行製程、或上述之組合。
接著以蝕刻製程如非等向蝕刻製程移除部份的介電材料層。如此一來,保留於閘極堆疊109之側壁上的部份介電材料層即間隔物單元108。
如第1A圖所示之某些實施例中,源極/汲極結構
112係形成於部份的鰭狀結構101上。在某些實施例中,移除部份鰭狀結構以形成靠近間隔物單元108的凹陷。如第1A圖所示之某些實施例中,接著進行磊晶成長製程以形成源極/汲極結構112。在某些實施例中,源極/汲極結構112亦作為應力源,其可施加應力至源極/汲極結構112之間的通道區上,即可改善載子移動率。
如第1A圖所示的某些實施例中,形成介電層114以
圍繞閘極堆疊109。在某些實施例中,介電材料層係沉積以覆蓋源極/汲極結構112、間隔物單元108、與閘極堆疊109。之後以平坦化製程移除部份介電材料層,直到露出閘極106。至此即形成介電層114。
在某些實施例中,介電材料層之組成為氧化矽、
氮氧化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟化矽酸鹽玻璃(FSG)、低介電常數材料、孔洞狀介電材料、其他合適材料、或上述之組合。在某些實施例中,介電材料層之沉積方法為CVD製程、ALD製程、旋轉塗佈製程、其他可行製程、或上述之組合。在某些實施例中,平坦化製程包含CMP製程、研磨製程、蝕刻製程、其他可行製程、或上述之組合。
在某些實施例中,進行多重蝕刻步驟以移除閘極
106。在某些實施例中,這些蝕刻步驟進行於相同的製程腔室中。
如第1B圖所示之某些實施例中,移除閘極106以形成凹陷116於間隔物單元108之間。在某些實施例中,接著移除閘極介電層104。在某些實施例中,凹陷116露出鰭狀結構101。一或多道蝕刻製程可用以形成凹陷116。
如第1C圖所示之某些實施例中,移除部份間隔物單元108以增加凹陷116之寬度。在某些實施例中,凹陷116的較上部份自凹陷116之頂部朝半導體基板100的方向逐漸變窄。在某些實施例中,蝕刻製程如非等向蝕刻製程係用以移除部份的間隔物單元108。藉由精細調整蝕刻製程的條件,可橫向蝕刻間隔物單元108的較上部份。在某些實施例中,蝕刻製程所用之反應氣體為氣體混合物,其可包含CF4、O2、CHF3、N2、Ar、NF3、He、HBr、Cl2、SF6、CH4、其他合適氣體、或上述之組合。在蝕刻步驟中,氣體混合物之組成可依需求變化。
在某些實施例中,蝕刻步驟時的壓力維持於約
1mtorr至約80mtorr之間。在某些實施例中,蝕刻步驟之功率介於約100W至約1500W之間。在某些實施例中,蝕刻步驟的溫度介於約10℃至約80℃之間。在某些實施例中,蝕刻步驟的時間介於約5秒至約600秒之間。
如第1D圖所示之某些實施例中,金屬閘極堆疊層
包含閘極介電層118、功函數層120、導電填充層122沉積填入凹陷116中。金屬閘極堆疊層可包含一或多個其他層狀物。舉例來說,阻障層可形成於閘極介電層118與功函數層120之間。
阻擋層可形成於功函數層120與導電填充層122之間。在某些實施例中,由於前述之蝕刻製程使凹陷116變寬,因此將金屬閘極堆疊填入凹陷之的步驟較容易。
在某些實施例中,閘極介電層118之組成為高介電
常數之介電材料。閘極介電層118可為氧化鉿、氧化鋯、氧化鋁、氧化鉿-氧化鋁合金、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、其他合適的高介電常數材料、或上述之組合。
功函數層120用以提供電晶體所需的功函數,以增
加裝置效能如改善的臨界電壓。在某些實施例中,功函數層120為n型金屬層,其可提供適用於裝置的功函數值(比如小於或等於約4.5eV)。在某些實施例中,功函數層120為p型金屬層,其可提供適用於裝置的功函數值(比如大於或等於約4.8eV)。
n型金屬層可包含金屬、金屬碳化物、金屬氮化
物、或上述之組合。舉例來說,n型金屬層包含氮化鈦、鉭、氮化鉭、其他合適材料、或上述之組合。p型金屬層可包含金
屬、金屬碳化物、金屬氮化物、其他合適材料、或上述之組合。
舉例來說,p型金屬包含氮化鉭、氮化鎢、鈦、氮化鈦、其他合適材料、或上述之組合。
功函數層120之組成亦可為鉿、鋯、鈦、鉭、鋁、
金屬碳化物(如碳化鉿、碳化鋯、碳化鈦、碳化鋁)、鋁化物、釕、鈀、鉑、鈷、鎳、導電金屬氧化物、或上述之組合。藉由精細調整功函數層120之厚度及/或組成,可調整其功函數等級。舉例來說,氮化鈦層可作為p型金屬層或n型金屬層,端視其厚度及/或組成。
在某些實施例中,導電填充層122之組成為金屬材
料,其可包含鎢、鋁、銅、其他合適材料、或上述之組合。金屬閘極堆疊層的形成可為多重沉積製程,其可包含CVD製程、ALD製程、PVD製程、電鍍製程、無電電鍍製程、旋轉塗佈植程、其他可行製程、或上述之組合。
如第1E圖所示之某些實施例中,進行平坦化製程
以移除間隔物單元106之間的凹陷116以外的部份金屬閘極堆疊層,即形成金屬閘極堆疊123。金屬閘極堆疊123包含閘極介電層118、功函數層120、與導電電極122'(部份的導電填充層122)。
如第1F圖所示之某些實施例中,移除部份金屬閘
極堆疊123以形成凹陷124。在某些實施例中,凹陷124的形成方法為回蝕刻製程。在某些實施例中,回蝕刻製程後的金屬閘極堆疊123具有實質上平坦的上表面。換言之,閘極介電層118、功函數層120、與導電電極122'的上表面實質上等高。在
某些實施例中,由於金屬閘極堆疊123具有實質上平坦的上表面,此將有利於之後形成導電接點於金屬閘極堆疊上。
在某些實施例中,回蝕刻製程所用之反應氣體為氣體混合物,其可包含BCl3、HBr、Cl2、SF6、Ar、N2、O2、SiCl4、CF4、CHF3、CH4、H2、其他合適氣體、或上述之組合。在蝕刻步驟中,氣體混合物之組成可依需求變化。
在某些實施例中,蝕刻步驟時的壓力維持於約1mtorr至約100mtorr之間。在某些實施例中,蝕刻步驟之功率介於約100W至約1500W之間。在某些實施例中,蝕刻步驟的溫度介於約10℃至約80℃之間。在某些實施例中,蝕刻步驟的時間介於約5秒至約600秒之間。
如第1G圖所示,沉積保護材料層125於介電層114及金屬閘極堆疊123上,以填入凹陷124中。在某些實施例中,保護材料層125之組成不同於間隔物單元106。在某些實施例中,保護材料層125之組成為介電材料,可包含氮化矽、氮氧化矽、碳化矽、碳氮化矽、氧化物、其他類似材料、其他合適材料、或上述之組合。在某些實施例中,保護材料層125之沉積方法為CVD製程、ALD製程、旋轉塗佈製程、其他可行製程、或上述之組合。
如第1H圖所示的某些實施例中,接著移除凹陷124之外的部份保護材料層125。如此一來,保留於凹陷124中的保護材料層125即保護單元126,如第1H圖所示。在某些實施例中,移除部份保護材料層125以形成保護單元126的方法,可為平坦化製程。在某些實施例中,平坦化製程包含化學機械拋光
(CMP)製程、研磨製程、蝕刻製程、其他可行製程、或上述之組合。
如第1H圖所示,保護單元126在靠近保護單元126
之底部126b處具有第一寬度W1,並在靠近保護單元126之頂部126t處具有第二寬度W2。第二寬度W2大於第一寬度W1。在某些實施例中,第一寬度W1介於約20nm至約40nm之間。在某些實施例中,第二寬度W2介於約25nm至約50nm之間。在某些實施例中,保護單元126自頂部126t朝底部126b的方向逐漸變窄。在某些實施例中,間隔物單元106自保護單元126之底部126b朝間隔物單元106之頂部106t的方向逐漸變窄。
如第1H圖所示,保護單元126具有厚度T。在某些
實施例中,厚度T介於約100Å至約500Å之間。在某些實施例中,鰭狀結構101與保護單元126上的金屬閘極堆疊123具有總高度H,其介於約300Å至約2000Å之間。在某些實施例中,厚度T與總高度H的比例(T/H)介於約1/20至約3/5之間。
如1H圖所示,保護單元126之側表面126s與自保護
單元126之底部126b延伸的想像平面P之間具有夾角θ。在某些實施例中,夾角θ介於約30度至約85度之間。在某些其他實施例中,夾角θ介於約40度至約80度之間。
如第11圖所示之某些實施例中,形成導電接點130
以電性連接至半導體基板100上的導電結構。在某些實施例中,導電接點130電性連接至鰭狀結構101上的源極/汲極結構112。在某些實施例中,在形成導電接點130前,先形成介電層128於第1H圖所示之結構上。之後可圖案化介電層128以形成接
點開口,其露出導電結構如源極/汲極結構112。
在某些實施例中,介電層128包含多層的介電層。在某些實施例中,介電層128包含之子層可作為蝕刻停止層。在某些實施例中,介電層128之組成為氧化矽、氮氧化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟化矽酸鹽玻璃(FSG)、低介電常數材料、孔洞狀介電材料、氮化矽、其他合適材料、或上述之組合。在某些實施例中,沉積介電層128後進行平坦化製程,以形成實質上平坦的上表面。在某些實施例中,介電層128之沉積方法為CVD製程、ALD製程、旋轉塗佈製程、其他可行製程、或上述之組合。在某些實施例中,介電層128之平坦化方法為CMP製程、研磨製程、蝕刻製程、其他可行製程、或上述之組合。
在某些實施例中,之後沉積導電材料層於介電層128上以填入接點開口。接著進行平坦化製程以移除接點開口之外的部份導電材料層。如此一來,保留於接點開口中的導電材料層將形成導電接點130,如第1I圖所示。
在某些實施例中,導電材料層之組成為鎢、鋁、銅、金、鉑、鈦、其他合適材料、或上述之組合。在某些實施例中,導電材料層之沉積方法為CVD製程、PVD製程、電鍍製程、無電電鍍製程、其他可行製程、或上述之組合。
由於部份移除間隔物單元106以加大凹陷116,之後形成的保護單元126亦具有較寬的較上部份。具有較寬的較上部份之保護單元126可在形成導電接點的步驟中保護金屬閘極堆疊123。如第1I圖所示,即使在形成接點開口時發生對不
準的誤差,保護單元126仍可保護其下之金屬閘極堆疊不受損傷。由於保護單元的形狀,保護單元126與間隔物單元106之間的界面頂部,將橫向地位於金屬閘極堆疊123之外。如此一來,形成接點開口的蝕刻品將不會穿過上述界面到達金屬閘極堆疊123,即保護金屬閘極堆疊123,並避免金屬閘極堆疊123與導電接點130之間的短路。如此一來,可明顯改善半導體裝置結構的效能與可信度。
如前所述,需小心控制側壁表面126s與想像平面P
之間的夾角θ至合適範圍。在某些實施例中,夾角θ介於約30度至約85度之間。在某些情況下,若夾角θ大於約85度,則第二寬度W2將過小而無法適當地保護金屬閘極堆疊123。在某些其他情況下,若夾角小於約30度,則第二寬度W2可能過大而使導電接點130的接合面積過大,且間隔物單元106之較上部份亦過薄而無法適當地保護金屬閘極堆疊123之側壁。
在某些實施例中,導電接點130直接接觸間隔物單
元106,如第1I圖所示。在某些實施例中,導電接點130亦直接接觸保護單元126。然而應理解的是本揭露實施例可具有多種變化及/或調整。第2圖係某些實施例中,半導體裝置結構的剖視圖。如第2圖所示,導電接點130直接接觸間隔物單元106。
然而在某些實施例中,導電接點130並未直接接觸保護單元126。
如前所述,金屬閘極堆疊123具有實質上平坦的上
表面。然而應理解本揭露之實施例並不侷限於此。本揭露實施例可具有多種變化及/或調整。第3A至3D圖係某些實施例中,
不同半導體裝置結構的剖視圖。
如第3A圖所示之某些實施例,導電電極122’自功
函數層120與閘極介電層118凸起。在某些實施例中,藉由精細地調整回蝕刻製程,導電電極122’的上表面122t之高度大於功函數層120與閘極介電層118的上表面之高度。舉例來說,蝕刻製程對功函數層120之蝕刻速率,大於對導電電極122’之蝕刻速率。
如第3A圖所示的某些實施例,形成保護單元126後
的導電電極122’其上表面122t,位於保護單元126之頂部126t與底部126b之間。在某些實施例中,功函數層120之上表面120t與閘極介電層118之上表面118t實質上等高。
之後形成導電接點以電性連接至導電電極122’,且
導電電極122’自功函數層120與閘極介電層118凸起。在某些實施例中,導電電極122’與後續形成之導電接點之接觸面積,大於第1I圖之結構中的接觸面積。
本揭露實施例可具有多種變化及/或調整。如第3B
圖所示,某些實施例藉由精細地調整回蝕刻製程,功函數層120之上表面120t的高度大於閘極介電層118之上表面的高度。在某些實施例中,功函數層120的上表面120t其高度,介於導電電極122’之上表面122t其高度與閘極介電層118之上表面118t其高度之間。
本揭露實施例可具有多種變化及/或調整。如第3C
圖所示,某些實施例之導電電極122’的上表面122t低於功函數層120的上表面120t與閘極介電層118的上表面118t。藉由精細
地調整回蝕刻製程,導電電極122’的上表面122t之高度小於功函數層120與閘極介電層118的高度。舉例來說,蝕刻製程對導電電極122’的蝕刻速大於對功函數層120的蝕刻速率。在某些實施例中,功函數層120的上表面120t與閘極介電層118的上表面118t具有實質上相同的高度。
本揭露實施例可具有多種變化及/或調整。如第3D
圖所示,藉由精細地調整回蝕刻製程,功函數層120之上表面120t之高度大於閘極介電層118之上表面的高度,且大於導電電極122’之上表面122t的高度。
本揭露之實施例形成之半導體裝置結構其閘極堆
疊上具有保護單元。保護單元的較上部份,比保護單元的較下部份寬。保護單元係用以保護閘極堆疊,使其在後續形成接點之步驟中免於損傷。上述結構可大幅改善半導體裝置結構的可信度與效能。
某些實施例提供之半導體裝置結構包含閘極堆疊
位於半導體基板上,以及保護單元位於閘極堆疊上。保護單元包含較上部份,以及較上部份與閘極堆疊之間的較下部份,且較上部份比較下部份寬。半導體裝置結構亦包含間隔物單元於保護單元的側表面及閘極堆疊的側壁上。半導體裝置結構更包含導電接點電性連接至半導體基板上的導電結構。
某些實施例提供之半導體裝置結構包含鰭狀結構
於半導體基板上,以及閘極堆疊於鰭狀結構上。半導體裝置結構亦包含保護單元位於閘極堆疊上。保護單元具有較上部份,以及較上部份與閘極堆疊之間的較下部份。較上部份比較下部
份寬。半導體裝置結構更包含間隔物單元於保護單元之側表面及閘極堆疊的側壁上。此外,半導體裝置結構包含導電接點電性連接至鰭狀結構上的源極/汲極結構。
某些實施例提供之半導體裝置結構的形成方法,
包括形成虛置閘極堆疊於半導體基板上,以及形成間隔物單元於虛置閘極堆疊的側壁上。上述方法亦包含移除虛置閘極堆疊,以形成凹陷於間隔物單元之間。上述方法亦包含移除部份的間隔物單元,使凹陷的較上部份變寬。此外,上述方法包含形成金屬閘極堆疊於凹陷中,並形成保護單元於金屬閘極堆疊上以填入凹陷。
某些實施例提供之半導體裝置結構包括閘極堆疊
位於半導體基板上,以及保護單元位於閘極堆疊上。保護單元的頂部比保護單元的底部寬。半導體裝置結構亦包含間隔物單元位於保護單元的側表面與閘極堆疊的側壁上。半導體裝置結構更包含導電接點電性連接至半導體基板上的導電結構。
某些實施例提供之半導體裝置結構,包括鰭狀結
構位於半導體基板上,以及閘極堆疊位於鰭狀結構上。半導體裝置結構亦包含保護單元位於閘極堆疊上,且保護單元的頂部比保護單元的底部寬。半導體裝置結構更包含間隔物單元位於保護單元的側表面與閘極堆疊的側壁上。此外,半導體裝置結構包含導電接點電性連接至鰭狀結構上的源極/汲極結構。
某些實施例提供之半導體裝置結構的形成方法,
包括:形成虛置閘極堆疊於半導體基板上,以及形成多個間隔物單元於虛置閘極堆疊的側壁上。上述方法亦包含移除虛置閘
極堆疊以形成凹陷於間隔物單元之間,以及移除部份間隔物單元,使凹陷的較上部份變寬。上述方法更包含形成金屬閘極堆疊於凹陷中,以及形成保護單元於凹陷中,以覆蓋金屬閘極堆疊。
上述實施例之特徵有利於本技術領域中具有通常
知識者理解本揭露。本技術領域中具有通常知識者應理解可採用本揭露作為基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本揭露之精神與範疇,並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
θ‧‧‧夾角
H‧‧‧總高度
P‧‧‧想像平面
T‧‧‧厚度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
100‧‧‧半導體基板
101‧‧‧鰭狀結構
106‧‧‧間隔物單元
112‧‧‧源極/汲極結構
114‧‧‧介電層
118‧‧‧閘極介電層
120‧‧‧功函數層
122’‧‧‧導電電極
123‧‧‧金屬閘極堆疊
126‧‧‧保護單元
126b‧‧‧底部
126s‧‧‧側表面
126t‧‧‧頂部
128‧‧‧介電層
130‧‧‧導電接點
Claims (9)
- 一種半導體裝置結構,包括:一閘極堆疊,位於一半導體基板上;一保護單元,位於該閘極堆疊上,其中該保護單元的頂部比該保護單元的底部寬;一間隔物單元,位於該保護單元的側表面與該閘極堆疊的側壁上;以及一導電接點,電性連接至該半導體基板上的一導電結構,其中該導電接點直接接觸該保護單元。
- 如申請專利範圍第1項所述之半導體裝置結構,其中該閘極堆疊包括一功函數層與一導電電極,且該功函數層圍繞該導電電極。
- 如申請專利範圍第2項所述之半導體裝置結構,其中該保護單元直接接觸該功函數層與該導電電極。
- 如申請專利範圍第1項所述之半導體裝置結構,其中該保護單元之側表面與自該保護單元之底部延伸之想像平面之間具有一夾角,且該夾角介於約30度至約85度之間。
- 如申請專利範圍第1項所述之半導體裝置結構,其中該導電接點直接接觸該間隔物單元。
- 一種半導體裝置結構,包括:一鰭狀結構,位於一半導體基板上;一閘極堆疊,位於該鰭狀結構上;一保護單元,位於該閘極堆疊上,其中該保護單元的頂部比該保護單元的底部寬; 一間隔物單元,位於該保護單元的側表面與該閘極堆疊的側壁上;以及一導電接點,電性連接至該鰭狀結構上的一源極/汲極結構,其中該導電接點直接接觸該保護單元。
- 如申請專利範圍第6項所述之半導體裝置結構,其中該導電接點直接接觸該間隔物單元。
- 一種半導體裝置結構的形成方法,包括:形成一虛置閘極堆疊於一半導體基板上;形成多個間隔物單元於該虛置閘極堆疊的側壁上;移除該虛置閘極堆疊以形成一凹陷於該些間隔物單元之間;移除部份間隔物單元,使該凹陷的較上部份變寬;形成一金屬閘極堆疊於該凹陷中;以及形成一保護單元於該凹陷中,以覆蓋該金屬閘極堆疊。
- 如申請專利範圍第8項所述之半導體裝置結構的形成方法,更包括:形成一導電接點以電性連接至該半導體基板上的一導電結構,且該導電接點直接接觸該間隔物單元、該導電單元、或上述之組合。
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