TWI571849B - Display device - Google Patents
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- TWI571849B TWI571849B TW105114939A TW105114939A TWI571849B TW I571849 B TWI571849 B TW I571849B TW 105114939 A TW105114939 A TW 105114939A TW 105114939 A TW105114939 A TW 105114939A TW I571849 B TWI571849 B TW I571849B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Description
本發明係關於一種顯示裝置，特別關於一種具有導線斷線偵測能力的顯示裝置。The present invention relates to a display device, and more particularly to a display device having a wire breakage detecting capability.
顯示裝置是由源極驅動電路與閘極驅動電路透過源極驅動線(資料線)與閘極驅動線(掃描線)來更新每個畫素的亮度，藉以更新畫面。然而閘極驅動線與源極驅動線由於製程的關係，往往容易發生斷線的問題。並且在製作、運送與使用等任何時間都可能在閘極驅動線或源極驅動線產生有斷線的問題。因此，如何在顯示裝置出廠後仍然能簡單、快速地偵測其中是否有斷線問題是一個待解決的問題。The display device updates the brightness of each pixel by the source driving circuit and the gate driving circuit through the source driving line (data line) and the gate driving line (scanning line), thereby updating the picture. However, due to the relationship between the gate drive line and the source drive line, the problem of disconnection is likely to occur. And at any time during production, transportation, and use, there may be a problem of disconnection in the gate drive line or the source drive line. Therefore, how to quickly and quickly detect whether there is a disconnection problem after the display device is shipped is a problem to be solved.
鑒於以上問題，本發明提出一種顯示裝置，得以在顯示裝置出廠後仍能簡單地偵測其中的各驅動線是否有斷線。In view of the above problems, the present invention provides a display device capable of simply detecting whether each of the drive lines is disconnected after the display device is shipped.
依據本發明一實施例的顯示裝置，具有驅動電路、多條驅動線、多個電晶體開關與讀取線。每條驅動線具有第一端與第二端，且每條驅動線的第一端連接於驅動電路。每個電晶體開關具有第一端、第二端與控制端。每個電晶體開關的第一端電性連接於第一電壓端，而每個電晶體開關的控制端電性連接於對應的一條驅動線的第二端。讀取線電性連接於每個電晶體開關的第二端。A display device according to an embodiment of the invention has a driving circuit, a plurality of driving lines, a plurality of transistor switches and a read line. Each of the driving lines has a first end and a second end, and the first end of each of the driving lines is connected to the driving circuit. Each transistor switch has a first end, a second end, and a control end. The first end of each transistor switch is electrically connected to the first voltage end, and the control end of each transistor switch is electrically connected to the second end of the corresponding one of the driving lines. The read line is electrically connected to the second end of each of the transistor switches.
綜上所述，本發明藉由加入受控於閘極驅動線或源極驅動線的電晶體開關，並藉由對應的電壓端所提供的信號，閘極驅動電路或源極驅動電路得以判斷是否有任何驅動線有斷線的問題。In summary, the present invention can be judged by adding a transistor switch controlled by a gate driving line or a source driving line, and by a signal provided by a corresponding voltage terminal, a gate driving circuit or a source driving circuit. Is there any problem with the drive line being broken?
以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理，並且提供本發明之專利申請範圍更進一步之解釋。The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.
以下在實施方式中詳細敘述本發明之詳細特徵以及優點，其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點，但非以任何觀點限制本發明之範疇。The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.
本發明所揭露的顯示裝置中所使用的薄膜電晶體電路架構乃所屬技術領域具有通常知識者得以依據本發明下列實施例自由設計。以下本發明均以N型薄膜電晶體(N-type thin-film transistor, N-type TFT)為例。請參照圖1，其係依據本發明一實施例的顯示裝置電路架構示意圖。如圖1所示，依據本發明一實施例的顯示裝置1000具有閘極驅動電路1100、源極驅動電路1200、多條閘極驅動線(掃描線)S 1~S N、多條源極驅動線(資料線)D 1~D M、多個電晶體開關TS 1~TS N與讀取線READ。每條閘極驅動線具有第一端與第二端，以圖1為例，閘極驅動線的第一端為左端(以圖1而言，X軸座標較小的一端)，而閘極驅動線的第二端為右端(以圖1而言，X軸座標較大的一端)。每條閘極驅動線的第一端連接於閘極驅動電路1100。每個電晶體開關具有第一端、第二端與控制端。每個電晶體開關的第一端電性連接於第一電壓端V 1，而每個電晶體開關的控制端電性連接於對應的一條閘極驅動線的第二端。讀取線READ電性連接於每個電晶體開關的第二端。於本實施例中，雖然讀取線READ電性連接至閘極驅動電路1100。然而於其他實施方式中，讀取線READ或是被外接至一個信號輸出端以便於使用者或檢測者進行量測，或是電性連接至源極驅動電路1200，本發明並不加以限制。此外，雖然本發明中的閘極驅動電路1100與源極驅動電路1200係分別於顯示裝置1000的左側與下側，然而所屬領域具有通常知識者當能依據本發明的精神自行配置驅動電路、驅動線與對應電晶體開關的位置及連接關係，本發明並不加以限制。 The thin film transistor circuit architecture used in the display device disclosed in the present invention is generally designed by those skilled in the art in accordance with the following embodiments of the present invention. Hereinafter, the present invention is exemplified by an N-type thin-film transistor (N-type TFT). Please refer to FIG. 1 , which is a schematic diagram of a circuit structure of a display device according to an embodiment of the invention. As shown in FIG. 1 , a display device 1000 according to an embodiment of the invention has a gate driving circuit 1100, a source driving circuit 1200, a plurality of gate driving lines (scanning lines) S 1 to S N , and a plurality of source drivers. Line (data line) D 1 ~D M , multiple transistor switches TS 1 ~TS N and read line READ. Each of the gate drive lines has a first end and a second end. As shown in FIG. 1 , the first end of the gate drive line is a left end (in FIG. 1 , the smaller end of the X-axis coordinate), and the gate The second end of the drive line is the right end (in Figure 1, the larger end of the X-axis coordinate). A first end of each gate drive line is coupled to the gate drive circuit 1100. Each transistor switch has a first end, a second end, and a control end. The first end of each of the transistor switches is electrically connected to the first voltage terminal V 1 , and the control end of each of the transistor switches is electrically connected to the second end of the corresponding one of the gate driving lines. The read line READ is electrically connected to the second end of each of the transistor switches. In the present embodiment, the read line READ is electrically connected to the gate drive circuit 1100. However, in other embodiments, the read line READ is externally connected to a signal output for measurement by the user or the detector, or is electrically connected to the source driving circuit 1200, and the invention is not limited thereto. In addition, although the gate driving circuit 1100 and the source driving circuit 1200 in the present invention are respectively on the left side and the lower side of the display device 1000, those skilled in the art can configure the driving circuit and drive according to the spirit of the present invention. The position and connection relationship between the line and the corresponding transistor switch are not limited by the present invention.
因此，請參照圖2A，其係依據本發明一實施例的正常的顯示裝置的信號時序圖。如圖2A所示，其中信號VS 1至信號VS N係由閘極驅動電路1100送到閘極驅動線S 1~S N的電壓，信號V 1即為第一電壓端V 1的電壓，信號VREAD則為讀取線READ所讀取到的電壓。於第一時間區間P 1至第N時間區間P N，閘極驅動電路1100分別對閘極驅動線S 1至閘極驅動線S N提供高準位的脈波(pulse)，並且於每個時間區間中，第一電壓端V 1也提供一個高準位脈波。其中閘極驅動線的脈波即為垂直同步信號(vertical synchronization signal, V-sync)，而第一電壓端V 1所提供的脈波的寬度，舉例而言，小於各閘極掃描線上的脈波(垂直同步信號)的寬度。從而在各個時間區間中，信號VREAD的電壓應該如圖2A所示，實質同步於第一電壓端V 1所提供的脈波。 Therefore, please refer to FIG. 2A, which is a signal timing diagram of a normal display device according to an embodiment of the present invention. As shown in FIG. 2A, the signal VS 1 to the signal VS N are the voltages sent from the gate driving circuit 1100 to the gate driving lines S 1 to S N , and the signal V 1 is the voltage of the first voltage terminal V 1 , and the signal VREAD is the voltage read by the read line READ. In the first time interval P 1 to the Nth time interval P N , the gate driving circuit 1100 provides a high-level pulse to the gate driving line S 1 to the gate driving line S N , respectively, and In the time interval, the first voltage terminal V 1 also provides a high level pulse wave. The pulse wave of the gate driving line is a vertical synchronization signal (V-sync), and the width of the pulse wave provided by the first voltage terminal V 1 is, for example, smaller than the pulse of each gate scanning line. The width of the wave (vertical sync signal). Whereby in each time interval, the voltage signal should VREAD FIG Figure 2A, substantially simultaneously a V pulse supplied to the first voltage terminal.
相對的，請參照圖2B其係依據本發明一實施例的異常的顯示裝置的信號時序圖。圖2B所對應的狀態是在閘極驅動線S 2上有斷線，因此於第二時間區間P 2中，電晶體開關TS 2不會導通，從而信號VREAD與第一電壓端V 1的信號不同步，從而使用者、閘極驅動電路1100或是源極驅動電路1200得以藉由比較第一電壓端V 1的信號與信號VREAD而判斷是否有閘極驅動線斷線以及哪一條閘極驅動線斷線。更具體來說，於一實施例中，第一電壓端V 1係電性連接於閘極驅動電路1100，並且第一電壓端V 1所提供的脈波實質上是由閘極驅動電路1100所產生。因此，閘極驅動電路1100依據其所產生給第一電壓端V 1的脈波與從讀取線READ所偵測到的信號VREAD，得以直接判斷兩者是否對應。 In contrast, please refer to FIG. 2B , which is a signal timing diagram of an abnormal display device according to an embodiment of the present invention. The state corresponding to FIG. 2B is that there is a disconnection on the gate driving line S 2 , so in the second time interval P 2 , the transistor switch TS 2 is not turned on, so that the signal VREAD and the signal of the first voltage terminal V 1 Not synchronized, so that the user, the gate driving circuit 1100 or the source driving circuit 1200 can determine whether there is a gate driving line disconnection and which gate driving by comparing the signal of the first voltage terminal V 1 with the signal VREAD. The line is broken. More specifically, in an embodiment, the first voltage terminal V 1 is electrically connected to the gate driving circuit 1100 , and the pulse wave provided by the first voltage terminal V 1 is substantially by the gate driving circuit 1100. produce. Therefore, the gate driving circuit 1100 can directly determine whether the two correspond to each other according to the pulse wave generated by the gate voltage V 1 and the signal VREAD detected from the read line READ.
於本發明另一實施例中，請參照圖3，其係依據本發明另一實施例的顯示裝置電路架構示意圖。相較於圖1的顯示裝置，圖3的實施例中，閘極驅動電路1100更具有一個電壓讀取電路1110，用以讀取輸入到讀取線的訊號V 1。從第一時間區間P 1開始直到最後一個時間區間P N為止，第一電壓端V 1均維持高電壓(例如為電源電壓VDD)。則請參照圖4A，其係依據本發明一實施例的正常的顯示裝置的信號時序圖。於圖4A中可以看到，只要有任意一條掃描線的電壓為高電壓，則信號VREAD就會是高電壓。若是其中掃描線S 2有斷線，則請參照圖4B，其係依據本發明一實施例的異常的顯示裝置的信號時序圖。由於掃描線S 2有斷線，因此在第二時間區間P 2中，即使閘極驅動電路1100對掃描線S 2送出高電壓，但是電晶體開關TD 2的閘極電壓並不會變成高電壓，而是維持低電壓。從而在第二時間區間P 2中，電晶體開關TD 2未導通，因此信號VREAD在第二時間區間P 2中維持低電壓。從而使用者、閘極驅動電路1100或是源極驅動電路1200得以藉由比較第一電壓端V 1的信號與信號VREAD而判斷是否有閘極驅動線斷線以及哪一條閘極驅動線斷線。 In another embodiment of the present invention, please refer to FIG. 3, which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. Compared to the display device of FIG. 1, FIG. 3 embodiment, the gate driving circuit 1100 having a greater voltage reading circuit 1110 for reading the input signal to the read line V 1. From the first time interval P 1 until the last time interval P N , the first voltage terminal V 1 maintains a high voltage (for example, the power supply voltage VDD). Please refer to FIG. 4A, which is a signal timing diagram of a normal display device according to an embodiment of the present invention. As can be seen in FIG. 4A, as long as the voltage of any one of the scan lines is high, the signal VREAD will be a high voltage. If the scan line S 2 has a broken line, please refer to FIG. 4B , which is a signal timing diagram of the abnormal display device according to an embodiment of the present invention. Since the scan line S 2 has a disconnection, in the second time interval P 2 , even if the gate drive circuit 1100 sends a high voltage to the scan line S 2 , the gate voltage of the transistor switch TD 2 does not become a high voltage. Instead, it maintains a low voltage. Thus, in the second time interval P 2 , the transistor switch TD 2 is not turned on, so the signal VREAD maintains a low voltage in the second time interval P 2 . So that the user, or the gate driving circuit 1100 to the source driver circuit 1200 by comparing a first voltage terminal V signal and a signal VREAD 1 and determines whether the gate driving line disconnection and which drives a gate line break .
然而，第一電壓端V 1所提供的電壓不必然要是直流電壓。請參照圖4C，其係依據本發明一實施例的正常的顯示裝置的信號時序圖。相較於圖4A的實施例，第一電壓端V 1所提供的電壓實質上可以具有任意波形，而圖4C的實施例中，第一電壓端V 1所提供的電壓為齒狀波(sawtooth wave)。因此在每當有任意一條掃描線上的電壓為高電壓時，信號VREAD的波形會對應於第一電壓端V 1所提供的波形。設若掃描線S 2有斷線，則請參照圖4D其係依據本發明一實施例的異常的顯示裝置的信號時序圖。由於掃描線S 2有斷線，因此在第二時間區間P 2中，即使閘極驅動電路1100對掃描線S 2送出高電壓，但是電晶體開關TD 2的閘極電壓並不會變成高電壓，而是維持低電壓。從而在第二時間區間P 2中，電晶體開關TD 2未導通，因此信號VREAD在第二時間區間P 2中維持低電壓。從而使用者、閘極驅動電路1100或是源極驅動電路1200得以藉由比較第一電壓端V 1的信號與信號VREAD而判斷是否有閘極驅動線斷線以及哪一條閘極驅動線斷線。 However, the voltage supplied by the first voltage terminal V 1 does not necessarily have to be a DC voltage. Please refer to FIG. 4C, which is a signal timing diagram of a normal display device according to an embodiment of the present invention. Compared with the embodiment of FIG. 4A, the voltage provided by the first voltage terminal V 1 may have an arbitrary waveform, and in the embodiment of FIG. 4C , the voltage provided by the first voltage terminal V 1 is a tooth waveform (sawtooth). Wave). Therefore, whenever an arbitrary scan line voltage is high voltage, VREAD waveform signal corresponding to the waveform will be a first voltage terminal V 1 is provided. If the scan line S 2 has a broken line, please refer to FIG. 4D , which is a signal timing diagram of the abnormal display device according to an embodiment of the present invention. Since the scan line S 2 has a disconnection, in the second time interval P 2 , even if the gate drive circuit 1100 sends a high voltage to the scan line S 2 , the gate voltage of the transistor switch TD 2 does not become a high voltage. Instead, it maintains a low voltage. Thus, in the second time interval P 2 , the transistor switch TD 2 is not turned on, so the signal VREAD maintains a low voltage in the second time interval P 2 . So that the user, or the gate driving circuit 1100 to the source driver circuit 1200 by comparing a first voltage terminal V signal and a signal VREAD 1 and determines whether the gate driving line disconnection and which drives a gate line break .
於本發明另一實施例中，請參照圖5，其係依據本發明另一實施例的顯示裝置電路架構示意圖。如圖5所示，依據本發明一實施例的顯示裝置1000具有閘極驅動電路1100、源極驅動電路1200、多條閘極驅動線(掃描線)S 1~S N、多條源極驅動線(資料線)D 1~D M、多個電晶體開關TD 1~TD M與讀取線READ。每條源極驅動線具有第一端與第二端，以圖5為例，源極驅動線的第一端為下端(以圖5而言，Y軸座標較小的一端)，而源極驅動線的第二端為上端(以圖5而言，Y軸座標較大的一端)。每條源極驅動線的第一端連接於源極驅動電路1100。每個電晶體開關具有第一端、第二端與控制端。每個電晶體開關的第一端電性連接於第一電壓端V 1，而每個電晶體開關的控制端電性連接於對應的一條源極驅動線的第二端。讀取線READ電性連接於每個電晶體開關的第二端。於本實施例中，雖然讀取線READ電性連接至源極驅動電路1200。然而於其他實施方式中，讀取線READ或是被外接至一個信號輸出端以便於使用者或檢測者進行量測，或是電性連接至閘極驅動電路1100，本發明並不加以限制。 In another embodiment of the present invention, please refer to FIG. 5 , which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. As shown in FIG. 5, a display device 1000 according to an embodiment of the present invention has a gate driving circuit 1100, a source driving circuit 1200, a plurality of gate driving lines (scanning lines) S 1 to S N , and a plurality of source drivers. Line (data line) D 1 ~ D M , multiple transistor switches TD 1 ~ TD M and read line READ. Each of the source driving lines has a first end and a second end. As shown in FIG. 5, the first end of the source driving line is a lower end (in FIG. 5, the smaller end of the Y-axis coordinate), and the source The second end of the drive line is the upper end (in Figure 5, the larger end of the Y-axis coordinate). A first end of each of the source driving lines is connected to the source driving circuit 1100. Each transistor switch has a first end, a second end, and a control end. The first end of each of the transistor switches is electrically connected to the first voltage terminal V 1 , and the control end of each of the transistor switches is electrically connected to the second end of the corresponding one of the source driving lines. The read line READ is electrically connected to the second end of each of the transistor switches. In the present embodiment, the read line READ is electrically connected to the source drive circuit 1200. However, in other embodiments, the read line READ is either externally connected to a signal output for measurement by the user or the detector, or electrically connected to the gate drive circuit 1100, and the invention is not limited thereto.
因此，請參照圖6A，其係依據本發明一實施例的正常的顯示裝置的信號時序圖。如圖6A所示，其中信號VS 1至信號VS N係由閘極驅動電路1100送到閘極驅動線S 1~S N的電壓，信號VD 1與信號VD 2係由源極驅動電路1200分別送到源極驅動線D 1與D 2的電壓，信號V 1即為第一電壓端V 1的電壓，信號VREAD則為讀取線READ所讀取到的電壓。一個畫面時間區間PF包含第一時間區間P 1至第N時間區間P N(也就是更新時間區間)以及空白時間區間PB，於第一時間區間P 1至第N時間區間P N，閘極驅動電路1100分別對閘極驅動線S 1至閘極驅動線S N提供高準位的脈波(pulse)，而在空白時間區間PB中，源極驅動電路1200對源極驅動線D 1至源極驅動線D M其中部份的源極驅動線依序提供高準位的脈波。 Therefore, please refer to FIG. 6A, which is a signal timing diagram of a normal display device according to an embodiment of the present invention. As shown in FIG. 6A, the signals VS 1 to VS N are sent to the gate driving lines S 1 -S N by the gate driving circuit 1100, and the signals VD 1 and VD 2 are respectively driven by the source driving circuit 1200. voltage signal V to the first voltage terminal. 1 is the source lines D 1 and D 2 of the V voltage, VREAD 1 compared with the signal read line to rEAD the read voltage. A picture time interval PF includes a first time interval P 1 to an Nth time interval P N (that is, an update time interval) and a blank time interval PB, in the first time interval P 1 to the Nth time interval P N , the gate drive The circuit 1100 provides a high-level pulse to the gate drive line S 1 to the gate drive line S N , respectively, and in the blank time interval PB , the source drive circuit 1200 pairs the source drive line D 1 to the source A portion of the source drive lines of the pole drive line D M sequentially provide high-level pulse waves.
舉例來說，在空白時間區間PB中，源極驅動電路1200先對源極驅動線D 1提供脈波，接著對源極驅動線D 2提供脈波，並且同時第一電壓端V 1也提供脈波。於一實施例中，第一電壓端提供的脈波的寬度小於源極驅動電路1200對各源極驅動線提供的脈波的寬度，然不以此為限。根據此實施例，在各個時間區間中，信號VREAD的電壓如圖6A所示，實質同步於第一電壓端V 1所提供的脈波。每一個畫面時間區間PF的空白時間區間PB例如被區分為四個偵測時間區間，而源極驅動電路1200於一個空白時間區間PB的四個偵測時間區間分別對源極驅動線織中的四條依序提供電壓。所提供的電壓(驅動電壓)需要能使電晶體開關導通。 For example, the blank time interval PB, a source driving circuit 1200 to provide a pulse wave to the source lines D 1, then provides a pulse wave of source lines D 2, and while the first terminal voltage V 1 is also provided Pulse wave. In one embodiment, the width of the pulse wave provided by the first voltage terminal is smaller than the width of the pulse wave provided by the source driving circuit 1200 for each source driving line, but is not limited thereto. According to this embodiment, in each time interval, the voltage signal VREAD 6A, the essence of the pulse wave in synchronization with the first voltage terminal V 1 is provided. The blank time interval PB of each picture time interval PF is divided into four detection time intervals, for example, and the source drive circuit 1200 is respectively in the source detection line in the four detection time intervals of one blank time interval PB. Four pieces of voltage are supplied in sequence. The voltage (drive voltage) supplied needs to be able to turn on the transistor switch.
相對的，請參照圖6B其係依據本發明一實施例的異常的顯示裝置的信號時序圖。圖6B所對應的狀態是在源極驅動線D 2上有斷線，因此於某一個空白時間區間PB中，信號VREAD與第一電壓端V 1的信號不同步，從而使用者、閘極驅動電路1100或是源極驅動電路1200得以藉由比較第一電壓端V 1的信號與信號VREAD而判斷是否有閘極驅動線斷線以及哪一條閘極驅動線斷線。 In contrast, please refer to FIG. 6B , which is a signal timing diagram of an abnormal display device according to an embodiment of the present invention. The state corresponding to FIG. 6B is that there is a disconnection on the source driving line D 2 , so in a certain blank time interval PB, the signal VREAD is not synchronized with the signal of the first voltage terminal V 1 , so that the user and the gate drive the source driver circuit 1100 or the circuit 1200 is generated by comparing a first voltage terminal V signal and a signal VREAD 1 and determines whether the gate driving line disconnection and which drives a gate line disconnection.
請參照圖7，其係依據本發明另一實施例的顯示裝置電路架構示意圖。如圖7所示，依據本發明另一實施例的顯示裝置1000具有閘極驅動電路1100、源極驅動電路1200、多條閘極驅動線(掃描線)S 1~S N、多條源極驅動線(資料線)D 1~D M、多個電晶體開關TD 1~TD M與讀取線READ。每條源極驅動線具有第一端與第二端，以圖7為例，源極驅動線的第一端為下端(以圖7而言Y軸座標較小的一端)，而源極驅動線的第二端為上端(以圖7而言Y軸座標較大的一端)。每條源極驅動線的第一端連接於源極驅動電路1200。每個電晶體開關具有第一端、第二端與控制端。每個電晶體開關的第一端電性連接於第一電壓端V 1，而每個電晶體開關的控制端電性連接於對應的一條源極驅動線的第二端。讀取線READ電性連接於每個電晶體開關的第二端。更具體來說，於圖7的實施例中，電晶體開關TD 1的第一端連接於第一電壓端V 1，電晶體開關TD 2的第一端連接於電晶體開關TD 1的第二端，每個電晶體開關串接，電晶體開關TD M的第一端連接於電晶體開關TD M-1的第二端而電晶體開關TD M的第二端連接至讀取線READ。因此於本實施例中，第一電壓端V 1於空白時間區間PB中提供一個脈波，而源極驅動電路1200於空白時間區間PB中同時對每條源極驅動線D 1至D M提供高電壓，從而使電晶體開關TD 1至電晶體開關TD M能同時導通。因此，使用者、閘極驅動電路1100或源極驅動電路1200得以藉由偵測空白時間區間PB中信號VREAD是否與第一電壓端V 1所提供的脈波對應，而判斷是否有任何一條源極驅動線有斷線的異常問題。 Please refer to FIG. 7, which is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. As shown in FIG. 7, a display device 1000 according to another embodiment of the present invention has a gate driving circuit 1100, a source driving circuit 1200, a plurality of gate driving lines (scanning lines) S 1 to S N , and a plurality of sources. Drive line (data line) D 1 ~D M , multiple transistor switches TD 1 ~TD M and read line READ. Each of the source driving lines has a first end and a second end. As shown in FIG. 7, the first end of the source driving line is a lower end (the smaller end of the Y-axis coordinate in FIG. 7), and the source is driven. The second end of the line is the upper end (the larger end of the Y-axis coordinate in Figure 7). The first end of each of the source driving lines is connected to the source driving circuit 1200. Each transistor switch has a first end, a second end, and a control end. The first end of each of the transistor switches is electrically connected to the first voltage terminal V 1 , and the control end of each of the transistor switches is electrically connected to the second end of the corresponding one of the source driving lines. The read line READ is electrically connected to the second end of each of the transistor switches. More specifically, in the embodiment of FIG. 7, the first end of the transistor switch TD 1 is connected to the first voltage terminal V 1 , and the first end of the transistor switch TD 2 is connected to the second end of the transistor switch TD 1 . End, each transistor switch is connected in series, the first end of the transistor switch TD M is connected to the second end of the transistor switch TD M-1 and the second end of the transistor switch TD M is connected to the read line READ. Therefore, in the embodiment, the first voltage terminal V 1 provides a pulse wave in the blank time interval PB, and the source driving circuit 1200 simultaneously supplies each of the source driving lines D 1 to D M in the blank time interval PB. The high voltage allows the transistor switch TD 1 to the transistor switch TD M to be turned on at the same time. Thus, a user, the gate driving circuit 1100 or the source driver circuit 1200 is detected by the pulse wave interval corresponding to the time blank signal PB whether the first VREAD voltage terminal V 1 is provided, and determines whether any one source The pole drive line has an abnormality of disconnection.
於另一實施例中，請參照圖8，其係依據本發明再一實施例的顯示裝置電路架構示意圖。如圖8所示，依據本發明一實施例的顯示裝置1000具有閘極驅動電路1100、源極驅動電路1200、多條閘極驅動線(掃描線)S 1~S N、多條源極驅動線(資料線)D 1~D M、多個電晶體開關TD 1~TD M與讀取線READ。每條源極驅動線具有第一端與第二端，以圖8為例，源極驅動線的第一端為下端(以圖8而言Y軸座標較小的一端)，而源極驅動線的第二端為上端(以圖8而言Y軸座標較大的一端)。每條源極驅動線的第一端連接於源極驅動電路1200。每個電晶體開關具有第一端、第二端與控制端。電晶體開關TD 1的第一端電性連接於第一電壓端V 11，電晶體開關TD 2的第一端電性連接於第一電壓端V 12，電晶體開關TD M的第一端電性連接於第一電壓端V 1M，而每個電晶體開關的控制端電性連接於對應的一條源極驅動線的第二端。讀取線READ電性連接於每個電晶體開關的第二端。更具體來說，於圖6的實施例中，電晶體開關TD 2的第一端連接於電晶體開關TD 1的第二端，每個電晶體開關串接，電晶體開關TD M的第一端連接於電晶體開關TD M-1的第二端而電晶體開關TD M的第二端連接至讀取線READ。因此於本實施例中，第一電壓端V 11至第一電壓端V 1M於空白時間區間PB中分別循序提供一個脈波，而源極驅動電路1200於空白時間區間PB中同時對每條源極驅動線D 1至D M提供高電壓，從而使電晶體開關TD 1至電晶體開關TD M能同時導通。因此，使用者、閘極驅動電路1100或源極驅動電路1200得以藉由偵測空白時間區間PB中信號VREAD是否與第一電壓端V 11至第一電壓端V 1M所提供的脈波對應，而判斷是否有任何一條源極驅動線有斷線的異常問題。具體來說，設若電晶體開關TD 2的控制端所連接的源極驅動線D 2有斷線問題，則第一電壓端V 11與第一電壓端V 12所提供的脈波無法被傳送至讀取線READ，因此經由信號VREAD，這樣的斷線問題得以被檢查出來。 In another embodiment, please refer to FIG. 8 , which is a schematic diagram of a circuit structure of a display device according to still another embodiment of the present invention. As shown in FIG. 8, a display device 1000 according to an embodiment of the present invention has a gate driving circuit 1100, a source driving circuit 1200, a plurality of gate driving lines (scanning lines) S 1 to S N , and a plurality of source drivers. Line (data line) D 1 ~ D M , multiple transistor switches TD 1 ~ TD M and read line READ. Each of the source driving lines has a first end and a second end. As shown in FIG. 8 , the first end of the source driving line is a lower end (the smaller end of the Y-axis coordinate in FIG. 8 ), and the source is driven. The second end of the line is the upper end (the larger end of the Y-axis coordinate in Figure 8). The first end of each of the source driving lines is connected to the source driving circuit 1200. Each transistor switch has a first end, a second end, and a control end. The first end of the transistor switch TD 1 is electrically connected to the first voltage terminal V 11 , the first end of the transistor switch TD 2 is electrically connected to the first voltage terminal V 12 , and the first end of the transistor switch TD M is electrically a first terminal connected to the voltage V 1M, and the control terminal of each transistor is electrically connected to a switching source electrode corresponding to the second end of the drive line. The read line READ is electrically connected to the second end of each of the transistor switches. More specifically, in the embodiment of FIG. 6, the first end of the transistor switch TD 2 is connected to the second end of the transistor switch TD 1 , and each of the transistor switches is connected in series, and the first of the transistor switches TD M The end is connected to the second end of the transistor switch TD M-1 and the second end of the transistor switch TD M is connected to the read line READ. Therefore, in the embodiment, the first voltage terminal V 11 to the first voltage terminal V 1M sequentially provide one pulse wave in the blank time interval PB, and the source driving circuit 1200 simultaneously pairs each source in the blank time interval PB. electrode driving lines D 1 provides a high voltage to the D M, so that the switching transistor to transistor TD 1 TD M switch can be turned on simultaneously. Therefore, the user, the gate driving circuit 1100 or the source driving circuit 1200 can detect whether the signal VREAD in the blank time interval PB corresponds to the pulse wave provided by the first voltage terminal V 11 to the first voltage terminal V 1M . And to determine whether any of the source drive lines have an abnormality of disconnection. Specifically, if the source driving line D 2 connected to the control terminal of the transistor switch TD 2 has a disconnection problem, the pulse wave provided by the first voltage terminal V 11 and the first voltage terminal V 12 cannot be transmitted to The line READ is read, so such a disconnection problem can be checked via the signal VREAD.
綜上所述，本發明藉由加入受控於閘極驅動線或源極驅動線的電晶體開關，並藉由對應的電壓端所提供的信號，閘極驅動電路或源極驅動電路得以判斷是否有任何驅動線有斷線的問題。In summary, the present invention can be judged by adding a transistor switch controlled by a gate driving line or a source driving line, and by a signal provided by a corresponding voltage terminal, a gate driving circuit or a source driving circuit. Is there any problem with the drive line being broken?
雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明。在不脫離本發明之精神和範圍內，所為之更動與潤飾，均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.
1000‧‧‧顯示裝置
1100‧‧‧閘極驅動電路
1110‧‧‧電壓重置電路
1200‧‧‧源極驅動電路
S1~SN‧‧‧閘極驅動線
D1~DM‧‧‧源極驅動線
TS1~TSN‧‧‧電晶體開關
TD1~TDM‧‧‧電晶體開關
READ‧‧‧讀取線
V1、V11~V1M‧‧‧第一電壓端
PF‧‧‧畫面時間區間
P1~PN、PB‧‧‧時間區間
VREAD、VS1~VSN、VD1、VD2‧‧‧信號1000‧‧‧ display device
1100‧‧‧ gate drive circuit
1110‧‧‧Voltage reset circuit
1200‧‧‧ source drive circuit
S 1 ~S N ‧‧‧ gate drive line
D 1 ~D M ‧‧‧Source drive line
TS 1 ~TS N ‧‧‧Chip Switch
TD 1 ~TD M ‧‧‧Chip Switch
READ‧‧‧ read line
V 1 , V 11 ~V 1M ‧‧‧first voltage end
PF‧‧‧ screen time interval
P 1 ~P N , PB‧‧‧ time interval
VREAD, VS 1 ~VS N , VD 1 , VD 2 ‧‧‧ signals
圖1係依據本發明一實施例的顯示裝置電路架構示意圖。 圖2A係依據本發明一實施例的正常的顯示裝置的信號時序圖。 圖2B係依據本發明一實施例的異常的顯示裝置的信號時序圖。 圖3係依據本發明另一實施例的顯示裝置電路架構示意圖。 圖4A係依據本發明一實施例的正常的顯示裝置的信號時序圖。 圖4B係依據本發明一實施例的異常的顯示裝置的信號時序圖。 圖4C係依據本發明一實施例的正常的顯示裝置的信號時序圖。 圖4D係依據本發明一實施例的異常的顯示裝置的信號時序圖。 圖5係依據本發明另一實施例的顯示裝置電路架構示意圖。 圖6A係依據本發明一實施例的正常的顯示裝置的信號時序圖。 圖6B係依據本發明一實施例的異常的顯示裝置的信號時序圖。 圖7係依據本發明另一實施例的顯示裝置電路架構示意圖。 圖8係依據本發明再一實施例的顯示裝置電路架構示意圖。FIG. 1 is a schematic diagram of a circuit structure of a display device according to an embodiment of the invention. 2A is a signal timing diagram of a normal display device in accordance with an embodiment of the present invention. 2B is a signal timing diagram of an abnormal display device in accordance with an embodiment of the present invention. 3 is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. 4A is a signal timing diagram of a normal display device in accordance with an embodiment of the present invention. 4B is a signal timing diagram of an abnormal display device in accordance with an embodiment of the present invention. 4C is a signal timing diagram of a normal display device in accordance with an embodiment of the present invention. 4D is a signal timing diagram of an abnormal display device in accordance with an embodiment of the present invention. FIG. 5 is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. 6A is a signal timing diagram of a normal display device in accordance with an embodiment of the present invention. 6B is a signal timing diagram of an abnormal display device in accordance with an embodiment of the present invention. FIG. 7 is a schematic diagram of a circuit structure of a display device according to another embodiment of the present invention. FIG. 8 is a schematic diagram of a circuit structure of a display device according to still another embodiment of the present invention.
1000‧‧‧顯示裝置 1000‧‧‧ display device
1100‧‧‧閘極驅動電路 1100‧‧‧ gate drive circuit
1200‧‧‧源極驅動電路 1200‧‧‧ source drive circuit
S1~SN‧‧‧閘極驅動線 S 1 ~S N ‧‧‧ gate drive line
D1~DM‧‧‧源極驅動線 D 1 ~D M ‧‧‧Source drive line
TS1~TSN‧‧‧電晶體開關 TS 1 ~TS N ‧‧‧Chip Switch
TD1~TDM‧‧‧電晶體開關 TD 1 ~TD M ‧‧‧Chip Switch
READ‧‧‧讀取線 READ‧‧‧ read line
V1‧‧‧第一電壓端 V 1 ‧‧‧first voltage end
Claims (9)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105114939A TWI571849B (en) | 2016-05-13 | 2016-05-13 | Display device |
| CN201610554145.5A CN106057108A (en) | 2016-05-13 | 2016-07-14 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105114939A TWI571849B (en) | 2016-05-13 | 2016-05-13 | Display device |
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| TWI571849B true TWI571849B (en) | 2017-02-21 |
| TW201740359A TW201740359A (en) | 2017-11-16 |
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| TW105114939A TWI571849B (en) | 2016-05-13 | 2016-05-13 | Display device |
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| CN (1) | CN106057108A (en) |
| TW (1) | TWI571849B (en) |
Citations (4)
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|---|---|---|---|---|
| TW582011B (en) * | 2000-01-06 | 2004-04-01 | Toshiba Corp | Array substrate and method of inspecting the same |
| TW200515357A (en) * | 2003-09-19 | 2005-05-01 | Wintest Corp | Inspection method and inspection device for display device and active matrix substrate used for display device |
| TW200528947A (en) * | 2004-02-24 | 2005-09-01 | Bing-Ru Wu | Programmable control single-chip integrated with memories and writing interface |
| TW200813926A (en) * | 2006-09-04 | 2008-03-16 | Hannstar Display Corp | Liquid crystal display |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008292834A (en) * | 2007-05-25 | 2008-12-04 | Hitachi Displays Ltd | Display device |
| US8946994B2 (en) * | 2012-09-25 | 2015-02-03 | Lg Display Co., Ltd. | Organic light emitting display device and driving method thereof |
| JP6089656B2 (en) * | 2012-12-07 | 2017-03-08 | 凸版印刷株式会社 | Display device and display method |
| CN203055406U (en) * | 2012-12-24 | 2013-07-10 | 北京京东方光电科技有限公司 | Signal line detecting device and display device for substrate |
-
2016
- 2016-05-13 TW TW105114939A patent/TWI571849B/en not_active IP Right Cessation
- 2016-07-14 CN CN201610554145.5A patent/CN106057108A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW582011B (en) * | 2000-01-06 | 2004-04-01 | Toshiba Corp | Array substrate and method of inspecting the same |
| TW200515357A (en) * | 2003-09-19 | 2005-05-01 | Wintest Corp | Inspection method and inspection device for display device and active matrix substrate used for display device |
| TW200528947A (en) * | 2004-02-24 | 2005-09-01 | Bing-Ru Wu | Programmable control single-chip integrated with memories and writing interface |
| TW200813926A (en) * | 2006-09-04 | 2008-03-16 | Hannstar Display Corp | Liquid crystal display |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201740359A (en) | 2017-11-16 |
| CN106057108A (en) | 2016-10-26 |
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