TWI554017B - Method for voltage detection by b-duty - Google Patents

Description

Voltage detection circuit and method for detecting voltage change

The invention mainly relates to a power conversion system, in particular to a detection circuit for detecting a voltage of a sinusoidal AC mains rectification in a device applied to an AC to DC power conversion, and providing a corresponding detection method. The voltage detection circuit easily monitors and detects the change state of the input voltage amplitude and outputs the detection result.

In a conventional power conversion system, an AC/DC converter is used to convert the AC input voltage V _AC provided by the grid into a desired DC voltage V _DC , and then the voltage converter is used to modulate the voltage V _{DC to} output the final tool. The DC output voltage V _{OUT of the} tiny ripple is a conventional technique used in existing AC/DC conversion systems. The problem is that the AC input voltage V _{AC does} not always have a stable peak or RMS value. When the AC input voltage V _{AC from the mains} enters an undervoltage or overvoltage condition, it may cause damage to the AC/DC converter. Therefore, it is necessary to monitor and judge the changing trend of the AC input voltage V _AC in real time.

In U.S. Patent Application No. US20090141523, a voltage divider is constructed using two resistors in series and a detection voltage reflecting a change in the input voltage V _AC is generated at a common node between them. The two resistors are connected in series between the DC power source V _M outputting the input voltage V _AC and the ground terminal. It is known to those skilled in the art that the conduction of current through the two resistors consumes power, even though the two resistors Just as an auxiliary detection component. In view of this, it is required to provide a device which can be effectively used for detecting the change of the input voltage V _AC , and the device can accurately reflect the trend of the voltage V _AC directly and without error, and is required to avoid the device for detecting the input voltage V _AC . Unnecessarily excessive energy consumption is a difficult problem to be solved.

In one embodiment, the present invention discloses a voltage detection circuit comprising: A rectifying circuit rectifies the alternating current voltage into a direct current input voltage; a detecting unit receives the input voltage and generates a detecting voltage signal having a different logic state according to the fluctuation of the input voltage; and one is used for cyclic charging and discharging a charging current source unit, wherein the detecting voltage signal sent by the detecting unit has a second state to charge the capacitor; and a discharging current source unit, the detecting voltage signal sent by the detecting unit has The first state causes the capacitor to discharge; a main comparator compares a voltage across the capacitor with a critical zero potential during an alternating charge and discharge of the capacitor, and outputs a detection signal with a trend indicating the change in the input voltage. .

The voltage detecting circuit triggers the detecting unit to generate a detecting voltage signal having a first state when the input voltage exceeds a preset value; and triggers the detecting unit to generate when the input voltage is lower than a preset value A detection voltage signal having a second state.

In the above voltage detecting circuit, in the detecting unit, an anode of a Zener diode is connected to a drain of a junction field effect transistor, and an input voltage is applied to the Zener diode cathode, and the preset is set. The value is equal to the breakdown voltage of the Zener diode, thereby generating a detection voltage signal at the source of the junction field effect transistor.

In the above voltage detecting circuit, the source of the junction field effect transistor JFET is connected to the non-inverting input terminal of a comparator in the detecting unit, and the inverting input terminal of the comparator inputs a threshold voltage V _TH ; when the input voltage is high At the preset value, the detected voltage signal potential is greater than the threshold voltage V _TH , and the detected voltage signal has a logic high first state, so that the driving signal outputted by the comparator of the detecting unit is at a high level; The voltage is lower than the preset value, so that the detected voltage signal potential is less than the threshold voltage V _TH , and the detected voltage signal has a logic low second state, so that the driving signal output by the comparator of the detecting unit is a low level.

Said voltage detection circuit, a charging current source unit comprises a voltage to current converter and out switch SW _1, out switch SW ₁ is connected between a voltage source and an input terminal of the voltage-current converter; when the detected voltage signal has a second state, the detecting unit transmits a drive signal turns on the switch SW _1, a voltage source for conversion into a charging current to the charging current source means, the charging current to the capacitor causes the capacitor to charge.

In the above voltage detecting circuit, the discharging current source unit comprises a voltage current converter and a switch SW ₂ , the switch SW _{2 is} connected between a voltage source and the input of the voltage current converter; when the detecting voltage signal has the first state, The detecting unit sends a driving signal to turn on the switch SW ₂ to supply a voltage source for converting the discharging current to the discharging current source unit, and the capacitor discharges the amount of the electric charge by the discharging current.

The voltage detecting circuit detects that the voltage signal is turned from the first state to the falling edge of the second state, starts charging the capacitor, and detects that the voltage signal is flipped from the second state to the rising edge of the first state, and starts to release the capacitor. The amount of charge; and each time the detected voltage signal is flipped from the first state to the second state, each time the capacitor is charged, an instantaneous discharge step is performed on the capacitor.

Said voltage detection circuit, a capacitor is provided in parallel with one end grounded and the switch SW _3, the drive signal detection unit transmitted after inverted by an inverter is supplied to a monostable flip-flop input terminal, and the monostable the output of the flip-flop is connected to the control terminal of the switch SW _3; and by the falling edge detection signal voltage by the rising edge of the inverted by an inverter, to trigger a monostable multivibrator for driving the transfer switch SW ₃ connected The output signal is turned on, and the switch SW _{3 is used} to perform instantaneous discharge on the capacitor.

The voltage detecting circuit supplies a reference input voltage having a reference effective value V _HVR to the detecting unit, and sets a Zener breakdown voltage of the Zener diode to be V _Z1 , and detects in one cycle of the reference input voltage. The first state of the voltage signal has a reference duty cycle D _B of: At the same time, it is set between the current value I ₁ for charging the capacitor and the current value I _{2 for} discharging the capacitor:

In the above voltage detecting circuit, when the actual duty ratio is greater than the reference duty ratio D _B , the detection signal outputted by the main comparator generates a high level in each period of the actual input voltage, and the result of the detection signal represents the actual input. The peak value of the voltage is greater than the peak value of the reference input voltage; or when the actual duty ratio is less than the reference duty ratio D _B , the detection signal output by the main comparator does not generate any high level in each period of the actual input voltage The result of the detection signal indicates that the peak value of the actual input voltage is smaller than the peak value of the reference input voltage.

The voltage detecting circuit connects the output end of the comparator in the detecting unit to the input end of a counter Counter, and when the counter detects that the comparison result of the comparator output of the detecting unit is low, the low level state is maintained for more than one period. At the preset time, it can be judged that the input voltage is in an undervoltage state.

In another embodiment, the present invention discloses a method for detecting a voltage change, comprising the steps of: rectifying an alternating current voltage into a direct current input voltage by using a rectifying circuit; receiving the input voltage by a detecting unit, and The fluctuation of the input voltage level, thereby generating a detection voltage signal having different logic states by the detecting unit; performing a cyclic charging and discharging program on one capacitor; and detecting the detection sent by the detecting unit during charging of the capacitor When the voltage signal has the second state, the capacitor is charged by a charging current source unit; during the discharging of the capacitor, when the detecting voltage signal sent by the detecting unit has the first state, using a discharging current source The unit discharges the capacitor; using a main comparator to compare the voltage across the capacitor with a critical zero potential during the alternating charge and discharge of the capacitor, with the main comparator output having the identified input voltage The comparison result of the change trend is used as the final detection signal for detecting the change of the input voltage.

In the above method, when the input voltage exceeds a preset value, the detecting unit is triggered to generate a detection voltage signal having a first state; and when the input voltage is lower than a preset value, triggering the detecting unit to generate A detected voltage signal of the second state.

In the above method, in the detecting unit, an anode of a Zener diode is connected to a drain of a junction field effect transistor JFET, and an input voltage is input from a Zener diode cathode, and the The preset value is equal to the breakdown voltage of the Zener diode, so that a detection voltage signal is generated at the source of the junction field effect transistor.

In the above method, the source of the junction field effect transistor JFET is connected to the non-inverting input terminal of a comparator in the detecting unit, and a threshold voltage V _TH is input at the inverting input terminal of the comparator; when the input voltage is high And at the preset value, the detected voltage signal potential is greater than the threshold voltage V _TH , and the detected voltage signal has a logic high first state, and the detection signal of the comparator output of the detecting unit is a high level; when the input voltage is Below the preset value, the detected voltage signal potential is less than the threshold voltage V _TH , and the detected voltage signal has a second state with a logic low, and the driving signal output by the comparator of the detecting unit is a low level.

The above method, the charging current source unit comprises a voltage to current converter ₁ and a switch SW, the switch SW is connected to the voltage converter is a voltage-current voltage source and the charging current source unit ₁ rotation between a current input terminal; when the detection voltage when a signal having a second state, the detection unit transmits the driving signal turns on the switch SW _1, to provide a voltage source for conversion into a charging current for the charging current source means, the charging current to the capacitor causes the capacitor to charge.

The above method, the discharge current source unit comprises a voltage to current converter ₂ and a switch SW, the switch SW is connected to the voltage converter is a voltage-current voltage source and the discharging current source unit ₂ revolutions between the current input terminal; when the detection voltage signal having a first state when the detecting unit transmits the driving signal turns on the switch SW _2, a voltage source for converting the discharge current into a discharge current source means the capacitor by a discharge current to discharge the electric charge amount.

In the above method, when the detected voltage signal is turned from the first state to the falling state of the second state, the capacitor is charged, and when the detected voltage signal is flipped from the second state to the rising edge of the first state, the capacitor is released. The amount of charge; and each time the detected voltage signal is flipped from the first state to the second state, each time the capacitor is charged, an instantaneous discharge step is performed on the capacitor.

The above-described method, a set _3, one end of the switch SW ₃ is grounded, the drive signal transmitted from the detecting unit capacitor in parallel with the switch SW is supplied to the charging and discharging of a monostable multivibrator and then through an inverter inverting input terminal further connecting an output of the monostable flip-flop to the control terminal of the switch SW _3; so the falling edge detection signal voltage by the rising edge of the inverted by an inverter, to trigger the monostable primary drive transfer the output signal of the switch SW ₃ is turned on, so that the use of state of the switch SW ₃ is turned on to discharge the capacitor instantaneously executed.

In the above method, a reference input voltage having a reference effective value V _HVR is supplied to the detecting unit, and the Zener breakdown voltage of the Zener diode is set to V _Z1 , and the voltage signal is detected within one cycle of the reference input voltage. The first state has a reference duty cycle D _B of: At the same time, it is set between the current value I _{1 of} the capacitor charging and the current value I _{2 for} discharging the capacitor:

In the above method, when the actual duty ratio is greater than the reference duty ratio D _B , the detection signal outputted by the main comparator will be triggered to generate a high level in each period of the actual input voltage, indicating that the peak value of the actual input voltage is greater than The peak value of the reference input voltage is large; or when the actual duty ratio is less than the reference duty ratio D _B , the detection signal that will trigger the output of the main comparator does not generate any high level in each period of the actual input voltage, indicating The peak value of the actual input voltage is smaller than the peak value of the reference input voltage.

100 107‧‧‧ nodes

101‧‧‧Connected field effect transistor

115‧‧‧Bridge rectifier

116‧‧‧Voltage Converter

121‧‧‧ comparator

122‧‧‧Inverter

123‧‧‧One-shot trigger

128‧‧‧Main comparator

215‧‧‧Detection unit

225‧‧‧Rectifier circuit

235‧‧‧Charge and discharge circuit

235a‧‧‧Charging current source unit

235b‧‧‧Discharge current source unit

255‧‧‧Voltage detection circuit

ZD1‧‧‧Zina diode

D1 D4‧‧‧ diode

GND‧‧‧ ground terminal

R1‧‧‧ resistance

V _HV ‧‧‧ input voltage

V _Z ‧‧‧ breakdown voltage

I _D ‧‧‧current

V _SG ‧‧‧ forward pressure drop

V _GS ‧‧‧ voltage between source and gate

V _P ‧‧‧ pinch-off voltage

V _S ‧‧‧Dynamic detection voltage signal

V _AC ‧‧‧AC voltage

A high frequency filter capacitor C _X ‧‧‧

C _bulk ‧‧‧ output capacitor

V _O ‧‧‧DC output voltage

D2, D3‧‧‧ Rectifier

C _VDD ‧‧‧Power Capacitor

D _B ‧‧‧ actual duty cycle

V _HV1 , V _HV2 , V _HV3 ‧‧‧ amplitude input voltage

V _HVR ‧‧‧voltage rms

C _T ‧‧‧Charge and discharge capacitor

Switch SW ₁ SW ₂ ‧‧‧

V _S3 ‧‧‧Detection voltage signal

C _VDD ‧‧‧Power Capacitor

V _DD ‧‧‧DC power supply voltage

The features and advantages of the present invention will be apparent from the following detailed description and reference to the accompanying drawings. Figure 1A shows the basic detection unit structure for detecting the change state of the input voltage V _HV .

FIG. 1B is an output level waveform of the detecting unit when the input voltage V _HV exceeds the Zener diode breakdown voltage.

2 is a rectified AC voltage V _AC to obtain a DC input voltage V _HV and applied to the detecting unit.

Figure 3 is a detection signal that produces different duty cycles under different amplitude or peak DC input voltages V _HV .

Fig. 4A shows a charge and discharge circuit with a charge and discharge capacitor C _T .

4B~4C show the charging and discharging timings induced by the capacitance C _T corresponding to the logic high or low of different detection voltage signals under different duty cycle detection voltage signals.

Figure 5 is a voltage detection circuit including a detection unit.

Fig. 6 is a result of detection signals outputted by the voltage detecting circuit of the input voltage V _HV at different amplitudes/peaks.

Referring to FIG. 1A, the basic detecting unit 215 mainly includes a junction field effect transistor (JFET) 101, and the detecting unit 215 further has a Zener diode ZD1, and the anode of the Zener diode ZD1 is connected to The JFET 101 has a drain, and the source of the JFET 101 is connected to the anode of a diode D1, and the cathode of the diode D1 is connected to the ground GND. Further, the control terminal of the JFET 101, such as a gate, is connected to the ground GND, and a resistor R1 is connected between the gate and the source of the JFET 101. An input voltage V _HV as a DC voltage is input to the detecting unit 215 at a node 100 connected to the cathode end of the Zener diode ZD1. The input voltage V _HV is usually obtained by AC mains full-wave rectification, and the AC input is complete. The sinusoidal waveform is converted to the same polarity for output, and the positive half cycle and the negative half cycle of the original AC sinusoidal waveform are fully utilized to be converted into a DC voltage V _HV .

In the first case, when the input voltage V _{HV is} larger than the breakdown voltage V _{Z of} the Zener diode ZD1, the Zener diode ZD1 undergoes a reversible or self-healing recovery Zener breakdown, thus resulting in Current I _D flows from the drain of JFET 101 to the source. The current I _D will flow through the resistor R1 and the diode D1, and the forward voltage drop V _SG across the resistor R1 will thus rise, but will also cause the voltage V _GS between the source and the gate of the JFET 101 to decrease. Under budget conditions where the requirements are not very accurate, the voltage V _GS between the source and the gate of JFET 101 is roughly balanced by a voltage value V _P which is the pinch-off voltage of the JFET, V _GS is equal to |V _P | Negative value. Conversely, the voltage V _SG across resistor R1 will be equal to a positive value of V _P . In the second case, when the input voltage V _{HV is} smaller than the breakdown voltage V _Z of the Zener diode ZD1, the Zener diode ZD1 is not broken down, and thus does not generate any current flowing through the JFET 101. That is, the crossover voltage V _SG across the resistor R1 will be equal to zero, and the detection unit 215 has no power consumption at this stage. There is no doubt that even in the first case, there is a voltage across the resistor R1, but in the second case, the detecting unit 215 has no power consumption when monitoring the change state of the input voltage V _HV , so the overall power consumption of the detecting circuit is Limited to a smaller range.

Referring to FIG. 1B, when the Zener diode ZD1 breaks down, the characteristic detecting unit 215 enters the first case where the input voltage V _{HV is} greater than the breakdown voltage V _Z , the time period occurring and the time from time t ₁ to t ₃ . The paragraph corresponds. Taking one period T as an example, at time t ₁ , the input voltage V _HV tends to rise above the breakdown voltage V _Z , and the input voltage V _{HV is} greater than the breakdown voltage V _Z is maintained until the time t ₃ , and begins at time t ₃ . The input voltage V _HV falls below the breakdown voltage V _Z . In the first case, the voltage at the source terminal of the JFET 101 has a non-zero voltage V _S , which indicates that the source output of the JFET 101 is substantially a logic high level. We believe that the voltage V _S output by the detecting unit 215 has the first a state. Referring to FIG. 1B, still in the period T, contrary to the first case, the Zener diode ZD1 does not break down, and the characteristic detecting unit 215 enters the input voltage V _{HV which is} smaller than the breakdown voltage V _Z . In both cases, the time period in which it occurs is before time t ₁ and after time t ₃ . In the second case, the source of the JFET 101 should have a zero voltage V _S , indicating that the source output of the JFET 101 is substantially a logic low level. We believe that the voltage V _S output by the detecting unit 215 has a second status.

The present invention is directed to the varying voltage value produced by the source terminal of JFET 101 as the dynamic detection voltage signal V _S output by detection unit 215 in response to a change in input voltage V _HV . Figure 1B also shows the level logic state of the detection voltage V _S in a duty cycle manner, so as to visually reflect the first case where the Zener diode ZD1 is broken down and the Zener diode ZD1 is not The second case of being penetrated. The input voltage V _HV reaches a peak at time t ₂ , and the duration between the time node t ₁ and the time node t ₃ is 2 (t ₂ −t ₁ ), and the first state of the detection voltage V _S is in one cycle T the total length is maintained within ₂ (t 2 -t _1), the duty ratio corresponding to the detection voltage V _S having a first state (B-Duty) is D _B, D _B is also understood that the Zener The breakdown period of the diode ZD1 accounts for the period ratio.

Referring to FIG. 2, the AC voltage V _AC provided by the power grid is filtered by the high frequency filter capacitor C _{X to} filter out the high frequency clutter signal, and then input to a bridge rectifier 115, which is full-wave rectified by the bridge rectifier 115, at an output capacitor C. _The expected DC voltage is generated on the _bulk , and the DC voltage stored in the capacitor C _bulk is modulated by the voltage converter 116, such as step-up or step-down modulation, to finally output a DC ripple DC voltage V _O , which is existing. Conventional technology used in AC/DC conversion systems. In the present invention, two rectifying diodes D2 and D3 are additionally connected to the two input terminals of the AC voltage V _AC to form a rectifying circuit 225, and the anode of the diode D2 is connected to the high frequency filtering capacitor C. _At one end of _X , the anode of the other diode D3 is connected to the opposite end of the high frequency filter capacitor C _X . The cathodes of both the rectifying diodes D2, D3 are connected together and are also connected at the node 100 with the cathode of the Zener diode ZD1. Therefore, the AC voltage V _AC provided by the power grid is synchronously supplied to the rectifier circuit 225 in addition to the AC/DC conversion system, and the AC voltage V _AC is rectified by the rectifier circuit 225 to generate a DC at the cathodes of both of the diodes D2 and D3. The input voltage V _HV is input to the detecting unit 215 at the node 100, and the input voltage V _HV can be referred to the DC ripple waveform of the magnitude change obtained by rectification in FIG. 1B.

As an option, the detection unit/circuit 215 is only different from the detection unit 215 of FIG. 1A in that the source terminal of the JFET 101 is connected to the anode of a diode D4, but the cathode of the diode D4 is connected to the ground GND. A power supply capacitor C _VDD is also connected between them. When the Zener diode ZD1 breaks down, the current flowing through the JFET 101 can charge and store the power supply capacitor C _VDD to provide a DC voltage source for the AC/DC conversion system. When the Zener diode ZD1 does not break down, the power supply capacitor C _{VDD is} not charged. In addition, the other operating mechanism of the detecting unit 215 is the same as that of the detecting unit 215 in FIG. 1A. The diode D4 is mainly used to avoid power supply backflow, and the voltage source provided by the power supply capacitor C _{VDD is} prevented from clamping the voltage V _S at the source terminal node of the JFET 101 to a high potential.

Referring to FIG. 3, it is shown that the actual duty ratio D _B changes with the amplitude of the input voltage V _HV . For comparison, several different peaks may be sequentially transmitted at the cathode end of the Zener diode ZD1 of the detecting unit 215 . Or the amplitude input voltages V _HV1 , V _HV2 , V _HV3 , the peak value of the input voltage V _{HV3 is} the largest, the peak value of the input voltage V _{HV2 is} the smallest, and the peak value of the input voltage V _HV1 is between the two, but their periods T is exactly the same. The duty ratio of the detection voltage signal V _S1 outputted by the detecting unit 215 when the input voltage V _HV1 is supplied is D _B1 , and the duty ratio of the detection voltage signal V _S2 outputted by the detecting unit 215 when the input voltage V _HV2 is supplied is D _B2 , when the input voltage V _HV3 is supplied, the duty ratio of the detection voltage signal V _S3 output by the detecting unit 215 is D _B3 . As will be explained later, when the input voltages of the input amplitudes are different, the duty ratio D _{B3 is the} largest, and the duty ratio D _{B1 is} smaller than D _B3 but larger than D _B2 .

Referring to FIG. 1B, the duty ratio D _B satisfies the following functional relationship:

Since the input voltage V _HV is the rectification result of the positive half cycle and the negative half cycle of the alternating current, the instantaneous value V _HV (t ₁ ) of the input voltage V _HV at the time t ₁ , and the effective value voltage V _{HVR of the} input voltage V _HV , The breakdown voltage value V _Z1 of the nanodiode ZD1 satisfies the following functional relationship:

And the following functional relationship is also satisfied between the instantaneous value V _HV (t ₂ ) of the input voltage V _HV at the time t ₂ and the rms voltage V _{HVR of} the input voltage V _HV :

It can be known from the phase relationship of the sinusoidal quantity that ωt ₁ and ωt ₂ satisfy the following functional relationship:

Ωt ₂ =90° (5)

Divide formula (4) by (5) and substitute the result of the two into formula (1) to get:

Convert the formula (6) to get:

In essence, there is a difference in the exchange of electricity between countries and regions, and the so-called rms value, or voltage RMS V _HVR, may be different. Now we use V _HVR =100V as an example, and the Zener diode ZD1 An optional breakdown voltage value V _Z1 =50V is substituted into equation (7) for explanation:

It can be inferred that 1-D _B = 0.23 under the above conditions, that is, D _B = 0.77. The rms rms of the grid is generally uniquely determined in some countries or regions, but the breakdown voltage value V _Z1 can be flexibly adjusted. For example, directly select a certain type of Zener diode ZD1 and select its breakdown voltage V _Z1 to some A specific size value, or a series of Zener diodes ZD1 in series, multiplies the V _Z1 value by changing the number of ZD1.

4A, the charging and discharging circuit 235, the design of a charge and discharge capacitance C _T for a charging current source unit 235a, turning on or off by a control switch SW _1, and the design of a charge and discharge capacitance C _T discharges a discharge current source unit 235b, on or off by a control switch SW _2. The charging and discharging capacitor C _{T is} connected between the node 107 and the ground GND, and the charging process and the discharging process performed on the capacitor C _T are alternately performed, and the driving signals transmitted by the detecting unit 215 are used to control the switches SW ₁ and SW ₂ . A charging unit charging current source 235a provides the current value I _1, the charging time is T _charge and discharge current and a discharge current source unit 235b is provided by I _2, the discharge time of _{the discharge} T, charging and discharging the capacitance charging and discharging load capacitance C _T formula I ₁ × T = I ₂ × T _{charge discharge.}

As the charge and discharge circuit 235 starts to oscillate, the switches SW ₁ and SW ₂ will alternately switch, one of which is turned on and the other must be turned off, causing the capacitor C _{T to} perform charging and then discharging, then the charge and discharge capacitor C _T The desired sawtooth voltage signal V _B is generated at node 107 at one end of the ground, and the charge and discharge circuit 235 is also a sawtooth signal generating circuit. The fully discharged capacitor C _T may have its voltage at one end node 107 reduced to zero, thus connecting node 107 to the inverting input of a main comparator 128 and the positive input of main comparator 128. Then, a critical potential close to zero is obtained. For example, when the positive phase input terminal is directly grounded to obtain a zero potential, when the potential of the node 107 decreases to zero, the output of the main comparator 128 is induced to send a detection signal having a logic high level.

4B is an example of charging and discharging according to the charging and discharging circuit 235 of FIG. 4A. The input voltage V _HV1 induces the detecting unit 215 to generate a logic level waveform of the detecting voltage signal V _S1 , and the input voltage V _HV2 induces the detecting unit 215 . A logic level waveform of the detection voltage signal V _S2 is generated, and the peak value of the input voltage V _HV1 is larger than the peak value of the input voltage V _HV2 . In the same period T, the duty ratio of the detection voltage signal V _S1 is obviously greater than the duty ratio of the detection voltage signal V _S2 . When the charging and discharging circuit 235 completes the startup and is in a stable operation phase, an input voltage V _{HV1 is taken} as an example to illustrate a charging and discharging cycle, in two adjacent periods T _n , T _n+1 before and after the input voltage V _HV1 . The detecting voltage signal V _S1 starts to charge the capacitor C _T during the previous period T _n from the high level state to the falling edge of the low level state, and continues uninterrupted charging until the detection voltage signal V _S1 is turned off. The rising edge of the period from the low level state to the high level state in a period T _n+1 phase, at the rising edge time, the capacitor C _T stops charging and synchronously starts to discharge, and the discharge ends after the detection voltage signal V _S1 A period T _n+1 phase is flipped from a high level state to a low level state moment, thereby completing a complete charge and discharge cycle.

For a complete charge and discharge cycle, the detection voltage signal V _{S is} used as the charging start point from the high level to the low level falling edge in the previous cycle, and the detection voltage signal V _{S is} low since the latter cycle. The timing at which the rising edge of the high level rises is as the charge cutoff point and the discharge start point, and the time at which the detected voltage signal V _S falls from the high level to the low level in the latter period is taken as the discharge cutoff point. Taking the input voltage V _HV1 as an example, it has a reference effective value V′ _HVR , that is, has a corresponding reference peak value, and the period in which the capacitor C _T is maintained for each charge is equal to 2t ₁ , and the detection voltage signal V _S1 has logic at this stage. a second state of low level; and a period in which the capacitor C _T is maintained for each discharge is equal to 2 (t ₂ -t ₁ ), and the detection voltage signal V _S1 has a first state of logic high level at this stage, and the preset is satisfied. Under the conditions of charging time and discharging time, the amount of electricity charged in the period 2t ₁ is exactly equal to the amount of electricity discharged in the period 2 (t ₂ -t ₁ ), that is, the detecting voltage signal V _{S1 is} lowered from the high level to the low level in the latter period. At the moment of the falling edge, the capacitor C _T is just discharged. When the input voltage is V _HV1 , the charging and discharging voltage variation trend of the capacitor C _{T is} represented by the sawtooth wave voltage signal V _B1 in FIG. 4B , and the duty ratio of the detecting voltage signal V _S1 is D _B1 . We use the time period 2t ₁ as the reference charging time of the charging reference time, and the time period 2 (t ₂ -t ₁ ) as the reference discharging time of the discharging reference time, and the duty ratio is D _B1 as the reference duty ratio.

Combined with D _B calculated by equation (6), the charge and discharge current of capacitor C _T accords with the functional relationship: I ₁ × t ₁ = I ₂ ×( t ₂ - t ₁ ) (9)

The charge and discharge are performed on the capacitor C _T in accordance with the charge current value I ₁ supplied from the charge current source unit 235a and the discharge current value I ₂ supplied from the discharge current source unit 235b. As an example, such as when D _B = 0.77, I I ₂ ratio of more than ₁ and equal to 0.77 and 0.23. According to the above, if the preset input voltage has the reference effective value V' _HVR , the capacitance in the charging period 2t ₁ is satisfied under the premise that the duty ratio D _B obtained by the formula (7) and the formula (10) is simultaneously satisfied. The charge of C _T is just discharged at the end of time period 2 (t ₂ -t ₁ ). We consider the duty ratio D _B taken at this time as the reference duty ratio D _B1 , which will be analyzed later. The case where the duty cycle is greater than the reference duty cycle, and the case where the actual duty cycle may be less than the reference duty cycle.

In one embodiment of FIG. 4C, the input voltage V _HV3 has a higher peak than the input voltage V _HV1 , wherein the charging period 2t" _{1 is} less than 2t ₁ but the discharging period 2 (t" ₂ -t" ₁ ) is greater than 2 (t _{2 -} t ₁ ), the actual duty ratio D _{B3 of the} corresponding detected voltage signal V _S3 will be greater than the reference D _B1 , and a waveform V as shown in FIG. 4C will be generated at the node 107 of the ungrounded end of the capacitor. _B3. in a complete charge and discharge cycles, the capacitance C _T having a low level period 2t "within _a smaller overall charge ratio of the charged detection voltage signal V _S3, the capacitor C _T is not sufficient in the detection voltage The entire period of time 2 (t" _{2 -} t" ₁ ) of the signal V _S3 having a high level is continuously discharged. It can be understood that in the discharge phase, that is, the detection voltage signal V _{S3 is} counted from a low level to a high level discharge starting point in one cycle, and the time point has not yet reached the detection voltage signal V _S3 from the high level in the period. At the moment of flipping to the falling edge of the low level, the amount of electricity stored by the capacitor C _T is released, which is equivalent to the actual discharge time being less than the preset discharge time period 2 (t" ₂ -t" ₁ ), and the voltage signal V _B3 A phenomenon equal to zero occurs during the time period 2 (t" _{2 -} t" ₁ ) in which the detection voltage signal V _S3 has the first state, instead of the charge at the end of the time period 2 (t" _{2 -} t" ₁ ) The amount is zero, and the charging/discharging voltage variation trend of the capacitor C _{T is} represented by the sawtooth voltage signal V _B3 in FIG. 4C.

In one embodiment of FIG. 4B, the input voltage V _HV2 has a smaller peak than the input voltage V _HV1 , wherein the charging period 2t' _{1 is} greater than 2t ₁ but the discharging period 2 (t' ₂ -t' ₁ ) is less than 2 (t ₂ -t ₁ ), and the peak value of the input voltage exceeds the breakdown voltage V _Z1 , the sawtooth wave voltage signal V _B2 is generated at the node 107, and the actual duty ratio D _{B2 of the} corresponding detected voltage signal V _S2 will be It is smaller than the reference D _B1 , which is the opposite of FIG. 4C. During a complete charge and discharge cycle, the capacitor C _T charges a very large amount of time during the time period 2t' ₁ in which the detection voltage signal V _S2 has a low level, and the detection voltage signal V _S2 has a high level for the entire period of time. 2 (t' ₂ -t' ₁ ) is not enough to completely discharge the power of the capacitor C _T . It can be understood that in the discharge phase, that is, the detection voltage signal V _{S2 is} counted from a low level to a high level discharge starting point in one cycle, and the time point is just before the detection voltage signal V _S2 is high in the period. At the time of the quasi-flip to the falling edge of the low level, if no additional discharge measures are taken, the capacitance C _T still has a charge amount remaining. At this time, the charging and discharging voltage variation trend of the capacitor C _{T is} represented by the sawtooth wave voltage signal V _B2 in FIG. 4B , and the capacitor will continue to be continued after the detection voltage signal V _{S2 is} turned from the high level to the low level falling edge. When C _{T is} charged, once the capacitance C _T remains excessively at the time of the falling edge, the amount of capacitance of the capacitor C _T continues to accumulate and the expected charging and discharging step cannot be completed. For a complete charge and discharge cycle, the timing of setting the detection voltage signal V _S2 from the high level to the low level falling edge in each period has been notified, regardless of whether the capacitor C _T still stores the amount of charge, the moment As the discharge cut-off point, at this cut-off point, it is necessary to actively trigger the residual charge amount of the discharge capacitor C _T , so that the charge amount of the capacitor C _T drops sharply. The scheme of actively releasing the capacitor C _T will be described below. As shown in FIG. 4B, the amount of charge of the conduction capacitor C _T is released to a value close to zero at a falling edge of the detection voltage signal V _S2 , substantially slightly greater than zero, for example, less than 0.1 volt, at the time of the falling edge, the voltage signal V _B2 The waveform drops vertically with almost no discharge slope.

In summary, when the detection voltage signal V _S has a duty ratio just equal to the reference D _B1 , after the discharge is started, the voltage signal V _B1 just happens to be equal to zero at the timing of detecting the falling edge of the voltage signal V _S . Once the detected voltage signal V _S has a duty ratio exceeding the reference D _B1 , after the discharge is started, the voltage signal V _B3 will be equal to zero at some point before the time of detecting each falling edge of the voltage signal V _S . . Once the detected voltage signal V _S has a duty ratio smaller than the reference D _B1 , after the start of the discharge, the voltage signal V _B2 is placed near zero and slightly larger than zero at each falling edge of the detected voltage signal V _S . status. In FIG. 4A, node 107 is coupled to the inverting input of main comparator 128, and the non-inverting input of main comparator 128 is coupled to ground, so that when the duty cycle is D _B1 , the output of main comparator 128 is at the input voltage. The logic high level can be outputted exactly once in each cycle of the V _HV , occurring at the time of detecting the falling edge of the voltage signal V _S . When the duty ratio is greater than D _B1 , the output of the main comparator 128 can output a logic high level in each cycle of the input voltage V _HV , occurring after the time of detecting the rising edge of the voltage signal V _S Before the moment of the falling edge. When the duty ratio is less than D _B1 , the output of the main comparator 128 cannot output a high level every period of the input voltage V _HV .

Referring back to FIG. 5, after the AC mains power V _AC by the high frequency filter capacitor C _X filter, supplied to a conventional bridge rectifier 115, an AC voltage V _AC by bridge rectifier 115 full-wave rectifier, the output of a The expected DC voltage is generated across the capacitor C _bulk . The AC voltage V _{AC is} also supplied to a rectifier circuit 225 of the voltage detection circuit 255. The anode of the diode D2 in the rectifier circuit 225 is connected to an input terminal for supplying an AC voltage V _AC , and the other diode D3 of the rectifier circuit 225 is The anode is connected to another input that provides an alternating voltage V _AC . The voltage detecting circuit 255 has a detecting unit 215, and the cathodes of the rectifying diodes D2 and D3 are connected together and commonly connected to the cathode of the Zener diode ZD1 in the detecting unit 215. The anode of the Zener diode ZD1 is connected to the drain of the JFET 101, and the source of the JFET 101 is connected to the anode of a diode D1, and the cathode of the diode D1 is connected to the ground GND with a resistor R2. The control terminal of the JFET 101, such as a gate, is connected to the ground GND, and a resistor R1 is connected between the gate and the source of the JFET 101. The detecting unit 215 further has a comparator 121 for transmitting the driving signal control switch SW ₁ , SW ₂ , SW _{3 to be} turned off or on, and inputting a threshold voltage V _TH greater than zero to the inverting input terminal of the comparator 121 The source of JFET 101 is coupled to the non-inverting input of comparator 121.

Referring to FIG. 5, the operation mechanism of the detecting unit 215 is shown. The input voltage V _HV is obtained by rectifying the alternating current V _AC through the rectifying circuit 225, and the input voltage V _{HV of the} direct current voltage is at the node 100 of the cathode end of the Zener diode ZD1. It is input to the detecting unit 215. As described above, when the input voltage V _{HV is} larger than the breakdown voltage V _{Z of} the Zener diode ZD1, Zener diode ZD1 undergoes Zener breakdown, and the detection unit 215 generates a voltage V _S that is preset. The threshold voltage V _{TH is} large, and the output end of the comparator 121 outputs a high level, which embodies a first state in which the detection voltage signal V _S has a high level. On the contrary, when the input voltage V _{HV is} smaller than the breakdown voltage V _Z of the Zener diode ZD1, the Zener diode ZD1 is not broken, and the voltage V _S output by the detecting unit 215 is greater than a preset threshold voltage. When the V _{TH is} small, the output of the comparator 121 will output a low level, which embodies a second state in which the detection voltage signal V _S is at a low level.

The charge and discharge circuit 235 of FIG. 4A is shown in detail in FIG. 5. The output of the comparator 121 is connected to the input of an inverter 124 in the voltage detection circuit 255, and the output of the inverter 124 is connected to a control terminal of the switch SW unit 235a in the charging current source _{1, a} switch SW is turned on or off for controlling the voltage-current converter 125 whether the program to start charging. The switch SW ₁ and the SW ₂ and SW ₃ appearing below are all three-port electronic switches. In addition to a set of opposite input terminals, the switches have a control terminal for controlling the connection or disconnection of the two input terminals. The selection method is, for example, a P-type or N-type MOS transistor or a bipolar transistor or a junction transistor or a combination thereof. A control terminal of the output of comparator 121 is also connected to a discharge current sync source unit 235b is a switch SW _2, the switch SW ₂ is turned on or off for controlling the voltage to current converter 126 if the program start discharge. The switch SW ₂ and the three-terminal switch SW ₁ have a similar structure. In the process of outputting the driving signal by the comparator 121, the control terminal of the switch SW ₁ is driven by the driving signal for the low level because of the action of the inverter 124. It is turned on and turned off by the driving of the high level driving signal, and at the same time, the control terminal of the switch SW ₂ is driven by the driving signal of the high level and driven by the driving signal of the low level. Turn it off, and note that both switches SW ₁ and SW ₂ cannot be turned on or off at the same time, but alternately open to each other.

In the charging current source unit 235a, a DC power supply voltage V _DD is applied to the converter 105 for supplying the operating voltage to the voltage-to-current converter 125, and the power supply voltage V _DD is also applied at the other node 106. out switch SW ₁ is connected in series between the 106 and the resistor R3 and the ground terminal GND. For the charging process, the resistor R3 prevents the power supply voltage V _{DD from being} directly shorted to the ground terminal when the switch SW _{1 is} turned on, and the power supply voltage V _{DD is} supplied to the voltage-to-current input terminal of the voltage-current converter 125. The current release terminal/output terminal of the voltage-to-current converter 125 is disposed to be connected to the node 107 of the ungrounded end of the charge and discharge capacitor C _T , and the voltage current converter 125 converts the received power source voltage V _DD to a size of I ₁ The charging current is charged to the capacitor C _T . Because the output of comparator 121 is only a low level at the output of the premise will be turned out switch SW _1, a charging current I ₁ is generated to charge the timing capacitor C _T only occurs when the input voltage V _HV ratio of the Zener diode When the breakdown voltage V _{Z of the} body ZD1 is low, that is, the second state phase in which the detection voltage signal V _S has a logic low occurs.

In the discharge current source unit 235b, a switch SW ₂ and a resistor R4 are connected in series between the node 106 and the ground GND, and a power supply voltage V _DD is applied to the node 106. When the switch SW _{2 is} turned on, the resistor R4 can avoid the power supply voltage V _DD directly. Shorted to ground, and the supply voltage V _{DD is} supplied to the voltage to current input of voltage to current converter 126. The current sinking/input terminal of the voltage-current converter 126 is disposed to be connected to the ungrounded end of the charging and discharging capacitor C _T , that is, the node 107. When the switch SW _{2 is} turned on, the voltage-current converter 126 converts the received power source voltage value into a discharge. current I _2, the guide when attempting to charge and discharge the capacitor C _T is discharged to the ground terminal, a size of the discharge current I ₂ of the capacitance C _T discharges embodiment. Since the output of the comparator 121 is only turned on under the premise of outputting a high level, the switch SW ₂ is turned on, and the discharge current I ₂ is generated to cause the discharge of the capacitor C _{T to} occur only at the input voltage V _HV than the Zener diode When the breakdown voltage V _{Z of the} body ZD1 is high, that is, the first state phase in which the detection voltage signal V _S has a logic high occurs.

A discharge current source unit 235b having a three-port switch SW is connected in parallel with the capacitor C _{T 3, 3} both the capacitance C _T and the switch SW are connected between the node 107 and the ground terminal, a diode D5 aid and capacitance C _T In parallel, the anode terminal is grounded and the cathode terminal is connected to node 107. Similarly, the anode of an auxiliary diode D6 is connected to node 107 and the cathode terminal is connected to node 105. For the discharge process, it has been clarified in the foregoing that the detection voltage signal V _S is set as the discharge cut-off point at the falling edge from the high level to the low level, and whether or not the capacitor C _T stores the amount of charge, it will be Trigger a charge release program that lasts for a nanosecond level. 5, in order to achieve this, we need to deliver a signal output terminal of the comparator 121 to the control terminal of the switch SW _3, although in some embodiments the input of the monoflop 123 may be an alternative embodiment Directly connected to the output of the comparator 121, but in the preferred embodiment, an inverter 122 can be further provided in the voltage detecting circuit 255. If the inverter 122 is enabled, as shown in FIG. The output of the inverter 121 is connected to the input of the inverter 122 in the voltage detecting circuit 255, and the output of the inverter 122 is directly connected to a one-shot flip-flop 123 (for example, a 100 ns one-shot flip-flop) an input terminal, an output terminal of monostable multivibrator 123 is connected to the control terminal of the switch SW _3. When the driving signal directly triggers the one-shot flip-flop 123, the detecting voltage signal V _S is flipped from the first state to each falling edge of the second state, that is, each falling edge of the driving signal output by the comparator 121 is triggered. the output signal of the monoflop 123 transmits at a high level to the switch SW ₃ is turned on. Considering that the one-shot flip-flop 123 can be set to either a falling edge trigger or a rising edge trigger, if the inverter 122 is enabled, the detected voltage signal V _S is still flipped from the first state to the second state. each time a falling edge, a rising edge of the inverted signal can be used to trigger the drive signal the output signal of the monoflop 123 transmits at a high level the switch SW ₃ is turned on. The output signal of the comparator 121 is inverted by the inverter 122 to an inverted signal of an edge triggered monoflop 123 sends a signal to the control terminal of the switch SW _3. In order to achieve the detection voltage signal V _S from each falling edge of the high level to the low level of inversion, the falling edge of the trigger turns on the switch SW ₃ are, driving the switch SW ₃ is turned ON nanosecond time, the capacitance C The amount of charge of _T is released to the ground. The monostable flip-flop 123 triggers the switch SW _{3 to be} turned on for a very short time, which can be regarded as an instantaneous discharge step. After each trigger signal is generated, the monostable flip-flop 123 enters a temporary steady state, and the transient steady state is maintained for a while and then returned. Steady state. The waveform of the voltage signal V _B at the node 107 at the falling edge of the detected voltage signal V _S is as shown by the voltage signal V _B2 in FIG. 4B , at which time the waveform of the voltage V _B2 drops vertically with almost no discharge slope.

Referring to Figure 5, the non-inverting input of main comparator 128 is coupled to ground, and the inverting input is coupled to node 107. The voltage signal V _B at node 107 has been set forth above. As shown in FIG. 4B, under the premise that the input voltage V _HV1 has the reference effective value V′ _HVR , the charging and discharging voltage variation trend of the capacitor C _{T is} represented by the sawtooth wave voltage signal V _B1 , and the time period 2t _{1 is} used as the charging reference time. The reference charging time, the time period 2 (t ₂ -t ₁ ) is used as the reference discharge time of the discharge reference time, and the duty ratio of the detection voltage signal V _S1 is the reference D _B1 , at which time the output of the main comparator 128 is The logic high level can be outputted once in each cycle of the input voltage V _HV1 at the time of detecting the falling edge of the voltage signal V _S1 . Still referring to FIG. 4B, once the detection voltage signal V _S2 has a duty ratio D _{B2 that} is less than D _B1 , the input voltage V _HV2 has a smaller peak value than the input voltage V _HV1 , and the voltage signal V _{B2 is} at the detection voltage signal V . Each falling edge of _S is placed near zero and slightly greater than zero, so the output of main comparator 128 is always low. Referring to FIG. 4C, when the input voltage V _HV3 has a higher peak than the input voltage V _HV1 , the actual duty ratio D _{B3 of the} corresponding detected voltage signal V _S3 will be greater than D _B1 and will be generated at node 107 at one end of the capacitor. The waveform V _{B3 is} calculated from the discharge phase of a charge and discharge cycle, that is, from the detection of the voltage signal V _S3 in a cycle from the low level to the high level of the discharge start point, the time point has not yet reached the detection voltage signal V _S3 At the moment when the period falls from the high level to the falling edge of the low level, the amount of power stored by the capacitor C _T is released, causing the voltage signal V _B3 to fall to a value equal to zero, and the output of the main comparator 128 is at the input. Each period of voltage V _HV3 can output a logic high level just when the charge of the capacitor C _T is zero.

Referring to FIG. 6, from the time period T _X to T _Y , the peak value of the actual input voltage V _HV is set to be gradually increased in the time dimension from the front to the back, and the change trend of the _AC mains V _AC can be judged according to the manner disclosed above. . During the time period T _X , the peak value of the actual input voltage V _HV exceeds the breakdown voltage V _Z , but the duty ratio of the detection voltage signal V _S is always lower than the reference duty ratio D _B1 , so the output of the main comparator 128 The output of the detection signal 300 is always at a low level. During the first period of the time period T _Y , the critical state input voltage V _{HV has} exactly the reference effective value V′ _HVR or an equivalent peak, and the output of the main comparator 128 outputs the logic high level 300a for the first time, which occurs in The time at which the falling edge of the voltage signal V _S is detected during this period. After the first period of the time period T _Y , the actual input voltage V _{HV of} each of the other periods has a higher peak value than the critical state, and the main comparator 128 outputs the capacitance of the capacitor C _T is zero in each period. One logic high level, such as high level signals 300b, 300c, etc. Assuming that the reference effective value V' _HVR is equal to 100V, the breakdown voltage value of the Zener diode ZD1 is V _Z1 = 50V, and D _B = 0.77 is derived. If the duty ratio exceeds 0.77, the input input voltage V _{HV is considered to be} the peak value. Or the amplitude starts to exceed 100 The high level result of the detection signal 300 outputted from the main comparator 128 can be visually displayed. Vice versa, where the duty cycle is less than 0.77, the peak or amplitude of the input input voltage V _HV begins to fall below 100. , Visual display may result from the low level detection signal output from the main comparator 128 out of 300, thereby to determine the trend of the input voltage V _HV, i.e. determines the input voltage V _HV equivalent trend Analyzing the alternating voltage V _AC The former is rectified by the latter.

In addition, as an option, although not shown in the figure, the output terminal of the comparator 121 may be connected to the input terminal of a counter Counter, and when the counter detects that the comparison result output by the comparator 121 is a low level and the low level When the state is maintained for more than a predetermined period of time T _BO , once the counter 121 does not receive the comparison result output by the comparator 121 to a high level within the preset de-bounce time T _BO , It is judged that the input voltage V _HV or the AC voltage V _AC is substantially in an undervoltage state, for example, when the preset time T _BO continues for more than one period T or several times of the period n×T, which is equivalent to the peak value of the actual input voltage V _HV The Zener breakdown voltage V _Z of the Zener diode ZD1 has not been exceeded, and the counter 121 can be triggered to output a protection signal to cut off the AC to DC power conversion device.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications in Any and all equivalent ranges and contents within the scope of the claims are intended to be within the scope and spirit of the invention.

107‧‧‧ nodes

128‧‧‧Main comparator

235‧‧‧Charge and discharge circuit

235a‧‧‧Charging current source unit

235b‧‧‧Discharge current source unit

C _T ‧‧‧Charge and discharge capacitor

Switch SW ₁ SW ₂ ‧‧‧

V _DD ‧‧‧DC power supply voltage

Claims (21)

A voltage detecting circuit includes: a rectifying circuit that rectifies an alternating current voltage into a direct current input voltage; and a detecting unit that receives the input voltage and generates a detecting voltage having different logic states according to fluctuations in the magnitude of the input voltage. a capacitor; a charging current source unit that charges the capacitor when the detected voltage signal has a second state; a discharge current source unit that causes the detecting voltage signal to have a first state Capacitor discharge; a main comparator that compares the voltage across the capacitor with a critical zero potential during the alternation of the charge and discharge of the capacitor and outputs a detection signal with a trend indicating the change in the input voltage. The voltage detecting circuit of claim 1, wherein the detecting unit triggers the detecting unit to generate a detecting voltage signal having a first state when the input voltage exceeds a preset value; and when the input voltage is lower than a preset value The detecting unit is triggered to generate a detection voltage signal having a second state. The voltage detecting circuit according to claim 2, wherein in the detecting unit, an anode of a Zener diode is connected to a drain of a junction field effect transistor and an input voltage is applied to the cathode thereof The preset value is equal to the breakdown voltage of the Zener diode, thereby generating a detection voltage signal at the source of the junction field effect transistor. The voltage detecting circuit according to claim 3, wherein the source of the junction field effect transistor is connected to the non-inverting input terminal of a comparator in the detecting unit, and the inverting input terminal of the comparator inputs a valve. Value voltage; when the input voltage is higher than the preset value, the detection voltage signal potential is greater than the threshold voltage, indicating that the detection voltage signal has a logic high first state, and the detection unit output of the detection unit is a high level When the input voltage is lower than the preset value, the detected voltage signal potential is less than the threshold voltage, and the detected voltage signal has a second state with a logic low, and the driving signal output by the comparator of the detecting unit is a low level. The voltage detecting circuit according to claim 1, wherein the charging current source unit comprises a voltage current converter and a switch connected between a voltage source and the input of the voltage current converter; when detecting the voltage signal When the second state is present, the detecting unit sends a driving signal to turn on the switch, and provides a charging current source unit with a voltage source for converting into a charging current, and the charging current is supplied to the capacitor to cause the capacitor to be charged. The voltage detecting circuit according to claim 1, wherein the discharge current source unit comprises a voltage current converter and a switch connected between a voltage source and the input of the voltage current converter; when detecting the voltage signal When the first state is present, the detecting unit sends a driving signal to turn on the switch, and the discharging current source unit is provided with a voltage source for converting into a discharging current, and the capacitor discharges the amount of the electric charge by the discharging current. The voltage detecting circuit according to claim 3, wherein the detecting voltage signal is turned from the first state to the falling edge of the second state, charging is started, and the detecting voltage signal is inverted from the second state to At the rising edge of the first state, the amount of charge of the capacitor is released; and each time the detected voltage signal is flipped from the first state to the falling state of the second state, an instantaneous discharge is performed on the capacitor before the capacitor starts charging. step. According to the voltage detecting circuit of claim 7, wherein a switch connected in parallel with the capacitor and grounded at one end is provided, and the driving signal sent by the detecting unit is inverted by an inverter and sent to a one-shot trigger. The input of the monostable flip-flop is connected to the control terminal of the switch; the falling edge of the detected voltage signal is inverted by the inverted edge of the inverter to trigger the monostable trigger transfer The output signal that drives the switch is turned on once, and the switch is used to perform instantaneous discharge on the capacitor. According to the voltage detecting circuit of claim 8, wherein a reference input voltage having a reference effective value V _HVR is supplied to the detecting unit, and the breakdown voltage of the Zener diode is set to V _Z1 at the reference. During a period of the input voltage, the first state of the detected voltage signal has a reference duty cycle D _B of: At the same time, it is set between the current value I _{1 of} the capacitor charging and the current value I _{2 for} discharging the capacitor: The voltage detecting circuit according to claim 9, wherein when the actual duty ratio is greater than the reference duty ratio D _B , the detection signal outputted by the main comparator generates a high level in each period of the actual input voltage. Precisely, indicating that the peak value of the actual input voltage is greater than the peak value of the reference input voltage; or when the actual duty ratio is less than the reference duty ratio D _B , the detection signal output by the main comparator will not be in each period of the actual input voltage. A high level is generated, indicating that the peak value of the actual input voltage is less than the peak value of the reference input voltage. According to the voltage detecting circuit of claim 4, wherein the output of the comparator in the detecting unit is connected to the input end of a counter, and when the counter detects that the comparison result of the comparator output of the detecting unit is When the low level is maintained and the low level state is maintained for more than a predetermined period of time, it can be judged that the input voltage is in an undervoltage state. A method for detecting a voltage change, comprising the steps of: rectifying an alternating current voltage into a direct current input voltage by using a rectifying circuit; inputting the input voltage to a detecting unit, and according to fluctuations in the magnitude of the input voltage, thereby The detecting unit generates a detecting voltage signal having different logic states; performing a cyclic charging and discharging program on one capacitor; and during the charging process of the capacitor, when the detecting voltage signal sent by the detecting unit has the second state, utilizing a charging current source unit charges the capacitor; during the discharging of the capacitor, when the detecting voltage signal sent by the detecting unit has the first state, discharging the capacitor by using a discharging current source unit; The main comparator compares the capacitance of the capacitor during the alternating charging and discharging with the critical zero potential, and the main comparator outputs a comparison result with a tendency to identify the input voltage as a detection signal. The method of claim 12, wherein the detecting unit is triggered to generate a detection voltage signal having a first state when the input voltage exceeds a preset value; and when the input voltage is lower than a preset value The detecting unit is triggered to generate a detection voltage signal having a second state. The method of claim 13, wherein in the detecting unit, an anode of a Zener diode is connected to a drain of a junction field effect transistor and an input voltage is applied to the cathode thereof. The preset value is equal to the breakdown voltage of the Zener diode, thereby generating a detection voltage signal at the source of the junction field effect transistor. The method of claim 14, wherein the source of the junction field effect transistor is connected to a non-inverting input of a comparator of the detection unit, and a valve is input to the inverting input of the comparator. Value voltage; when the input voltage is higher than the preset value, the detection voltage signal potential is greater than the threshold voltage, indicating that the detection voltage signal has a logic high first state, and the detection unit output of the detection unit is a high level When the input voltage is lower than the preset value, the detected voltage signal potential is less than the threshold voltage, and the detected voltage signal has a second state with a logic low, and the driving signal output by the comparator of the detecting unit is a low level. The method of claim 12, wherein the charging current source unit comprises a voltage current converter and a switch connected between a voltage source and the input of the voltage current converter; In the two states, the detecting unit sends a driving signal to turn on the switch, provides a voltage source for converting the charging current to the charging current source unit, and supplies the charging current to the capacitor to cause the capacitor to be charged. The method of claim 12, wherein the discharge current source unit comprises a voltage current converter and a switch connected between a voltage source and the input of the voltage current converter; In one state, the detecting unit sends a driving signal to turn on the switch, and supplies a voltage source for converting the discharging current to the discharging current source unit, and the capacitor discharges the amount of the electric charge by the discharging current. The method of claim 14, wherein the detecting of the voltage signal is started by charging the capacitor at a falling edge of the detecting voltage signal from the first state to the second state, and detecting the voltage signal from The second state is flipped to the rising edge of the first state, and the amount of charge of the capacitor is released; and each time the detected voltage signal is flipped from the first state to the second state, each time before the capacitor starts charging The capacitor performs an instantaneous discharge step. According to the method of claim 18, wherein a switch connected in parallel with the capacitor and grounded at one end is provided, so that the driving signal sent by the detecting unit is inverted by an inverter and then sent to a one-shot trigger. The input end of the device, and the output end of the monostable flip-flop is connected to the control end of the switch; the rising edge of the detected voltage signal is inverted by the inverted edge of the inverter to trigger the monostable trigger transfer An output signal that drives the switch to be turned on once, and an instantaneous discharge of the capacitor is performed by turning on the switch. The method according to claim 19, wherein a reference input voltage having a reference effective value V _HVR is supplied to the detecting unit, and the breakdown voltage of the Zener diode is set to V _Z1 at the reference input voltage. In one cycle, the first state of the detected voltage signal has a reference duty cycle D _B of: At the same time, it is set between the current value I _{1 of} the capacitor charging and the current value I _{2 for} discharging the capacitor: The method according to claim 20, wherein, when the actual duty ratio is greater than the reference duty ratio D _B , the detection signal output by the main comparator generates a high level in each period of the actual input voltage. Indicates that the peak value of the actual input voltage is greater than the peak value of the reference input voltage; or when the actual duty ratio is less than the reference duty ratio D _B , the detection signal output by the main comparator does not generate a high level in each period of the actual input voltage , indicating that the peak value of the actual input voltage is smaller than the peak value of the reference input voltage.