TWI549298B - Semiconductor device having epitaxial structures - Google Patents

Semiconductor device having epitaxial structures Download PDF

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TWI549298B
TWI549298B TW100125944A TW100125944A TWI549298B TW I549298 B TWI549298 B TW I549298B TW 100125944 A TW100125944 A TW 100125944A TW 100125944 A TW100125944 A TW 100125944A TW I549298 B TWI549298 B TW I549298B
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concentration
layer
semiconductor material
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semiconductor
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TW201306260A (en
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廖晉毅
宣騰竣
賴一銘
簡金城
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聯華電子股份有限公司
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具有磊晶結構之半導體元件Semiconductor component having epitaxial structure

本發明係關於一種磊晶結構之半導體元件,尤指一種具有磊晶源極/汲極之金氧半導體電晶體(metal-oxide-semiconductor,MOS transistor)。The present invention relates to a semiconductor device having an epitaxial structure, and more particularly to a metal-oxide-semiconductor (MOS transistor) having an epitaxial source/drain.

磊晶(epitaxial)結構係廣泛地用於半導體製程中,舉例來說,習知技術常利用選擇性磊晶成長(selective epitaxial growth,SEG)技術於一單晶基板內形成一晶格排列與基板相同之磊晶層,例如矽鍺(silicon germanium,SiGe)磊晶層,作為增高式源極/汲極(raised source/drain),或者嵌入式源極/汲極(recessed source/drain)。利用矽鍺磊晶層之晶格常數(lattice constant)大於矽基板晶格之特點,矽鍺磊晶層係對MOS電晶體的通道區產生應力,故可增加通道區的載子遷移率(carrier mobility),並藉以增加MOS電晶體的速度。Epitaxial structures are widely used in semiconductor processes. For example, conventional techniques often use selective epitaxial growth (SEG) techniques to form a lattice arrangement and substrate in a single crystal substrate. The same epitaxial layer, such as a silicon germanium (SiGe) epitaxial layer, acts as a raised source/drain, or as a recessed source/drain. The lattice constant of the germanium epitaxial layer is greater than that of the germanium substrate lattice, and the germanium epitaxial layer stresses the channel region of the MOS transistor, thereby increasing the carrier mobility of the channel region (carrier) Mobility) and thereby increase the speed of the MOS transistor.

利用矽鍺磊晶層作為源極/汲極固然可有效提升元件效能,但矽鍺磊晶層的製作係大大地增加了半導體製程的複雜度以及製程控制的難度。舉例來說,雖然矽鍺磊晶層中的鍺含量越高,其可對通道區產生越大的應力。然而,考慮到鍺含量對於矽鍺磊晶層臨界厚度的影響,以及超出臨界厚度後矽鍺磊晶層產生的應力鬆弛(relax)效應對元件的負面影響,矽鍺磊晶層中的鍺含量不能無限制的增加。除了鍺含量的高低控制問題,矽鍺磊晶層尚面對後續金屬矽化物(silicide)製程中,金屬易與磊晶層中的鍺形成結塊(agglomeration),而造成接面漏電(junction leakage)的問題。此外,習知技術更觀察到因矽鍺磊晶層與矽基底的接面(interface)晶格常數差異過大,而導致元件啟始電壓(threshold voltage)突然發生下降(roll-off)的問題。The use of a germanium epitaxial layer as a source/drain can effectively improve component performance, but the fabrication of the germanium epitaxial layer greatly increases the complexity of the semiconductor process and the difficulty of process control. For example, although the germanium content in the germanium epitaxial layer is higher, it can generate greater stress on the channel region. However, considering the effect of niobium content on the critical thickness of the epitaxial layer and the negative effect of the stress relaxation effect of the epitaxial layer on the element beyond the critical thickness, the niobium content in the epitaxial layer Can not increase without limit. In addition to the high and low control of the bismuth content, the bismuth layer is still facing the subsequent metal silicide process, and the metal easily forms agglomeration with the bismuth in the epitaxial layer, causing junction leakage. )The problem. In addition, the prior art has observed that the interface lattice constant of the epitaxial layer and the germanium substrate is too large, causing a sudden roll-off of the component threshold voltage.

由此可知,矽鍺磊晶層的存在雖可有效改善元件效能,但仍存有許多亟待改善之處。It can be seen that although the presence of the germanium epitaxial layer can effectively improve the component performance, there are still many areas for improvement.

因此,本發明之一目的係在於提供一種可改善上述問題之具有磊晶結構之半導體元件。Accordingly, it is an object of the present invention to provide a semiconductor device having an epitaxial structure which can improve the above problems.

根據本發明所提供之申請專利範圍,係提供一種具有磊晶結構之半導體元件,該半導體元件包含有一設置於一基底上之閘極結構、設置於該閘極結構兩側之該基底內的磊晶結構、以及一設置於該磊晶結構上之未摻雜(undoped)覆蓋層。該磊晶結構包含一種摻雜質、一第一半導體材料與一第二半導體材料,該第一半導體材料具有一第一晶格常數,該第二半導體材料具有一第二晶格常數,且該第二晶格常數大於該第一晶格常數,該未摻雜覆蓋層亦包含該第一半導體材料與該第二半導體材料。該磊晶結構中該第二半導體材料具有一第一濃度,該未摻雜覆蓋層中該第二半導體材料至少具有一第二濃度,且該第二濃度小於該第一濃度。According to the patent application scope of the present invention, there is provided a semiconductor device having an epitaxial structure, the semiconductor device comprising a gate structure disposed on a substrate, and a protrusion disposed in the substrate on both sides of the gate structure a crystal structure, and an undoped cover layer disposed on the epitaxial structure. The epitaxial structure includes a doping material, a first semiconductor material and a second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor material having a second lattice constant, and the The second lattice constant is greater than the first lattice constant, and the undoped cladding layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material has a first concentration in the epitaxial structure, the second semiconductor material in the undoped cap layer has at least a second concentration, and the second concentration is less than the first concentration.

根據本發明所提供之申請專利範圍,另提供一種具有磊晶結構之半導體元件,該半導體元件包含有一設置於一基底上之閘極結構、一對設置於該閘極結構兩側之該基底內之凹槽、一分別設置於該閘極結構兩側之該凹槽內之磊晶結構、以及一形成於該凹槽內之未摻雜底層,且該未摻雜底層係設置於該磊晶結構與該基底之間。該磊晶結構包含一種摻雜質、一第一半導體材料與一第二半導體材料,該第一半導體材料具有一第一晶格常數,該第二半導體材料具有一第二晶格常數,且該第二晶格常數大於該第一晶格常數。而該未摻雜底層係覆蓋該凹槽之側壁與該凹槽之底部,且包含該第一半導體材料與該第二半導體材料。該磊晶結構中該第二半導體材料具有一第一濃度,該未摻雜底層中該第二半導體材料至少具有一第二濃度,且該第二濃度小於該第一濃度。According to the patent application scope of the present invention, there is further provided a semiconductor device having an epitaxial structure, the semiconductor device comprising a gate structure disposed on a substrate, and a pair of the substrate disposed on both sides of the gate structure a recess, an epitaxial structure respectively disposed in the recess on both sides of the gate structure, and an undoped underlayer formed in the recess, and the undoped underlayer is disposed on the epitaxial layer Between the structure and the substrate. The epitaxial structure includes a doping material, a first semiconductor material and a second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor material having a second lattice constant, and the The second lattice constant is greater than the first lattice constant. The undoped underlayer covers the sidewall of the recess and the bottom of the recess and includes the first semiconductor material and the second semiconductor material. The second semiconductor material has a first concentration in the epitaxial structure, the second semiconductor material in the undoped underlayer has at least a second concentration, and the second concentration is less than the first concentration.

根據本發明所提供之具有磊晶結構之半導體元件,該磊晶結構可作為該半導體元件之源極/汲極。該磊晶結構表面係形成有一具有較低鍺濃度的未摻雜覆蓋層,因此可避免金屬矽化物製程中,金屬易與磊晶層中的鍺形成結塊、進而造成接面漏電的問題。此外,本發明所提供之磊晶結構半導體元件,係於凹槽內的磊晶結構與基底之間設置一鍺濃度較低的未摻雜底層,以避免矽鍺磊晶層與矽基底的接面晶格排列差異過大、進而導致元件啟始電壓突然發生下降的問題。According to the semiconductor element having an epitaxial structure provided by the present invention, the epitaxial structure can serve as a source/drain of the semiconductor element. The surface of the epitaxial structure is formed with an undoped cap layer having a lower germanium concentration, thereby avoiding the problem that the metal is easily agglomerated with germanium in the epitaxial layer during the metal telluride process, thereby causing leakage of the junction. In addition, the epitaxial semiconductor device provided by the present invention is provided with a lower concentration of undoped underlayer between the epitaxial structure in the recess and the substrate to avoid the connection between the epitaxial layer and the germanium substrate. The difference in the lattice arrangement of the face is too large, which in turn causes a sudden drop in the starting voltage of the component.

請參閱第1圖,第1圖係為本發明所提供之具有磊晶結構之半導體元件之一第一較佳實施例之示意圖。如第1圖所示,本較佳實施例所提供之具有磊晶結構之半導體元件100包含一基底102,而在基底102上,係設置有一閘極結構110。閘極結構110包含一閘極絕緣層112,其可包含高介電常數(high dielectric constant,high-k)材料或氧化矽。閘極結構110亦包含一由圖案化硬遮罩116定義之閘極電極114,其可包含金屬材料或多晶矽。半導體元件100尚包含設置於閘極結構110兩側之基底102內的輕摻雜汲極(lightly-doped drain,LDD) 118、一設置於閘極結構110側壁的側壁子120、以及一對設置於閘極結構110兩側之基底102內,尤其設置於側壁子120兩側之基底102內的凹槽122。Please refer to FIG. 1. FIG. 1 is a schematic view showing a first preferred embodiment of a semiconductor device having an epitaxial structure according to the present invention. As shown in FIG. 1, the semiconductor device 100 having an epitaxial structure according to the preferred embodiment includes a substrate 102, and a gate structure 110 is disposed on the substrate 102. The gate structure 110 includes a gate insulating layer 112, which may comprise a high dielectric constant (high-k) material or tantalum oxide. The gate structure 110 also includes a gate electrode 114 defined by a patterned hard mask 116, which may comprise a metallic material or a polysilicon. The semiconductor device 100 further includes a lightly doped drain (LDD) 118 disposed in the substrate 102 on both sides of the gate structure 110, a sidewall spacer 120 disposed on the sidewall of the gate structure 110, and a pair of settings. In the substrate 102 on both sides of the gate structure 110, in particular, grooves 122 are provided in the substrate 102 on both sides of the sidewall spacer 120.

請繼續參閱第1圖。待基底102完成一清洗步驟去除原生氧化物或其他不純物之後,係進行一選擇性磊晶成長(SEG)方法,於凹槽122內分別形成一磊晶結構130。換句話說,本較佳實施例所提供之半導體元件100更包含一磊晶結構130,設置於閘極結構110兩側之基底102內,尤其是閘極結構110兩側基底102的凹槽122內。磊晶結構130包含一第一半導體材料與一第二半導體材料,該第一半導體材料具有一第一晶格常數,該第二半導體材料具有一第二晶格常數,且該第二晶格常數大於該第一晶格常數。在本較佳實施例中,第一半導體材料可包含矽,而第二半導體材料可包含鍺。也就是說,磊晶結構130係包含矽鍺,但不限於此。此外,本較佳實施例中第二半導體材料濃度,即磊晶矽鍺材料中的鍺濃度係可為36%,但不限於此。利用矽鍺的晶格常數大於基底102之晶格常數之特性,磊晶矽鍺層係產生結構上應變而作為一應變矽結構,並帶動通道區部分之單晶矽之晶格與能帶結構(band structure)發生改變,進而可增加通道區的載子遷移率,提升半導體元件100之效能。此外,如第1圖所示,磊晶結構130之表面與基底102之表面不共平面,且磊晶結構130之表面係高於基底102之表面。Please continue to see Figure 1. After the substrate 102 completes a cleaning step to remove the native oxide or other impurities, a selective epitaxial growth (SEG) method is performed to form an epitaxial structure 130 in the recess 122, respectively. In other words, the semiconductor device 100 of the preferred embodiment further includes an epitaxial structure 130 disposed in the substrate 102 on both sides of the gate structure 110, especially the recess 122 of the substrate 102 on both sides of the gate structure 110. Inside. The epitaxial structure 130 includes a first semiconductor material and a second semiconductor material, the first semiconductor material has a first lattice constant, the second semiconductor material has a second lattice constant, and the second lattice constant Greater than the first lattice constant. In the preferred embodiment, the first semiconductor material may comprise germanium and the second semiconductor material may comprise germanium. That is, the epitaxial structure 130 includes germanium, but is not limited thereto. In addition, the concentration of the second semiconductor material in the preferred embodiment, that is, the concentration of germanium in the epitaxial germanium material may be 36%, but is not limited thereto. By using the lattice constant of germanium to be larger than the lattice constant of the substrate 102, the epitaxial layer is structurally strained as a strained crucible structure, and drives the lattice and band structure of the single crystal germanium in the channel region. A change in the band structure can increase the carrier mobility of the channel region and improve the performance of the semiconductor device 100. In addition, as shown in FIG. 1, the surface of the epitaxial structure 130 is not coplanar with the surface of the substrate 102, and the surface of the epitaxial structure 130 is higher than the surface of the substrate 102.

此外,可在形成磊晶結構130之前、形成磊晶結構130之後,甚至於形成磊晶結構130的同時進行一離子佈植製程,以將半導體元件100所需的p型或n型摻雜質佈植進入磊晶結構130,使磊晶結構130包含半導體元件100所需的p型或n型摻雜質,並使其可作為半導體元件100的一源極/汲極。由於上述離子佈植製程以及可選用的摻雜質係為熟習該項技藝之人士所知者,故於此係不予贅述。In addition, an ion implantation process may be performed before the epitaxial structure 130 is formed, after the epitaxial structure 130 is formed, or even when the epitaxial structure 130 is formed, to obtain the p-type or n-type dopant required for the semiconductor device 100. The implant enters the epitaxial structure 130 such that the epitaxial structure 130 includes the p-type or n-type dopant required for the semiconductor device 100 and serves as a source/drain of the semiconductor device 100. Since the ion implantation process described above and the optional doping system are known to those skilled in the art, they are not described herein.

如前所述,為了避免在金屬矽化物製程中發生金屬與磊晶結構130中的鍺形成結塊而造成接面漏電的問題,係可於磊晶結構130表面形成一覆蓋層,例如一純矽之覆蓋層(圖未示),作為金屬矽化物製程的反應場所。然而,由於純矽覆蓋層中的鍺濃度為0%,而磊晶結構130內的鍺濃度為36%,兩者差異過大,而使得純矽覆蓋層容易產生一波浪狀(wavy)表面。舉例來說,由原子力顯微鏡(atomic force microscope,以下簡稱為AFM)檢測純矽覆蓋層的表面,可得知純矽覆蓋層之均方根表面粗糙度(root mean square roughness)約為4.21奈米(nanometer,以下簡稱為nm)。此一粗糙表面係不利於後續製程,甚至影響到下方磊晶結構130的應力。As described above, in order to avoid the problem of junction leakage caused by the formation of agglomerates between the metal and the epitaxial structure 130 in the metal telluride process, a cover layer may be formed on the surface of the epitaxial structure 130, such as a pure The cover layer of the crucible (not shown) serves as a reaction site for the metal telluride process. However, since the germanium concentration in the pure germanium coating layer is 0%, and the germanium concentration in the epitaxial structure 130 is 36%, the difference between the two is too large, so that the pure germanium coating layer easily generates a wavy surface. For example, the surface of a pure tantalum coating layer is detected by an atomic force microscope (AFM), and the root mean square roughness of the pure tantalum coating layer is about 4.21 nm. (nanometer, hereinafter referred to as nm). This rough surface is not conducive to subsequent processes, and even affects the stress of the underlying epitaxial structure 130.

由此可知,不具純矽覆蓋層的磊晶結構130會發生結塊的問題;而具有鍺濃度與磊晶結構130差異過大的覆蓋層又造成粗糙表面而不利於後續製程。為了解決此一兩難的問題,本較佳實施例係於此提供一非純矽之未摻雜覆蓋層140,設置於磊晶結構130上。未摻雜覆蓋層140亦包含上述之第一半導體材料與第二半導體材料,即包含矽鍺。在本較佳實施例中,未摻雜覆蓋層140係為一如第1圖所示之單一膜層,且未摻雜覆蓋層140中第二半導體材料之濃度,即鍺濃度係小於磊晶結構130之鍺濃度,例如可等於25%。此外,本較佳實施例中的未摻雜覆蓋層140厚度係可為150埃(angstrom),但不限於此。It can be seen that the epitaxial structure 130 without the pure germanium cap layer may cause agglomeration; and the cap layer having the germanium concentration and the epitaxial structure 130 is too large to cause a rough surface, which is unfavorable for subsequent processes. In order to solve this dilemma, the preferred embodiment provides an undoped undoped cap layer 140 disposed on the epitaxial structure 130. The undoped cap layer 140 also includes the first semiconductor material and the second semiconductor material described above, ie, containing germanium. In the preferred embodiment, the undoped cap layer 140 is a single film layer as shown in FIG. 1 , and the concentration of the second semiconductor material in the undoped cap layer 140 is less than that of the epitaxial layer. The concentration of germanium in structure 130 can be, for example, equal to 25%. In addition, the thickness of the undoped cap layer 140 in the preferred embodiment may be 150 angstroms, but is not limited thereto.

此外,本較佳實施例所提供之半導體元件100更可包含一未摻雜底層150,設置於凹槽122內,且設置於基底102與磊晶結構130之間。未摻雜底層150係覆蓋凹槽122之底部與側壁,底層150可為單一膜層或複合膜層,且包含上述之第一半導體材料與第二半導體材料,即包含矽鍺。未摻雜底層150中第二半導體材料之濃度,即鍺濃度係小於磊晶結構130之鍺濃度,且介於10~25%,且鍺濃度係由下而上遞增。有關未摻雜底層150之特徵將於後續實施例中詳細說明,故於此係不予贅述。In addition, the semiconductor device 100 of the preferred embodiment further includes an undoped underlayer 150 disposed in the recess 122 and disposed between the substrate 102 and the epitaxial structure 130. The undoped underlayer 150 covers the bottom and sidewalls of the recess 122. The bottom layer 150 can be a single film layer or a composite film layer, and includes the first semiconductor material and the second semiconductor material described above, that is, containing germanium. The concentration of the second semiconductor material in the undoped bottom layer 150, that is, the germanium concentration is less than the germanium concentration of the epitaxial structure 130, and is between 10 and 25%, and the germanium concentration is increased from bottom to top. The features of the undoped underlayer 150 will be described in detail in the subsequent embodiments, and thus are not described herein.

根據本第一較佳實施例所提供之具有磊晶結構之半導體元件100,其磊晶結構130之表面係形成有一單一膜層之非純矽未摻雜覆蓋層140。未摻雜覆蓋層140係包含矽鍺,且鍺濃度較佳為25%。由於未摻雜覆蓋層140之鍺濃度為25%,而磊晶結構130之鍺濃度為36%,兩者差異較低,因此形成於磊晶結構130表面之未摻雜覆蓋層140可獲得一較為平坦的表面。經由AFM檢測未摻雜覆蓋層140的表面,可得知未摻雜覆蓋層140之均方根表面粗糙度約為0.75 nm,與純矽覆蓋層之均方根表面粗糙度(4.21 nm)相較,其表面粗糙度大為改善。此外,由於未摻雜覆蓋層140之鍺濃度較低,故亦可降低金屬矽化物製程中,金屬與鍺形成結塊之問題。According to the semiconductor device 100 having an epitaxial structure according to the first preferred embodiment, the surface of the epitaxial structure 130 is formed with a single film layer of a non-pure germanium undoped cap layer 140. The undoped cap layer 140 contains ruthenium and the ruthenium concentration is preferably 25%. Since the germanium concentration of the undoped cap layer 140 is 25%, and the germanium concentration of the epitaxial structure 130 is 36%, the difference between the two is low, so that the undoped cap layer 140 formed on the surface of the epitaxial structure 130 can obtain one. A relatively flat surface. The surface of the undoped cap layer 140 is detected by AFM, and the root mean square surface roughness of the undoped cap layer 140 is about 0.75 nm, which is comparable to the root mean square surface roughness (4.21 nm) of the pure germanium cap layer. In comparison, the surface roughness is greatly improved. In addition, since the germanium concentration of the undoped cap layer 140 is low, the problem of agglomeration of the metal and the germanium in the metal telluride process can also be reduced.

接下來請參閱第2圖,第2圖係為本發明所提供之具有磊晶結構之半導體元件之一第二較佳實施例之示意圖。值得注意的是,第二較佳實施例中,與第一較佳實施例相同之元件係以相同之符號說明。如第2圖所示,本較佳實施例所提供之具有磊晶結構之半導體元件100包含一基底102,而在基底102上,係設置有一閘極結構110。閘極結構110包含一閘極絕緣層112,其可包含high-k材料或氧化矽。閘極結構110亦包含一由圖案化硬遮罩116定義之閘極電極114,其可包含金屬材料或多晶矽。半導體元件100尚包含設置於閘極結構110兩側之基底102內的LDDs 118、一設置於閘極結構110側壁的側壁子120、以及一對設置於閘極結構110兩側之基底102內,尤其設置於側壁子120兩側之基底102內的凹槽122。Next, please refer to FIG. 2, which is a schematic view showing a second preferred embodiment of a semiconductor device having an epitaxial structure according to the present invention. It is to be noted that in the second preferred embodiment, the same components as those of the first preferred embodiment are denoted by the same reference numerals. As shown in FIG. 2, the semiconductor device 100 having an epitaxial structure provided by the preferred embodiment includes a substrate 102, and a gate structure 110 is disposed on the substrate 102. The gate structure 110 includes a gate insulating layer 112, which may comprise a high-k material or tantalum oxide. The gate structure 110 also includes a gate electrode 114 defined by a patterned hard mask 116, which may comprise a metallic material or a polysilicon. The semiconductor device 100 further includes LDDs 118 disposed in the substrate 102 on both sides of the gate structure 110, a sidewall spacer 120 disposed on the sidewall of the gate structure 110, and a pair of substrates 102 disposed on opposite sides of the gate structure 110. In particular, grooves 122 are provided in the substrate 102 on both sides of the side wall sub-120.

請繼續參閱第2圖。本較佳實施例所提供之半導體元件100更包含一磊晶結構130,設置於閘極結構110兩側之基底102內,尤其是閘極結構110兩側基底102的凹槽122內。磊晶結構130包含一第一半導體材料與一第二半導體材料,該第一半導體材料具有一第一晶格常數,該第二半導體材料具有一第二晶格常數,且該第二晶格常數大於該第一晶格常數。在本較佳實施例中,第一半導體材料可包含矽,而第二半導體材料可包含鍺。也就是說,磊晶結構130係包含矽鍺。此外,本較佳實施例中第二半導體材料濃度,即磊晶矽鍺材料中的鍺濃度係可為36%,但不限於此。此外,如第2圖所示,磊晶結構130之表面係高於基底102之表面。Please continue to see Figure 2. The semiconductor device 100 of the preferred embodiment further includes an epitaxial structure 130 disposed in the substrate 102 on both sides of the gate structure 110, particularly in the recess 122 of the substrate 102 on both sides of the gate structure 110. The epitaxial structure 130 includes a first semiconductor material and a second semiconductor material, the first semiconductor material has a first lattice constant, the second semiconductor material has a second lattice constant, and the second lattice constant Greater than the first lattice constant. In the preferred embodiment, the first semiconductor material may comprise germanium and the second semiconductor material may comprise germanium. That is, the epitaxial structure 130 includes germanium. In addition, the concentration of the second semiconductor material in the preferred embodiment, that is, the concentration of germanium in the epitaxial germanium material may be 36%, but is not limited thereto. Further, as shown in FIG. 2, the surface of the epitaxial structure 130 is higher than the surface of the substrate 102.

如前所述,為了解決前述的兩難問題,本較佳實施例係於此提供一未摻雜覆蓋層140,設置於磊晶結構130上。值得注意的是,本較佳實施例中未摻雜覆蓋層140係為一如第2圖所示之複合膜層,未摻雜覆蓋層140至少包含一第一單層140a與一第二單層140b,且第一單層140a係形成於第二單層140b與磊晶結構130之間。未摻雜覆蓋層140(包含第一單層140a與第二單層140b)亦包含上述之第一半導體材料與第二半導體材料,即包含矽鍺。第一單層140a中的鍺具有一第一濃度,而第二單層140b中的鍺具有一第二濃度,第一濃度與第二濃度皆低於磊晶結構130之鍺濃度,且第二濃度低於第一濃度。在本較佳實施例中,第一濃度較佳為25%,而第二濃度較佳為0%。換句話說,第二較佳實施例係提供一鍺濃度由下而上逐漸降低之複合覆蓋層140。此外,本較佳實施例中的未摻雜覆蓋層140厚度係可為150埃,但不限於此。值得注意的是,在本較佳實施例中第一單層140a之厚度與第二單層140b之厚度具有一比例,且該比例約等於1:2。As described above, in order to solve the aforementioned dilemma, the preferred embodiment provides an undoped cap layer 140 disposed on the epitaxial structure 130. It should be noted that, in the preferred embodiment, the undoped cover layer 140 is a composite film layer as shown in FIG. 2, and the undoped cover layer 140 includes at least a first single layer 140a and a second single The layer 140b and the first single layer 140a are formed between the second single layer 140b and the epitaxial structure 130. The undoped cap layer 140 (including the first monolayer 140a and the second monolayer 140b) also includes the first semiconductor material and the second semiconductor material described above, that is, including germanium. The crucible in the first single layer 140a has a first concentration, and the crucible in the second monolayer 140b has a second concentration, the first concentration and the second concentration are both lower than the germanium concentration of the epitaxial structure 130, and the second The concentration is lower than the first concentration. In the preferred embodiment, the first concentration is preferably 25% and the second concentration is preferably 0%. In other words, the second preferred embodiment provides a composite cover layer 140 having a reduced concentration of germanium from bottom to top. In addition, the thickness of the undoped cap layer 140 in the preferred embodiment may be 150 angstroms, but is not limited thereto. It should be noted that in the preferred embodiment, the thickness of the first single layer 140a has a ratio to the thickness of the second single layer 140b, and the ratio is approximately equal to 1:2.

如前所述,本較佳實施例所提供之半導體元件100更可包含一未摻雜底層150。有關未摻雜底層150之特徵將於後續實施例中詳細說明,故於此係不予贅述。As described above, the semiconductor device 100 provided by the preferred embodiment further includes an undoped underlayer 150. The features of the undoped underlayer 150 will be described in detail in the subsequent embodiments, and thus are not described herein.

根據本第二較佳實施例所提供之具有磊晶結構之半導體元件100,其磊晶結構130之表面係形成有一複合膜層之未摻雜覆蓋層140。複合覆蓋層140包含第一單層140a與第二單層140b,第一單層140a與第二單層140b皆包含矽鍺,且第一單層140a中鍺濃度較佳為25%,第二單層140b中鍺濃度較佳為0%,且第二單層140b之厚度大於第一單層140a之厚度。也就是說複合覆蓋層140係為一鍺濃度由下而上遞減之複合膜層。未摻雜覆蓋層140之第一單層140a之鍺濃度為25%,其設置於鍺濃度為0%的第二單層140b與鍺濃度為36%之磊晶結構130中間,故可作為兩者之緩衝層,也因此形成於磊晶結構130表面之複合覆蓋層140可獲得一較為平坦的表面。經由AFM檢測複合覆蓋層140的表面,可得知複合覆蓋層140之均方根表面粗糙度約為0.76 nm,與純矽覆蓋層之均方根表面粗糙度(4.21 nm)相較,其表面粗糙度大為改善。此外,由於複合覆蓋層140之第二單層140b中的鍺濃度為0%,因此第二單層140b可作為金屬矽化物製程的反應場所,並可根本性地避免金屬矽化物製程中金屬與鍺形成結塊之問題。According to the semiconductor device 100 having an epitaxial structure according to the second preferred embodiment, the surface of the epitaxial structure 130 is formed with an undoped cap layer 140 of a composite film layer. The composite cover layer 140 includes a first single layer 140a and a second single layer 140b. The first single layer 140a and the second single layer 140b each include a crucible, and the first single layer 140a preferably has a germanium concentration of 25%. The germanium concentration in the single layer 140b is preferably 0%, and the thickness of the second single layer 140b is greater than the thickness of the first single layer 140a. That is to say, the composite cover layer 140 is a composite film layer whose concentration is decreased from bottom to top. The first single layer 140a of the undoped cap layer 140 has a germanium concentration of 25%, and is disposed between the second single layer 140b having a germanium concentration of 0% and the epitaxial structure 130 having a germanium concentration of 36%, so that it can be used as two The buffer layer, and thus the composite cover layer 140 formed on the surface of the epitaxial structure 130, can obtain a relatively flat surface. The surface of the composite cover layer 140 is detected by AFM, and the root mean square surface roughness of the composite cover layer 140 is about 0.76 nm, which is compared with the root mean square surface roughness (4.21 nm) of the pure tantalum cover layer. The roughness is greatly improved. In addition, since the germanium concentration in the second single layer 140b of the composite cover layer 140 is 0%, the second single layer 140b can be used as a reaction site for the metal telluride process, and the metal and the metal telluride process can be fundamentally avoided. The problem of agglomeration is formed.

接下來請參閱第3圖,第3圖係為本發明所提供之具有磊晶結構之半導體元件之一第三較佳實施例之示意圖。值得注意的是,第三較佳實施例中,與第一較佳實施例相同之元件如基底102、閘極結構110、LDD118、側壁子120、凹槽122、以及形成於凹槽122內的磊晶結構130係以相同之符號說明。且由於第三較佳實施例所提供之半導體元件所包含之各元件係於前述第一較佳實施例與第二較佳實施例相同,故於此係不再贅述,而僅說明本較佳實施例與前述第一較佳實施例以及第二較佳實施例不同之處。請繼續參閱第3圖。如前所述,本較佳實施例所提供之半導體元件100所包含之磊晶結構130亦包含矽鍺。此外,本較佳實施例中第二半導體材料濃度,即磊晶矽鍺材料中的鍺濃度係可為36%,但不限於此。此外,如第3圖所示,磊晶結構130之表面係高於基底102之表面。Referring to FIG. 3, FIG. 3 is a schematic view showing a third preferred embodiment of a semiconductor device having an epitaxial structure according to the present invention. It should be noted that in the third preferred embodiment, the same components as the first preferred embodiment, such as the substrate 102, the gate structure 110, the LDD 118, the sidewall spacers 120, the recesses 122, and the recesses 122 are formed in the recesses 122. The epitaxial structure 130 is illustrated by the same reference numerals. The components included in the semiconductor device provided in the third preferred embodiment are the same as the second preferred embodiment in the first preferred embodiment, and therefore will not be described again, but only preferred. The embodiment is different from the first preferred embodiment and the second preferred embodiment described above. Please continue to see Figure 3. As described above, the epitaxial structure 130 included in the semiconductor device 100 provided by the preferred embodiment also includes germanium. In addition, the concentration of the second semiconductor material in the preferred embodiment, that is, the concentration of germanium in the epitaxial germanium material may be 36%, but is not limited thereto. Further, as shown in FIG. 3, the surface of the epitaxial structure 130 is higher than the surface of the substrate 102.

如前所述,為了解決前述的兩難問題,本較佳實施例係於此提供一未摻雜覆蓋層140,設置於磊晶結構130上。值得注意的是,本較佳實施例中未摻雜覆蓋層140係為一如第3圖所示之複合膜層,未摻雜覆蓋層140至少包含一第一單層140a、一第二單層140b與一第三單層140c。如第3圖所示,且第一單層140a與第三單層140c係形成於第二單層140b與磊晶結構130之間,而第三單層140c係形成於第一單層140a與第二單層140b之間。未摻雜覆蓋層140(包含第一單層140a、第二單層140b與第三單層140c)亦包含上述之第一半導體材料與第二半導體材料,即包含矽鍺。第一單層140a中的鍺具有一第一濃度、第二單層140b中的鍺具有一第二濃度、而第三單層140c中的鍺具有一第三濃度,且第一濃度、第二濃度、與第三濃度皆低於磊晶結構130之鍺濃度。在本較佳實施例中,第一濃度較佳為25%、第二濃度較佳為0%、而第三濃度則介於第一濃度與第二濃度之間。舉例來說,第三濃度較佳為10%,但不限於此。換句話說,第二較佳實施例係提供一鍺濃度由下而上逐漸降低之複合覆蓋層140。此外,本較佳實施例中的未摻雜覆蓋層140厚度係可為150埃,但亦不限於此。值得注意的是,在本較佳實施例中第一單層140a之厚度、第二單層140b之厚度、與第三單層140c之厚度具有一比例,且該比例約等於1:1:1。As described above, in order to solve the aforementioned dilemma, the preferred embodiment provides an undoped cap layer 140 disposed on the epitaxial structure 130. It should be noted that, in the preferred embodiment, the undoped cap layer 140 is a composite film layer as shown in FIG. 3, and the undoped cap layer 140 includes at least a first single layer 140a and a second sheet. Layer 140b and a third single layer 140c. As shown in FIG. 3, the first single layer 140a and the third single layer 140c are formed between the second single layer 140b and the epitaxial structure 130, and the third single layer 140c is formed on the first single layer 140a. Between the second single layer 140b. The undoped cap layer 140 (including the first single layer 140a, the second single layer 140b, and the third single layer 140c) also includes the first semiconductor material and the second semiconductor material described above, that is, including germanium. The crucible in the first single layer 140a has a first concentration, the crucible in the second monolayer 140b has a second concentration, and the crucible in the third monolayer 140c has a third concentration, and the first concentration, the second concentration The concentration and the third concentration are both lower than the concentration of the epitaxial structure 130. In the preferred embodiment, the first concentration is preferably 25%, the second concentration is preferably 0%, and the third concentration is between the first concentration and the second concentration. For example, the third concentration is preferably 10%, but is not limited thereto. In other words, the second preferred embodiment provides a composite cover layer 140 having a reduced concentration of germanium from bottom to top. In addition, the thickness of the undoped cap layer 140 in the preferred embodiment may be 150 angstroms, but is not limited thereto. It should be noted that in the preferred embodiment, the thickness of the first single layer 140a, the thickness of the second single layer 140b, and the thickness of the third single layer 140c have a ratio, and the ratio is approximately equal to 1:1:1. .

如前所述,本較佳實施例所提供之半導體元件100更可包含一未摻雜底層150。有關未摻雜底層150之特徵將於後續實施例中詳細說明,故於此係不予贅述。As described above, the semiconductor device 100 provided by the preferred embodiment further includes an undoped underlayer 150. The features of the undoped underlayer 150 will be described in detail in the subsequent embodiments, and thus are not described herein.

根據本第三較佳實施例所提供之具有磊晶結構之半導體元件100,其磊晶結構130之表面係形成有一複合膜層之覆蓋層140。複合覆蓋層140由下而上包含第一單層140a、第三單層140c、與第二單層140b,第一單層140a、第三單層140c與第二單層140b皆包含矽鍺,且第一單層140a中鍺濃度較佳為25%,第三單層140c中鍺濃度較佳為10%,而第二單層140b中鍺濃度較佳為0%,且第一單層140a、第三單層140c與第二單層140b之厚度約略相等。也就是說複合覆蓋層140係為一鍺濃度由下而上遞減之複合膜層。由於覆蓋層140之第一單層140a與第三單層140c之鍺濃度分別為25%與10%,其設置於鍺濃度為0%的第二單層140b與鍺濃度為36%之磊晶結構130中間,故可作為兩者中之緩衝層。且由於第二單層140b與磊晶結構130中具有兩層濃度遞減的單層,其濃度梯度差更緩,因此形成於磊晶結構130表面之複合覆蓋層140可獲得一更為平坦的表面。以AFM檢測複合覆蓋層140的表面,可得知複合覆蓋層140之均方根表面粗糙度約為0.65 nm,與純矽覆蓋層之均方根表面粗糙度(4.21 nm)相較,其表面粗糙度係獲得一超出預期之改善。此外,由於複合覆蓋層140之第二單層140b中的鍺濃度為0%,因此第二單層140b可作為金屬矽化物製程的反應場所,並可根本性地避免金屬矽化物製程中金屬與鍺形成結塊之問題。According to the semiconductor device 100 having an epitaxial structure according to the third preferred embodiment, the surface of the epitaxial structure 130 is formed with a cover layer 140 of a composite film layer. The composite cover layer 140 includes a first single layer 140a, a third single layer 140c, and a second single layer 140b from bottom to top. The first single layer 140a, the third single layer 140c, and the second single layer 140b all include a defect. The concentration of germanium in the first single layer 140a is preferably 25%, the concentration of germanium in the third single layer 140c is preferably 10%, and the concentration of germanium in the second single layer 140b is preferably 0%, and the first single layer 140a The thickness of the third single layer 140c and the second single layer 140b are approximately equal. That is to say, the composite cover layer 140 is a composite film layer whose concentration is decreased from bottom to top. Since the germanium concentrations of the first single layer 140a and the third single layer 140c of the cap layer 140 are 25% and 10%, respectively, the second single layer 140b having a germanium concentration of 0% and the epitaxial layer having a germanium concentration of 36% are disposed. The structure 130 is intermediate, so it can be used as a buffer layer in both. And because the second single layer 140b and the epitaxial structure 130 have two layers of decreasing concentration, the concentration gradient difference is more gentle, so the composite cover layer 140 formed on the surface of the epitaxial structure 130 can obtain a flat surface. . The surface of the composite cover layer 140 is detected by AFM, and the root mean square surface roughness of the composite cover layer 140 is about 0.65 nm, which is compared with the root mean square surface roughness (4.21 nm) of the pure tantalum cover layer. Roughness achieved an unexpected improvement. In addition, since the germanium concentration in the second single layer 140b of the composite cover layer 140 is 0%, the second single layer 140b can be used as a reaction site for the metal telluride process, and the metal and the metal telluride process can be fundamentally avoided. The problem of agglomeration is formed.

接下來請參閱第4圖至第5圖,第4圖至第5圖分別為本發明所提供之具有磊晶結構之半導體元件之一第四至第五較佳實施例之示意圖。值得注意的是,第四及第五較佳實施例中,與第一較佳實施例相同之元件如基底102、閘極結構110、LDD118、側壁子120、凹槽122、以及形成於凹槽122內的磊晶結構130係以相同之符號說明。且由於第四與第五較佳實施例所提供之半導體元件所包含之各元件係於前述較佳實施例相同,故於此係不再贅述,而僅說明本較佳實施例與前述實施例不同之處。Next, please refer to FIG. 4 to FIG. 5 , which are schematic diagrams showing fourth to fifth preferred embodiments of the semiconductor device having an epitaxial structure according to the present invention. It should be noted that in the fourth and fifth preferred embodiments, the same components as the first preferred embodiment, such as the substrate 102, the gate structure 110, the LDD 118, the sidewall spacers 120, the recesses 122, and the recesses are formed in the recesses. The epitaxial structure 130 within 122 is illustrated by the same reference numerals. The components included in the semiconductor device provided in the fourth and fifth preferred embodiments are the same as those in the foregoing preferred embodiment, and thus are not described herein again, but only the preferred embodiment and the foregoing embodiment are described. the difference.

如第4圖所示,第四較佳實施例係於凹槽122內分別形成一未摻雜底層150,即上述第一至第三較佳實施例中所述以及第1圖至第3圖所繪示之未摻雜底層150。未摻雜底層150係設置於磊晶結構130與基底102之間,且未摻雜底層150係覆蓋凹槽122之側壁與底部。如前所述,未摻雜底層150亦包含第一半導體材料與第二半導體材料,即包含矽鍺。為了避免磊晶結構130與基底102的接面晶格排列差異過大而導致元件啟始電壓突然發生下降的問題,本較佳實施例所提供之未摻雜底層150係為一單一膜層,且單一底層150中之鍺濃度係低於磊晶結構130之鍺濃度,例如可約等於25%。As shown in FIG. 4, the fourth preferred embodiment forms an undoped underlayer 150 in the recess 122, that is, in the first to third preferred embodiments and the first to third embodiments. The undoped underlayer 150 is depicted. The undoped underlayer 150 is disposed between the epitaxial structure 130 and the substrate 102, and the undoped underlayer 150 covers the sidewalls and the bottom of the recess 122. As previously mentioned, the undoped underlayer 150 also includes a first semiconductor material and a second semiconductor material, ie, comprising germanium. The undoped underlayer 150 provided in the preferred embodiment is a single film layer, in order to avoid the problem that the starting lattice voltage of the epitaxial structure 130 and the substrate 102 are too large to cause a sudden drop in the starting voltage of the device. The concentration of germanium in the single underlayer 150 is less than the germanium concentration of the epitaxial structure 130, for example, may be approximately equal to 25%.

此外值得注意的是,由於未摻雜底層150之設置係用以避免磊晶結構130與基底102的接面晶格常數差異過大而導致的問題,因此覆蓋凹槽122底部之未摻雜底層150厚度不宜過厚,而佔據了應變矽(即磊晶結構130)可形成的空間,進而降低應變矽提供與通道區域之應力。因此本較佳實施例中覆蓋凹槽122側壁之未摻雜底層150的厚度與覆蓋凹槽122底部之未摻雜底層150的厚度具有一比例,且該比例約等於1:1。在相同的鍺濃度條件下,當單一底層150在50托耳(Torr)的壓力狀態形成時,覆蓋凹槽122側壁之單一底層150的厚度與覆蓋凹槽122底部之單一底層150的厚度約為1:2,導致可形成磊晶結構130的空間減少。因此,本較佳實施例中係於10托耳的壓力條件下形成單一底層150,而可獲得一覆蓋凹槽122側壁之單一底層150的厚度與覆蓋凹槽122底部之單一底層150的厚度趨近1:1的理想結果。It is also worth noting that since the undoped underlayer 150 is disposed to avoid the problem caused by the excessive lattice constant difference between the epitaxial structure 130 and the substrate 102, the undoped underlayer 150 covering the bottom of the recess 122 is covered. The thickness should not be too thick, and occupy the space that the strain enthalpy (ie, the epitaxial structure 130) can form, thereby reducing the strain 矽 providing stress to the channel region. Therefore, in the preferred embodiment, the thickness of the undoped underlayer 150 covering the sidewalls of the recess 122 has a ratio to the thickness of the undoped underlayer 150 covering the bottom of the recess 122, and the ratio is approximately equal to 1:1. At the same germanium concentration, when a single bottom layer 150 is formed at a pressure of 50 Torr, the thickness of the single bottom layer 150 covering the sidewalls of the recess 122 and the thickness of the single bottom layer 150 covering the bottom of the recess 122 are approximately 1:2, resulting in a reduction in the space in which the epitaxial structure 130 can be formed. Therefore, in the preferred embodiment, a single underlayer 150 is formed under a pressure of 10 Torr, and a thickness of a single underlayer 150 covering a sidewall of the recess 122 and a thickness of a single underlayer 150 covering the bottom of the recess 122 are obtained. The ideal result of nearly 1:1.

根據本第四較佳實施例所提供之具有磊晶結構之半導體元件100,其磊晶結構130與基底102之間係形成有一單一膜層之未摻雜底層150。未摻雜底層150係包含矽鍺,且鍺濃度較佳為25%。由於未摻雜底層150之鍺濃度為25%,且設置於鍺濃度為36%之磊晶結構130與鍺濃度為0%之基底102之間,故未摻雜底層150可作為兩者之一緩衝層,藉以避免磊晶結構130與基底102的接面晶格常數差異過大而導致元件啟始電壓突然發生下降的問題。此外本較佳實施例所提供之單一底層150係具有覆蓋凹槽122側壁之厚度與覆蓋凹槽122底部之厚度的比例為1:1之特徵,因此單一底層150不會佔據用以形成磊晶結構130之可貴空間。也就是說,本較佳實施例所提供之單一底層150係可在不影響應力的前提下有效改善元件啟始電壓突然發生下降的問題。According to the semiconductor device 100 having an epitaxial structure according to the fourth preferred embodiment, an undoped underlayer 150 having a single film layer is formed between the epitaxial structure 130 and the substrate 102. The undoped underlayer 150 contains ruthenium and the ruthenium concentration is preferably 25%. Since the undoped underlayer 150 has a germanium concentration of 25% and is disposed between the epitaxial structure 130 having a germanium concentration of 36% and the substrate 102 having a germanium concentration of 0%, the undoped underlayer 150 can be used as one of the two. The buffer layer avoids the problem that the starting voltage of the element suddenly drops due to the difference in the lattice constant of the junction between the epitaxial structure 130 and the substrate 102. In addition, the single bottom layer 150 provided by the preferred embodiment has the feature that the ratio of the thickness of the sidewall of the recess 122 to the thickness of the bottom of the recess 122 is 1:1, so that the single underlayer 150 does not occupy the epitaxial layer. The valuable space of structure 130. That is to say, the single bottom layer 150 provided by the preferred embodiment can effectively improve the problem that the starting voltage of the component suddenly drops without affecting the stress.

接下來請參閱第5圖,如前所述第5圖為本發明所提供之具有磊晶結構之半導體元件之一第五較佳實施例之示意圖。如第5圖所示,第五較佳實施例係於凹槽122內分別形成一未摻雜底層150,即上述第一至第三較佳實施例中所述以及第1圖至第3圖所繪示之未摻雜底層150。未摻雜底層150係設置於磊晶結構130與基底102之間,且未摻雜底層150係覆蓋凹槽122之側壁與底部。如前所述,未摻雜底層150亦包含第一半導體材料與第二半導體材料,即包含矽鍺。值得注意的是,本較佳實施例所提供之未摻雜底層150係為一複合底層,其由下而上依序包含一第一單層150a、一第二單層150b與一第三單層150c。第一單層150a中的鍺具有一第一濃度、第二單層150b中的鍺具有一第二濃度、而第三單層150c中的鍺具有一第三濃度,第一濃度、第二濃度、與第三濃度皆低於磊晶結構130之鍺濃度,且第三濃度大於第二濃度、而第二濃度又大於第一濃度。舉例來說,第一濃度係為10%、第二濃度係為17%、而第三濃度係為25%。換句話說,本較佳實施例係提供一鍺濃度由下而上遞增之複合底層150。此外,第一單層150a、第二單層150b、與第三單層150c之厚度具有一比例,且該比例係介於1:1:1與1:1:2。值得注意的是,隨著第一單層150a、第二單層150b、與第三單層150c之厚度比例的增加,具有覆蓋凹槽122側壁之複合底層150厚度與覆蓋凹槽122底部之複合底層150厚度的比例就越趨近1:1。Next, please refer to FIG. 5. FIG. 5 is a schematic view showing a fifth preferred embodiment of the semiconductor device having an epitaxial structure according to the present invention. As shown in FIG. 5, the fifth preferred embodiment forms an undoped underlayer 150 in the recess 122, that is, in the first to third preferred embodiments and the first to third embodiments. The undoped underlayer 150 is depicted. The undoped underlayer 150 is disposed between the epitaxial structure 130 and the substrate 102, and the undoped underlayer 150 covers the sidewalls and the bottom of the recess 122. As previously mentioned, the undoped underlayer 150 also includes a first semiconductor material and a second semiconductor material, ie, comprising germanium. It should be noted that the undoped underlayer 150 provided in the preferred embodiment is a composite underlayer comprising a first single layer 150a, a second single layer 150b and a third single from bottom to top. Layer 150c. The crucible in the first single layer 150a has a first concentration, the crucible in the second monolayer 150b has a second concentration, and the crucible in the third monolayer 150c has a third concentration, the first concentration and the second concentration. And the third concentration is lower than the germanium concentration of the epitaxial structure 130, and the third concentration is greater than the second concentration, and the second concentration is greater than the first concentration. For example, the first concentration is 10%, the second concentration is 17%, and the third concentration is 25%. In other words, the preferred embodiment provides a composite underlayer 150 having a germanium concentration increasing from bottom to top. In addition, the first single layer 150a, the second single layer 150b, and the thickness of the third single layer 150c have a ratio, and the ratio is between 1:1:1 and 1:1:2. It should be noted that as the ratio of the thicknesses of the first single layer 150a, the second single layer 150b, and the third single layer 150c increases, the thickness of the composite bottom layer 150 covering the sidewalls of the recess 122 and the bottom of the covering recess 122 are combined. The ratio of the thickness of the bottom layer 150 is closer to 1:1.

根據本第五較佳實施例所提供之具有磊晶結構之半導體元件100,其磊晶結構130與基底102之間係形成有一複合膜層之未摻雜底層150。複合底層150包含第一單層150a、第二單層150b、與第三單層150c,且第一單層150a、第二單層150b、與第三單層150c皆包含矽鍺。由於複合底層150之第一單層150a、第二單層150b、與第三單層150c的鍺濃度分別由10%增加為17%、再增加為25%,因此設置於鍺濃度為0%的基底102與鍺濃度為36%之磊晶結構130中間的複合底層150係可作為兩者中之緩衝層。且由於複合底層150係為一濃度遞增的複合膜層,故可使基底102與磊晶結構130的濃度梯度差更緩,不但可避免磊晶結構130與基底102的接面晶格常數差異過大而導致元件啟始電壓突然發生下降的問題,本較佳實施例所提供之複合底層150係具有覆蓋凹槽122側壁之厚度與覆蓋凹槽122底部之厚度的比例更趨近1:1之特徵,因此複合底層150更不會佔據用以形成磊晶結構130之可貴空間。也就是說,本較佳實施例所提供之複合底層150係可在不影響應力的前提下更有效地改善元件啟始電壓突然發生下降的問題。According to the semiconductor device 100 having an epitaxial structure according to the fifth preferred embodiment, an undoped underlayer 150 of a composite film layer is formed between the epitaxial structure 130 and the substrate 102. The composite underlayer 150 includes a first single layer 150a, a second single layer 150b, and a third single layer 150c, and the first single layer 150a, the second single layer 150b, and the third single layer 150c all contain germanium. Since the germanium concentrations of the first single layer 150a, the second single layer 150b, and the third single layer 150c of the composite underlayer 150 are increased from 10% to 17% and then increased to 25%, respectively, the germanium concentration is set to 0%. The composite underlayer 150 between the substrate 102 and the epitaxial structure 130 having a germanium concentration of 36% can serve as a buffer layer in both. Moreover, since the composite underlayer 150 is a composite film layer with increasing concentration, the difference in concentration gradient between the substrate 102 and the epitaxial structure 130 can be made more gentle, and the difference in lattice constant between the epitaxial structure 130 and the substrate 102 can be avoided. The composite underlayer 150 provided in the preferred embodiment has the feature that the thickness of the sidewall of the recess 122 and the thickness of the bottom of the recess 122 are closer to 1:1. Therefore, the composite underlayer 150 does not occupy the valuable space for forming the epitaxial structure 130. That is to say, the composite underlayer 150 provided by the preferred embodiment can more effectively improve the problem that the starting voltage of the component suddenly drops without affecting the stress.

此外需注意的是,本發明所提供之第四至第五較佳實施例係可與上述第一至第三較佳實施例排列組合,務以使得具有磊晶結構130之半導體元件100獲得最佳電性表現為目標。In addition, it should be noted that the fourth to fifth preferred embodiments provided by the present invention can be combined with the first to third preferred embodiments described above, so that the semiconductor device 100 having the epitaxial structure 130 is obtained the most. Excellent electrical performance is the goal.

綜上所述,根據本發明所提供之具有磊晶結構之半導體元件,該磊晶結構表面係形成有一具有較低鍺濃度的未摻雜覆蓋層,因此可避免金屬矽化物製程中,金屬易與磊晶層中的鍺形成結塊、進而造成接面漏電的問題。此外,本發明所提供之磊晶結構半導體元件,係於凹槽內的磊晶結構與基底之間設置一鍺濃度較低的未摻雜底層,以避免矽鍺磊晶層與矽基底的接面晶格排列差異過大、進而導致元件啟始電壓突然發生下降的問題。In summary, according to the semiconductor device having an epitaxial structure provided by the present invention, the surface of the epitaxial structure is formed with an undoped cap layer having a lower germanium concentration, thereby avoiding metal thinning in the metal germanide process. The problem of agglomeration with the tantalum in the epitaxial layer, thereby causing leakage of the junction. In addition, the epitaxial semiconductor device provided by the present invention is provided with a lower concentration of undoped underlayer between the epitaxial structure in the recess and the substrate to avoid the connection between the epitaxial layer and the germanium substrate. The difference in the lattice arrangement of the face is too large, which in turn causes a sudden drop in the starting voltage of the component.

以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100...半導體元件100. . . Semiconductor component

102...基底102. . . Base

110...閘極結構110. . . Gate structure

112...閘極絕緣層112. . . Gate insulation

114...閘極電極114. . . Gate electrode

116...圖案化硬遮罩116. . . Patterned hard mask

118...輕摻雜汲極118. . . Lightly doped bungee

120...側壁子120. . . Side wall

122...凹槽122. . . Groove

130...磊晶結構130. . . Epitaxial structure

140...未摻雜覆蓋層140. . . Undoped cover

140a...第一單層140a. . . First single layer

140b...第二單層140b. . . Second single layer

140c...第三單層140c. . . Third single layer

150...未摻雜底層150. . . Undoped bottom layer

150a...第一單層150a. . . First single layer

150b...第二單層150b. . . Second single layer

150c...第三單層150c. . . Third single layer

第1圖係為本發明所提供之具有磊晶結構之半導體元件之一第一較佳實施例之示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing a first preferred embodiment of a semiconductor device having an epitaxial structure according to the present invention.

第2圖係為本發明所提供之具有磊晶結構之半導體元件之一第二較佳實施例之示意圖。2 is a schematic view showing a second preferred embodiment of a semiconductor element having an epitaxial structure provided by the present invention.

第3圖係為本發明所提供之具有磊晶結構之半導體元件之一第三較佳實施例之示意圖。Figure 3 is a schematic view showing a third preferred embodiment of a semiconductor device having an epitaxial structure provided by the present invention.

第4圖係為本發明所提供之具有磊晶結構之半導體元件之一第四較佳實施例之示意圖。Figure 4 is a schematic view showing a fourth preferred embodiment of a semiconductor device having an epitaxial structure provided by the present invention.

第5圖係為本發明所提供之具有磊晶結構之半導體元件之一第五較佳實施例之示意圖。Figure 5 is a schematic view showing a fifth preferred embodiment of a semiconductor device having an epitaxial structure provided by the present invention.

100...半導體元件100. . . Semiconductor component

102...基底102. . . Base

110...閘極結構110. . . Gate structure

112...閘極絕緣層112. . . Gate insulation

114...閘極電極114. . . Gate electrode

116...圖案化硬遮罩116. . . Patterned hard mask

118...輕摻雜汲極118. . . Lightly doped bungee

120...側壁子120. . . Side wall

122...凹槽122. . . Groove

130...磊晶結構130. . . Epitaxial structure

140...未摻雜覆蓋層140. . . Undoped cover

140a...第一單層140a. . . First single layer

140b...第二單層140b. . . Second single layer

150...未摻雜底層150. . . Undoped bottom layer

Claims (26)

一種具有磊晶源極/汲極之半導體元件,包含有:一閘極結構,設置於一基底上;磊晶結構,設置於該閘極結構兩側之該基底內,該磊晶結構包含一種摻雜質、一第一半導體材料與一第二半導體材料,該第一半導體材料具有一第一晶格常數,該第二半導體材料具有一第二晶格常數,且該第二晶格常數大於該第一晶格常數,該磊晶結構中該第二半導體材料具有一第一濃度;以及一未摻雜覆蓋層,設置於該磊晶結構上,該未摻雜覆蓋層包含該第一半導體材料與該第二半導體材料,該未摻雜覆蓋層中該第二半導體材料至少具有一第二濃度,該第二濃度小於該第一濃度,且該第二濃度至少為25%。 A semiconductor device having an epitaxial source/drainage, comprising: a gate structure disposed on a substrate; an epitaxial structure disposed in the substrate on both sides of the gate structure, the epitaxial structure comprising a doped material, a first semiconductor material and a second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor material having a second lattice constant, and the second lattice constant being greater than The first lattice constant, the second semiconductor material has a first concentration in the epitaxial structure; and an undoped cap layer disposed on the epitaxial structure, the undoped cap layer comprising the first semiconductor The material and the second semiconductor material, the second semiconductor material in the undoped cap layer has at least a second concentration, the second concentration is less than the first concentration, and the second concentration is at least 25%. 如申請專利範圍第1項所述之半導體元件,更包含:輕摻雜汲極,設置於該閘極結構兩側之該基底內;以及一側壁子,設置於該閘極結構之側壁上。 The semiconductor device of claim 1, further comprising: a lightly doped drain disposed in the substrate on both sides of the gate structure; and a sidewall disposed on a sidewall of the gate structure. 如申請專利範圍第1項所述之半導體元件,其中該第一半導體材料包含矽,該第二半導體材料包含鍺。 The semiconductor component of claim 1, wherein the first semiconductor material comprises germanium and the second semiconductor material comprises germanium. 如申請專利範圍第1項所述之半導體元件,其中該第二濃度等於25%。 The semiconductor component of claim 1, wherein the second concentration is equal to 25%. 如申請專利範圍第1項所述之半導體元件,其中該未摻雜覆蓋層包含一單一膜層或一複合膜層。 The semiconductor device of claim 1, wherein the undoped cap layer comprises a single film layer or a composite film layer. 如申請專利範圍第5項所述之半導體元件,其中該複合膜層至少包含一第一單層與一第二單層,該第一單層係形成於該第二單層與該磊晶結構之間,該第一單層具有該第二濃度,該第二單層中該第二半導體材料具有一第三濃度,且該第三濃度等於0%。 The semiconductor device of claim 5, wherein the composite film layer comprises at least a first single layer and a second single layer, the first single layer being formed on the second single layer and the epitaxial structure The first monolayer has the second concentration, the second semiconductor material in the second monolayer has a third concentration, and the third concentration is equal to 0%. 如申請專利範圍第6項所述之半導體元件,其中該第一單層與該第二單層之厚度具有一比例,且該比例等於1:2。 The semiconductor device of claim 6, wherein the first single layer has a ratio to the thickness of the second single layer, and the ratio is equal to 1:2. 如申請專利範圍第6項所述之半導體元件,其中該複合膜層更包含一第三單層,設置於該第一單層與該第二單層之間,該第三單層中之該第二半導體材料具有一第四濃度,且該第四濃度係介於該第二濃度與該第三濃度之間。 The semiconductor device of claim 6, wherein the composite film layer further comprises a third single layer disposed between the first single layer and the second single layer, wherein the third single layer The second semiconductor material has a fourth concentration, and the fourth concentration is between the second concentration and the third concentration. 如申請專利範圍第8項所述之半導體元件,其中該第四濃度約等於10%。 The semiconductor component of claim 8, wherein the fourth concentration is approximately equal to 10%. 如申請專利範圍第8項所述之半導體元件,其中該第一單層、該第二單層與該第三單層之厚度具有一比例,且該比例等於1:1:1。 The semiconductor device of claim 8, wherein the first single layer, the second single layer and the third single layer have a ratio of a thickness, and the ratio is equal to 1:1:1. 如申請專利範圍第1項所述之半導體元件,更包含一複合底層, 設置於該磊晶結構與該基底之間,且該複合底層包含該第一半導體材料與該第二半導體材料。 The semiconductor component according to claim 1, further comprising a composite underlayer, And disposed between the epitaxial structure and the substrate, and the composite underlayer includes the first semiconductor material and the second semiconductor material. 如申請專利範圍第11項所述之半導體元件,其中該複合底層中之該第二半導體材料之濃度係介於10~25%。 The semiconductor device of claim 11, wherein the concentration of the second semiconductor material in the composite underlayer is between 10 and 25%. 如申請專利範圍第12項所述之半導體元件,其中該複合底層中之該第二半導體材料之濃度係由下而上遞增。 The semiconductor device of claim 12, wherein the concentration of the second semiconductor material in the composite underlayer is increased from bottom to top. 一種具有磊晶結構之半導體元件,包含有:一閘極結構,設置於一基底上;一對凹槽,設置於該閘極結構兩側之該基底內;一磊晶結構,分別設置於該閘極結構兩側之該凹槽內,該磊晶結構包含一種摻雜質、一第一半導體材料與一第二半導體材料,該第一半導體材料具有一第一晶格常數,該第二半導體材料具有一第二晶格常數,且該第二晶格常數大於該第一晶格常數,該磊晶結構中該第二半導體材料具有一第一濃度;一未摻雜底層,形成於該凹槽內,且設置於該磊晶結構與該基底之間,該未摻雜底層係覆蓋該凹槽之側壁與該凹槽之底部,且包含該第一半導體材料與該第二半導體材料,該未摻雜底層中該第二半導體材料至少具有一第二濃度,且該第二濃度小於該第一濃度;以及一未摻雜覆蓋層,設置於該磊晶結構上,該未摻雜覆蓋層包含該 第一半導體材料與該第二半導體材料,該未摻雜覆蓋層中該第二半導體材料之一濃度至少為25%。 A semiconductor device having an epitaxial structure, comprising: a gate structure disposed on a substrate; a pair of grooves disposed in the substrate on both sides of the gate structure; an epitaxial structure disposed on the substrate In the recess on both sides of the gate structure, the epitaxial structure comprises a doping material, a first semiconductor material and a second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor The material has a second lattice constant, and the second lattice constant is greater than the first lattice constant, wherein the second semiconductor material has a first concentration in the epitaxial structure; an undoped underlayer is formed in the concave In the trench, and disposed between the epitaxial structure and the substrate, the undoped underlayer covers the sidewall of the recess and the bottom of the recess, and includes the first semiconductor material and the second semiconductor material, The second semiconductor material in the undoped underlayer has at least a second concentration, and the second concentration is less than the first concentration; and an undoped cap layer disposed on the epitaxial structure, the undoped cap layer Including a first semiconductor material and the second semiconductor material, wherein one of the second semiconductor materials in the undoped cap layer has a concentration of at least 25%. 如申請專利範圍第14項所述之半導體元件,更包含:輕摻雜汲極,設置於該閘極結構兩側之該基底內;以及一側壁子,設置於該閘極結構之側壁上。 The semiconductor device of claim 14, further comprising: a lightly doped drain disposed in the substrate on both sides of the gate structure; and a sidewall disposed on a sidewall of the gate structure. 如申請專利範圍第14項所述之半導體元件,其中該第一半導體材料包含矽,該第二半導體材料包含鍺。 The semiconductor component of claim 14, wherein the first semiconductor material comprises germanium and the second semiconductor material comprises germanium. 如申請專利範圍第14項所述之半導體元件,其中該第二濃度等於25%。 The semiconductor component of claim 14, wherein the second concentration is equal to 25%. 如申請專利範圍第14項所述之半導體元件,其中覆蓋該凹槽側壁之該未摻雜底層之厚度與覆蓋該凹槽底部之該未摻雜底層之厚度具有一比例,且該比例約等於1:1。 The semiconductor device of claim 14, wherein a thickness of the undoped underlayer covering the sidewall of the recess has a ratio to a thickness of the undoped underlayer covering the bottom of the recess, and the ratio is approximately equal to 1:1. 如申請專利範圍第18項所述之半導體元件,其中該未摻雜底層包含一單一底層或一複合底層。 The semiconductor component of claim 18, wherein the undoped underlayer comprises a single underlayer or a composite underlayer. 如申請專利範圍第19項所述之半導體元件,其中該複合底層至少包含一第一單層、一第二單層與一第三單層,由下而上依序形成於該凹槽側壁與該凹槽底部。 The semiconductor device according to claim 19, wherein the composite underlayer comprises at least a first single layer, a second single layer and a third single layer, which are sequentially formed on the sidewall of the groove from bottom to top. The bottom of the groove. 如申請專利範圍第20項所述之半導體元件,其中該第三單層具有該第二濃度,該第二單層具有一第三濃度,該第一單層具有一第四濃度,該第二濃度係大於該第三濃度,且該第三濃度係大於該第四濃度。 The semiconductor device of claim 20, wherein the third single layer has the second concentration, the second single layer has a third concentration, and the first single layer has a fourth concentration, the second The concentration system is greater than the third concentration, and the third concentration is greater than the fourth concentration. 如申請專利範圍第21項所述之半導體元件,其中該第三濃度係為17%,而該第四濃度係為10%。 The semiconductor device according to claim 21, wherein the third concentration is 17% and the fourth concentration is 10%. 如申請專利範圍第21項所述之半導體元件,其中該第一單層、該第二單層與該第三單層之厚度比例係介於1:1:1與1:1:2。 The semiconductor device according to claim 21, wherein the first single layer, the second single layer and the third single layer have a thickness ratio of 1:1:1 and 1:1:2. 如申請專利範圍第14項所述之半導體元件,更包含一複合覆蓋層,設置於該磊晶結構上,且該複合覆蓋層包含該第一半導體材料與該第二半導體材料。 The semiconductor device of claim 14, further comprising a composite cover layer disposed on the epitaxial structure, wherein the composite cover layer comprises the first semiconductor material and the second semiconductor material. 如申請專利範圍第24項所述之半導體元件,其中該複合覆蓋層中之該第二半導體材料之濃度係介於0~25%。 The semiconductor device according to claim 24, wherein the concentration of the second semiconductor material in the composite coating layer is between 0 and 25%. 如申請專利範圍第25項所述之半導體元件,其中該複合覆蓋層中之該第二半導體材料之濃度係由下而上遞減。 The semiconductor device of claim 25, wherein the concentration of the second semiconductor material in the composite cover layer decreases from bottom to top.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080067609A1 (en) * 2006-09-20 2008-03-20 Kim Myung-Sun Semiconductor Device Including Field Effct Transistor and Method of Forming the Same
US20090108308A1 (en) * 2007-10-31 2009-04-30 Jusung Engineering Co., Ltd Transistor and method of fabricating the same
US20100093147A1 (en) * 2008-10-14 2010-04-15 Chin-I Liao Method for forming a semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080067609A1 (en) * 2006-09-20 2008-03-20 Kim Myung-Sun Semiconductor Device Including Field Effct Transistor and Method of Forming the Same
US20090108308A1 (en) * 2007-10-31 2009-04-30 Jusung Engineering Co., Ltd Transistor and method of fabricating the same
US20100093147A1 (en) * 2008-10-14 2010-04-15 Chin-I Liao Method for forming a semiconductor device

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