TWI500123B - Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods - Google Patents

Description

Adhesive semiconductor structure comprising interconnect layers of one or more electrical, optical, and fluid interconnects Formation method and application of the bonded semiconductor structure formed by the method

The present invention relates to a method of forming a bonded semiconductor structure using a three-dimensional integration technique, and a bonded semiconductor structure formed using such methods.

The three dimensional integration of two or more semiconductor structures can bring many benefits to microelectronic applications. For example, a three-dimensional spatial accumulation of microelectronic components can improve electrical performance and power consumption while reducing the area occupied by components. For related information, see The Handbook of 3D Integration, edited by P. Garrou et al. (Wiley-VCH Publishing, 2008).

The three-dimensional spatial accumulation of the semiconductor structure can be achieved by attaching a semiconductor die to other one or more semiconductor dies (ie, die-to-die (D2D)), A semiconductor die is attached to one or more semiconductor wafers (ie, die-to-wafer (D2W)), and a semiconductor wafer is attached to one or more other semiconductor wafers (ie, wafer-to-wafer Round (W2W)).

The bonding technique used to bond a semiconductor structure to another semiconductor structure can be classified in different ways. One is to classify the two semiconductor structures by an intermediate material, and the second is the key interface. Whether electrons (ie, current) are allowed to be classified through the interface. The so-called "direct bonding method" is to establish a direct solid-to-solid chemical bond between two semiconductor structures to bond them together without using between the two semiconductor structures. The method of bonding materials in the middle. At present, a metal-to-metal direct bonding method has been developed for bonding a metal material on a surface of a first semiconductor structure to a metal material on a surface of a second semiconductor structure.

The metal-to-metal direct bonding method can also be classified according to the temperature range at which each method operates. For example, some metal-to-metal direct bonding methods are performed at relatively high temperatures, thus causing at least partial melting of the metallic material at the bonding interface. Such direct bonding processes may not be suitable for bonding processed semiconductor structures containing one or more component structures, as their relatively high temperatures may adversely affect previously formed component structures.

The "hot press bonding" method is performed at a high temperature between 200 ° C (200 ° C) and approximately 500 ° C (500 ° C), usually between approximately 300 ° C (300 ° C) and approximately 400 ° C A direct bonding method of applying pressure between the bonding surfaces between (400 ° C).

Other direct bonding methods have also been developed, which can be carried out at temperatures of 200 degrees Celsius (200 ° C) or lower. For such direct bonding processes performed at 200 degrees Celsius (200 ° C) or lower, this specification is referred to as an "ultra-low temperature" direct bonding process. The ultra-low temperature direct bonding process can be carried out by careful removal of surface impurities and surface compounds (eg, native oxide layers), and by increasing the area of intimate contact between the two surfaces on an atomic scale. The area of intimate contact between the two surfaces is typically achieved by grinding the bonding surfaces to reduce the surface roughness to a value close to the atomic scale, applying pressure between the bonding surfaces to cause plastic deformation, or both grinding keys. The surface of the junction is then stressed to achieve such plastic deformation. After direct physical contact between the two surfaces, a one-click wave is initiated at and along the interface between the two abutting surfaces. When the wavefront propagates through the bonding interface between the two abutting surfaces, a direct chemical bond is established between the two abutting surfaces at the wavefront.

Some ultra-low temperature direct bonding methods can be applied without the need to apply pressure at the bonding interface between the bonding surfaces, but in other ultra-low temperature direct bonding methods, in order to achieve a suitable bonding strength at the bonding interface, the bonding can be performed. Pressure is applied to the bonding interface between the surfaces. In the art to which the present invention pertains, an ultra-low temperature direct bonding method for applying pressure between bonding surfaces is generally referred to as a "surface assisted bonding" or "SAB" method. Therefore, in the present specification, "surface auxiliary bonding" and "SAB" mean and include a first material against a second material at a temperature of 200 degrees Celsius (200 ° C) or lower, and Pressure is applied to the bonding interface between the bonding surfaces to directly bond the first material to any direct bonding process of the second material.

The purpose of this summary is to present a series of concepts in a concise form. These concepts are further detailed in the exemplary embodiments of the invention. This summary is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

In some embodiments, the invention includes a method of forming a bonded semiconductor structure. In accordance with such methods, a substrate structure can be provided that includes a relatively thin layer of material on a relatively thick substrate body. A plurality of thinner material layers are formed that penetrate the through wafer interconnect and penetrate the first substrate structure. A first processed semiconductor structure is bonded over the thinner material layer of the first substrate structure, and the first substrate structure is bonded to the first substrate structure opposite to one side of the thicker substrate body At least one electrically conductive component is electrically coupled to at least one of the through wafer interconnects. A layer of transfer material is provided over the first processed semiconductor structure opposite the first processed semiconductor structure opposite the first substrate structure. Forming electrical interconnections, optical interconnections in the layer of transfer material And fluid interconnecting at least one of them. A second processed semiconductor structure is provided over the layer of transfer material opposite the surface of the first processed semiconductor structure. The thicker substrate body of the substrate structure is removed leaving a thinner layer of material of the substrate structure bonded to the processed semiconductor structure. At least one of the through-wafer interconnects of the through-wafer interconnects can be electrically coupled to one of the conductive features of the other structure.

In other embodiments, the invention includes bonded semiconductor structures fabricated using the methods described herein. For example, in some embodiments, the present invention includes a bonded semiconductor structure comprising a substrate structure, a plurality of processed semiconductor structures, and a layer of transfer material over the processed semiconductor structures, the The semiconductor structure is processed opposite one side of the substrate structure. The substrate structure includes a relatively thin layer of one material that is penetrated by a plurality of through-wafer interconnects, and a relatively thick one of the substrate bodies bonded to the layer of material. The processed semiconductor structures are electrically coupled to the through wafer interconnects in a side of the thinner material layer opposite the thicker substrate body. At least one of an electrical interconnect, an optical interconnect, and a fluid interconnect is disposed in the layer of transfer material.

The description of the present specification is not intended to be an actual description of any particular semiconductor structure, component, system or method, but is merely an idealized description for describing embodiments of the invention.

The use of any headings in this specification should not be construed as limiting the scope of the embodiments of the invention, which is defined by the scope of the following claims and their legal equivalents. The concepts described under any particular heading also generally apply to the rest of the specification.

This specification is hereby incorporated by reference. In addition, the patent standard claimed with respect to the present invention The references cited herein, regardless of how they are described in the specification, are not admitted as prior art.

In the present specification, the term "semiconductor structure" means and includes any structure used in the formation of a semiconductor element. For example, a semiconductor structure includes a die and a wafer (eg, a carrier substrate and an element substrate), and an assembled or composite structure containing two or more grains and/or crystals that are stacked on each other in three dimensions. Round. The semiconductor structure also includes fully fabricated semiconductor components, as well as intermediate structures formed during fabrication of the semiconductor components.

In the present specification, the term "processed semiconductor structure" means and includes any semiconductor structure having at least one or more component structures that have been partially formed. The processed semiconductor structure is a subset of the semiconductor structure, and all of the processed semiconductor structures are semiconductor structures.

In the present specification, the term "bonded semiconductor structure" means and includes any structure having two or more semiconductor structures attached thereto. The bonded semiconductor structure is a subset of the semiconductor structure, and all of the bonded semiconductor structures are semiconductor structures. In addition, one or more of the processed semiconductor structures in the bonded semiconductor structure are also processed semiconductor structures.

In the present specification, the term "elemental structure" means and includes any part of a processed semiconductor structure that is, includes, or defines at least a portion of an active or passive component of a semiconductor component. It is to be formed above or in the semiconductor structure. For example, the component structure includes active and passive components of the integrated circuit, such as transistors, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

In the present specification, the term "electrical interconnection" means and includes a semiconductor structure by electrically providing at least a portion of a current path between at least two component structures. Any conductive parts that are joined together.

In the present specification, the term "through-wafer interconnect" or "TWI" means and includes any conductive via that penetrates at least a portion of a first semiconductor structure, spanning the first semiconductor structure and a second semiconductor An interface between the structures provides a structural and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure. In the technical field of the present invention, there are other names for penetrating wafer interconnects, such as "through silicon vias", "through substrate vias", and "through". Through-wafer vias, or the abbreviation of the above name, such as "TSV" or "TWV". The direction through which the through-wafer interconnect penetrates a semiconductor structure is generally substantially perpendicular to the substantially planar major surfaces of the semiconductor structure (ie, parallel to the "Z" axis). The penetrating wafer interconnect is an electrical interconnect.

In the present specification, the term "optical interconnection" means and includes any component in a semiconductor structure for providing a path between at least two optical element structures that facilitates the transmission of electromagnetic waves of one or more wavelengths. radiation. Although the term "optical" is used in relation to vision, it is outside the visible or visible region of the electromagnetic radiation spectrum (for example, one or both of the visible and infrared segments of the electromagnetic radiation spectrum) One or more wavelengths of electromagnetic radiation, optical interconnects may also be used to provide a path thereto.

In the present specification, the term "fluid interconnection" means and includes any component in a semiconductor structure for providing a fluid path or a portion of a channel for transporting a fluid through the semiconductor structure. At least part of it. For example, a fluid interconnect can include a first portion of a fluid passage that interconnects a second portion of the fluid passage with a third portion of the fluid passage.

According to some embodiments of the invention, a recyclable substrate structure can be temporarily bonded to a half lead Body structure and used for the formation of a bonded semiconductor structure. After the semiconductor structure is processed, the recyclable substrate structure can be removed from the semiconductor structure to form the bonded semiconductor structure. The processing can include providing a layer of transfer material on the semiconductor structure, forming at least one of an electrical interconnect, an optical interconnect, and a fluid interconnect in the layer of transfer material, and bonding another processed semiconductor structure to the Transfer the material layer above.

1A through 1C illustrate the fabrication of a substrate structure 120 (Fig. 1C) that may be employed in accordance with some embodiments of the present invention. Referring to FIG. 1A, a substrate structure 100 is provided that includes a relatively thin layer of material 102 on a relatively thick substrate body 104. In some embodiments, the substrate structure 100 can comprise a wafer level substrate having an average diameter of hundreds of meters or more. As an example of non-limiting properties, the thinner material layer 102 can have an average thickness of about 20 microns (20 μm) or less, about 2 microns (2.0 μm) or less, about 1.5 microns (1.5 μm), or Thinner, or even about 1 micron (1 μm) or thinner. The thicker substrate body 104 has an average thickness, for example, of between about 600 microns (600 μm) and a few centimeters.

The thinner material layer 102 can comprise a semiconductor material such as tantalum or niobium. Such a semiconductor material may be polycrystalline or at least substantially composed of a single crystal material, and such semiconductor material may be doped or undoped. In other embodiments, the thinner material layer 102 may comprise a ceramic material such as an oxide (eg, yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), etc.), a nitride (eg, nitrogen). Hydrazine (Si ₃ N ₄ ), boron nitride (BN), etc., or an oxynitride (such as cerium oxynitride (SiON)).

The thicker substrate body 104 can have a composition that is different from the composition of the thinner material layer 102, but can itself comprise a semi-conductive material as described above with respect to the thinner material layer 102. Body material or a ceramic material. In other embodiments, the thicker substrate body 104 can comprise a metal or metal alloy.

In some embodiments, a temporary bonding technique can be utilized, such as that disclosed in U.S. Patent Application Serial No. 12/837,326, the entire disclosure of which is incorporated herein by reference. In this specification, the thinner material layer 102 is temporarily attached to the thicker substrate body 104.

The thicker substrate body 104 can comprise a portion of the substrate structure 100 that is recyclable and reusable, as described in more detail below.

Referring to FIG. 1B, a plurality of through wafer interconnects 112 can be formed and penetrated through the thinner material layer 102 to form the substrate structure 110 of FIG. 1B. Various different methods of forming the through-wafer interconnects 112 are known in the art to which the present invention pertains and may be employed in embodiments of the present invention. As a non-limiting example, one of the patterned mask layers may be provided on the exposed major surface of the thinner material layer 102. The patterned mask layer can include a plurality of apertures that penetrate the patterned mask layer at locations where the through-wafer interconnects 112 are to be formed through the thinner material layer 102. The vias penetrating the thinner material layer 102 can then be etched using an etch process such as an anisotropic wet chemical etch process or an anisotropic dry reactive ion etch process. After the through holes are formed, the patterned mask layer can be removed, and then one or more conductive metals or metal alloys (such as copper or a copper alloy) are filled into the through holes to form the through crystals. Circular interconnect 112. For example, one or more of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroless plating process, and an electrolytic plating process may be used to provide a conductive material in the via holes. After the conductive material is deposited or otherwise provided in the through holes, an etching or polishing process can be utilized, which will still exist. Any conductive material on the surface 102 is removed to form the through wafer interconnects 112.

After forming the through-wafer interconnects 112 that penetrate the thinner material layer 102, one or more of the thinner material layers 102 may be selectively opposite one of the thicker substrate bodies 104. A distribution layer (RDL) 122 is formed over the thinner material layer 102 to form the substrate structure 120 shown in FIG. 1C. As is known in the art to which the present invention pertains, a redistribution layer can be used to redistribute the position of an electrical component of a first structure or component to accommodate a pattern of conductive features on another structure or component to be coupled. In other words, a redistribution layer may have a first conductive component pattern in its first mask and a second conductive component pattern in a second surface opposite the first surface, wherein the first surface The conductive members are electrically connected to the corresponding conductive members on the opposite second side through the redistribution layer.

As shown in FIG. 1C, the redistribution layer 122 can include a plurality of electrically conductive features 124 disposed within and surrounded by a dielectric material 126. The conductive features 124 can include one or more of a conductive pad, laterally extending conductive or conductive traces, and longitudinally extending conductive vias. In addition, the redistribution layer 122 may comprise a plurality of layers formed by sequentially covering one layer, wherein each layer includes a conductive member 124 and a dielectric material 126, and the conductive member 124 in one layer may be connected to the conductive member 124 of the adjacent layer. There is direct physical contact and electrical contact, such that the conductive members 124 of the redistribution layer 122 extend from the surface of the redistribution layer 122 continuously through the dielectric material 126 to the redistribution layer 122. The opposite side. On the side of the redistribution layer 122 adjacent to the thinner material layer 102 and the through-wafer interconnects 112, the patterns of the conductive members 124 in the redistribution layer 122 can be matched with the patterns The patterns of the through-wafer interconnects 112 are complementary such that the through-wafer interconnects 112 are in direct physical contact with the corresponding conductive features 124 in the redistribution layer 122. And electrical contact. As described above, the pattern of the conductive members 124 in the redistribution layer 122 may be redistributed from one surface of the redistribution layer 122 across the thickness of the redistribution layer 122 to the other side of the redistribution layer 122.

Referring to FIG. 1D, after the redistribution layer 122 is formed, at least one processed semiconductor structure 132A can be bonded to the thinner material layer 102 of the substrate structure 120 opposite to one of the thicker substrate bodies 104. Above the thin material layer 102 to form the structure 130 of Figure 1D. For example, the at least one processed semiconductor structure 132A can be directly bonded to the redistribution layer 122, as shown in FIG. 1D.

In some embodiments, a plurality of processed semiconductor structures 132A, 132B, 132C can be bonded to the thinner material layer on a side of the thinner material layer 102 of the substrate structure 120 opposite one of the thicker substrate body 104. The redistribution layer 122 above 102 is as shown in FIG. 1D. The processed semiconductor structures 132A, 132B, 132C may be juxtaposed in a lateral direction along a common plane that is parallel to one of the major surfaces of the first substrate structure 120, as shown in FIG. 1D. In other words, each of the processed semiconductor structures 132A, 132B, 132C can occupy a different area on the substrate structure 120, and a plane can be drawn from its location that passes through the processed semiconductors. Each of the structures 132A, 132B, 132C has a semiconductor structure processed and is parallel to one of the major surfaces of the first substrate structure 120.

One or more of the processed semiconductor structures 132A, 132B, 132C may comprise, for example, a semiconductor die, and may also include an electronic signal processor, a memory component, and a photovoltaic component (eg, a light emitting diode, a laser, a photodiode) One or more of a polar body, a solar cell, and the like.

Bonding the processed semiconductor structures 132A, 132B, 132C to the substrate structure 120 The conductive features 134 of the processed semiconductor structures 132A, 132B, 132C can be electrically interconnected with the conductive features 124 of the redistribution layer 122 and the through wafers that penetrate the thinner material layer 102. 112 coupled.

The bonding process used to bond the processed semiconductor structures 132A, 132B, 132C to the substrate structure 120 can be performed at one or more temperatures of about 400 ° C or less. In some embodiments, the processed semiconductor structures 132A, 132B, 132C can be bonded using a hot or non-hot press direct bonding process implemented at one or more temperatures of about 400 ° C or less. To the substrate structure 120. In some embodiments, the processed semiconductor structures 132A, 132B, 132C can be bonded to the substrate structure using an ultra-low temperature direct bonding process implemented at one or more temperatures of about 200 ° C or less. 120. In some examples, the bonding process can be carried out at a temperature of about room temperature. Performing the bonding process at such lower temperatures can avoid unintentional damage to the component structures in the processed semiconductor structures 132A, 132B, 132C. Moreover, in some embodiments, the bonding process can include a surface assist bonding process. The direct bonding process can include a direct bonding process of an oxide to oxide (eg, ceria versus cerium oxide), and/or a direct bonding process of a metal to metal (eg, copper to copper).

In some embodiments, additional processed semiconductor structures may be stacked over the processed semiconductor structures 132A, 132B, 132C and associated with the processed semiconductor structures 132A using one or more three-dimensional spatial accumulation processes. 132B and 132C are electrically and physically coupled. An example of such processes will be described below with reference to Figures 1E to 1H.

Referring to FIG. 1E, after the processed semiconductor structures 132A, 132B, 132C are bonded to the substrate structure 120, a dielectric material 138 can be deposited on the processed semiconductor junctions. The upper and the periphery of the structures 132A, 132B, and 132C are formed to form the structure 140 of FIG. 1E. The dielectric material 138 can comprise, for example, a polymeric material or an oxide material (e.g., yttria), and the dielectric material 138 can utilize, for example, a spin coating process or a chemical vapor deposition (CVD) process. And deposition. An oxide material that can be deposited at low stress and relatively high deposition rates may be a suitable material. The composition of the oxide material does not decompose due to subsequent processing, such as tempering at temperatures up to 400 °C. As an example of non-limiting properties, in some embodiments, the dielectric material 138 can comprise an oxide layer having a thickness greater than 30 microns (30 μm), which is enhanced by a plasma at a temperature of about 400 ° C. A vapor deposition (PECVD) process is deposited. The oxide layer can be deposited at a rate of between 1.8 microns per minute and 3.0 microns per minute. The residual stress of such a deposited film can be as low as about 15 MPa.

The dielectric material 138 can be deposited in a conformal manner over the structure 130 of FIG. 1D such that the exposed major surface 139 of the dielectric material 138 includes peaks and valleys. The peaks may be located above the processed semiconductor structures 132A, 132B, 132C, which may be located above the area between the processed semiconductor structures 132A, 132B, 132C, as shown in FIG. 1E.

Referring to FIG. 1F, the exposed major surface 139 of the dielectric material 138 can be planarized, and a portion of the dielectric material 138 can be removed to pass the processed semiconductor structures 132A, 132B, 132C through the dielectric. Material 138 is exposed and forms structure 150 as shown in FIG. 1F. For example, a chemical etching process (dry or wet), a mechanical polishing process, or a chemical mechanical polishing (CMP) process can be used to planarize the exposed major surface 139 of the dielectric material 138 and remove the dielectric. a part of the electrical material 138 and make these The processed semiconductor structures 132A, 132B, 132C are exposed through the dielectric material 138.

As shown in FIG. 1G, an additional plurality of through wafer interconnects 162 may be formed and passed at least partially through the processed semiconductor structures 132A, 132B, 132C to form the structure 160. The additional through-wafer interconnects 162 formed may extend from the exposed major surfaces of the processed semiconductor structures 132A, 132B, 132C through the processed semiconductor structures 132A, 132B, 132C to the The conductive features 134 within the semiconductor structures 132A, 132B, 132C are processed. The through wafer interconnects 162 can be formed as described above with respect to forming the through wafer interconnects 112. However, the temperature of the processes can be limited to about 400 ° C or less to avoid damaging the component structures within the processed semiconductor structures 132A, 132B, 132C.

Referring to FIG. 1H, after forming the additional through-wafer interconnects 162, additional processed semiconductor structures 132D, 132E, 132F may be provided in the vertical direction using the processes described above with reference to FIGS. 1D through 1G. The upper portion is over the processed semiconductor structures 132A, 132B, 132C to form the bonded semiconductor structure 170 shown in FIG. 1H. As an example, a processed semiconductor structure 132D can be directly bonded to the processed semiconductor structure 132A, a processed semiconductor structure 132E can be directly bonded to the processed semiconductor structure 132B, and a processed semiconductor structure 132F can be directly bonded. The resulting semiconductor structure 132C is bonded. The bonding process temperature may be limited to about 400 ° C or lower to avoid damaging the component structures in the processed semiconductor structures 132A to 132F, and the bonding processes may include a hot pressing direct bonding process, A non-hot pressing direct bonding process, or an ultra-low temperature direct bonding process. Moreover, in some embodiments, the direct bonding processes can include surface assist bonding processes.

In this configuration, the processed semiconductor structures 132D, 132E, 132F are disposed in the longitudinal direction of the processed semiconductor structures 132A along a line perpendicular to the major surfaces of the first substrate structure 120, Above 132B and 132C. For example, the processed semiconductor structure 132A and the processed semiconductor structure 132D are disposed along a common line perpendicular to one of the major surfaces of the first substrate structure 120, and are disposed one above the other in the longitudinal direction. In other words, a common line can be drawn from the processed semiconductor structure 132A and the processed semiconductor structure 132D, which passes through the processed semiconductor structure 132A and the processed semiconductor structure 132D perpendicular to the first substrate. The major surfaces of structure 120.

After the processed semiconductor structures 132D, 132E, 132F are bonded to the processed semiconductor structures 132A, 132B, 132C, additional through-wafer interconnects 172 can be formed and at least partially passed through the portions. Semiconductor structures 132D, 132E, 132F have been processed. The additional through-wafer interconnects 172 formed may extend from the exposed major surfaces of the processed semiconductor structures 132D, 132E, 132F through the processed semiconductor structures 132D, 132E, 132F to the Through-wafer interconnect 162 or other conductive features of the processed semiconductor structures 132A, 132B, 132C. The through wafer interconnects 172 can be formed as described above with respect to forming the through wafer interconnects 112. However, the temperature of the processes can be limited to about 400 ° C or less to avoid damaging the component structures within the processed semiconductor structures 132A through 132F.

The processes described above with respect to Figures 1D through 1G may be repeated one or more times as needed to accumulate any number of other processed semiconductor structural layers in the three-dimensional spatial accumulation process in the longitudinal direction. Above the semiconductor structures 132A-132F.

After forming the bonded semiconductor structure 170 of FIG. 1H, a transferred material layer 212 (FIG. 1K) can be provided to the processed semiconductors on the opposite side of the processed semiconductor structures 132A-132F opposite the substrate structure 120. Above the structures 132A to 132F. An example of a method that can be used to provide the transfer material layer 212 (Fig. 1K) over the processed semiconductor structures 132A-132F is described below with reference to Figures 1I through 1K.

As a non-limiting example, the transfer material layer 212 may be provided over the processed semiconductor structures 132A-132F using the SMARTCUT® process referred to in the art to which the present invention pertains to form the bonded semiconductor of FIG. 1K. Structure 210. Such processes are detailed, for example, in U.S. Patent No. RE 39,484 (issued to Bruel on February 6, 2007), U.S. Patent No. 6,303,468 (issued to Aspar et al. on October 16, 2001), and U.S. Patent No. 6,335,258. (issued to Aspar et al. on January 1, 2002), US Patent 6,756,286 (issued to Moriceau et al. on June 29, 2004), and US Patent 6,809,044 (issued to Aspar et al. on October 26, 2004). And U.S. Patent No. 6,946,365 issued to Aspar et al.

Referring to FIG. 1I, in a SMARTCUT® process, a plurality of ions (eg, one or more of hydrogen ions, helium ions, or inert gas ions) can be implanted along an ion implantation plane 192 with an additional substrate structure 190. In some embodiments, the timing of implantation of the ions into the additional substrate structure 190 can be prior to bonding the additional substrate structure 190 over the processed semiconductor structures 132A-132F, as described below with respect to FIG. 1J. .

The additional substrate structure 190 can comprise a semiconductor material such as tantalum or niobium. Such a semiconductor material may be polycrystalline or at least substantially composed of a single crystal material, and such semiconductor material may be doped or undoped. In other embodiments, the additional substrate structure 190 can comprise a ceramic material such as an oxide (eg, yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), etc.), a nitride (eg, nitrogen). Hydrazine (Si ₃ N ₄ ), boron nitride (BN), etc., or an oxynitride (such as cerium oxynitride (SiON)). In some embodiments, the additional substrate structure 190 can comprise a wafer level substrate.

The ions may be implanted in a direction substantially perpendicular to one of the generally planar major surfaces of the additional substrate structure 190. As is known in the art to which the present invention pertains, the depth at which the ions are implanted into the additional substrate structure 190 is at least partially a function of the energy of the ions implanted into the additional substrate structure 190. In general, ions implanted at lower energies have a relatively shallow depth of implantation, and ions implanted at higher energies have a relatively deep implant depth.

The ions may be implanted into the additional substrate structure 190 at a predetermined energy, the predetermined energy being selected to implant the ions into the additional substrate structure 190 at a desired depth. The timing at which the ions are implanted into the additional substrate structure 190 can be prior to or after the additional substrate structure 190 is bonded over the processed semiconductor structures 132A-132F, as described below with respect to FIG. 1J. As a specific, non-limiting example, the ion implantation plane 192 can be disposed at a depth D within the additional substrate structure 190 that is about 100 nanometers from one of the major surfaces 194 of the additional substrate structure 190 ( 100 nm) to approximately 1,000 nm (1,000 nm). As is known in the art to which the present invention pertains, the depth at which some ions are implanted may inevitably not be the desired implant depth D, and as the ions from the major surface of the additional substrate structure 190 to the additional A plot of the depth of the substrate structure 190, such as before the bond, may show a curve that is generally bell-shaped (symmetric or asymmetrical) having a desired implant depth A maximum.

After implanting ions into the additional substrate structure 190, the ions can define an ion implantation plane 192 (shown in phantom in Figure 1I) within the additional substrate structure 190. The ion implantation plane 192 can include a layer or region within the additional substrate structure 190 that is aligned (eg, centered about) with the plane having the highest ion concentration within the additional substrate structure 190. The ion implantation plane 192 can define a weakened region within the additional substrate structure 190 that can be stripped or split along the weakened region in a subsequent process.

Referring to FIG. 1J, the additional substrate structures 190 are bonded to the processed semiconductor structures 132A in the semiconductor structure 170 of FIG. 1H, opposite to one of the processed semiconductor structures 132A-132F opposite to the first substrate structure 120. Above 132F, a bonded semiconductor structure 200 as shown in FIG. 1J is formed. In some embodiments, the additional substrate structure 190 can be bonded to the bonded semiconductor structure 170 using a direct bonding process. Additionally, the additional substrate structure 190 can be selectively bonded to the bonded semiconductor structure 170 using a bonding material (not shown). Such a bonding material may comprise, for example, one or more of cerium oxide, cerium nitride, and a mixture of the two. Such bonding material may be formed or otherwise provided to one or both of the additional substrate structure 190 and the abutting surfaces of the bonding semiconductor structure 170 to improve bonding therebetween.

In some embodiments, the additional substrate structure 190 can be bonded to the bonded semiconductor structure 170 at a temperature of about 400 ° C or less, or even at a temperature of about 350 ° C or less. However, in other embodiments, the bonding process can be performed at a higher temperature.

After the relatively thick additional substrate structure 190 is bonded to the bonded semiconductor structure 170, the additional substrate structure 190 can be thinned to form the transfer material layer 212 and FIG. 1K. The illustrated semiconductor structure 210 is shown. A portion 196 (see FIG. 1J) of the additional substrate structure 190 can be removed from the additional substrate structure 190 while leaving a relatively thin layer of transfer material 212 on the surface 103 of the bonded semiconductor structure 170.

For example, the additional substrate structure 190 can be heated to cause the additional substrate structure 190 to crack or break along the ion implantation plane 192. In some embodiments, the temperature of the additional substrate structure 190 during this cleavage process can be maintained at about 400 ° C or less, or even at about 350 ° C or less. In other embodiments, however, the cleavage process can be performed at a higher temperature. Additionally, a mechanical force may be selectively applied to the additional substrate structure 190 to cause or assist in rupturing the additional substrate structure 190 along the ion implantation plane 192.

In other embodiments, the additional substrate structure 190 (eg, a layer having an average thickness greater than about 100 microns) can be bonded to the bonded semiconductor structure 170, followed by the opposite substrate structure 190 opposite the bonded semiconductor One side of the structure 170 thins the additional substrate structure 190, and the thinner transfer material layer 212 is provided over the bonded semiconductor structure 170. For example, the additional substrate structure 190 can be thinned by exposing the primary surface removal material from one of the additional substrate structures 190. For example, material may be removed from the additional substrate structure 190 using a chemical process (eg, a wet or dry chemical etch process), a mechanical process (eg, a grinding or honing process), or via a chemical mechanical polishing (CMP) process. The main surface is removed by exposure. By performing such bonding and thinning processes, the thickness of the thinner material layer 102 can be greater than 20 microns (20 μm) in some embodiments. In other embodiments, the thickness of the thinner material layer 102 can be less than 20 microns (20 μm) in some embodiments. In some embodiments, such processes can be carried out at one or more temperatures of about 400 ° C or less, or even about 350 ° C or less. But in other embodiments, such processes can be more Perform at high temperatures.

In other embodiments, the thinner transition material layer 212 can be formed in situ over the exposed major surface of the bonded semiconductor structure 170 (e.g., on the surface). For example, the bonded semiconductor structure 210 of FIG. 1K can be formed by depositing a semiconductor material such as germanium, polysilicon or amorphous germanium onto a desired thickness on one of the exposed major surfaces of the bonded semiconductor structure 170. In some embodiments, the deposition process can be performed at about one or more temperatures of about 400 ° C or less, or even at about 350 ° C or less. For example, as is known in the art, a low temperature deposition process for forming the thinner transfer material layer 212 can be performed using a plasma enhanced chemical vapor deposition process. In other embodiments, however, the deposition process can be performed at higher temperatures.

The bonded semiconductor structure 210 of Figure 1K is an intermediate structure that can be further processed to form a finished semiconductor component. For example, after forming the bonded semiconductor structure 210 of FIG. 1K, at least one of electrical interconnection, optical interconnection, and fluid interconnection can be formed in the transfer material layer 212, and can be accumulated in another three-dimensional space. In the process, one or more additional processed semiconductor structures are provided over the layer of transfer material 212.

An example of an embodiment of a method that can be used to form one or more electrical interconnections in the transfer material layer 212 of the bonded semiconductor structure 210 of FIG. 1K is described below with reference to FIGS. 2A through 2E.

Referring to FIG. 2A, a plurality of electrical interconnects 302 may be formed in the transfer material layer 212 to form the bonded semiconductor structure 300 of FIG. 2A. In some embodiments, the electrical interconnects 302 can include through-wafer interconnects, and each electrical interconnect 302 can extend through the transfer material layer 212 to the through-wafer interconnects 172 In one of these, each electrical interconnect 302 is structurally and electrically coupled to one of the through wafer interconnects 172. The electrical mutual Connection 302 can comprise a conductive material such as a metal or metal alloy (e.g., copper or a copper alloy). The electrical interconnects 302 can be formed using the methods previously described with respect to the through wafer interconnects 112 as described above with respect to FIG. 1B.

After the electrical interconnects 302 are formed in the transfer material layer 212, one or more redistribution layers can be selectively disposed on the transfer material layer 212 opposite one of the processed semiconductor structures 132A-132F. A (RDL) 312 is formed over the transfer material layer 212 to form the bonded semiconductor structure 310 shown in FIG. 2B. The redistribution layer 312 can include a plurality of conductive features 314 disposed within and surrounded by a dielectric material 316 that can be associated with the redistribution layer as previously described with reference to FIG. 1C. Formed by the description of 122. The conductive features 314 can include one or more of a conductive pad, laterally extending conductive or conductive traces, and longitudinally extending conductive vias. In addition, the redistribution layer 312 may comprise a plurality of layers formed by sequentially covering one layer, wherein each layer includes a conductive member 314 and a dielectric material 316.

Referring to FIG. 2C, after the redistribution layer 312 is formed, at least one processed semiconductor structure 322 can be bonded to the transfer material layer 212 on the opposite side of the transfer material layer 212 opposite the processed semiconductor structures 132A-132F. Above, to form the bonded semiconductor structure 320 of FIG. 2C. For example, the at least one processed semiconductor structure 322 can be directly bonded to the redistribution layer 312, as shown in FIG. 2C. One or more conductive features 324 of the processed semiconductor structure 322, such as bond pads, may be structurally and electrically coupled to the conductive features 314 of the redistribution layer 312, and the transfer material layer 212. Electrical interconnects 302 are coupled.

As a non-limiting example, the additional processed semiconductor component 322 can include half The conductor die may also include one or more of an electronic signal processor, a memory component, and a photovoltaic component (eg, a light emitting diode, a laser, a photodiode, a solar cell, etc.).

The additional processed semiconductor structure 322 can be directly bonded to the dielectric material 316 or the electrical interconnect 314 of the redistribution layer 312, or directly to the dielectric material 316 and the electrical interconnect 314 of the redistribution layer 312. . The direct bonding process used to bond the additional processed semiconductor component 322 to the dielectric material 316 and/or the electrical interconnects 314 can be performed at one or more temperatures of about 400 ° C or less. In some embodiments, the bonding process can include a hot press direct bonding process or a non-hot press direct bonding process performed at one or more temperatures of about 400 ° C or less. In other embodiments, the bonding process can comprise an ultra-low temperature direct bonding process implemented at one or more temperatures of about 200 ° C or less. In some examples, the bonding process can be carried out at a temperature of about room temperature. Moreover, in some embodiments, the bonding process can include a surface assisted bonding process. The direct bonding process can include a direct bonding process of an oxide to oxide (eg, yttria to yttrium oxide), and/or a direct bonding process of a metal to metal (eg, copper to copper).

Referring to FIG. 2D, after the additional processed semiconductor structure 322 is bonded to the bonded semiconductor structure 310 of FIG. 2B, the thicker substrate body 104 of the first substrate structure 120 can be removed, leaving the thinner material. Layer 102 and the through-wafer interconnects 112 penetrating therethrough are bonded to the redistribution layer 122 and the processed semiconductor structures 132A-132F. For example, the thicker substrate body 104 can be separated and recovered from the thinner material layer 102 in a manner that does not cause significant or unrepairable damage to the thicker substrate body 104.

After the thicker substrate body 104 of the substrate structure 120 is removed from the bonded semiconductor structure 320 (FIG. 2C), the thicker substrate body 104 can be recovered and reused. For example, In a bonded semiconductor structure forming method such as described below, the thicker substrate body 104 can be reused one or more times.

On each exposed end of the through wafer interconnect 112, a conductive bump 332 can be selectively provided to form the bonded semiconductor structure 330 of FIG. 2D. The conductive bumps 332 may comprise a conductive metal or metal alloy, such as a reflow solderable alloy, and the conductive bumps 332 may cause the through-wafer interconnects 112 in the bonded semiconductor structure 330 to be in the structure. It is electrically and electrically apt to couple with a conductive member of another structure, which may be one of a higher grade substrate or component, or a higher grade one of the substrates or components.

For example, in FIG. 2E, the bonded semiconductor structure 330 of FIG. 2D can be structurally and electrically coupled to a structure 342 to form the bonded semiconductor structure 340 of FIG. 2E. For example, the structure 342 can include another processed semiconductor structure or a printed circuit board. As shown in FIG. 2E, the structure 342 can include a plurality of conductive features 344 and a surrounding dielectric material 346. For example, the conductive members 344 can include a bond pad. The conductive bumps 332 can be aligned and abutted against the conductive members 344. The conductive bumps 332 may be heated to cause the materials of the conductive bumps 332 to reflow. Thereafter, the material may be cooled and solidified to form the conductive vias 112 and the conductive portions of the structures 342. Structural and electrical bonding between components 344.

The bonded semiconductor structure 340 of Figure 2E can be further processed as needed to suit its intended use. As a non-limiting example, a protective coating or cladding material may be provided over at least a portion of the bonded semiconductor structure 340, and/or materials between and around the structure 342 and each of the conductive bumps 332. Between layers 102, a protective bonding material is provided.

As previously mentioned, in the transfer material layer 212 of the bonded semiconductor structure 210 of FIG. 1K, in addition to the formation of electrical interconnections, optical interconnections and fluid interconnections can be formed. An example of an embodiment of a method that can be used to form one or more optical interconnects in the transfer material layer 212 of the bonded semiconductor structure 210 of FIG. 1K is described below with reference to FIGS. 3A through 3C and FIGS. 4A through 4D.

As shown in FIG. 3A, one or more optical interconnects 402 can be formed in the layer of transfer material 212. In some embodiments, the optical interconnects 402 can comprise columns (eg, cylinders) that are generally perpendicular to the vertical direction (ie, perpendicular from the perspective of FIG. 3A), the columns having the composition, dimensions, and The shape is such that it appears as a waveguide of electromagnetic radiation of one or more wavelengths. The optical interconnects 402 may comprise those known in the art as "optical vias" (OVs) or "through silicon optical vias" (TSOVs).

The composition of the optical interconnects 402 can be different from the composition of the transfer material layer 212 such that there is a change in refractive index across the boundary between the optical interconnects 402 and the transfer material layer 212. In other words, the transfer material layer 212 can comprise a material exhibiting a first index of refraction, and the optical interconnects 402 can comprise a material exhibiting a different second index of refraction. As a non-limiting example, in some embodiments, the transfer material layer 212 can comprise germanium, and the optical interconnects 402 can comprise a polymeric material (eg, a polynorbornene polymer material).

Various processes for forming such optical interconnects 402 are known in the art to which the present invention pertains and may be employed in embodiments of the present invention. An example of a method that can be used to fabricate such optical interconnects 402 in the layer of transfer material 212 is described below with reference to Figures 4A through 4D. 4A is an enlarged, simplified view of the transfer material layer 212. As shown in the figures, a plurality of apertures 404 can be formed and penetrated through the layer of transfer material 212. To form the apertures 404, a mask layer having a pattern can be provided on the exposed major surface 406 of the layer of transfer material 212. The patterned mask layer can include apertures penetrating the patterned mask layer at locations where the apertures 404 (and the optical interconnects 402) are to be formed through the layer of transfer material 212. The apertures 404 that penetrate the layer of transfer material 212 can then be etched using an etch process (eg, an anisotropic wet chemical etch process, or an anisotropic dry reactive ion etch process).

If the transfer material layer 212 comprises germanium, the exposed surfaces 408 of the transfer material layer 212 may be selectively oxidized to form a layer of germanium dioxide on the exposed surfaces 408. In this configuration, the layer of oxide material can serve as an optical covering material surrounding the optical interconnects 402.

Referring to FIG. 4B, after forming the apertures 404, the patterned mask layer can be removed, and a polymer is coated on the exposed main surface 406 of the transfer material layer 212 and at least a portion of the apertures 404. Precursor material. For example, a liquid polymer precursor material 410 can be applied to the exposed major surface 406 of the layer of transfer material 212 and at least a portion of the apertures 404 using a spin coating process. The surfaces within the apertures 404 may optionally be covered with at least a portion of a dielectric material, such as cerium oxide, another oxide material, or a nitride material. As shown in FIG. 4B, in some embodiments, the polymer precursor material 410 may only be partially filled within the pores 404 after the preliminary deposition process.

Referring to FIG. 4C, a pressure may be applied over the deposited liquid polymer precursor material 410 by means such as a pressurized gas, causing the polymer precursor material 410 to at least substantially fill the pores 404, after which the polymerization may be made. The precursor material 410 is polymerized, To form a solid polymer material 412 disposed within the apertures 404. In some methods, the material 410 can enter and fill the apertures 404 without the aid of any applied pressure.

After the solid polymer material 412 is provided in the apertures 404, excess solid polymer material 412 can be disposed over the major surface 406 of the layer of transfer material 212 as shown in FIG. 4C. As shown in FIG. 4D, excess solid polymer material 412 over the major surface 406 can be removed using, for example, a chemical etching process, a mechanical polishing process, and/or a chemical mechanical polishing (CMP) process. Removal of the excess solid polymer material 412 will define and form the optical interconnects 402 that include the remainder of the polymeric material 412 within the voids 404.

Referring again to FIG. 3A, each optical interconnect 402 can be individually aligned and optically coupled to a waveguide or other optical component or structure within the processed semiconductor structures 132A-132F (eg, laser, light emitting diode, optoelectronics). Diode, etc.).

Referring to FIG. 3B, after the optical interconnects 402 are formed in the transfer material layer 212, at least one processed semiconductor structure 422 can be disposed on the transfer material layer 212 opposite to one of the processed semiconductor structures 132A-132F. Bonded over the layer of transfer material 212 to form the bonded semiconductor structure 420 of FIG. 3B. As a non-limiting example, the additional processed semiconductor component 422 can include a semiconductor die, and can also include one or more photovoltaic components 424 (eg, light emitting diodes, lasers, photodiodes, solar cells, etc.) ), which is configured to receive and/or emit electromagnetic radiation. As shown in FIG. 3B, the processed semiconductor component 422 can also include one or more waveguides 426, which can include laterally extending sections and/or longitudinally extending sections (from the perspective of FIG. 3B). The waveguides 426 can be operationally (ie, Optoelectronically coupled to the optoelectronic components 424, electromagnetic radiation is transmitted between the optoelectronic components 424 via the waveguides 426. The waveguides 426 can also be operatively coupled to the optical interconnects 402 in the layer of transfer material 212 and can be coupled to other active device structures within the bonded semiconductor structure 420 (or to an optical output portion for coupling) To the other optical active component outside the bonded semiconductor structure 420).

The additional processed semiconductor structure 422 can be bonded directly to the transfer material layer 212. The direct bonding process used to bond the additional processed semiconductor component 422 to the transfer material layer 212 can be performed at one or more temperatures of about 400 ° C or less. In some embodiments, the bonding process can include a hot press direct bonding process or a non-hot press direct bonding process performed at one or more temperatures of about 400 ° C or less. In other embodiments, the bonding process can comprise an ultra-low temperature direct bonding process implemented at one or more temperatures of about 200 ° C or less. In some examples, the bonding process can be carried out at a temperature of about room temperature. Moreover, in some embodiments, the bonding process can include a surface assisted bonding process. The direct bonding process can include a direct bonding process of an oxide to oxide (eg, yttria to yttrium oxide), and/or a direct bonding process of a metal to metal (eg, copper to copper).

Referring to FIG. 3C, after the additional processed semiconductor structure 422 is bonded to the bonded semiconductor structure 400 of FIG. 3B to form the bonded semiconductor structure 420, the bonding can be performed as described above with reference to FIGS. 2D and 2E. The semiconductor structure 420 is further processed to form the bonded semiconductor structure 430 shown in FIG. 3C. For example, the thicker substrate body 104 of the first substrate structure 120 can be removed (and optionally recycled and reused) and A conductive bump 432 is provided on the exposed end of the through wafer interconnect 112, and the resulting structure can be structurally and electrically coupled to the other structure 434 to form the bonded semiconductor structure shown in FIG. 3C. 430. For example, the structure 434 can include another processed semiconductor structure or a printed circuit board. As shown in FIG. 3C, the structure 434 can include a plurality of conductive features 436 (eg, bond pads) and a surrounding dielectric material 438. The conductive bumps 432 can be aligned, abutted, and bonded to the conductive features 436 to form structural and electrical bonds between the through wafer interconnects 112 and the conductive features 436 of the structures 434. .

The bonded semiconductor structure 430 of Figure 3C can be further processed as needed to suit its intended use. As a non-limiting example, a protective coating or cladding material may be provided over at least a portion of the bonded semiconductor structure 430, and/or materials between and around the structure 434 and each of the conductive bumps 432. Between layers 102, a protective bonding material is provided.

An example of an embodiment of a method that can be used to form one or more fluid interconnects in the transfer material layer 212 of the bonded semiconductor structure 210 of FIG. 1K is described below with reference to Figures 5A through 5E.

The fluid interconnects to be formed may be part of a fluid circuit through which a fluid may flow to cool the processed semiconductor structures within the bonded semiconductor structure during operation.

As shown in FIG. 5A, one or more recesses (eg, trenches) 502 may be formed (eg, at least partially) through the transfer material layer 212 to form the bonded semiconductor structure 500 illustrated in FIG. 5A. For example, as shown in FIGS. 5A and 5B, a single groove 502 may be formed in the transfer material layer 212 and passed at least partially through the transfer material layer 212. 502 has a coiled shape that traverses across the layer of transfer material 212. However, in other embodiments of the invention, the one or more grooves 502 can have any other shape.

Various processes that can be used to form such grooves 502 are known in the art to which the present invention pertains and can be employed in embodiments of the present invention. As a non-limiting example, one of the patterned mask layers may be provided on the exposed major surface of the transfer material layer 212. The patterned mask layer can include one or more apertures that penetrate the patterned mask layer at locations where the one or more recesses 502 are to be formed in the layer of transfer material 212. The one or more recesses 502 can then be etched into the layer of transfer material 212 using an etch process (eg, an anisotropic wet chemical etch process, or an anisotropic dry reactive ion etch process). Once the one or more recesses 502 are formed, the patterned mask layer can be removed.

Referring to FIG. 5C, in some embodiments, a layer of protective material 512 may be provided to cover at least the exposed surfaces of the layer of transfer material 212 within the recesses 502. In some embodiments, the layer of protective material 512 may also be provided on the major surface 214 of the layer of transfer material 212 outside the recesses 502, as shown in FIG. 5C.

The layer of protective material 512 can be used to protect the exposed surfaces of the layer of transfer material 212 within the recesses 502 from being exposed to fluids interconnecting the fluids formed by the recesses 502. damage. For example, in embodiments where the transfer material layer 212 comprises tantalum or niobium, the layer of protective material 512 can comprise tantalum oxide or tantalum oxide, respectively. Such an oxide material may be formed by oxidizing the surface of the transfer material layer 212 (for example, using a low temperature oxidation process) or by depositing an oxide material such as a low temperature chemical vapor deposition (CVD) process.

Referring to FIG. 5D, after the recesses 502 are formed in the transfer material layer 212, another material layer 522 may be provided over the transfer material layer 212 to cover and seal the recesses 502 to form The bonded semiconductor structure 520 shown in FIG. 5D. One or more fluid interconnects 504 (ie, fluid channels) may be defined by covering and enclosing the recesses 502, passing through the bonded semiconductor structure at an interface between the transfer material layer 212 and the material layer 522. 520.

The material layer 522 can comprise at least a portion of a substrate structure. In some embodiments, the material layer 522 can also comprise at least a portion of a wafer level substrate structure. The material layer 522 can comprise, for example, any of the materials mentioned above in relation to the additional substrate structure 190 of FIG. In some embodiments, the material layer 522 can have the same composition as the transfer material layer 212.

As a non-limiting example, the material layer 522 can be provided over the transfer material layer 212 using a SMARTCUT® process, as previously described with reference to Figures 1I and 1J. For example, a plurality of ions (eg, one or more of hydrogen ions, helium ions, or inert gas ions) can be implanted along an ion implantation plane into an additional substrate structure (not shown), followed by the additional substrate The structure is bonded to the transfer material layer 212, after which the additional substrate structure is broken along the ion implantation plane to remove a portion of the substrate structure leaving the material layer 522 bonded to the transfer material Layer 212.

The material layer 522 can be bonded directly to the transfer material layer 212. The direct bonding process used to bond the layer of material 522 to the layer of transfer material 212 can be carried out at one or more temperatures of about 400 ° C or less. In some embodiments, the bonding process can be included in a large A hot press direct bonding process performed at one or more temperatures of about 400 ° C or less. In other embodiments, the bonding process can comprise an ultra-low temperature direct bonding process implemented at one or more temperatures of about 200 ° C or less. In some examples, the bonding process can be carried out at a temperature of about room temperature. Moreover, in some embodiments, the bonding process can include a surface assisted bonding process. The direct bonding process can include a direct bonding process of an oxide to oxide (eg, yttria to yttrium oxide), and/or a direct bonding process of a metal to metal (eg, copper to copper).

In some embodiments, a bonding layer 524 can be formed or otherwise provided on the surface of the material layer 522 to be bonded to the transfer dielectric material 212. For example, in embodiments where the layer of protective material 512 also includes an oxide layer, the bonding layer 524 can comprise an oxide layer (eg, hafnium oxide). Matching the bonding layer 524 and the composition of the layer of protective material 512 may also facilitate bonding of the material layer 522 to the transfer in a direct bonding process (eg, an oxide-to-oxide direct bonding process). Dielectric material 212.

After the recesses 502 in the layer of transfer material 212 are covered with the material layer 522 and sealed to form the fluid interconnects 504, one or more access openings 532A, 532B may be formed to penetrate The material layer 522 extends to the fluid interconnect 504 in the transfer material layer 212, as shown in the bonded semiconductor structure 530 of FIG. 5E. For example, the access openings 532A, 532B that penetrate the material layer 522 and extend to the fluid interconnect 504 may be formed in the bonded semiconductor structure 530 using a masking and etching process as described above. . For example, a first access opening 532A can lead to a first end of a fluid interconnect 504, and a second access opening 532B can lead to an opposite second end of the fluid interconnect 504. In this fabric, the first An access opening 532A can provide access to one of the fluid interconnects 504, and the second access opening 532B can provide a fluid outlet away from the fluid interconnect 504. Next, a first fluid conduit 534A can be coupled to the first access opening 532A and a second fluid conduit 534B can be coupled to the second access opening 532B, as shown in FIG. 5E.

In this configuration, during operation and use of the processed semiconductor structures 132A-132F in the bonded semiconductor structure 530, a fluid (eg, a cooling fluid) can flow through the first fluid conduit 534A and the first An access opening 532A enters the fluid interconnect 504, flows through the fluid interconnect 504, and then flows out of the fluid interconnect 504 via the second access opening 532B and the second fluid conduit 534B, such as the fluid The directional arrows in the conduits 534A, 534B are presented. As such, one or more fluid interconnects 504 can be formed in the layer of transfer material 212.

After forming the bonded semiconductor structure 530 of FIG. 5E, the bonded semiconductor structure 530 can be further processed, as described above with respect to the bonded semiconductor structure 320 with reference to FIGS. 2C through 2E, and as previously described with reference to FIG. 3B and 3C is described with respect to the bonded semiconductor structure 420.

As discussed above, embodiments of the present invention enable inter-strataelectric, optical, and microfluidic interconnects to be fabricated in bonded semiconductor structures that are stacked in a three-dimensional space, the bonded semiconductor structures Multiple layers are included, each layer containing one or more processed semiconductor structures. In these embodiments described above, each cross-layer interconnect layer contains only a single type of interconnect (i.e., one of an electrical interconnect, an optical interconnect, and a fluid interconnect). In other embodiments of the present invention, one or more of the cross-layer interconnect layers may include two or three different types of interconnections (eg, Such as electrical and optical interconnects, electrical and fluid interconnects, optical and fluid interconnects, or electrical, optical, and fluid interconnects. The interconnect layers can be formed by the method described above, the regions of the transfer material layer 212 that are intended to contain a certain type of interconnect are covered and protected by a mask, and the mask layer is not covered on the transfer material layer 212. Another type of interconnection is made in different regions. The mask is then removed, another mask is overlaid on the previously fabricated interconnect, and another type of interconnect is made on the transfer material layer 212 that does not cover the different regions of the mask.

6 is a simplified partial cross-sectional perspective view of a bonded semiconductor structure 600 comprising two inter-layer interconnect layers 602A and 602B, which may be implemented as described above in accordance with the method of the present invention Example production.

The bonded semiconductor structure 600 includes a processed semiconductor structure 132A-132F of a first layer 604A, processed semiconductor structures 132G-132L of a second layer 604B, and processed semiconductor structures 132M-132R of a third layer 604C. The processed semiconductor structures 132A to 132R may comprise, for example, semiconductor dies, and may also include an electronic signal processor, a memory element, and a photovoltaic element (eg, a light emitting diode, a laser, a photodiode, a solar cell). Etc.) One or more of them. In the layers 604A-604C, some of the processed semiconductor structures 132A-132R may be stacked one on another in the longitudinal direction or may be operatively coupled to each other.

Each of the interconnect layers 602A and 602B can comprise a transfer material layer 212 as described above. As shown in FIG. 6, each of the interconnect layers 602A and 602B includes at least one electrical interconnect 302, at least one optical interconnect 402, and at least one fluid interconnect 504. In some embodiments, the electrical interconnects 302, optical interconnects 402, and fluid interconnects 504 One or more of the ones may be operatively coupled to one or more of the processed semiconductor structures 132A-132R.

The bonded semiconductor structure 600 also includes a substrate structure 120 as previously described, and the processed semiconductor structures 132A-132F of the first layer 604A are bonded over the substrate structure 120. As discussed above, the substrate structure 120 can include a relatively thin layer of material 102 on a relatively thick substrate body 104 with a plurality of through wafer interconnects 112 formed and penetrating the layer of material. 102. Moreover, a redistribution layer 122 can be provided over the material layer 102 as previously described. As shown in FIG. 6, in some embodiments, at least one optical interconnect 402 and/or at least one microfluidic interconnect 504 can also be formed in the thinner material layer 102.

In addition, as shown in FIG. 6, each of the interconnect layers 602A and 602B can include a redistribution layer 122 that can be used to redistribute the electrical interconnects 302, optical interconnects 402, and fluid interconnects. 504.

The processes described above can be repeated any number of times to form any desired number of processed semiconductor structure layers between the interconnect layers.

After forming the bonded semiconductor structure 600 shown in FIG. 6, the bonded semiconductor structure 600 can be further processed, as described above with respect to the bonded semiconductor structure 320 with reference to FIGS. 2C through 2E, and as previously described with reference to FIG. 3B and 3C are described with respect to the bonded semiconductor structure 420.

In the bonded semiconductor structure 600 of FIG. 6, each interconnect layer includes electrical interconnects, optical interconnects, and fluid interconnects. In other embodiments, each interconnect layer may comprise only a single type of interconnect, or only two types of interconnects.

For example, FIG. 7 presents a bonded semiconductor structure 700 that is similar to the bonded semiconductor structure 600 of FIG. 6 and that has processed a processed semiconductor structure 132A-132F, a second layer 604B of a first layer 604A. Semiconductor structures 132G through 132L, and processed semiconductor structures 132M through 132R of a third layer 604C. A first cross-layer interconnect layer 702A is disposed between the processed semiconductor structures 132A-132F of the first layer 604A and the processed semiconductor structures 132G-132L of the second layer 604B, and a second cross-layer interconnect layer 702B is disposed. Disposed between the processed semiconductor structures 132G-132L of the second layer 604B and the processed semiconductor structures 132M-132R of the third layer 604C.

Each of the interconnect layers 702A and 702B can comprise a transfer material layer 212 as described above. As shown in FIG. 7, each of the interconnect layers 702A and 702B includes at least one electrical interconnect 302. The first interconnect layer 702A also includes a fluid interconnect 504, but does not include any optical interconnects 402. The second interconnect layer 702B includes an optical interconnect 402 but does not include any fluid interconnects 504. For example, when one or more of the processed semiconductor structures 132A-132L in the embodiment comprise a high power semiconductor component (eg, an electronic signal processor), and in the embodiment, the processed semiconductor structures 132M are One or more of the 132Rs may be suitable for this configuration when one or more optical components (such as lasers, light-emitting diodes, or photodiodes) are included.

The bonded semiconductor structure 700 also includes a substrate structure 120 as previously described, and the processed semiconductor structures 132A-132F of the first layer 604A are bonded over the substrate structure 120. As discussed above, the substrate structure 120 can comprise a relatively thin layer of material 102 on a relatively thick substrate body 104, and a plurality of through wafer interconnects 112 are formed and worn. The material layer 102 is penetrated. Moreover, a redistribution layer 122 can be provided over the material layer 102 as previously described. Although not shown in FIG. 7, in some embodiments, at least one optical interconnect 402 and/or at least one microfluidic interconnect 504 can also be formed in the thinner material layer 102.

In addition, as shown in FIG. 7, each of the interconnect layers 702A and 702B may also include a redistribution layer 122 that may be used to redistribute the electrical interconnects 302, optical interconnects 402, and fluid interconnects. 504.

After forming the bonded semiconductor structure 700 shown in FIG. 7, the bonded semiconductor structure 700 can be further processed, as described above with respect to the bonded semiconductor structure 320 with reference to FIGS. 2C through 2E, and as previously described with reference to FIG. 3B and 3C are described with respect to the bonded semiconductor structure 420.

Exemplary embodiments of other non-limiting properties of the invention are described below.

Embodiment 1 : A method of forming a bonded semiconductor structure, comprising: providing a substrate structure comprising a relatively thin layer of material on a relatively thick substrate body; forming a plurality of through wafers Connecting the thinner material layer of the first substrate structure; bonding a first processed semiconductor structure to a thinner material layer of the first substrate structure opposite to one side of the thicker substrate body Above the thinner material layer, and electrically coupling at least one of the first processed semiconductor structures to at least one of the through wafer interconnects; The processed semiconductor structure is opposite to one side of the first substrate structure, a layer of transfer material is provided over the first processed semiconductor structure; electrical interconnects, optical interconnects, and fluid interconnects are formed in the layer of transfer material At least one of the same; a second processed semiconductor structure is provided on the side of the transfer material opposite to the first processed semiconductor structure Overlying the layer of transfer material; removing a thicker substrate body of the substrate structure, leaving a thinner layer of material of the substrate structure bonded to the first processed semiconductor structure; and interconnecting the through wafers At least one of the through-wafer interconnects is electrically coupled to one of the conductive members of the other structure.

Embodiment 2: The method of Embodiment 1, wherein providing the substrate structure further comprises temporarily bonding the thinner material layer to the thicker substrate body, and wherein the thicker substrate body of the substrate structure is removed, leaving Bonding the thinner material layer of the substrate structure to the at least one processed semiconductor structure includes separating the thicker substrate body from the thinner material layer.

Embodiment 3: The method of Embodiment 1 or Embodiment 2, further comprising forming at least one redistribution layer on the thinner material on a side of the thinner material layer of the substrate structure opposite to one side of the thicker substrate body After the layer is over, the first processed semiconductor structure is bonded over the thinner material layer of the substrate structure, and wherein the first processed semiconductor structure is bonded over the thinner material layer of the substrate structure The bonding of the first processed semiconductor structure to the redistribution layer is included.

The method of any one of embodiments 1 to 3, wherein the first processed semiconductor structure is bonded to one or more of less than about 400 ° C above the thinner material layer of the substrate structure. The first processed semiconductor structure is bonded over the thinner layer of material of the substrate structure at a temperature.

Embodiment 5: The method of any of embodiments 1 to 4, further comprising selecting the other structure to include a printed circuit board.

Embodiment 6: The method of any of embodiments 1 to 5, further comprising forming the first processed semiconductor structure over the thinner layer of material of the substrate structure to form an additional One penetrates the wafer interconnect to penetrate the first processed semiconductor structure.

The method of any of embodiments 1 to 6, further comprising reusing the thicker substrate body of the substrate structure in a method of forming a bonded semiconductor structure.

The method of any one of embodiments 1 to 7, wherein the first processed semiconductor structure is opposite to the one side of the first substrate structure, the transfer material layer is provided to the first processed semiconductor The structure includes: bonding an additional substrate structure comprising one of the semiconductor materials over the first processed semiconductor structure at a side of the first processed semiconductor structure opposite to the first substrate structure; and forming the transfer A layer of material comprising at least a portion of the semiconductor material of the additional substrate structure.

Embodiment 9: The method of Embodiment 8, further comprising: implanting ions along the ion implantation plane into the additional substrate structure; and bonding the additional substrate structure over the first processed semiconductor structure Thereafter, the additional substrate structure is fractured along the ion implantation plane.

Embodiment 10: The method of embodiment 9, wherein the breaking the additional substrate structure along the ion implantation plane comprises heating the additional substrate structure to one or more temperatures below about 400 ° C to cause the Additional substrate structures break along the ion implantation plane.

The method of any one of embodiments 1 to 10, wherein an electrical interconnection, an optical interconnection, and a fluid interconnection are formed in the layer of the transfer material, at least one of which comprises forming an electrical property in the layer of the transfer material Two or more of interconnections, optical interconnections, and fluid interconnections.

The method of any one of embodiments 1 to 11, wherein an electrical interconnect, an optical interconnect, and a fluid interconnect are formed in the layer of transfer material, at least one of which comprises forming an additional plurality of through wafers Interconnected to penetrate the layer of transfer material.

Embodiment 13: The method of Embodiment 12, further comprising: coupling at least one of the additional through-wafer interconnects electrically coupled to one of the conductive components of the second processed semiconductor structure .

The method of any one of embodiments 1 to 11, wherein an electrical interconnection, an optical interconnection, and a fluid interconnection are formed in the layer of transfer material, at least one of which comprises forming at least one optical interconnection such that Penetrating the layer of transfer material.

Embodiment 15: The method of embodiment 14, wherein the second processed semiconductor structure comprises at least one optical component, and wherein the method further comprises operatively interacting the at least one optical interconnect with the second processed semiconductor structure The at least one optical component is coupled.

The method of any one of embodiments 1 to 11, wherein an electrical interconnection, an optical interconnection, and a fluid interconnection are formed in the layer of transfer material, at least one of which comprises forming at least one in the layer of transfer material Fluid interconnection.

Embodiment 17: A bonded semiconductor structure comprising: a substrate structure comprising: a plurality of through-wafer interconnects penetrating a relatively thin layer of material; and bonding to the layer of material a relatively thick substrate body; wherein the thinner material layer is electrically coupled to the plurality of processed semiconductor structures that penetrate the wafer interconnect; a first processed semiconductor structure opposite one side of the substrate structure, a transfer material layer over the first processed semiconductor structure; and an electrical interconnect, an optical interconnect, and a fluid interconnect in the transfer material layer One.

Embodiment 18: The bonded semiconductor structure of Embodiment 17, wherein the thinner material layer has an average thickness of about one and a half microns (1.5 [mu]m) or less.

Embodiment 19: The bonded semiconductor structure of Embodiment 17 or Embodiment 18, further comprising at least two of an electrical interconnect, an optical interconnect, and a fluid interconnect in the layer of transfer material.

Embodiment 20: The bonded semiconductor structure of any of embodiments 17 to 19, further comprising at least one additional processed layer over the transfer material layer opposite the one of the transferred semiconductor structures Semiconductor structure.

Embodiment 21: The bonded semiconductor structure of Embodiment 20, wherein at least one of the electrical interconnect, the optical interconnect, and the fluid interconnect in the layer of transfer material is operatively coupled to the at least one additional processed semiconductor structure.

The above-described exemplary embodiments are not intended to limit the scope of the invention, as these embodiments are only examples of the embodiments of the invention, and the invention is defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the invention. In fact, various modifications of the invention, such as a substitute for a useful combination of the elements, in addition to those shown and described herein, will be apparent from the description of the specification. Become obvious. In other words, one or more of the features of any one of the exemplary embodiments described herein may be combined with one or more features of another exemplary embodiment described herein as an additional embodiment of the invention. Such modifications and embodiments are also within the scope of the appended claims.

100, 110, 120‧‧‧ substrate structure

102‧‧‧Material layer

103‧‧‧ Bonded surface of semiconductor structure

104‧‧‧Substrate body

112, 162, 172‧‧‧through wafer interconnect

122, 312‧‧‧ redistribution layer

124, 134, 324, 344, 436‧‧‧ conductive parts

126, 138, 316‧‧‧ Dielectric materials

132A, 132B, 132C, 132D, 132E, 132F, 132G, 132H, 1321, 132J, 132K, 132L, 132M, 132N, 132O, 132P, 132Q, 132R‧‧‧ processed semiconductor structures

139, 406‧‧‧ exposed main surface

130, 140, 150, 160, 170, 200, 210, 300, 310, 320, 330, 400, 420, 500, 520, 530, 600 ‧ ‧ bonded semiconductor structure

190‧‧‧Additional substrate structure

192‧‧‧Ion implantation plane

194‧‧‧ main surface

196‧‧‧One part of the additional substrate structure

212‧‧‧Transfer material layer

302, 314‧‧‧ Electrical interconnection

322, 422‧‧‧Processed semiconductor components

332, 432‧‧‧ conductive bumps

342‧‧‧ Electrically coupled to a structure

346, 438‧‧‧ Around dielectric materials

402‧‧‧ Optical Interconnection

404‧‧‧ pores

408‧‧‧ exposed surface

410‧‧‧Polymer precursor material

412‧‧‧Solid polymer materials

424‧‧‧Optoelectronic components

426‧‧‧Band

502‧‧‧ Groove

504‧‧‧ Fluid Interconnect

512‧‧‧Protective materials

522‧‧‧Material layer

524‧‧‧bonding layer

532A, 532B‧‧‧ access opening

534A‧‧‧First fluid pipeline

534B‧‧‧Second fluid pipeline

602A, 602B‧‧‧cross-layer interconnect layer

604A‧‧‧ first floor

604B‧‧‧ second floor

604C‧‧‧ third floor

While the specification has been described in the specification of the invention, and the claims of the invention are intended to be It is easy to understand the advantages of the embodiments of the present invention, 1A to 1K are simplified cross-sectional views of a semiconductor structure depicting the formation of an intermediate structure that can be formed during fabrication of a bonded semiconductor structure in accordance with an exemplary embodiment of the present invention; FIGS. 2A through 2E are semiconductors A simplified cross-sectional view of a structure, in accordance with an exemplary embodiment of the present invention, forming a bonded semiconductor structure from the intermediate structure illustrated in FIG. 1K, wherein an electrical interconnect is formed in a transfer semiconductor layer on the intermediate structure; 3A through 3C are simplified cross-sectional views of a semiconductor structure depicting another bonded semiconductor structure formed from the intermediate structure illustrated in FIG. 1K in accordance with other exemplary embodiments of the present invention, wherein an optical interconnect is formed in the intermediate structure 4A to 4D are simplified cross-sectional views of a semiconductor structure depicting optical interconnections formed in accordance with examples of techniques that may be employed in the methods described in FIGS. 3A through 3C; FIGS. 5A through 5E are semiconductor structures A simplified cross-sectional view depicting another bonded semiconductor structure formed from the intermediate structure illustrated in FIG. 1K in accordance with other exemplary embodiments of the present invention, wherein the flow An interconnect is formed in the transfer semiconductor layer on the intermediate structure; FIG. 6 is a simplified partial cross-sectional perspective view of a bonded semiconductor structure in a three-dimensional space, the bonded semiconductor structure can be formed using an embodiment of the method of the present invention And the bonded semiconductor structure comprises a plurality of processed semiconductor structure layers, wherein the processed semiconductor structure layers have interconnect layers, and the interconnect layers have three different types of interconnects; and FIG. 7 is in three A simplified partial cross-sectional perspective view of another bonded semiconductor structure that is spatially accumulated, the bonded semiconductor structure can be formed using an embodiment of the method of the present invention, and the bonding The semiconductor structure includes a plurality of processed semiconductor structure layers having interconnect layers between the processed semiconductor structure layers, the interconnect layers having two different types of interconnects.

100‧‧‧Material structure

102‧‧‧Material layer

104‧‧‧Substrate body

Claims (21)

A method of forming a bonded semiconductor structure, comprising: providing a substrate structure comprising a relatively thin layer of material on a relatively thick substrate body; forming a plurality of through wafers Through a wafer interconnect that penetrates a relatively thin layer of material of the substrate structure and forms an interconnect layer comprising the relatively thin layer of material and the plurality of through wafer interconnects; a relatively thin layer of material opposite the one side of the relatively thick substrate body, bonding a first processed semiconductor structure over the relatively thin layer of material, and at least one of the first processed semiconductor structures Conductive features are electrically coupled to at least one of the through-wafer interconnects of the through-wafer interconnects; a layer of transfer material is provided on the first processed semiconductor structure opposite one side of the substrate structure Overlying the first processed semiconductor structure; forming at least one of an electrical interconnect, an optical interconnect, and a fluid interconnect in the layer of transfer material; wherein the layer of transfer material is opposite one side of the first processed semiconductor structure, Providing a second processed semiconductor structure over the layer of transfer material; removing a relatively thick substrate body of the substrate structure and leaving a relatively thin layer of material of the substrate structure bonded to the first processed Semiconductor structure; At least one of the through-wafer interconnects of the through-wafer interconnects is electrically coupled to one of the conductive features of the other structure. The method of claim 1, wherein the providing the substrate structure further comprises temporarily bonding the relatively thin layer of material to the relatively thick substrate body, and wherein the relatively thick substrate body of the substrate structure is removed And bonding the relatively thin layer of material of the substrate structure to the at least one processed semiconductor structure comprises separating the relatively thick substrate body from the relatively thinner layer of material. The method of claim 1, further comprising forming at least one redistribution layer over the relatively thinner material layer on a side of the relatively thinner material layer of the substrate structure opposite the one of the relatively thicker substrate body Thereafter, the first processed semiconductor structure is bonded over a relatively thin layer of material of the substrate structure, and wherein the first processed semiconductor structure is bonded over a relatively thin layer of material of the substrate structure The bonding of the first processed semiconductor structure to the redistribution layer is included. The method of claim 1, wherein the first processed semiconductor structure is bonded to the relatively thin layer of material of the substrate structure at one or more temperatures below about 400 ° C, The first processed semiconductor structure is bonded over a relatively thin layer of material of the substrate structure. The method of claim 1, further comprising selecting the other structure to include a printed circuit board. The method of claim 1, further comprising bonding the first processed semiconductor structure over a relatively thin layer of material of the substrate structure to form an additional plurality of through-wafer interconnects Passing through the first processed semiconductor structure. The method of claim 1, further comprising reusing the relatively thick substrate body of the substrate structure in a method of forming a bonded semiconductor structure. The method of claim 1, wherein the first processed semiconductor structure is opposite to one side of the substrate structure, the layer of the transfer material being provided over the first processed semiconductor structure comprises: at the first Processing the semiconductor structure opposite to one side of the substrate structure, bonding an additional substrate structure comprising one of the semiconductor materials over the first processed semiconductor structure; and forming the transfer material layer to include the additional substrate structure At least a portion of the semiconductor material. The method of claim 8, further comprising: implanting ions along the ion implantation plane into the additional substrate structure; and bonding the additional substrate structure over the first processed semiconductor structure The additional substrate structure is fractured along the ion implantation plane. The method of claim 9 wherein the additional substrate structure is fractured along the ion implantation plane comprising heating the additional substrate structure to less than about 400 ° C. One or more temperatures to cause the additional substrate structure to fracture along the ion implantation plane. The method of claim 1, wherein the forming of the electrical interconnect, the optical interconnect, and the fluid interconnect in the layer of transfer material comprises at least one of forming an electrical interconnect, an optical interconnect, and Two or more of the fluid interconnections. The method of claim 1, wherein the forming at least one of the electrical interconnect, the optical interconnect, and the fluid interconnect in the layer of transfer material comprises forming an additional plurality of through-wafer interconnects to penetrate The layer of transfer material. The method of claim 12, further comprising coupling at least one of the additional through-wafer interconnects electrically coupled to one of the second processed semiconductor structures. The method of claim 1, wherein the forming at least one of the electrical interconnect, the optical interconnect, and the fluid interconnect in the layer of transfer material comprises forming at least one optical interconnect to penetrate the layer of transfer material. The method of claim 14, wherein the second processed semiconductor structure comprises at least one optical component, and wherein the method further comprises operatively interacting the at least one optical interconnect with the second processed semiconductor structure At least one optical component is coupled. The method of claim 1, wherein the layer of the transfer material is formed At least one of the electrical interconnect, the optical interconnect, and the fluid interconnect includes forming at least one fluid interconnect in the layer of transfer material. A bonded semiconductor structure comprising: a substrate structure comprising: a plurality of through-wafer interconnects penetrating a relatively thin layer of material; comprising the relatively thin layer of material and the plurality of through-crystals An interconnect layer of a circular interconnect; and a relatively thick one of the substrate bodies bonded to the relatively thinner material layer; wherein the relatively thinner material layer is opposite to one of the relatively thicker substrate bodies, in electrical Upper to be coupled to the plurality of processed semiconductor structures penetrating the wafer interconnect; wherein the first processed semiconductor structure is opposite to one side of the substrate structure, one of the transfer material layers above the first processed semiconductor structure; And at least one of an electrical interconnection, an optical interconnection, and a fluid interconnection in the layer of transfer material. The bonded semiconductor structure of claim 17, wherein the relatively thin material layer has an average thickness of about one and a half micrometers (1.5 μm) or less. The bonded semiconductor structure of claim 17 further comprising at least two of the electrical interconnection, the optical interconnection, and the fluid interconnection in the layer of the transfer material. The bonded semiconductor structure of claim 17, further comprising at least one additional processed semiconductor structure over the transfer material layer opposite the one of the processed semiconductor structures. The bonded semiconductor structure of claim 20, wherein at least one of the electrical interconnect, the optical interconnect, and the fluid interconnect in the layer of transfer material is operatively coupled to the at least one additional processed semiconductor structure.