TWI500015B - Bi-direction circuit, gate driver and testing circuit utilizing the same - Google Patents

Description

Bidirectional selection circuit, gate driver and test circuit using the bidirectional selection circuit

The present invention relates to a gate driver, and more particularly to a gate driver for bidirectional scanning.

The bi-direction circuit is used as a circuit for determining the scanning direction in a shift register. The signal propagation delay and the voltage level of the transmitted signal are very important issues. The shorter the signal transfer delay, the higher the operating frequency of the shift register can be. The voltage level of the transmitted signal is directly related to the noise margin, which is related to the anti-noise capability of the circuit. However, in the thin-film-transistor process (TFT process), since the process limits the type of the transistor, the bidirectional circuit in the TFT process tends to have a long transfer delay and the transmitted signal. The voltage level may not be ideal. How to shorten the transfer delay of the bidirectional circuit in the TFT process and make the voltage level of the transmitted signal more accurate is a problem to be overcome.

In view of the above problems, the present invention proposes a bidirectional selection circuit And a gate driver and test circuit using the bidirectional selection circuit. The disclosed bidirectional circuit uses a parasitic capacitance to push the control terminal voltage of the switch to a voltage level higher than the input signal, thereby ensuring that the switch can completely transmit the input signal to the output of the bidirectional circuit.

A bidirectional selection circuit according to one or more embodiments of the present invention includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. The first switch has a first end, a second end, and a control end, wherein the first end of the first switch and the control end of the first switch are coupled to a first selection end. The second switch has a first end, a second end, and a control end, wherein the first end of the second switch is coupled to the second end of the first switch, and the second end of the second switch is coupled to a reset end, The control end of the two switches is coupled to the second selection end. The third switch has a first end, a second end, and a control end, wherein the first end of the third switch and the control end of the third switch are coupled to the second selection end. The fourth switch has a first end, a second end, and a control end, wherein the first end of the fourth switch is coupled to the second end of the third switch, and the second end of the fourth switch is coupled to the reset end, and the fourth The control end of the switch is coupled to the first selection end. The fifth switch has a first end, a second end, and a control end, wherein the first end of the fifth switch is coupled to the first input end, and the control end of the fifth switch is coupled to the second end of the first switch, the fifth The second end of the switch is coupled to the output end. The sixth switch has a first end, a second end, and a control end, wherein the first end of the sixth switch is coupled to the second input end, and the control end of the sixth switch is coupled to the second end of the third switch, sixth The second end of the switch is coupled to the output end.

In an embodiment of the present invention, an application of the foregoing two-way power is disclosed The gate driver of the circuit, the gate driver includes a plurality of shift registers, and each of the shift registers uses the aforementioned bidirectional circuit.

In another embodiment of the present invention, a test circuit applying the foregoing bidirectional circuit is disclosed, which can be used to test whether the functions of a plurality of shift registers are normal.

The above description of the present invention and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention.

1, 3A, 3B‧‧‧ bidirectional circuit

4, SR ₁ ~ SR _N ‧ ‧ shift register

41‧‧‧Control circuit

5‧‧‧Test circuit

C _35A , C _35B , C _36A , C _36B ‧‧‧ capacitors

IN ₁ , IN ₂ ‧‧‧ input

OUT‧‧‧ output

SW ₁ ~SW ₆ ‧‧‧Switch

SEL ₁ , SEL ₂ ‧‧‧Selection

SCAN ₁ , SCAN ₂ ‧‧‧ control line

RST‧‧‧Reset

V _RST ‧‧‧Reset voltage

V _S1 , V _S2 ‧‧‧Selection signal

V _IN1 , V _IN2 ‧‧‧ input signal

V _C5 , V _C6 ‧‧‧ control voltage

V _OUT ‧‧‧ output signal

V _H ‧‧‧High voltage

V _L ‧‧‧Low voltage

V _BOOST ‧‧‧ON voltage

VTH‧‧‧ threshold voltage

T ₁ ~T ₉ ‧‧‧ time

1 is a schematic diagram of a bidirectional circuit in accordance with an embodiment of the present invention.

2 is a timing diagram of a plurality of voltage waveforms in accordance with an embodiment of the present invention.

3A is a schematic diagram of a bidirectional circuit in accordance with an embodiment of the present invention.

Figure 3B is a schematic diagram of a bidirectional circuit in accordance with an embodiment of the present invention.

4 is a schematic diagram of a shift register circuit in accordance with an embodiment of the present invention.

Figure 5 is a diagram showing a bidirectional circuit applied to a shift register according to an embodiment of the present invention. Circuit diagram of the test circuit.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to further illustrate the aspects of the invention, but not any The views limit the scope of the invention.

In view of the foregoing, the present invention discloses a bidirectional circuit that can be applied to a thin-film-transistor process (TFT process). The disclosed bidirectional circuit can be used in the gate driver and test circuit of the display panel, and the disclosed bidirectional circuit has a shorter propagation delay and a larger noise margin.

Please refer to FIG. 1 , which is a schematic diagram of a bidirectional circuit according to an embodiment of the invention. As shown, a first bidirectional circuit of FIG. 1 comprises a first switch SW _1, a second switch SW _2, the third switch SW _3, the fourth switch SW _4, the fifth switch SW ₅ and the sixth switch SW _6. The six switches are thin film transistor switches, and as shown in Figure 1, the six switches are all N-type transistors. However, in another embodiment, the six switches may also be P-type transistors.

A first terminal of a first switch SW ₁ and the control terminal of the first switch SW ₁ (gate terminal) are coupled to the first selection terminal of the SEL ₁ a bidirectional circuit, and a second terminal of the first switch SW ₁ is coupled to the control terminal of the fifth switch SW _5. The first end of the second switch SW ₂ is coupled to the second end of the first switch SW ₁ and the control end of the fifth switch SW ₅ . The second end of the second switch SW ₂ is coupled to the reset terminal RST, and the control end of the second switch SW ₂ is coupled to the second selection terminal SEL _{2 of the} bidirectional circuit 1 . The first end of the fifth switch SW ₅ is coupled to the first input terminal IN _{1 of the} bidirectional circuit 1 , and the second end of the fifth switch SW ₅ is coupled to the output end OUT of the bidirectional circuit 1 .

The control terminal of the third switch SW ₃ a first end of the third switch SW ₃ are coupled to the second selection terminal of the bidirectional circuit SEL _2, and the second terminal of the third switch SW ₃ is coupled to the sixth switch SW The control end of ₆ . The first end of the fourth switch SW ₄ is coupled to the second end of the third switch SW ₃ and the control end of the sixth switch SW ₆ . The second end of the fourth switch SW ₄ is coupled to the reset terminal RST, and the control end of the fourth switch SW ₄ is coupled to the first selection terminal SEL _{1 of the} bidirectional circuit ₁ . The first end of the sixth switch SW ₆ is coupled to the second input terminal IN _{2 of the} bidirectional circuit 1 , and the second end of the sixth switch SW ₆ is coupled to the output end OUT of the bidirectional circuit 1 .

The first selection terminal SEL _{1 is configured} to receive the first selection signal V _S1 , and the second input terminal SEL _{2 is configured} to receive the second input signal V _S1 , and the first input terminal IN _{1 is configured} to receive the first input signal V _IN1 , and The second input terminal IN _{2 is for} receiving the second input signal V _IN2 , and the reset terminal RST is for receiving the reset voltage V _RST , wherein the reset voltage V _RST is a low voltage V _L in this embodiment. In this embodiment, the control terminal voltage of the fifth switch SW ₅ is the control voltage V _C5 , the control terminal voltage of the sixth switch SW ₆ is the control voltage V _C6 , and the output signal VOUT is output from the output terminal OUT.

Fig. 2 is a timing chart of a plurality of voltage waveforms according to an embodiment of the present invention. Please refer to Figs. 1 and 2 hereinafter. Between the first time point T ₁ and the fifth time point T ₅ , the voltage level of the first selection signal V _S1 is a high voltage V _H , and the voltage level of the second selection signal V _S2 is a low voltage V _L , so Between the first time point T _{1 and the} second time point T ₂ , the first switch SW ₁ increases the voltage level of the control voltage V _C5 , and the voltage level of the control voltage V _C6 is used by the fourth switch SW ₄ pulls down to the reset voltage V _RST , that is, the low voltage V _L , at which time the voltage level of the output signal V _OUT is the low voltage V _L . When the control voltage V _C5 voltage level is pulled up to the high voltage V _H is equal to minus the first threshold voltage VTH ₁ switch SW, the voltage difference between the control terminal of the first out switch SW ₁ is exactly equal to the second end a first switch SW of the threshold voltage _{VTH. 1,} the first no longer out switch SW ₁ is turned on while the control voltage V _C5 threshold voltage VTH is maintained at a high voltage V _H of subtracting the first out switch SW _1. Since both ends of the parasitic capacitance between the control terminal of the fifth switch SW _5, the fifth switch SW so that the voltage difference across the control terminal ₅ will be fixed to a high voltage minus the threshold voltage VTH V _H and V _L of the low voltage Difference.

Wherein, at the second time point T ₂ , the voltage level of the first input signal V _IN1 changes from the low voltage V _L to the high voltage V _H , so that it can be seen that the control voltage V _C5 is started from the second time point T ₂ . The voltage level is raised to the turn-on voltage V _BOOST by the parasitic capacitance between both ends of the fifth switch SW ₅ and the control terminal. At this time, the voltage value of the turn-on voltage V _BOOST can be described by the following equation (1): V _BOOST = 2V _H - V _L - VTH (1) and the potential difference between the turn-on voltage V _BOOST and the high voltage V _H can be expressed as the following equation (2) :V _BOOST -V _H =V _H -V _L -VTH (2) Therefore, assuming that the threshold voltages of the first switch SW ₁ and the fifth switch SW ₅ are both the threshold voltage VTH, as long as the high voltage V _H and the low voltage V _When the potential difference of _L is greater than or equal to twice the threshold voltage VTH, it can be ensured that when the voltage level of the first input signal V _IN1 is the high voltage V _H , the fifth switch SW ₅ can be turned on until the voltage level of the output signal V _OUT is also Pulled high to high voltage V _H as shown in Figure 2. However, in practice, the potential difference between the high voltage V _H and the low voltage V _L is greater than twice the threshold voltage VTH.

At the third time point T ₃ , the voltage level of the first input signal V _IN1 changes from the high voltage V _H to the low voltage V _L , so the voltage level of the output signal V _OUT is pulled to the fifth switch SW ₅ . The voltage level of an input signal V _{IN1 is} the same, that is, the low voltage V _L . Although at the same time, the voltage level of the second input signal V _IN2 changes from the low voltage V _L to the high voltage V _H , since the voltage level of the control voltage V _C6 is pulled to the low voltage by the fourth switch SW ₄ , the sixth switch SW ₆ does not conduct, so the voltage level change of the second input signal V _IN does not affect the voltage level of the output signal V _OUT . More specifically, between the first time point T ₁ and the fifth time point T ₅ , the sixth switch SW ₆ is not turned on, so the voltage level change of the second input signal V _IN2 does not affect the output signal V. The voltage level of _OUT .

At the fourth time point T ₄ , the voltage level of the first input signal V _{IN1 changes} from the low voltage V _L to the high voltage V _H , so the voltage level of the output signal V _OUT is pulled to the first by the fifth switch SW _{5 .} The voltage level of the input signal V _{IN1 is} the same, that is, the high voltage V _H .

At the fifth time point T ₅ , the voltage level of the first selection signal V _S1 changes from the high voltage V _H to the low voltage V _L , and the voltage level of the second selection signal V _S2 changes from the low voltage V _L to the low voltage V _H , Therefore, after the fifth time point T ₅ , the second switch SW ₂ gradually increases the voltage level of the control voltage V _C6 , and the voltage level of the control voltage V _C5 is pulled to the reset voltage V by the second switch SW _{2 . RST} , that is, the low voltage V _L , so the sixth switch SW _{6 is} turned on after the fifth time point T ₅ , and the fifth switch SW ₅ is turned off. And since the voltage levels of the first input signal V _IN1 and the second input signal V _IN2 are changed from the high voltage V _H to the low voltage V _L at the fifth time point, the fifth time point T ₅ starts, and the output signal V _OUT is output. The voltage level is forcibly pulled by the sixth switch SW ₆ to be the same as the second input signal. When the voltage level of the control voltage V _C6 is pulled up to be equal to the high voltage V _H minus the threshold voltage VTH of the third switch SW ₃ (here, the threshold voltages of the six switches are all the same), the third switch SW ₃ the voltage difference between the control terminal and the second terminal of the switch SW is exactly equal to the third threshold voltage VTH _3, and therefore the third switch SW is turned on _{no. 3,} while the control voltage V _C6 was maintained at a high voltage V _H subtracting three switch SW of the threshold voltage VTH _3. Since the parasitic capacitance between the control terminal of the sixth switch SW ₆ and the two ends, the voltage difference across the control terminal of the sixth switch SW ₆ will be fixed to a high voltage by subtracting the threshold voltage VTH V _H and V _L of the low voltage Difference.

Thereafter, at the sixth time point T ₆ , the voltage level of the second input signal V _IN2 changes from the low voltage V _L to the high voltage V _H , so that it can be seen that the control voltage V _C6 starts from the sixth time point T ₆ . The voltage level is pushed to the turn-on voltage V _BOOST by the parasitic capacitance between the both ends of the sixth switch SW ₆ and the control terminal. As described above, as long as the potential difference between the high voltage V _H and the low voltage V _L is greater than or equal to twice the threshold voltage VTH, it can be ensured that when the voltage level of the second input signal V _IN2 is the high voltage V _H , the sixth switch SW ₆ It can be turned on until the voltage level of the output signal V _OUT is also pulled high to the high voltage V _H , as shown in Figure 2.

In the seventh time point T _7, the voltage level of the second input signal V _IN2 of the low voltage V _L becomes a quasi from the high voltage V _H, the output signal V _OUT of the voltage level of the sixth switch SW ₆ is pulled to the first The voltage level of the two input signals V _{IN2 is} the same, that is, the low voltage V _L . Although at the same time, the voltage level of the first input signal V _IN1 changes from the low voltage V _L to the high voltage V _H , since the voltage level of the control voltage V _C5 is pulled to the low voltage by the second switch SW ₄ , the fifth switch SW ₅ does not conduct, so the voltage level change of the first input signal V _IN1 does not affect the voltage level of the output signal V _OUT . More specifically, between the fifth time point T ₅ and the ninth time point T ₉ , the fifth switch SW ₅ is not turned on, so the voltage level change of the first input signal V _IN1 does not affect the output signal V. The voltage level of _OUT .

At the eighth time point T ₈ , the voltage level of the second input signal V _{IN2 changes} from the low voltage V _L to the high voltage V _H , so the voltage level of the output signal V _OUT is pulled to the second by the sixth switch SW _{6 .} The voltage level of the input signal V _{IN2 is} the same, that is, the high voltage V _H .

According to the foregoing embodiment, the control voltage V _C5 and the control voltage V _{C6 of the} present invention can selectively change correspondingly when the first input signal V _IN1 and the second input signal V _IN2 are changed, so that the fifth switch SW ₅ and / Or the sixth switch SW ₆ has a high conduction capability, so the propagation delay is shortened.

In an embodiment of the present invention, please refer to FIGS. 3A and 3B, which are schematic diagrams of a bidirectional circuit according to an embodiment of the present invention. As shown in FIG. 3A, the bidirectional circuit 3A of FIG. 3A further includes a capacitor C _35A and a capacitor C _36A as compared with the bidirectional circuit 1 of FIG. The capacitor C _{35A is} electrically connected between the control end and the second end of the fifth switch SW ₅ , and the capacitor C _{36A is} electrically connected between the control end and the second end of the sixth switch SW ₆ . The fifth switch SW ₅ and the sixth switch SW ₆ of the bidirectional circuit 1 in FIG. 1 are controlled by a parasitic capacitance such that the voltage levels of the first input signal V _IN1 and the second input signal V _IN2 are increased, and the control voltage V is _C5 and the control voltage V _C6 can be raised to the turn-on voltage V _BOOST , however, due to the non-ideal characteristics of the circuit, the control voltage V _C5 and the control voltage V _C6 may gradually decrease due to leakage current, and are no longer maintained at the turn-on voltage V _BOOST . Therefore, the additional increase of the capacitance C _35A and the capacitance C _36A can alleviate the phenomenon that the leakage current causes the control voltage V _C5 and the control voltage V _{C6 to} gradually decrease. Alternatively, as shown in FIG. 3B, the bidirectional circuit 3B may have a capacitor C _35B electrically connected between the control end of the fifth switch SW ₅ and the first end, and a capacitor C _36B electrically connected to the sixth switch SW. The control end of ₆ is between the first end and the first end.

For the embodiment of the above-described bidirectional circuit used in the shift register, please refer to FIG. 4, which is a schematic diagram of a shift register circuit according to an embodiment of the present invention. As shown in FIG. 4, the shift register 4 may include a structure of a bidirectional circuit and includes a control circuit and a switch SW ₇ and a switch SW ₈ . Wherein the control terminal of the switch SW ₇ is electrically coupled to the control circuit 41, a first terminal of the switch SW ₇ is electrically coupled to the clock terminal CLK while the second end is electrically coupled to the output terminal OUT. Since the voltage level of the signal transmitted from the bidirectional circuit to the control circuit 41 can be an accurate high voltage V _H or a low voltage V _L . Therefore, the voltage level pre-stored at the control terminal of the switch SW ₇ can also be an accurate high voltage V _H or a low voltage V _L . When the voltage level of the pulse terminal CLK is raised from the low voltage V _L to the high voltage V _H , the voltage level of the control terminal of the switch SW ₇ is like the control voltage V _C5 or the control voltage V _{C6 in the} bidirectional circuit, and can be increased by the parasitic capacitance to Higher voltage level. Thereby, the voltage of the output terminal OUT of the shift register 4 is changed faster.

In an embodiment of the present invention, please refer to FIG. 5, which is a circuit diagram of a bidirectional circuit applied to a shift register test circuit according to an embodiment of the invention. As shown in FIG. 5, when the shift register is to be tested, the circuit architecture may include a positive scan control line SCAN ₁ , an inverse scan control line SCAN ₂ , shift register SR ₁ to SR _N and a test circuit 5, wherein The circuit configuration of the test circuit 5 is essentially the bidirectional circuit 1 of the present invention. The first input terminal V _{IN1 of the} test circuit 5 is electrically coupled to the output terminal of the shift register SR _N , and the second input terminal V _{IN2 of the} test circuit 5 is electrically coupled to the shift register SR _{1 .} The first selection terminal SEL _{1 of the} test circuit 5 is electrically coupled to the positive scan control line SCAN ₁ and the second selection terminal SEL _{2 is} electrically coupled to the flyback control line SCAN ₂ . Therefore, when the voltage level of the positive scan control line SCAN ₁ is a high voltage and the voltage level of the reverse scan control line SCAN ₂ is a low voltage, the output terminal OUT of the test circuit 5 can correctly output the shift temporarily after a period of time. The output voltage level of the register SR _N is, and when the voltage level of the positive scan control line SCAN ₁ is a low voltage and the voltage level of the anti-sweep control line SCAN ₂ is a high voltage, the test circuit 5 is tested after a period of time. the output terminal OUT can be correctly output voltage at the output shift register SR ₁ bit quasi. Thereby, it can be verified whether the signal transfer function of the shift registers SR ₁ to SR _N is normal. For example, if the voltage level of the positive scan control line SCAN ₁ is a high voltage and the voltage level of the reverse scan control line SCAN ₂ is a low voltage, when the input terminal of the shift register SR ₁ receives a square wave If, after a period of time, the waveform of the signal output by the output terminal OUT of the test circuit 5 (for example, the voltage level of the signal and the time difference between the positive edge and the negative edge of the signal) is correct, it represents the shift register SR ₁ The signal transmission function to SR _N is normal, otherwise the signal transmission function representing at least one of the shift registers SR ₁ to SR _N is abnormal.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1‧‧‧Bidirectional circuit

IN ₁ , IN ₂ ‧‧‧ input

OUT‧‧‧ output

SW ₁ ~SW ₆ ‧‧‧Switch

SEL ₁ , SEL ₂ ‧‧‧Selection

RST‧‧‧Reset

V _RST ‧‧‧Reset voltage

V _S1 , V _S2 ‧‧‧Selection signal

V _IN1 , V _IN2 ‧‧‧ input signal

V _C5 , V _C6 ‧‧‧ control voltage

V _OUT ‧‧‧ output signal

Claims (8)

A bidirectional selection circuit includes: a first switch having a first end, a second end, and a control end, wherein the first end of the first switch is coupled to the control end of the first switch Connected to a first selection end; a second switch having a first end, a second end, and a control end, wherein the first end of the second switch is coupled to the second end of the first switch The second end of the second switch is coupled to a reset end, the control end of the second switch is coupled to a second select end, and the third switch has a first end, a second end, and a a control terminal, wherein the first end of the third switch and the control end of the third switch are coupled to the second selection end; a fourth switch has a first end, a second end, and a control end, The first end of the fourth switch is coupled to the second end of the third switch, the second end of the fourth switch is coupled to the reset end, and the control end of the fourth switch is coupled to the first end a fifth switch having a first end, a second end, and a control end, wherein the first end of the fifth switch is coupled a first input end, the control end of the fifth switch is coupled to the second end of the first switch, the second end of the fifth switch is coupled to an output end, and a sixth switch has a first One end, a second end, and a control end, wherein the first end of the sixth switch is coupled to a second input end, and the sixth switch is controlled The terminal is coupled to the second end of the third switch, and the second end of the sixth switch is coupled to the output end. The bidirectional selection circuit of claim 1, wherein the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are all the same type of transistors, and the weight The terminal is coupled to a low voltage. The bidirectional selection circuit of claim 1, wherein when the first selection end is coupled to a high voltage, the second selection end is coupled to a low voltage for outputting the voltage level of the first selection end . The bidirectional selection circuit of claim 3, wherein when the first selection terminal is coupled to the low voltage, the second selection terminal is coupled to the high voltage for outputting the voltage level of the second selection terminal . The bidirectional selection circuit of claim 1, further comprising: a first capacitor, the first end of the first capacitor is coupled to the second end of the first switch, and the second end of the first capacitor is coupled And a second capacitor, the first end of the second capacitor is coupled to the second end of the third switch, and the second end of the second capacitor is coupled to the output end. The bidirectional selection circuit of claim 1, further comprising: a first capacitor, the first end of the first capacitor is coupled to the second end of the first switch, and the second end of the first capacitor is coupled a first end of the fifth switch; and a second capacitor, the first end of the second capacitor is coupled to the second end of the third switch, and the second end of the second capacitor is coupled to the second end The first end of the six switch. A gate driver includes: a plurality of shift register units, wherein each of the shift register units comprises a bidirectional selection circuit, the bidirectional selection circuit comprising: a first switch having a first end and a second And a control end, wherein the first end of the first switch and the control end of the first switch are coupled to a first selection end; and the second switch has a first end, a second end, and a control terminal, wherein the first end of the second switch is coupled to the second end of the first switch, the second end of the second switch is coupled to a reset end, and the control end of the second switch is coupled a second switch having a first end, a second end, and a control end, wherein the first end of the third switch and the control end of the third switch are coupled to the first end The second switch has a first end, a second end, and a control end, wherein the first end of the fourth switch is coupled to the second end of the third switch, the fourth switch The second end is coupled to the reset end, and the control end of the fourth switch is coupled to the first selection end; a first end, a second end, and a control end, wherein the first end of the fifth switch is coupled to a first input end, and the control end of the fifth switch is coupled to the first switch a second end, the second end of the fifth switch is coupled to an output end, and a sixth switch having a first end, a second end, and a control end, The first end of the sixth switch is coupled to the second input end, the control end of the sixth switch is coupled to the second end of the third switch, and the second end of the sixth switch is coupled to the output The first input end is coupled to a first input signal, and the second input end is coupled to a second input signal for a first voltage level coupled to the first select end The second voltage level coupled to the second selection terminal selectively outputs the first input signal or the second input signal as a gate signal. A test circuit for testing a gate driver, the test circuit comprising: a first switch having a first end, a second end, and a control end, wherein the first end of the first switch and the first The control end of the switch is coupled to the first select terminal; the second switch has a first end, a second end, and a control end, wherein the first end of the second switch is coupled to the first end The second end of the switch is coupled to a reset end, the control end of the second switch is coupled to a second select end, and the third switch has a first end and a a second end and a control end, wherein the first end of the third switch and the control end of the third switch are coupled to the second selection end; and the fourth switch has a first end and a second end And a control terminal, wherein the first end of the fourth switch is coupled to the second end of the third switch, the second end of the fourth switch is coupled to the reset end, and the control end of the fourth switch Coupling to the first selection end; a fifth switch having a first end, a second end, and a control end, wherein the fifth The first end of the switch is coupled to a first end, the control end of the fifth switch is coupled to the second end of the first switch, and the second end of the fifth switch is coupled to an output end; a sixth switch having a first end, a second end, and a control end, wherein the sixth switch The first end is coupled to a second input end, the control end of the sixth switch is coupled to the second end of the third switch, and the second end of the sixth switch is coupled to the output end; wherein the gate The pole driver is configured to sequentially output an N-level gate signal, the first input terminal is configured to receive a first-stage gate signal of the gate driver, and the second input terminal is configured to receive the N-th gate of the gate driver a first gate terminal for receiving a first gate when the gate driver sequentially outputs the gate signals from the first gate signal to the Nth gate signal in sequence a voltage, the second selection terminal is configured to receive a second voltage, and when the gate driver sequentially outputs the gate signals from the Nth gate signal to the first gate signal, The first selection end is configured to receive the second voltage, and the second selection end is configured to receive the first voltage.