TWI496261B - Electical device package structure and method of fabricating the same - Google Patents

Electical device package structure and method of fabricating the same Download PDF

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Publication number
TWI496261B
TWI496261B TW101124254A TW101124254A TWI496261B TW I496261 B TWI496261 B TW I496261B TW 101124254 A TW101124254 A TW 101124254A TW 101124254 A TW101124254 A TW 101124254A TW I496261 B TWI496261 B TW I496261B
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TW
Taiwan
Prior art keywords
conductive
pattern
electronic component
layer
conductive pattern
Prior art date
Application number
TW101124254A
Other languages
Chinese (zh)
Other versions
TW201403772A (en
Inventor
Tzyy Jang Tseng
Shu Sheng Chiang
Tsung Yuan Chen
Shih Lian Cheng
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW101124254A priority Critical patent/TWI496261B/en
Publication of TW201403772A publication Critical patent/TW201403772A/en
Application granted granted Critical
Publication of TWI496261B publication Critical patent/TWI496261B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Description

Electronic component packaging structure and manufacturing method thereof

The present invention relates to an element package structure and a method of fabricating the same, and more particularly to an electronic component package structure and a method of fabricating the same.

In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and functional electronic products continue to evolve. In these electronic products, a circuit board on which electronic components are mounted is usually disposed. As electronic products continue to be designed toward light, thin, short, and small trends, the thickness of circuit boards is becoming thinner.

However, in the prior art, the manufacturer will separately fabricate electronic components and circuit boards for carrying the electronic components. Thereafter, the electronic component is packaged on the wiring board to form an electronic component package structure. This method is not only time-consuming, but also the overall thickness of the electronic component package structure is not easily reduced. In view of the above, how to develop a method for manufacturing a thin electronic component package structure is one of the goals that the developer desires to achieve.

The present invention provides an electronic component packaging method which can produce an electronic component package structure having a small overall thickness.

The present invention provides an electronic component package structure having a small overall thickness.

An embodiment of the present invention provides an electronic component packaging method including the steps of: providing a circuit substrate, the circuit substrate including the substrate, and the configuration a first conductive pattern on the substrate, the electronic component is disposed on the circuit substrate, wherein the electronic component has at least one electrode, and a dielectric layer is formed on the circuit substrate to cover the electronic component, the electrode, and the first conductive pattern, wherein the first The conductive pattern forms a first recess pattern on the dielectric layer. The dielectric layer is patterned to form a via extending to the first conductive pattern and a second recess pattern that communicates through the via and exposes the electrode. A conductive material is filled in the through hole and the second recess pattern to form a conductive via in the via hole and to form a second conductive pattern in the second recess pattern, and to remove the substrate. Forming a first solder resist layer and a second solder resist layer on the first conductive pattern and the second conductive pattern, respectively, wherein the first solder resist layer exposes a portion of the first conductive pattern, and the second solder resist layer exposes a portion The second conductive pattern.

An embodiment of the present invention provides an electronic component package structure including a dielectric layer, an electronic component, a first conductive pattern, a second conductive pattern, a conductive via, a first solder resist layer, and a second solder resist layer. The dielectric layer has a first surface, a second surface opposite to the first surface, a first recess pattern disposed on the first surface and recessed on the first surface, and disposed on the second surface and recessed on the second surface a second recess pattern and at least a consistent aperture extending from the first recess pattern to the second recess pattern. The electronic component is buried in the dielectric layer and has at least one electrode that is exposed to the second recessed pattern. The first conductive pattern fills the first recess pattern, the second conductive pattern fills the second recess pattern to be connected to the electrodes of the electronic component, and the conductive via fills the through hole to connect the first conductive pattern and the second conductive pattern. The first solder resist layer is disposed on the first surface of the dielectric layer and the first conductive pattern, and exposes a portion of the first conductive pattern. The second solder resist layer is disposed on the second surface of the dielectric layer and the second conductive pattern, and exposes a portion of the second conductive pattern.

Based on the above, in the present invention, the electronic component can be buried in the dielectric layer to greatly reduce the overall thickness of the electronic component package structure. In addition, the overall thickness of the electronic component package structure can be further reduced by filling a conductive pattern in the recess pattern of the dielectric layer to form a conductive pattern.

The above described features and advantages of the present invention will be more apparent from the following description.

Electronic component packaging method

1A to 1K are schematic cross-sectional views showing an electronic component packaging method according to an embodiment of the present invention. Referring first to FIG. 1A and FIG. 1B , first, a circuit substrate 110 (shown in FIG. 1B ) is provided. The circuit substrate 110 includes a substrate 112 and a first conductive pattern 114 disposed on the substrate 112 . In the present embodiment, the substrate 112 includes a substrate 112a and a barrier layer 112b covering the opposite surfaces of the substrate 112a. The material of the substrate 112a is, for example, a metal or a polymer, and the material of the barrier layer 112b is, for example, a metal (including aluminum or nickel) or a polymer, but the invention is not limited thereto.

In the present embodiment, the method of providing the wiring substrate 110 includes the following steps. First, as shown in FIG. 1A, a substrate 112 and a first conductive layer 116 disposed on the substrate 112 are provided. Next, as shown in FIG. 1B, the first conductive layer 116 is patterned to form a plating seed layer 118 and a first conductive pattern 114 on the plating seed layer 118. Further, in the present embodiment, the step of patterning the first conductive layer 116 to form the first conductive pattern 114 includes performing a semi-additive process. This embodiment The material of the plating seed layer 118 and the first conductive pattern 114 may be the same, and the material of the plating seed layer 118 and the first conductive pattern 114 is, for example, copper.

However, the method of providing a circuit substrate of the present invention is not limited to the above. 2A and 2B illustrate a method of providing a circuit substrate according to another embodiment of the present invention. Referring to FIG. 2A and FIG. 2B , first, a circuit substrate 110A (shown in FIG. 2B ) is provided. The circuit substrate 110 includes a substrate 112 and a first conductive pattern 114 disposed on the substrate 112 . In particular, the first conductive pattern 114 exposes a portion of the substrate 112. In detail, as shown in FIG. 2A, the substrate 112 and the first conductive layer 116 disposed on the substrate 112 may be provided first. Next, as shown in FIG. 2B, the first conductive layer 116 is patterned to form the first conductive pattern 114. In this embodiment, the step of patterning the first conductive layer 116 to form the first conductive pattern 114 includes performing a subtractive process. In short, in other embodiments, the plating seed layer 118 may not be formed to form the first conductive pattern 114. In this way, in the electronic component packaging method, the step of removing the plating seed layer 118 (FIG. 1H) can be omitted, and the electronic component packaging method is simpler. In addition, it should be noted that the circuit substrate provided by the method shown in FIG. 2A and FIG. 2B is also applicable to the following process steps (as shown in FIG. 1C to FIG. 1G and FIG. 1J and FIG. 1K), thereby forming an electronic component package structure. . Those in the field who have the usual knowledge can infer, and therefore will not be detailed one by one in subsequent paragraphs.

Referring to FIG. 1C, the electronic component 120 is then disposed on the circuit substrate 110. The electronic component 120 has at least one electrode 122. In the embodiment, in the step of disposing the electronic component 120 on the circuit substrate 110, the electronic component 120 may be disposed on the plating seed layer 118. Please refer to Figure 1D, Next, a dielectric layer 130 is formed on the circuit substrate 110 to cover the electronic component 120, the electrode 122, and the first conductive pattern 114. The first conductive pattern 114 forms a first recess pattern 132 on the dielectric layer 130.

In the embodiment, the dielectric layer 130 can cover the electronic component 120 and the first conductive pattern 114 in a comprehensive manner. One of the purposes of forming the dielectric layer 130 on the circuit substrate 110 is to fix the electronic component 120 on the circuit substrate 110. In the present embodiment, the material of the dielectric layer 130 is, for example, a high molecular polymer.

Referring to FIG. 1E, the dielectric layer 130 is patterned to form a through hole 134 extending to the first conductive pattern 114 and a second recess pattern 136 that communicates through the hole 134 and exposes the electrode 122. In this embodiment, the second recess pattern 136 may have a first recess 136a and two second recesses 136b on opposite sides of the first recess 136a, and the depth of any of the second recesses 136b is greater than the depth of the first recess 136a. . In the present embodiment, the step of patterning the dielectric layer 130 includes irradiating a laser beam 130 (not shown) to form the through hole 134 and the second recess pattern 136. Further, since the through holes 134 and the second recess patterns 136 are different in degree of depression, in the embodiment, the laser beam can be irradiated to the medium through a gray scale mask (not shown). The electrical layer 130 is formed to form a through hole 134 and a second recess pattern 136. For example, the gray scale reticle may have a first light transmission area with high transmittance, a second light transmission area with medium transmittance, and a third light transmission area with low transmittance, and part of the laser beam passes through After the first light-transmissive region having high transmittance, a through-hole 134 having a deep recessed depth may be formed in the dielectric layer 130, and a portion of the laser beam passes through the second light-transmitting region having a medium transmittance. A second recess 136b having a second recessed depth is formed in the dielectric layer 130, and a portion of the laser beam is formed. The first recess 136a having a shallow degree of depression may be formed in the dielectric layer 130 by the third light-transmissive region having low transmittance.

Referring to FIG. 1F and FIG. 1G, the conductive material 140 is filled in the through hole 134 and the second recess pattern 136 to form the conductive via 142 in the through hole 134 and form the second in the second recess pattern 136. Conductive pattern 144 (shown in Figure 1G). In detail, as shown in FIG. 1F, the second conductive layer 140a may be formed on the second recess pattern 136, wherein the second conductive layer 140a extends into the through hole 134 and the second recess pattern 136, and the second conductive layer The 140a comprehensively covers the dielectric layer 130. In the present embodiment, the second conductive layer 140a may be formed on the second recess pattern 136 by a plating process. However, the invention is not limited thereto. Next, as shown in FIG. 1G, a portion of the second conductive layer 140a is removed leaving a conductive via 142 filled in the via 136 and a second conductive pattern 144 filled in the second recess pattern 136.

Referring to FIG. 1G and FIG. 1H, the substrate 112 is removed. As shown in FIG. 1H, in the present embodiment, after the substrate 112 is removed, the plating seed layer 118 can be further removed. In the present embodiment, the plating seed layer 118 can be removed using an etching process. Referring to FIG. 1J , the first solder resist layer 152 and the second solder resist layer 154 are respectively formed on the first conductive pattern 114 and the second conductive pattern 144 . The first solder resist layer 152 exposes a portion of the first conductive pattern 114. The second solder resist layer 154 exposes a portion of the second conductive pattern 144. In the embodiment, the second solder resist layer 154 may expose a portion of the second conductive pattern 144 connected to the conductive via 142.

Referring to FIG. 1K, next, a protective layer 160 is formed, wherein a portion of the first conductive pattern 114 exposed by the first solder resist layer 152 and the second solder resist layer are formed. A portion of the second conductive pattern 114 exposed by the 154 forms a plurality of pads P, and the protective layer 160 covers at least one of the pads P. In this embodiment, the material of the protective layer 160 is, for example, gold. Then, a solder ball 170 is formed in which the solder ball 170 is connected to at least one pad P. Thus, the electronic component package structure 100 of the present embodiment is completed.

Electronic component package structure

Referring to FIG. 1K , the electronic component package structure 100 of the present embodiment includes a dielectric layer 130 , an electronic component 120 , a first conductive pattern 114 , a second conductive pattern 144 , a conductive via 142 , a first solder resist layer 152 , and a second Solder mask layer 154.

The dielectric layer 130 has a first surface 130a, a second surface 130b opposite to the first surface 130a, a first recess pattern 132 disposed on the first surface 130a and recessed on the first surface 130a, and disposed on the second surface 130b. And at least one second recess pattern 136 recessed in the second surface 130b and at least the consistent hole 134 extending from the first recess pattern 132 to the second recess pattern 136. The electronic component 120 is buried in the dielectric layer 130 and has at least one electrode 122. The electrode 122 is exposed to the second recess pattern 136.

The first conductive pattern 114 is filled in the first recess pattern 132. The second conductive pattern 144 is filled in the second recess pattern 136 to be connected to the electrode 122 of the electronic component 120. In the present embodiment, the first conductive pattern 114 is substantially aligned with the first surface 130a, and the second conductive pattern 144 is substantially aligned with the second surface 130b. It should be noted that, in this embodiment, the second recess pattern 136 may have a first recess 136a and a second recess 136a opposite to the second The second second recess 136b of the side, and the depth of any of the second recesses 136b is greater than the depth of the first recess 136a. A portion of the second conductive pattern 144 filled in the second recess 136b may be shielded by a portion of the second conductive pattern 144 filled in the first recess 136a. Therefore, by the shielding effect of the portion of the second conductive pattern 144 filled in the first recess 136a, the probability that the electrical signal transmitted in the portion of the second conductive pattern 144 filled in the second recess 136b is disturbed by external noise can be greatly reduced. .

The conductive via 142 is filled in the via 134 to connect the first conductive pattern 114 and the second conductive pattern 144. The first solder resist layer 152 is disposed on the first surface 130a of the dielectric layer 130 and the first conductive pattern 114, and exposes a portion of the first conductive pattern 114. The second solder resist layer 154 is disposed on the second surface 130b of the dielectric layer 130 and the second conductive pattern 144, and exposes a portion of the second conductive pattern 144. In the present embodiment, a portion of the second conductive pattern 114 exposed by the second solder resist layer 154 is connected to the conductive via 142.

The electronic component package structure 100 of the present embodiment may further include a protective layer 160. A portion of the first conductive pattern 114 exposed by the first solder resist layer 152 and a portion of the second conductive pattern 144 exposed by the second solder resist layer 154 form a plurality of pads P. The protective layer 160 covers at least one pad P. The electronic component package structure 100 of the present embodiment may optionally include a solder ball 170. The solder 170 ball connects at least one pad P.

It is to be noted that, in the electronic component package structure 100 of the present embodiment, since the first conductive pattern 114, the second conductive pattern 144, and the electronic component 120 are buried in the dielectric layer 130, the electronic component package structure 100 The overall thickness can be greatly reduced, resulting in the use of electronic components The electronic device of the structure 100 can have the advantages of being thin and thin in appearance.

In summary, in the present invention, the electronic component can be buried in the dielectric layer to greatly reduce the overall thickness of the electronic component package structure. In addition, the overall thickness of the electronic component package structure can be further reduced by filling a conductive pattern in the recess pattern of the dielectric layer to form a conductive pattern.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Electronic component packaging structure

110‧‧‧Line substrate

112‧‧‧Base

112a‧‧‧Substrate

112b‧‧‧Barrier layer

114‧‧‧First conductive pattern

116‧‧‧First conductive layer

118‧‧‧Electroplating seed layer

120‧‧‧Electronic components

122‧‧‧ electrodes

130‧‧‧Dielectric layer

130a‧‧‧ first surface

130b‧‧‧second surface

132‧‧‧First recessed pattern

134‧‧‧through holes

136‧‧‧second recessed pattern

136a‧‧‧first depression

136b‧‧‧second depression

140‧‧‧Electrical materials

140a‧‧‧Second conductive layer

142‧‧‧ conductive through holes

144‧‧‧Second conductive pattern

152‧‧‧First solder mask

154‧‧‧Second solder mask

160‧‧‧Protective layer

170‧‧‧ solder balls

1A to 1K are schematic cross-sectional views showing an electronic component packaging method according to an embodiment of the present invention.

2A and 2B illustrate a method of providing a circuit substrate according to another embodiment of the present invention.

100‧‧‧Electronic component packaging structure

114‧‧‧First conductive pattern

120‧‧‧Electronic components

122‧‧‧ electrodes

130‧‧‧Dielectric layer

130a‧‧‧ first surface

130b‧‧‧second surface

132‧‧‧First recessed pattern

134‧‧‧through holes

136‧‧‧second recessed pattern

136a‧‧‧first depression

136b‧‧‧second depression

140‧‧‧Electrical materials

142‧‧‧ conductive through holes

144‧‧‧Second conductive pattern

152‧‧‧First solder mask

154‧‧‧Second solder mask

160‧‧‧Protective layer

170‧‧‧ solder balls

Claims (6)

  1. An electronic component packaging method includes: providing a circuit substrate, the circuit substrate comprising a substrate and a first conductive pattern disposed on the substrate; and an electronic component disposed on the circuit substrate, the electronic component having at least one electrode Forming a dielectric layer on the circuit substrate to cover the electronic component, the electrode, and the first conductive pattern, wherein the first conductive pattern forms a first recess pattern on the dielectric layer; patterning the dielectric layer An electric layer to form a uniform hole extending to the first conductive pattern and a second recess pattern connecting the through hole and exposing the electrode; after forming the through hole and the second recess pattern, filling the conductive material with In the through hole and the second recess pattern, a conductive via is formed in the through hole and a second conductive pattern is formed in the second recess pattern; the substrate is removed; and a first solder resist layer is removed And a second solder resist layer is formed on the first conductive pattern and the second conductive pattern, wherein the first solder resist layer exposes a portion of the first conductive pattern, and the second solder resist The second conductive pattern portion is exposed.
  2. The electronic component packaging method of claim 1, wherein the method of providing the circuit substrate comprises: providing the substrate and a first conductive layer disposed on the substrate; and patterning the first conductive layer to Forming a plating seed layer and positioning The first conductive pattern on the seed layer is electroplated.
  3. The electronic component packaging method of claim 1, wherein in the step of forming the dielectric layer, the dielectric layer is formed on the circuit substrate to comprehensively cover the electronic component and the first conductive pattern.
  4. The electronic component packaging method of claim 1, wherein the second recess pattern has a first recess and two second recesses on opposite sides of the first recess, and any of the second recesses The depth is greater than the depth of the first recess.
  5. The electronic component packaging method of claim 1, wherein the step of filling the conductive material in the through hole and the second recess pattern comprises: forming a second conductive layer on the second recess pattern, The second conductive layer extends into the through hole and the second recess pattern and comprehensively covers the dielectric layer; removing part of the second conductive layer to leave the conductive via filled in the through hole and The second conductive pattern is filled in the second recess pattern.
  6. The electronic component packaging method of claim 1, wherein the method of providing the circuit substrate comprises: providing the substrate and a first conductive layer disposed on the substrate; and patterning the first conductive layer to The first conductive pattern is formed, wherein the first conductive pattern exposes a portion of the substrate.
TW101124254A 2012-07-05 2012-07-05 Electical device package structure and method of fabricating the same TWI496261B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW101124254A TWI496261B (en) 2012-07-05 2012-07-05 Electical device package structure and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101124254A TWI496261B (en) 2012-07-05 2012-07-05 Electical device package structure and method of fabricating the same

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TW201403772A TW201403772A (en) 2014-01-16
TWI496261B true TWI496261B (en) 2015-08-11

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI577248B (en) * 2016-07-19 2017-04-01 欣興電子股份有限公司 Circuit board and method of manufacturing the carrier

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100314352A1 (en) * 2009-06-12 2010-12-16 Unimicron Technology Corp. Fabricating method of embedded package structure
US8097943B2 (en) * 2007-12-06 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming wafer level ground plane and power ring

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8097943B2 (en) * 2007-12-06 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming wafer level ground plane and power ring
US20100314352A1 (en) * 2009-06-12 2010-12-16 Unimicron Technology Corp. Fabricating method of embedded package structure

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