TWI492364B - 半導體裝置、製造半導體裝置的方法及電子裝置 - Google Patents

半導體裝置、製造半導體裝置的方法及電子裝置 Download PDF

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TWI492364B
TWI492364B TW100146811A TW100146811A TWI492364B TW I492364 B TWI492364 B TW I492364B TW 100146811 A TW100146811 A TW 100146811A TW 100146811 A TW100146811 A TW 100146811A TW I492364 B TWI492364 B TW I492364B
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Taiwan
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electrode
semiconductor
semiconductor element
hole
semiconductor device
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TW100146811A
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English (en)
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TW201238030A (en
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Toshiya Akamatsu
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Fujitsu Ltd
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Description

半導體裝置、製造半導體裝置的方法及電子裝置 發明領域
於此中所討論的實施例是有關於半導體裝置、製造半導體裝置的方法、及使用半導體裝置的電子裝置。
 發明背景
覆晶晶片連接是為一種把半導體元件(半導體晶片)連接到電路板的方法。在覆晶晶片連接中，例如，像是錫凸塊般的突起電極(連接端子)是形成在半導體元件與電路板中之任一者或兩者上俾可利用該等突起電極把該等半導體元件與該電路板連接。近期，如此的覆晶晶片連接已應用到具有一種一晶片是堆疊在另一晶片上且是連接到該另一晶片之晶片在晶片上(chip-on-chip)結構的半導體裝置。
就一具有該晶片在晶片上結構的半導體裝置而言，一具有連接端子的晶片可以被覆晶晶片連接到另一具有導通型貫孔(feedthrough vias)的晶片以致於該等連接端子是連接到該等導通型貫孔(見，例如，日本早期公開專利公告第2007-180529號案)。
在用於把一半導體元件之突起電極連接到一電路板之突起電極或者像一半導體元件般之電子元件之突起電極的覆晶晶片連接中，該等突起電極的位移是會發生，其導致像是未連接狀態與短路般的連接故障。例如，如此的連接故障會由於在半導體元件與連接該半導體元件之電子元件之間的橫向位移，即，該半導體元件與該電子元件中之一者之突起電極朝另一元件之突起電極之旁邊的位移，以及在該半導體元件與該電子元件之間之在與該等元件之表面平行之方向上的轉動位移而發生。
 發明概要
根據本發明之一特徵，一種半導體裝置包括一具有一第一突起電極的第一半導體元件、一具有一第二突起電極的電子元件、及一置於該第一半導體元件與該電子元件之間的基板。該基板具有一第一貫孔，而且該第一突起電極與該第二突起電極是在該第一貫孔內部連接在一起。
本發明之目的和優點將會藉著在申請專利範圍中具體指出的元件和組合來實現與達成。
要了解的是前面的大致描述與後面的詳細描述皆是為範例與說明而並非本發明的限制。
圖式簡單說明
第1圖描繪一半導體裝置的範例結構；第2A至2C圖描繪第一實施例的第一範例半導體裝置；第3圖描繪一突起電極及其附近的範例結構；第4A和4B圖描繪無中間半導體元件被使用的第一情況；第5圖描繪無中間半導體元件被使用的第二情況；第6A和6B圖描繪無中間半導體元件被使用的第三情況；第7圖描繪該第一實施例的第二範例半導體裝置；第8圖描繪該第一實施例的第三範例半導體裝置；第9圖描繪一第一電子裝置的範例結構；第10圖描繪一第二電子裝置的範例結構；第11A和11B圖描繪第二實施例的範例半導體裝置；第12圖描繪第三實施例的第一範例半導體裝置；第13圖描繪該第三實施例的第二範例半導體裝置；第14圖描繪該第三實施例之半導體裝置的範例結構；第15A至15D圖描繪一種形成該第三實施例之半導體裝置的範例方法；第16A至16C圖描繪該在第15A至15D圖中所示之形成該第三實施例之半導體裝置之範例方法的連續步驟；第17A和17B圖描繪第四實施例的範例半導體裝置；第18圖描繪該第四實施例之半導體裝置的範例結構；第19A至19C圖描繪一具有貫孔之範例半導體元件的第一形成步驟；第20A至20C圖描繪該具有貫孔之範例半導體元件的第二形成步驟；第21A至21C圖描繪該具有貫孔之範例半導體元件的第三形成步驟；第22A至22C圖描繪另一具有貫孔之範例半導體元件的第一形成步驟；第23A至23C圖描繪該具有貫孔之另一範例半導體元件的第二形成步驟；第24A至24C圖描繪該具有貫孔之另一範例半導體元件的第三形成步驟；第25A至25C圖描繪該具有貫孔之另一範例半導體元件的第四形成步驟；第26A至26C圖描繪該具有貫孔之另一範例半導體元件的第五形成步驟；第27A至27C圖描繪該具有貫孔之另一範例半導體元件的第六形成步驟；第28A至28C圖描繪一具有貫孔與凹坑之範例半導體元件的第一形成步驟；第29A至29C圖描繪該具有貫孔與凹坑之範例半導體元件的第二形成步驟；第30A至30C圖描繪該具有貫孔與凹坑之範例半導體元件的第三形成步驟；第31A至31C圖描繪該具有貫孔與凹坑之範例半導體元件的第四形成步驟；第32A至32C圖描繪該具有貫孔與凹坑之範例半導體元件的第五形成步驟；第33A和33B圖描繪一第一變化；第34圖描繪一第二變化；第35A和35B圖描繪一第三變化；第36A至36C圖描繪一第四變化；及第37A和37B圖描繪一第五變化。
 較佳實施例之詳細說明
本發明的實施例將會配合該等附圖在下面作說明，其中，相同的標號從頭到尾標示相同的元件。
第1圖描繪一半導體裝置的範例結構。第1圖是為該半導體裝置之主要部份的示意橫截面圖。
在第1圖中所示的半導體裝置1包括一半導體元件2、一電子元件3、和一基板4。
該半導體元件2是為，例如，一半導體晶片，而且在其之表面中之至少一者上具有一突起電極2a。該電子元件3是為，例如，一半導體元件(半導體晶片)或者一電路板，而且在其之表面中之至少一者上具有一突起電極3a。
該基板4是為一平板狀元件，而且是由，例如，一半導體元件、一電路板、一樹脂基板、或一陶瓷基板形成。該基板4在其之預定位置處具有一貫孔4a，而且該貫孔4a是足夠大供該等突起電極2a和3a裝配至該貫孔4a內。
該半導體元件2的突起電極2a和該電子元件3的突起電極3a是藉著像是錫般的連接部份5在該基板4的貫孔4a內部連接在一起。
在基板4之貫孔4a內部之該等相對突起電極2a與3a之間的連接減少在該半導體裝置1中突起電極2a與3a相對彼此之橫向位移的風險。即使當其他電極是形成在該等突起電極2a和3a附近時，在貫孔4a內部之該等相對突起電極2a與3a之間的連接也減少在該等突起電極2a與3a與該等其他電極之間之短路的風險。
由於在半導體元件2與電子元件3之間之橫向位移與短路的風險是如上所述被降低，在該半導體裝置1中之該半導體元件2與該電子元件3之間之連接的可靠度是被改進。
該半導體裝置現在將會更詳細地作描述。
首先，一第一實施例會作描述。
於此中，一具有所謂之兩半導體元件之突起電極是連接在一起之晶片在晶片上結構的半導體裝置將會配合該等圖式詳細地作描述。
第2A至2C圖描繪該第一實施例的一範例半導體裝置。第2A和2B圖是為一主要部份的示意橫截面圖，描繪在突起電極被連接在一起之前的範例狀態，而第2C圖是為該主要部份的示意橫截面圖，描繪在該等突起電極被連接在一起之後的範例狀態。
在第2C圖中所示的半導體裝置10包括兩個半導體元件20和30和一置於它們之間的半導體元件40。該等半導體元件20和30分別具有要連接在一起的突起電極21和31。
如在第2A圖中所示，該半導體元件20具有至少一個突起電極21，在此中具有三個突起電極21，形成於該等表面中之一者上，位在預定的位置。在連接到該半導體元件30之相對之突起電極31之前該等突起電極21各具有一由，例如，銅(Cu)構成且從半導體元件20之表面延伸出來的柱部21a和一形成在該柱部21a之末端的焊接部21b。該等焊接部21b被熱處理俾可具有一半球狀形狀。
類似地，該半導體元件30具有至少一個突起電極31，於此中具有三個突起電極31，形成於該等表面中之一者上。在連接到該半導體元件20之相對之突起電極21之前該等突起電極31各具有一由，例如，Cu構成且從半導體元件30之表面延伸出來的柱部31a和一形成於該柱部31a之末端的焊接部31b。該等焊接部31b被熱處理俾可具有一半球狀形狀。該半導體元件30的突起電極31是形成在對應於半導體元件20之突起電極21之位置的位置。
該半導體元件20的突起電極21與該半導體元件30的突起電極31是所謂的柱電極(柱狀電極)。
第3圖描繪該等突起電極中之一者及其附近的範例結構。第3圖示意地描繪在第2A圖中所示之半導體元件20之X部份的範例結構。
該半導體元件20包括一像是矽(Si)基體般的半導體基體61和一個形成在該半導體基體61之最外層上的元件區域62。像是半導體般的元件是形成在該元件區域62。一佈線層63是在該元件區域62是置於該半導體基體61與該佈線層63之下置於該半導體基體61上。該佈線層63包括電氣連接到形成於元件區域62之元件的導電部份(導線、貫孔) 63a及覆蓋該等導電部份63a的絕緣部份63b。於此中，該佈線層63是由，例如，一第一佈線層64、一第二佈線層65、一第三佈線層66、和一第四佈線層67層疊而成。一由，例如，鋁(Al)構成的電極68和一由一或多個層形成且是部份地覆蓋該電極68的保護薄膜69是在一絕緣部份63c是置於該佈線層63與該絕緣部份63c之下置於該佈線層63上。該絕緣部份63c包括一導電部份63d，而該電極68是置於該導電部份63d上。包括該柱部份21a和該焊接部份21b的突起電極21是被形成俾可連接到該經由該保護薄膜69曝露的電極68。
雖然第3圖僅描繪在第2A圖中之X部份的結構，包括半導體元件20之其他突起電極21的其他部份也會具有相似的結構。此外，包括半導體元件30之突起電極31的部份也會具有相似的結構。
如在第2A圖中所示，置於半導體元件20與30之間的半導體元件40在對應於該等突起電極21和31之位置的位置具有貫孔41(於此中具有三個)。再者，該半導體元件40具有數個由，例如，錫構成且形成於一與半導體元件30相對之表面上的凸塊42。於此中該等凸塊42具有，例如，一半球狀形狀。
該半導體元件40不必作用如在半導體裝置10內之電路的部份。當該半導體元件40不作用如該等電路的部份時，即，當該半導體元件40是為一偽元件，該半導體元件40的凸塊42不被用作電氣連接用的端子(連接到在第2A至2C圖中所示之例子中之下半導體元件30的端子)。
為了形成如在第2C圖中所示的半導體裝置10，如在第2A圖中所示的該上半導體元件20、該下半導體元件30、和該中間半導體元件40是首先被準備。
隨後，該中間半導體元件40被定位以致於形成有凸塊42的表面是與下半導體元件30之形成有突起電極31的表面相對，而半導體元件30的突起電極31與半導體元件40的貫孔41是對準。在對準之後，半導體元件40是安裝在該半導體元件30之上以致於該等突起電極31是如在第2B圖中所示裝配到該等貫孔41內。
該半導體元件40之包括凸塊42之厚度的厚度是被設定以致於當該半導體元件40是如上所述安裝在該半導體元件30之上時，該等突起電極31之柱部31a和焊接部31b的末端部份是在沒有從貫孔41突出之下容納在該等貫孔41內。或者，該等柱部31a的高度和該等焊接部31b的高度是被設定以致於該等柱部31a和該等焊接部31b的末端部份是在沒有從貫孔41突出之下容納在貫孔41內。
該半導體元件40的所有凸塊42會與該半導體元件30的表面接觸。或者，一個或多個凸塊42可以與該半導體元件30的表面分隔。在這例子中，所有該等凸塊42是與該半導體元件30的表面接觸。由於該等凸塊42，該半導體元件40在該等凸塊42的位置處變成與該半導體元件30成點-接觸。與全部突起電極31在沒有凸塊42之下被裝配至半導體元件40之貫孔41內的情況比較起來，這有助於該等突起電極31至該等貫孔41的插入以致於該等突起電極31之包括焊接部31b的末端部份是容納在該等貫孔41內。例如，該等突起電極31是易於裝配至該等貫孔41內以致於即使當半導體元件30的平坦度是與半導體元件40之平坦度不同或者一些貫孔41的形狀與其他貫孔41的形狀稍有不同時，該等突起電極31之包括焊接部31b的末端部份是容納在該等貫孔41內。
在該半導體元件40被安裝在該半導體元件30之上之後，該半導體元件20被定位以致於形成有突起電極21的表面是相對於該等貫孔41而該半導體元件30之形成有突起電極31的表面是形成，而該半導體元件20之突起電極21、該等貫孔41、和該等突起電極31是如在第2B圖中所示對準。在該對準之後，該半導體元件20被安裝在該等半導體元件30和40之上之後以致於該半導體元件20的突起電極21是裝配在該等貫孔41內。
該半導體元件40被設置以致於該等突起電極31不從該等貫孔41突出，而該等突起電極21是裝配至在該等貫孔41內部剩餘的上空間內。該半導體元件40之包括凸塊42之厚度的厚度被設定以致於該等突起電極21之柱部21a和焊接部21b的末端部份是容納在該等貫孔41的空間內。或者，該等柱部21a的高度和該等焊接部21b的高度被設定以致於該等柱部21a和該等焊接部21b的末端部份是容納在該等貫孔41內。藉由這樣，該等突起電極21之包括焊接部21b的末端部份和該等突起電極31之包括焊接部31b的末端部份是容納在該等貫孔41內。
該等焊接部21b和31b是在這狀態下被迴焊俾可整合成連接部50，而該等半導體元件20和30是藉著該等連接部50和該等柱部21a和31a來連接在一起。這時，該等連接部50與該等柱部21a和31a的末端部份是位在該置於半導體元件20和30之間之半導體元件40的貫孔41內部。
在形成半導體裝置10的以上所述的方法中，當該半導體元件30的突起電極31被置放俾不從貫孔41突出時，該半導體元件20的突起電極21是裝配至半導體元件40的貫孔41內。這允許該等突起電極21和31在該等果孔41內部彼此相對，並且降低該等突起電極21和31在焊接部被迴焊之前之橫向位移的風險。再者，在焊接的迴焊之前該等半導體元件20和30之旋轉位移(如在第5圖中所示的θ方向)的風險也降低。
第4A至6B圖描繪無使用中間半導體元件的情況。第4A、4B、6A、和6B圖是為要被連接之半導體元件之主要部份的示意橫截面圖，而第5圖是為要被連接之半導體元件之主要部份的示意平面圖。
當具有以上所述之貫孔41的半導體元件40未被使用時，該半導體元件20的突起電極21和該半導體元件30的突起電極31是首先如在第4A圖中所示對準。隨後，該等突起電極21的焊接部21b和該等突起電極31的焊接部31b變成彼此接觸，而且被迴焊。由於在突起電極21之末端的焊接部21b與在突起電極31之末端的焊接部31是，例如，半球狀，在突起電極21和31的凸表面彼此接觸且焊料在迴焊焊接期間溶化之前，橫向位移會由於半導體元件20的重量、震動、或其他理由而如在第4B圖中所示發生在該等半導體元件20和30之間。除了橫向位移之外，如在第5圖中所示之θ方向上的位移會發生在半導體元件20和30之間(半導體元件30是由虛線表示)。
當像是所謂之微凸塊般之具有小高度的突起電極23和33是分別形成在半導體元件20和30時，在θ方向上的位移或橫向位移也會發生，如在第6A圖中所示。此外，當具有小高度的突起電極33是形成在半導體元件20與半導體元件30中之任一者上時(例如，如在第6B圖中所示形成在半導體元件30上)，以上所述的位移也會發生。即使當突起電極21的焊接部21b和突起電極31的焊接部不是半球狀時，在半導體元件20和30之間的位移也會由於，例如，如上所述的震動而發生。
反之，以上所述的半導體裝置10使用具有貫孔41的半導體元件40，而在該半導體裝置10的形成期間該等半導體元件20和30是被定位以致於該等突起電極21和31是裝配至該等貫孔41內而且是在該等貫孔41內部連接。這有效地降低在焊接部被迴焊之前突起電極21與31之橫向位移以及半導體元件20與30在θ方向上之位移的風險。
再者，突起電極21和31在貫孔41內部的連接降低在焊接部被迴焊之後於彼此相鄰置放之相鄰之柱部21a、柱部31a、與連接部50組之間之短路的風險。
此外，由於半導體裝置10利用柱電極作為突起電極21和31，該等連接部50與該等半導體元件20和30的表面是彼此分隔分別對應於突起電極21和31之長度的距離。結果，在迴焊焊接期間或者在半導體裝置10正運作時施加到連接部50的剪應力(shear stress)是降低。
雖然半導體裝置10的範例結構和形成半導體裝置10的範例方法業已在以上作描述，在半導體裝置10中所使用之半導體元件20、30、和40的結構未被限定為以上所述的那些。例如，半導體元件20和30的尺寸與半導體元件20之突起電極21和半導體元件30之突起電極31的數目和佈局未被限定為以上所述的那些。該半導體元件40的尺寸、該等貫孔的數目和佈局、及該等凸塊42的數目和佈局也未被限定為以上所述的那3。雖然未被描繪，連接到突起電極21和31的重繞線(rewiring lines)可以形成在半導體元件20和30的表面。
在半導體裝置10中所使用的半導體元件40現在將會更詳細地作描述。
第7圖描繪該第一實施例的另一範例半導體裝置。第7圖是為該第一實施例之範例半導體裝置之主要部份的示意橫截面圖。
該半導體元件40的貫孔41被形成具有一個與半導體元件20之突起電極21之直徑和半導體元件30之突起電極31之直徑相同或更大的直徑以致於該等突起電極21和31是裝配在該貫孔41內。當該貫孔41的直徑是比突起電極21和31的直徑大時，間隙是遺留在貫孔41的側壁(內壁)與柱部21a和31a及連接部50之間。這些間隙防止該等柱部21a和31a及該連接部50與該貫孔41的側壁接觸。
如果該貫孔41的側壁具有一導電區域且該等柱部21a和31a及該連接部50與該導電區域接觸的話，該半導體裝置10會故障。從這觀點看，該半導體元件40之貫孔41的側壁可以是電氣絕緣的。例如，該貫孔41的側壁可以如在第7圖中所示由一絕緣薄膜43覆蓋。這有效地降低半導體元件40與柱部21a和31a及連接部50之電氣連接的風險。
雖然第7圖描繪絕緣薄膜43是形成在貫孔41之側壁上以及在半導體元件40之部份的前和後表面上，該絕緣薄膜43是可以被形成俾可至少覆蓋該貫孔41的側壁。此外，除了形成有像是連接端子(例如，凸塊42)般之導電部份的導電區域之外，該絕緣薄膜43可以是形成在該半導體元件40的整個前或後表面上。
此外，一個在半導體裝置10之半導體元件20與30之間的空間可以是由像是填膠(underfill)般的樹脂填充。
第8圖描繪該第一實施例的另一範例半導體裝置。第8圖是為該第一實施例之範例半導體裝置之主要部份的示意橫截面圖。
如在第8圖中所示，一個在該等於半導體元件40之貫孔41內部(於此中，在側壁是以絕緣薄膜43覆蓋的貫孔內部)連接之半導體元件20和30之間的空間可以是以樹脂70填充。該樹脂70可以是，例如，經常被用作填膠的環氧樹脂。於半導體元件20和30之間之包括在突起電極21和31被連接之後餘留在貫孔41內部之間隙的空間，例如，是以該樹脂70填充。該樹脂70更增進半導體裝置10對抗熱與物理應力的連接可靠度。
以上所述的半導體裝置10可以被安裝在一電路板上。
第9和10圖描繪包括安裝有該第一實施例之半導體裝置之電路板之裝置(電子裝置)的範例結構。第9和10圖是為該第一實施例之範例電子裝置之主要部份的示意橫截面圖。
在第9圖中所示的電子裝置100包括一電路板(底基板)101和一導線連接在該電路板101上的半導體裝置10。在這電子裝置100中，一是在一半導體元件40置於它們之間之下連接到一半導體元件20的半導體元件30是利用由，例如，金(Au)構成的導線102電氣連接到該電路板101。該半導體元件30包括，例如，連接到該半導體元件30之內部電路與突起電極31的導線34，而且該等導線34是連接到該等導線102的一端。
於此中該半導體元件40可以是，例如，一偽元件。在這情況中，凸塊42不作用如連接到半導體元件30的端子。或者，該半導體元件40可以是一作用如在半導體裝置10內之部份之電路的半導體元件(主動元件)。在這情況中，該等凸塊42可以作用如連接到半導體元件30的端子。當一主動元件是使用作為半導體元件40時，該等導線34的預定圖案是依據，例如，半導體元件40的功能或者凸塊42的佈局來形成在該半導體元件30上。
在第9圖中，該半導體元件40之貫孔41的側壁是由一絕緣薄膜43覆蓋。一個在半導體元件20與30之間的空間可以由像是填膠般的樹脂填充。此外，在電路板101上的導線102和半導體裝置10(當一個在半導體元件20與30之間的空間未由樹脂填充時包括該空間)可以利用像是密封樹脂般的樹脂來密封。
在第10圖中所示的電子裝置110包括一電路板(底基板)111和一利用錫球112安裝到該電路板111的半導體裝置10。一半導體元件30包括，例如，像是貫矽導孔(through-silicon vias(TSVs)般的導通型電極35，而該導通型電極35是經由該等錫球112來電氣連接到該電路板111。
如在第9圖中所示的電子裝置100中，於第10圖中所示之電子裝置110內的半導體元件40可以是一偽元件或者一主動元件。當該半導體元件40是為一主動元件時，凸塊42作用如連接到該半導體元件30的端子。依據半導體元件40之形態的一預定圖案是形成在該半導體元件30上。例如，如在第10圖中所示之連接凸塊與導通型電極35的導線36是形成在該半導體元件30上。
在第10圖中，該半導體元件40之貫孔41的側壁也是由一絕緣薄膜43覆蓋。此外，在該等半導體元件20與30之間的一個空間或者在該半導體元件30與該電路板111之間的一個空間可以由像是填膠般的樹脂填充。此外，在電路板111上的半導體裝置10(當在該等半導體元件20與30之間的空間和在該半導體元件30與該電路板111之間的空間未由樹脂填充時包括該等空間)可以利用樹脂來密封。
接著，一第二實施例將會作描述。
在以上的描述中，該等半導體元件20和30是在半導體元件40介於它們之間之下來連接在一起。該半導體元件40可以被整合成一個一半導體元件與一像是電路板般之電子元件是連接在一起的結構。
第11A和11B圖描繪一第二實施例的範例半導體裝置。第11A圖是為一主要部份的示意橫截面圖，描繪在突起電極是連接在一起之前的範例狀態，而第11B圖是為一主要部份的示意橫截面圖，描繪在該等突起電極是連接在一起之前的範例狀態。
在第11A和11B圖中所示的一半導體裝置140包括一半導體元件20、一電路板(底基板)150、和一置於該半導體元件20與該電路板150之間的半導體元件40。具有預定圖案之導電部份形成在表面上和內部的一樹脂基板、一陶瓷基板、一半導體基體等等是可以被使用作為該電路板150。如在第11A圖中所示，要連接到該半導體元件20之一突起電極21的一突起電極151是形成在該電路板150上，位於一個對應於該突起電極21之位置(或者半導體元件40之貫孔41的位置)的位置。在連接到該突起電極21之前該突起電極151包括一柱部151a和一形成於該柱部151a之末端的半球狀焊接部151b。類似地，該突起電極21包括一柱部21a和一形成於該柱部21a之末端的半球狀焊接部21b。
該半導體元件40是安裝在該電路板150上以致於該突起電極151是裝配至該貫孔41內，而該半導體元件20的突起電極21然後是裝配到該貫孔41內。在該等突起電極21和151是裝配在該貫孔41內時，該突起電極21的柱部21a和該突起電極151的柱部151a是藉著將該等焊接部21b和151b迴焊來由一如在第11B圖中所示之連接部(一個由焊接部21b與151b整合成的連接部)160連接在一起。
由於該等突起電極21和151是在該貫孔41內部連接，該等突起電極21和151之位移的風險是降低。此外，在相對之突起電極21和151組之間之短路的風險也是降低。
在該電子裝置140內的半導體元件40可以是一偽元件或者一主動元件。第11A和11B圖描繪該半導體元件40是為一主動元件，而凸塊42是用作連接到形成於電路板150上之電極152之端子的一種情況。
在第11A和11B圖中，該半導體元件40之貫孔41的側壁是由一絕緣薄膜43覆蓋。一個在該半導體元件20與該電路板150之間的空間可以是由像是填膠般的樹脂填充。
接著，一第三實施例將會作描述。
雖然一具有一貫孔41之像是半導體元件40(偽元件或主動元件)般的基板是在以上的描述中使用，具有類似之貫孔之不同類型的基板是可以被使用。
第12和13圖描繪該第三實施例的範例半導體裝置。第12和13圖是為該第三實施例之範例半導體裝置之主要部份的示意橫截面圖。
在第12圖中所示的半導體裝置170包括一在半導體元件20與30之間之具有一貫孔181之像是樹脂基板或陶瓷基板般的基板180。在第13圖中所示的半導體裝置190包括一在一半導體元件20與一電路板150之間的基板180。
凸塊182是形成在該基板180之與在第12圖中之半導體元件30和在第13圖中之電路板150相對的一表面上。然而，這些凸塊182不是必要地形成。該基板180可以是，例如，一單一樹脂基板或單一陶瓷基板。此外，該基板180可以是在內部或表面上形成有預定圖案之導電部的一樹脂基板、陶瓷基板等等，即一電路板。當該貫孔181是簡單地形成時，在該等導電部是因基板180的形態而曝露在貫孔181的側壁的情況中，該側壁會由以上所述的絕緣薄膜43覆蓋。
當如此的基板180是使用時，在第12圖中所示之半導體裝置170中的突起電極21和31與在第13圖中所示之半導體裝置190中的突起電極21和151是以與以上所述之那些相同的形式在該貫孔181內部連接。這降低以上所述之位移與短路的風險。
一個在第12圖中所示之半導體元件20和30之間的空間與一個在第13圖中所示之半導體元件20與電路板150之間的空間是可以由像是底膠般的樹脂填充。
第14圖描繪該第三實施例之半導體裝置的範例結構。第14圖是為該第三實施例之範例半導體裝置之主要部份的示意橫截面圖。
在第14圖中所示的半導體裝置170A包括半導體元件20A和30A以及一介於該等半導體元件20A和30A之間之具有貫孔181A的樹脂基板180A。突起電極21A和31A是在該等貫孔181A內部連接。在該半導體裝置170A中，該半導體元件20A是為，例如，一記憶體元件(記憶體晶片)，而該半導體元件30A是為，例如，一邏輯元件(邏輯晶片)。
該樹脂基板180A在其之內部和表面上具有預定圖案的導電部，而且是作用如一電路板。在該等導電部之中，形成於該樹脂基板180A之其中一表面上位在預定位置的導線183A是描繪在第14圖中。該等導線183A是連接到錫球184A。
凸塊182A是形成在該樹脂基板180A之與半導體元件30A相對的表面上。該等凸塊182A是連接到在樹脂基板180A內部的導電部及連接到在樹脂基板180A之表面上的導線183A。另一方面，該半導體元件30A在一與樹脂基板180A相對的表面上是形成有導線37A。該等導線37A是連接到在半導體元件30內的元件和該等突起電極31A。該等導線37A是連接到樹脂基板180A的凸塊182A。
在半導體元件20A與30A之間的空間，即，在半導體元件20A與樹脂基板180A之間、在半導體元件30A與樹脂基板180A之間、以及在貫孔181A內部的空間是由樹脂70A填充。
包括這半導體裝置170A的一電子裝置可以藉由使用錫球184A把半導體裝置170A連接到一電路板來被得到。
如在第14圖中所示的半導體裝置170A是可以利用如在，例如，第15A至15D圖和16A至16C圖中所示的方法來形成。
第15A至15D與16A至16C圖描繪一種形成該第三實施例之半導體裝置的範例方法。第15A至15D與16A至16C圖是為在每個形成步驟中一主要部份的示意橫截面圖。
首先，該等半導體元件20A和30A與該樹脂基板180A是被準備。隨後，如在第15A圖中所示，樹脂基板180A的貫孔181A和半導體元件30A的突起電極31A是對準。在對準之後，半導體元件30A是安裝在該樹脂基板180A之上以致於該等突起電極31A是裝配在該等貫孔181A內，如在第15B圖中所示。這時，該樹脂基板180A的凸塊182A是連接到該半導體元件30A的導線37A。
接著，安裝有半導體元件30A之樹脂基板180A的位置是如在第15C圖中所示上下顛倒。隨後，半導體元件20A的突起電極是與該等貫孔181A對準。在對準之後，該半導體元件20A是安裝在該樹脂基板180A之上以致於該等突起電極21A是裝配到該等已裝配有突起電極31A的貫孔181A內，如在第15D圖中所示。藉由迴焊焊接部，該等突起電極21A和31A是在該等貫孔181A內部連接在一起。那就是說，柱部21Aa和31Aa是藉著由焊接部21Ab和31Ab(在第15A至15D圖中)整合而成的連接部50A來在貫孔181A內部連接在一起，如在第16A圖中所示。
在該等半導體元件20A和30A是在樹脂基板180A介於它們之間之下連接在一起之後，在該半導體元件20A與該樹脂基板180A和在該半導體元件30A與該樹脂基板180A之間的空間是以樹脂70A填充，如在第16B圖中所示。這時，在餘留在貫孔181A內之間隙內部的空間也是以樹脂70A填充。
在以樹脂70A填充該等空間之後，該等錫球184A是連接到樹脂基板180A的導線183A，如在第16C圖中所示。這完成如在第14圖中所示之半導體裝置170A的形成。
為了藉由把半導體裝置170A安裝在一電路板上來形成一電子裝置，該等錫球184A可以用來把該半導體裝置170A連接到該電路板。
接著，一第四實施例將會作描述。
在以上的描述中，該兩半導體元件的突起電極是在置於該兩半導體元件之間之基板的貫孔內部連接在一起。這結構可以應用到三個或更多個半導體元件被使用的情況。
第17A和17B圖描繪一第四實施例的範例半導體裝置。第17A圖是為一主要部份的示意橫截面圖，描繪在連接半導體元件之前的範例狀態，而第17B圖是為該主要部份的示意橫截面圖，描繪在連接該等半導體元件之後的範例狀態。
如在第17B圖中所示，一半導體裝置200包括一個由四個連接在一起之半導體元件210,220,230,和240形成的疊層。
如在第17A圖中所示，第一層的半導體元件210具有形成在上表面上的突起電極211及形成在上表面的凹坑212。該等突起電極211各包括一柱部211a和一形成在柱部211a之末端的半球狀焊接部211b。電極212a是形成於該等凹坑212的底表面上。
該第二層的半導體元件220具有形成於上和下表面上的突起電極221、形成在上表面的凹坑222、和穿過該半導體元件220的貫孔223。該等突起電極221各包括一柱部221a和一形成於柱部221a之末端的半球狀焊接部221b。電極222a是形成於凹坑222的底表面上。
該第三層的半導體元件230具有形成於下表面上的突起電極231、形成於上表面的凹坑232、和穿過該半導體元件230的貫孔233。該等突起電極231各包括一柱部231a和一形成於柱部231a之末端的半球狀焊接部231b。電極232a是形成在凹坑232的底表面上。
該第四層的半導體元件240具有形成於下表面上的突起電極241。該等突起電極241各包括一柱部241a和一形成在柱部241a之末端的半球狀焊接部241b。
當這些半導體元件210,220,230,和240是堆疊且連接時，例如，第二層的半導體元件220是安裝在該半導體元件210之上以致於該第一層的半導體元件210的突起電極211是裝配在該等貫孔223內。這時，在半導體元件220之下表面上的突起電極221是裝配至半導體元件210的凹坑212內。該等半導體元件210和220被形成以致於當該半導體元件220是安裝在該半導體元件210之上時該等突起電極211不從該等貫孔223突出。
接著，該第三層的半導體元件230是安裝在該半導體元件220之上以致於在第二層之半導體元件220之上表面上的突起電極221是裝配在該等貫孔233內。這時，半導體元件230的一些突起電極231是裝配至該半導體元件220之裝配有突起電極211的貫孔223內，而餘下的突起電極231是裝配至半導體元件220的凹坑222內。該等半導體元件220和230被形成以致於當該半導體元件230是安裝在該半導體元件220之上時該等突起電極221不從該等貫孔233突出。
接著，該第四層的半導體元件240是安裝在該第三層的半導體元件230之上。這時，該半導體元件240的一些突起電極241是裝配到該半導體元件230之裝配有突起電極221的貫孔233內，而餘下的突起電極241是裝配到半導體元件230的凹坑232內。
在該等半導體元件210,220,230,和240是這樣堆疊之後，該等焊接部被迴焊。藉著這樣，突起電極211和231是在該等貫孔223內部連接在一起，而該等突起電極221和241是在該等貫孔233內部連接在一起，如在第17B圖中所示。那就是，該等柱部211a和231a是藉著由焊接部211b和231b整合而成的連接部251來連接在一起，而該等柱部221a和241a是藉著由焊接部221b和241b整合而成的連接部252來連接在一起。在該迴焊焊接期間，該等突起電極221是連接到在該等凹坑212上的電極212a，該等突起電極231是連接到在該等凹坑222上的電極222a，而該等突起電極241是連接到在該等凹坑232上的電極232a，如在第17B圖所示。
這樣，該等半導體元件210,220,230,和240是連接在一起，得到如在第17B圖中所示的半導體裝置200。
該半導體元件220之貫孔223的側壁和該半導體元件230之貫孔233的側壁可以由絕緣薄膜覆蓋。在該等半導體元件210與220之間、在該等半導體元件220與230之間、和在該等半導體元件230與240之間的空間是可以由像是填膠般的樹脂填充。
雖然以上所述的半導體裝置200包括由四個連接在一起之半導體元件210,220,230,和240形成的疊層，包括五個或更多個半導體元件的半導體裝置是可以根據以上所述的例子來形成。
不同之半導體元件在該等貫孔或者該等凹坑內部的連接降低以上所述之位移與短路的風險，藉此導致高連接可靠度的半導體裝置200。再者，該等突起電極在該等突起電極裝配在該等貫孔與該等凹坑內之後的連接降低該等突起電極之位移的風險，並且允許三個或者更多個半導體元件在一次迴焊焊接中於同一時間被連接。那就是，如果該等半導體元件不具有貫孔或者凹坑的話，例如，迴焊焊接在每次該等半導體元件被堆疊與連接時是必需的，而在該等半導體元件之間的位移在所有該等場合中是可能發生的。反之，當該等半導體元件具有以上所述的貫孔和凹室時，在該等半導體元件之位移的風險被降低時，該半導體裝置是藉著一次迴焊焊接來有效地形成。
雖然在以上的描述中該疊層僅包括該等半導體元件，該疊層可以包括像是電路板般的電子元件。即使當在該四個半導體元件210,220,230,和240當中之該等半導體元件210,220,和230中之任一者是以一電路板替代時，一包括該疊層的電子裝置產生與以上所述之那些相同的效果。
第18圖描繪該第四實施例之半導體裝置的範例結構。第18圖是為該第四實施例之範例半導體裝置之主要部份的示意橫截面圖。
在第18圖中所示的半導體裝置300包括一個由四個連接在一起之半導體元件310,320,330,和340形成的疊層。
該第一層的半導體元件310和該第二層的半導體元件320是被設置以致於該半導體元件310之具有區域(電路區域)310a的上表面和該半導體元件320之具有電路區域320a的下表面是彼此相對。該等電路區域包括形成在其中之像是電晶體與導線層般的元件。該第三層的半導體元件330和該第四層的半導體元件340是被設置以致於該半導體元件330之具有電路區域330a的上表面和該半導體元件340之具有電路區域340a的下表面是彼此相對。
該第一層的半導體元件310具有突起電極311、凹坑312、和電極312a形成在具有電路區域310a的上表面上。該等突起電極311是連接到重繞線314(它們中的一些是連接到該等電極312a)。
該第二層的半導體元件320具有突起電極321形成在其之上和下表面上和凹坑322與電極322a形成在未形成有電路區域320a的上表面上。該等突起電極321是連接到重繞線324(它們中的一些是連接到該電極322a)。再者，該半導體元件320具有貫孔323。
該第三層的半導體元件330具有突起電極331形成在未形成有電路區域330a的下表面上和凹坑332與電極332a形成在具有電路區域330a的上表面上。該等突起電極331和該等電極332a是連接到重繞線334。再者，該半導體元件330具有貫孔333。
該第四層的半導體元件340具有突起電極341形成在具有電路區域340a的下表面上。該等突起電極341是連接到重繞線344。
在第一層之半導體元件310與第三層之半導體元件330之間彼此相對的突起電極311和331是裝配到第二層之半導體元件320的貫孔323內，而且是在該等貫孔323內部連接在一起。那就是，柱部311a和331a是在該等貫孔323內部藉著連接部351來連接。
在第二層之半導體元件320與第四層之半導體元件340之間彼此相對的突起電極321和341是裝配到第三層之半導體元件330的貫孔333內，而且是在該等貫孔333內部連接在一起。那就是，柱部321a和341a是在該等貫孔333內部藉著連接部352來連接。
在第二層之半導體元件320之具有電路區域320a之下表面上的突起電極321是裝配至該第一層之半導體元件310的凹坑312內，而且是連接到該等電極312a。即，該等柱部321a是經由焊接部來連接到該等電極312a。
第三層之半導體元件330的一些突起電極331是裝配至第二層之半導體元件320的凹坑322內，而且是連接到該等電極322a。即，該等柱部331a是經由焊接部來連接到該電極322a。
第四層之半導體元件340的一些突起電極341是裝配至第三層之半導體元件330的凹坑332內，而且是連接到該等電極332a。即，該等柱部341a是經由焊接部來連接到該等電極332a。
該四個半導體元件310,320,330,和340可以在一次迴焊焊接中在同一時間連接在一起。
在具有以上所述之結構之半導體裝置300中之訊號傳遞路徑的例子是在第18圖中由虛線箭頭表示。在該半導體裝置300中，如上連接的該四個半導體元件310,320,330,和340是彼此合作來實現預定的處理功能。
在如上所形成的半導體裝置300中，該等貫孔323和333以及凹坑312,322,和332是能夠降低半導體元件310,320,330,和340之位移與短路的風險。此外，該半導體裝置300是藉一次迴焊焊接來有效地形成。
隨後，形成僅具有貫孔或同時具有貫孔與凹坑之半導體元件的範例方法將會作描述。
首先，一種形成具有貫孔之半導體元件的範例方法將會配合第19A至21C圖來依序作描述。第19A至21C圖是為在每個形成步驟中之主要部份的示意橫截面圖。
第19A至19C圖描繪一具有貫孔之範例半導體元件的第一形成步驟。
如在第19A圖中所示，一支撐基板501是利用黏著劑500來連接到一半導體元件400的後表面。於此中，各包括一柱部401a與一形成於柱部401a之末端之焊接部401b的突起電極401是形成在該半導體元件400之與後表面相對的前表面上。該半導體元件400是為一主動元件，而該等突起電極401是形成在該具有電路區域(形成有像是電晶體與導線層般之元件的區域)的前表面上。接著，一光阻502是形成在該半導體元件400的前表面上，如在第19B圖中所示。隨後，開孔502a是利用光刻技術形成在該光阻502中，位於要形成貫孔的區域，如在第19C圖中所示。
第20A至20C圖描繪具有貫孔之範例半導體元件的第二形成步驟。
在該等開孔502a是形成於該光阻502中之後，孔洞403a是利用光阻502作為光罩藉著乾蝕刻來形成於該半導體元件400中，如在第20A圖中所示。隨後，該光阻502是從半導體元件400移除，如在第20B圖中所示，而一支撐基板504是利用黏著劑503連接到該半導體元件400的前表面，如在第20C圖中所示。
第21A至21C圖描繪具有貫孔之範例半導體元件的第三形成步驟。
在該支撐基板504被連接之後，背研磨被執行以致於該半導體元件400被縮減到一預定厚度，如在第21A圖中所示。這時，事先已形成在半導體元件400之前表面中的孔洞403a出現在該後表面，導致貫孔403形成在半導體元件400中。在該背研磨之後，由，例如，二氧化矽(SiO2 )構成的絕緣薄膜404是形成，如在第21圖中所示。該等絕緣薄膜404可以是藉著，例如，熱氧化或者化學蒸氣沉積法(CVT)來形成。在絕緣薄膜404的形成之後，黏著劑503和支撐基板504被移除。這完成如在第21C圖中所示之半導體元件400a的形成。其他電子元件的突起電極是裝配至該半導體元件400a的貫孔403內。
雖然以上所述的半導體元件400a(400)是為一主動元件，一是為偽元件的半導體元件也能夠以相同的形式形成。
此外，形成以上所述之具有該等包括柱部401a之突起電極401之半導體元件400a的方法也可以用來在一不具有如此之柱電極的半導體元件中形成貫孔。例如，置於該兩在第一和第二實施例中所述之要連接之半導體元件之間的該半導體元件40(偽元件或主動元件)也可以依據如在第19A至21C圖中所示的方法來形成。
接著，形成具有貫孔之半導體裝置的另一範例方法將會配合第22A至27C圖來依序作描述。第22A至27C圖是為在每個形成步驟中一主要部份的示意橫截面圖。
第22A至22C圖描繪具有貫孔之另一範例半導體元件的第一形成步驟。
如在第22A和22B圖中所示，一支撐基板701是利用黏著劑700來連接到一半導體元件600之形成有突起電極601的前表面。於此中，該等突起電極601各包括一柱部601a和一形成在柱部601a之末端的焊接部601b。該半導體元件600是為一具有突起電極601形成在具有電路區域之表面上的主動元件，而且是被縮減成一預定厚度。在該支撐基板701的連接之後，一光阻702是形成於該半導體元件600之與形成有突起電極601之前表面相對的後表面上，如在第22C圖中所示。
第23A至23C圖描繪具有貫孔之另一範例半導體元件的第二形成步驟。
在光阻702的形成之後，開孔702a是利用光刻技術形成在該光阻702中，於貫孔要被形成的區域，如在第23A圖中所示。在開孔702a的形成之後，貫孔603是利用光阻702作為光阻藉著乾蝕刻來形成在該半導體元件600，如在第23B圖中所示。在貫孔603的形成之後，光阻702是從半導體元件600移去，如在第23C圖中所示。
第24A至24C圖描繪具有貫孔之另一範例半導體元件的第三形成步驟。
在光阻702的移去之後，由，例如，SiO2 構成的絕緣薄膜604是藉著，例如，熱氧化或CVD來形成，如在第24A圖中所示。在絕緣薄膜604的形成之後，一種子層605是形成，如在第24B圖中所示，而一光阻703是形成，如在第24C圖中所示。
在光阻703的形成之後，開孔703a是在要形成有重繞線的區域中形成，如在第25A圖中所示。隨後，重繞線606是藉著電鍍來形成在該等開孔703a中的種子層605上，如在第25B圖中所示。在重繞線606的形成之後，光阻703是被移去，如在第25C圖中所示。
第26A至26C圖描繪具有貫孔之另一範例半導體元件的第五形成步驟。
在光阻703的移去之後，另一光阻704是形成，如在第26A圖中所示，而開孔704a是形成在要形成有突起電極的區域內，如在第26B圖中所示。隨後，柱部607a是藉著電鍍來形成在開孔704a內的重繞線606上，而再者，焊接部607b是形成在柱部607a上以致於突起電極607被形成，如在第26C圖中所示。突起電極607的高度可以藉由控制，例如，光阻704的厚度以及電鍍的條件(電鍍時間、電流密度、以及其他參數)來作調整。
第27A至27C圖描繪具有貫孔之另一範例半導體元件的第六形成步驟。
在突出電極607的形成之後，光阻704被移去，如在第27A圖中所示。隨後，種子層605之在光阻704之移去之後出現的部份是藉著蝕刻來被移去，如在第27B圖中所示。在蝕刻之後，焊接部607b是藉著迴焊來成形，而黏著劑700與支撐基板701是被移去。這完成一半導體元件600a的形成，如在第27C圖中所示。其他電子元件的突起電極是裝配至半導體元件600a的貫孔603內。
雖然以上所述的半導體元件600a(600)是為一主動元件，一是為一偽元件的半導體元件也能夠以相同的形式形成。
此外，形成以上所述之具有突起電極601在前表面和突起電極607在後表面之半導體元件600a的方法也可以用來根據如在第22A至27C圖中所示的例子來形成僅具有突起電極607在後表面的半導體元件。即，在第22A至27C圖中所示的方法在沒有突起電極601之下可以利用半導體元件600來被實現。
接著，一種形成具有貫孔與凹坑之範例半導體元件的方法將會作描述。
該方法能夠以與在第22A至22C圖和第23A至23C圖中所示之方法相同的形式來實現直到該等貫孔被形成為止。於此中，連續步驟的例子將會配合第28A至32C圖來依序描述。第28A至32C圖是為在每個形成步驟中一主要部份的示意橫截面圖。
第28A至28C圖描繪具有貫孔與凹坑之範例半導體元件的第一形成步驟。
於如在第22A至22C圖與第23A至23C圖中所示貫孔603被形成和光阻702被移去之後，另一光阻705是如在第28A圖中所示被形成，而開孔705a是如在第28B圖中所示形成在要形成有凹坑的區域內。在開孔705a的形成之後，凹坑608是利用光阻705作為光阻藉著乾蝕刻來形成在該半導體元件600，如在第28C圖中所示。
第29A至29C圖描繪具有貫孔與凹坑之範例半導體元件的第二形成步驟。
在凹坑608的形成之後，光阻705是如在第29A圖中所示被移去，而絕緣薄膜604是如在第29B圖中所示藉著，例如，熱氧化或CVD來形成。在絕緣薄膜604的形成之後，一種子層605是如在第29C圖中所示被形成。
第30A至30C圖描繪具有貫孔與凹坑之範例半導體元件的第三形成步驟。
在種子層605的形成之後，一光阻703是如在第30A圖中所示被形成，而開孔703a是如在第30B圖中所示形成在要形成有重繞線的區域內和在凹坑608內。隨後，在凹坑608內部的重繞線606與電極609是如在第30C圖中所示藉著電鍍來形成在開孔703a內的種子層605上。隨後，光阻703被移去。
第31A至31C圖描繪具有貫孔與凹坑之範例半導體元件的第四形成步驟。
在重繞線606與電極609的形成之後，另一光阻704是如在第31A圖中所示被形成，而開孔704a是如在第31B圖中所示形成在要形成有突起電極的區域內。隨後，柱部607a是藉著電鍍來形成於開孔704a內的重繞線606上，而再者，焊接部607b是形成在柱部607a上以致於突起電極607是如在第31C圖中所示被形成。
第32A至32C圖描繪具有貫孔與凹坑之範例半導體元件的第五形成步驟。
在突起電極607的形成之後，光阻704是被移去，如在第32A圖中所示。隨後，種子層605之在光阻704之移去之後出現的部份是藉著蝕刻來被移去，如在第32B圖中所示。在蝕刻之後，該等焊接部607b是藉著迴焊來被成形，而黏著劑700和支撐基板701是被移去。這完成一半導體元件600b的形成，如在第32C圖中所示。其他電子元件的突起電極是裝配至半導體元件600b的貫孔603和凹坑608內。
該半導體元件600b(600)可以是一主動元件或者一偽元件。
此外，形成以上所述之具有突起電極601在前表面與突起電極607在後表面之半導體元件600b的方法也可以用來依據在第28A至32C圖中所示的例子形成僅具有突起電極607在後表面的半導體元件。
雖然包括由數個連接在一起之電子元件形成之疊層的半導體裝置是在上面被描述，該等半導體裝置的形態不被限定為以上所述的那些，而可以是適當地作改變。
第33A和33B圖描繪一第一變化。第33A和33B圖是為一半導體元件、一電子元件、和一基板之主要部份的示意橫截面圖。
如在第33A和33B圖中所示，要連接在一起之半導體元件810的突起電極811和電子元件(半導體元件、電路板等等)820的相對突起電極821不是必要地包括分別形成於突起電極811和821上的焊接部811b和821b。例如，如在第33A圖中所示，僅半導體元件810的突起電極811會包括柱部811a和形成於柱部811a上的焊接部811b，而電子元件820的突起電極821會僅包括柱部821a。或者，如在第33B圖中所示，僅該電子元件820的突起電極821會包括柱部821a和形成在柱部821a上的焊接部821b，而半導體元件810的突起電極811會僅包括柱部811a。在第33A或33B圖中所示之任一結構中的該等突起電極811和821可以在一基板(半導體元件、樹脂基板、陶瓷基板等等)830的貫孔831內部連接在一起。
第34圖描繪一第二變化。第34圖是為該半導體元件、該電子元件、與該基板之主要部份的示意橫截面圖。
如在第34圖中所示，置於半導體元件810與電子元件820之間的基板830在兩表面上可以具有凸塊832。例如，當該等突起電極811和821是在貫孔831內部連接時，在上表面上的凸塊832會與半導體元件810接觸，而在下表面上的凸塊會與電子元件820接觸。當該基板830是為一主動元件時，在上和下表面上的凸塊832會被使用作為連接到半導體元件810與電子元件820的端子。
第35A和35B圖描繪一第三變化。第35A和35B圖是為該基板之主要部份的示意平面圖。
該基板830的貫孔831和凸塊832(換句話說，該半導體元件810的突起電極、該電子元件820的突起電極821、和該基板830的凸塊832)可以是如在第35A和35B圖中所示被配置。例如，該等貫孔831和凸塊832可以是如在第35A圖中所示交替地配置。此外，該等貫孔831可以是如在第35B圖中所示配置在該等佈設在中央區域內之凸塊832的外週緣四周。在任一情況中，於半導體元件810與電子元件820之連接期間之位移與短路的風險是有效地降低。
該等貫孔831不是必要地形成在整個基板830，而形成在該基板830的兩個或更多個貫孔831對於像是位移般的問題產生一些正面效果。
第36A至36C圖描繪一第四變形。第36A至36C圖是為該半導體元件、該電子元件、與該基板之主要部份的示意橫截面圖。
形成在基板830的貫孔831不是必要地為圓柱狀的。例如，該等貫孔831可以是逐漸往一邊漸細以致於如同在第36A圖中所示的貫孔831A一樣，接近半導體元件810之開孔的直徑是比遠離半導體元件810之開孔的直徑大。或者，該等貫孔831可以是逐漸往一邊漸細以致於如同在第36B圖中所示的貫孔831B一樣，接近電子元件820之開孔的直徑是比遠離電子元件820之開孔的直徑大。此外，該等貫孔831可以是如同在第36C圖中所示的貫孔831C一樣在接近半導體元件810的開孔與接近電子元件820的開孔之間緊縮，該等緊縮部份的直徑是比開孔的直徑小。
圓柱狀、逐漸往一邊漸細、或者緊縮式貫孔831的最小直徑最好是設定為相等於突起電極811和821之直徑的一倍或者比它大但比兩倍小。這有效地減少像是突起電極811和821在被裝配至貫孔831內時之位移般的問題。
第37A和37B圖描繪一第五變化。第37A和37B圖是為該半導體元件、該電子元件、與該基板之主要部份的示意橫截面圖。
該半導體元件810的突起電極811和該電子元件820的突起電極821不受限制為柱電極。例如，由，例如，Au構成的金屬凸塊811A是可以用作半導體元件810的突起電極，而該等金屬凸塊811A與作用如電子元件820之電極的突起電極821是可以經由焊接部821b來在貫孔831內部連接在一起，如在第37A和37B圖中所示。
或者，作用如柱電極的突起電極811是用於半導體元件810，而金屬凸塊可以被使用作為電子元件820的突起電極。此外，金屬凸塊可以同時用於半導體元件810以及電子元件820。
以上所述之實施例的例子現在將會作描述。
[例子1]
具有形成於其上之突起電極之3.5mm x 7mm的一半導體元件(於此後稱為”第一半導體元件”)是被準備。該等突起電極各包括一直徑30μm以及高度35μm的Cu柱部和形成在柱部之末端之高度10μm的錫-銀(SnAg)焊料，而且它們是在50μm的間距下排列。
再者，由Si構成之具有突起電極形成於其上之尺寸為15mm x 15mm的一底基板(於此後稱為”Si底基板”)是被準備。該等突起電極具有與在第一半導體元件上之突起電極相同的尺寸和結構，而且是以與在第一半導體元件上之突起電極相同的圖案來配置。
此外，在沒有一主動層之下一Si基板是被使用作為一具有貫孔的半導體元件(於此後稱為”第二半導體元件”)。該第二半導體元件是被形成如後。首先，直徑35μm的孔洞是以與第一半導體元件之突起電極相同的圖案藉著乾蝕刻來形成於該Si基板的表面。隨後，該Si基板的厚度是藉著背研磨該Si基板的後表面來縮減成50μm。這時，事先形成在前表面的孔洞是出現在後表面，造成貫孔。隨後，絕緣薄膜是藉著低溫CVD或熱氧化來形成在該Si基板的後表面上(研磨表面)上以及在該等貫孔內部。這完成第二半導體元件的形成。當連接端子是形成在這第二半導體元件上時，在貫孔與絕緣薄膜是如以上形成之前，電路圖案、凸塊等等是可以形成在該Si基板上。
為了把第一半導體元件安裝在Si底基板上，首先，形成有貫孔的第二半導體元件是利用覆晶式黏晶機(flip-chip bonder)來安裝在該Si底基板之上以致於該第二半導體元件的貫孔與該Si底基板的突起電極是對準。接著，第一半導體元件的突起電極與第二半導體元件的貫孔是對準，而該第一半導體元件是利用該覆晶式黏晶機來被安裝。隨後，該疊層是在氮氣大氣下於一迴焊爐中加熱到240℃以致於該Si底基板與該第一半導體元件是連接在一起。
為了比較，該第一半導體元件是在沒有利用具有貫孔的第二半導體元件之下安裝在該Si底基板之上，而該疊層是在該迴焊爐內被加熱以致於該第一半導體元件與該Si底基板是連接在一起。
具有及不具有第二半導體元件的樣品是被製成。特別地，十個樣品是以該Si底基板和該第一半導體元件是利用該第二半導體元件來連接之如此的方式製成。另外十個樣品是以該Si底基板與該第一半導體元件是在沒有利用該第二半導體元件來連接之如此的方式製成。然後，它們的電氣連接是被測量。結果，使用該第二半導體元件的樣品無電氣連接故障，表示在所有十個樣品中該Si底基板與該第一半導體元件是能夠連接在一起。另一方面，在該十個沒有利用第二半導體元件來形成之樣品中有兩個是出現電氣連接故障。這結果確認利用第二半導體元件把該Si底基板與該第一半導體元件連接的優點。
[例子2]
由樹脂構成之具有突起電極形成於其上之尺寸為35mm x 35mm的一底基板是被準備。該等突起電極具有與第一半導體元件之突起電極相同的尺寸和結構，而且是以與第一半導體元件之突起電極相同的圖案來配置。以上所述的第一半導體元件是利用以上所述的第二半導體元件來安裝在該樹脂底基板之上。
為了達成這樣，首先，形成有貫孔的第二半導體元件是利用一覆晶式黏晶機來安裝在該樹脂底基板之上以致於該第二半導體元件的貫孔和該樹脂底基板的突起電極是對準。接著，該第一半導體元件的突起電極以及該第二半導體元件的貫孔是對準，而該第一半導體元件是利用該覆晶式黏晶機來被安裝。隨後，該疊層該疊層是在氮氣大氣下於一迴焊爐中加熱到240℃以致於該樹脂底基板與該第一半導體元件是連接在一起。
為了比較，該第一半導體元件是在沒有利用具有貫孔的第二半導體元件之下安裝在該樹脂底基板之上，而該疊層是在該迴焊爐內被加熱以致於該第一半導體元件與該樹脂底基板是連接在一起。
具有及不具有第二半導體元件的樣品是被製成。特別地，十個樣品是以該樹脂底基板和該第一半導體元件是利用該第二半導體元件來連接之如此的方式製成。另外十個樣品是以該樹脂底基板與該第一半導體元件是在沒有利用該第二半導體元件來連接之如此的方式製成。然後，它們的電氣連接是被測量。結果，使用該第二半導體元件的樣品無電氣連接故障，表示在所有十個樣品中該樹脂底基板與該第一半導體元件是能夠連接在一起。另一方面，在該十個沒有利用第二半導體元件來形成的樣品中有兩個是出現電氣連接故障。這結果確認利用第二半導體元件把該樹脂底基板與該第一半導體元件連接的優點。
如上所述，一形成有貫孔的基板(半導體元件、樹脂基板、陶瓷基板等等)是介於兩個電子元件(半導體元件、電路板等等)之間，而該兩個電子元件的突起電極是在該等貫孔內部連接在一起。這降低在安裝期間位移的風險並且改進在該等電子元件之間之連接的可靠性。
此外，即使在三個或更多個電子元件被堆疊與連接的情況中，介於中間之電子元件(基板)的貫孔作用如導引者，並且降低該等下電子元件之由在該等電子元件之堆疊期間之負荷、震動、及其他原因而引致之位移的風險。這允許該三個或者更多個堆疊電子元件藉著一次迴焊焊接來被連接，而藉此導致在生產率上的改進。
於此中所述的所有例子和條件語言是傾向於為了幫助讀者了解本發明及由發明人所提供之促進工藝之概念的教育用途，並不是把本發明限制為該等特定例子和條件，且在說明書中之該等例子的組織也不是涉及本發明之優劣的展示。雖然本發明的實施例業已詳細地作描述，應要了解的是，在沒有離開本發明的精神與範疇之下，對於本發明之實施例之各式各樣的改變、替換、與變化是能夠完成。
1．．．半導體裝置
2．．．半導體元件
2a．．．突起電極
3．．．電子元件
3a．．．突起電極
4．．．基板
4a．．．貫孔
10．．．半導體裝置
20．．．半導體元件
20A．．．半導體元件
21．．．突起電極
21A．．．突起電極
21Aa．．．柱部
21a．．．柱部
21b．．．焊接部
30．．．半導體元件
30A．．．半導體元件
31．．．突起電極
31A．．．突起電極
31Aa．．．柱部
31a．．．柱部
31b．．．焊接部
34．．．導線
35．．．導通型電極
36．．．導通型電極
37A．．．導線
40．．．半導體元件
41．．．貫孔
42．．．凸塊
43．．．絕緣薄膜
50．．．連接部
50A．．．連接部
61．．．半導體基體
62．．．元件區域
63．．．佈線層
63a．．．導電部份
63b．．．絕緣部份
63c．．．絕緣部份
64．．．第一佈線層
65．．．第二佈線層
66．．．第三佈線層
67．．．第四佈線層
68．．．電極
69．．．保護薄膜
70．．．樹脂
70A．．．樹脂
100．．．電子裝置
101．．．電路板
102．．．導線
110．．．電子裝置
140．．．半導體裝置
150．．．電路板
151．．．突起電極
151a．．．柱部
151b．．．焊接部
152．．．電極
160．．．連接部
170．．．半導體裝置
170A．．．半導體裝置
180．．．基板
180A．．．基板
181．．．貫孔
182．．．凸塊
182A．．．凸塊
183A．．．導線
184A．．．錫球
190．．．半導體裝置
200．．．半導體裝置
210．．．半導體元件
211．．．突起電極
211a．．．柱部
211b．．．焊接部
212．．．凹坑
212a．．．電極
220．．．半導體元件
221．．．突起電極
221a．．．柱部
221b．．．焊接部
222．．．凹坑
222a．．．電極
223．．．貫孔
230．．．半導體元件
231．．．突起電極
231a．．．柱部
231b．．．焊接部
232．．．凹坑
232a．．．電極
233．．．貫孔
240．．．半導體元件
241．．．突起電極
241a．．．柱部
241b．．．焊接部
251．．．連接部
252．．．連接部
300．．．半導體裝置
310．．．半導體元件
310a．．．電路區域
311．．．突起電極
312．．．凹坑
312a．．．電極
314．．．重繞線
320．．．半導體元件
320a．．．電路區域
321．．．突起電極
322．．．凹坑
322a．．．電極
323．．．貫孔
324．．．重繞線
330．．．半導體元件
330a．．．電路區域
331．．．突起電極
332．．．凹坑
332a．．．電極
333．．．貫孔
334．．．重繞線
340．．．半導體元件
340a．．．電路區域
341．．．突起電極
344．．．重繞線
351．．．連接部
352．．．連接部
400．．．半導體元件
400a．．．半導體元件
401．．．突起電極
401a．．．柱部
401b．．．焊接部
403．．．貫孔
403a．．．孔洞
404‧‧‧絕緣薄膜
500‧‧‧黏著劑
501‧‧‧支撐基板
502‧‧‧光阻
502a‧‧‧開孔
503‧‧‧黏著劑
504‧‧‧支撐基板
600‧‧‧半導體元件
600a‧‧‧半導體元件
600b‧‧‧半導體元件
601‧‧‧突起電極
601a‧‧‧柱部
601b‧‧‧焊接部
603‧‧‧貫孔
604‧‧‧絕緣薄膜
605‧‧‧種子層
606‧‧‧重繞線
607‧‧‧突起電極
607a‧‧‧柱部
607b‧‧‧焊接部
608‧‧‧凹坑
609‧‧‧電極
700‧‧‧黏著劑
701‧‧‧支撐基板
702‧‧‧光阻
702a‧‧‧開孔
703‧‧‧光阻
703a‧‧‧開孔
704‧‧‧光阻
704a‧‧‧開孔
705‧‧‧光阻
705a‧‧‧開孔
810‧‧‧半導體元件
811‧‧‧突起電極
811A‧‧‧金屬凸塊
811a‧‧‧柱部
811b‧‧‧焊接部
820‧‧‧電子元件
821‧‧‧突起電極
821a‧‧‧柱部
821b‧‧‧焊接部
830‧‧‧基板
831‧‧‧貫孔
831A‧‧‧貫孔
831B‧‧‧貫孔
831C‧‧‧貫孔
832‧‧‧凸塊
第1圖描繪一半導體裝置的範例結構；
第2A至2C圖描繪第一實施例的第一範例半導體裝置；
第3圖描繪一突起電極及其附近的範例結構；
第4A和4B圖描繪無中間半導體元件被使用的第一情況；
第5圖描繪無中間半導體元件被使用的第二情況；
第6A和6B圖描繪無中間半導體元件被使用的第三情況；
第7圖描繪該第一實施例的第二範例半導體裝置；
第8圖描繪該第一實施例的第三範例半導體裝置；
第9圖描繪一第一電子裝置的範例結構；
第10圖描繪一第二電子裝置的範例結構；
第11A和11B圖描繪第二實施例的範例半導體裝置；
第12圖描繪第三實施例的第一範例半導體裝置；
第13圖描繪該第三實施例的第二範例半導體裝置；
第14圖描繪該第三實施例之半導體裝置的範例結構；
第15A至15D圖描繪一種形成該第三實施例之半導體裝置的範例方法；
第16A至16C圖描繪該在第15A至15D圖中所示之形成該第三實施例之半導體裝置之範例方法的連續步驟；
第17A和17B圖描繪第四實施例的範例半導體裝置；
第18圖描繪該第四實施例之半導體裝置的範例結構；
第19A至19C圖描繪一具有貫孔之範例半導體元件的第一形成步驟；
第20A至20C圖描繪該具有貫孔之範例半導體元件的第二形成步驟；
第21A至21C圖描繪該具有貫孔之範例半導體元件的第三形成步驟；
第22A至22C圖描繪另一具有貫孔之範例半導體元件的第一形成步驟；
第23A至23C圖描繪該具有貫孔之另一範例半導體元件的第二形成步驟；
第24A至24C圖描繪該具有貫孔之另一範例半導體元件的第三形成步驟；
第25A至25C圖描繪該具有貫孔之另一範例半導體元件的第四形成步驟；
第26A至26C圖描繪該具有貫孔之另一範例半導體元件的第五形成步驟；
第27A至27C圖描繪該具有貫孔之另一範例半導體元件的第六形成步驟；
第28A至28C圖描繪一具有貫孔與凹坑之範例半導體元件的第一形成步驟；
第29A至29C圖描繪該具有貫孔與凹坑之範例半導體元件的第二形成步驟；
第30A至30C圖描繪該具有貫孔與凹坑之範例半導體元件的第三形成步驟；
第31A至31C圖描繪該具有貫孔與凹坑之範例半導體元件的第四形成步驟；
第32A至32C圖描繪該具有貫孔與凹坑之範例半導體元件的第五形成步驟；
第33A和33B圖描繪一第一變化；
第34圖描繪一第二變化；
第35A和35B圖描繪一第三變化；
第36A至36C圖描繪一第四變化；及
第37A和37B圖描繪一第五變化。
10．．．半導體裝置
20．．．半導體元件
21．．．突起電極
21a．．．柱部
30．．．半導體元件
31．．．突起電極
31a．．．柱部
40．．．半導體元件
41．．．貫孔
42．．．凸塊
50．．．連接部

Claims (18)

  1. 一種半導體裝置，包含：一具有一第一表面與一從該第一表面突起之第一電極的第一半導體元件；一具有一第二表面與一從該第二表面突起之第二電極的電子元件；及一置於該第一表面與該第二表面之間的基板，其中該基板具有與該第一表面相對之一第三表面、與該第二表面相對之一第四表面和在該第三表面與該第四表面之間的一第一貫孔；該第一電極與該第二電極是被插入在該第一貫孔中並且在該第一貫孔內部連接在一起；以及該第二表面與該第四表面是有間隔的。
  2. 如申請專利範圍第1項所述之半導體裝置，其中，該第一貫孔的一側壁是被隔離。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第一半導體元件具有一第二貫孔，且該基板具有一從該第三表面突起且被插入在該第二貫孔內的第三電極。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該電子元件具有一凹坑，且該基板具有一從該第四表面突起且被插入在該凹坑內的第四電極。
  5. 如申請專利範圍第1項所述之半導體裝置，其中 該第一電極具有一第一柱部，該第二電極具有一第二柱部，及一個把該第一柱部之末端與該第二柱部之末端連接在一起的連接部是存在於該第一貫孔內部。
  6. 如申請專利範圍第1項所述之半導體裝置，其中，該電子元件是為一第二半導體元件。
  7. 如申請專利範圍第1項所述之半導體裝置，其中，該電子元件是為一電路板。
  8. 如申請專利範圍第1項所述之半導體裝置，其中，該基板是為一第三半導體元件。
  9. 如申請專利範圍第1項所述之半導體裝置，其中，該基板是為一電路板、一樹脂基板、或一陶瓷基板。
  10. 如申請專利範圍第1項所述之半導體裝置，其中，在該第一半導體元件與該電子元件之間的空間和在該第一貫孔內部的空間是由一絕緣元件填充。
  11. 如申請專利範圍第1項所述之半導體裝置，其中，該第一電極的直徑和該第二電極的直徑是比該第一貫孔的直徑小。
  12. 如申請專利範圍第1項所述之半導體裝置，其中，該第一電極與該第二電極中之一者或兩者是為一金屬凸塊。
  13. 如申請專利範圍第1項所述之半導體裝置，其中，該基板具有一電氣連接到該第一半導體元件與該電子元件中之一者或兩者的導電部份。
  14. 一種製造半導體裝置的方法，該方法包含： 把一具有一第三表面、一第四表面和在該第三表面與該第四表面之間的一第一貫孔的基板置於一電子元件之上，該電子元件具有與該第四表面相對之一第二表面及一從該第二表面突起的第二電極，以致於該第二電極是被插入在該第一貫孔內；把一具有與該第三表面相對之一第一表面及一從該第一表面突起之第一電極的半導體元件置於該基板之上，以致於該第一電極是被插入在該第一貫孔內；及在該第一貫孔內部連接被插入在該第一貫孔內之該第一電極與被插入在該第一貫孔內之該第二電極；其中該第二表面與該第四表面是有間隔的。
  15. 如申請專利範圍第14項所述之方法，其中該半導體元件具有一第二貫孔，該基板具有一從該第三表面突起之第三電極，及該半導體元件於該基板之上的置放包括在該第一電極被插入在該第一貫孔中時把該第三電極插入在該第二貫孔中。
  16. 如申請專利範圍第14項所述之方法，其中該電子元件具有一凹坑，該基板具有一從該第四表面突起之第四電極，及該基板於該電子元件之上的置放包括在該第二電極被插入至該第一貫孔內時把該第四電極插入該凹坑內。
  17. 如申請專利範圍第14項所述之方法，其中該第一電極與該第二電極在一起的連接包括藉著一 連接部來把一被包括在該第一電極內之第一柱部的末端與一被包括在該第二電極內之第二柱部的末端在該第一貫孔內部連接在一起。
  18. 一種電子裝置，包含：一半導體裝置；及一電路板，該半導體裝置是安裝在該電路板之上，其中該半導體裝置包括一具有一第一表面與一從該第一表面突起之第一電極的半導體元件，一具有一第二表面與一從該第二表面突起之第二電極的電子元件，及一置於該第一表面與該第二表面之間的基板，該基板具有與該第一表面相對之一第三表面、與該第二表面相對之一第四表面和在該第三表面與該第四表面之間的一貫孔，該第一電極與該第二電極是被插入在該貫孔中並且在該貫孔內部連接在一起，以及該第二表面與該第四表面是有間隔的。
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