TWI486941B - Reset apparatus and method thereof for a display - Google Patents

Description

Display reset device and operation method thereof

The present invention relates to a reset device, and more particularly to a display reset device that can quickly eliminate image sticking after the flat display is turned off.

Generally, a flat panel display uses a driving circuit to control the generation of grayscale signals of a plurality of pixels (Pixel) on the panel of the flat panel display. The driving module mainly includes a gate driver (Gate Driver) electrically connected to the plurality of scanning lines (or gate lines) to respectively output a gate pulse signal (Gate Pulse Signal) to each corresponding pixel, and a source The source driver is electrically connected to the plurality of data lines to respectively transmit a data signal to each corresponding pixel, and each of the scanning lines and each of the data lines are respectively connected with an active element of a corresponding pixel. The two polar ends (such as the gate and source of the thin film transistor). When the gate driver sequentially outputs the gate pulse signals to turn on the thin film transistors connected to each of the scan lines one by one, the source driver simultaneously outputs corresponding data signals to store the thin film transistors on the data lines. The capacitor (Cs) and the liquid crystal capacitor (Clc) are charged to the desired pixel potential to display different gray levels.

However, due to the charging relationship, the conventional flat panel display accumulates electric charge in the liquid crystal capacitor between the two corresponding electrodes (such as the common electrode and the display electrode) after being displayed for a long time, so as to maintain the electric potential at a specific pixel potential; At this time, if the power supply of the flat panel display is turned off (Power off), some of the last image may remain on the instant screen. This phenomenon not only does not meet the user's visual expectation, but also reduces the display of the flat panel display panel. Show quality.

In order to solve the phenomenon of shutdown afterimage, a reset circuit is usually used. At the moment after the system is turned off, the output of each data line is grounded or connected to a common voltage, so that the charge stored in the liquid crystal capacitor is reset. The reset path provided by the circuit is released. However, the reset circuit alone, after all, provides a limited reset path, and the efficiency of releasing the charge is not good, resulting in the problem that the afterimage is not completely eliminated. And if you want to increase the reset path, it is necessary to increase the reset circuit area, which in turn affects the overall size of the flat panel display.

The present invention provides a reset device for avoiding the problem that the residual image is not completely eliminated due to insufficient number of reset paths of a single reset circuit after the flat display is turned off.

According to one aspect of the present invention, a reset device for a display is provided, wherein the display includes a source driver for driving a plurality of data lines. The reset device includes: a charge sharing circuit and a reset controller. The charge sharing circuit is coupled to the source driver, and the reset controller is coupled to the charge sharing circuit. When the reset signal resets the display, the reset controller activates the charge sharing circuit to provide a charge discharge according to the reset signal. path.

In an embodiment of the present invention, the charge sharing circuit further includes a plurality of first transmission gates and a plurality of second transmission gates, the first transmission gate being coupled between a data line and a common electrode line, and the second transmission gate It is coupled between two data lines, so that the data lines are grouped in pairs. Each of the first transmission gate and the second transmission gate further includes: a first switch and a second switch connected in parallel The first switch is coupled to the first switch.

In an embodiment of the present invention, the resetter controller further includes: an OR gate and an inverter coupled to the OR gate, wherein the OR gate generates a first ON signal according to the reset signal, and the reverse The phase inversion of the first open signal generates a second turn-on signal, wherein the first turn-on signal turns on the first switch, and the second turn-on signal turns on the second switch, so that the data connected to the first transfer gate is The line is electrically connected to the common electrode line.

In an embodiment of the invention, the resetter controller further includes: a reverse OR gate, a first inverter coupled to the reverse gate, a switch, and a second inverter coupled switch. The reverse gate generates a first turn-on signal according to the reset signal, and the first inverter inverts the first turn-on signal to generate a second turn-on signal, and the switch generates a third turn-on signal according to the reset signal, and The second inverter inverts the third turn-on signal to generate a fourth turn-on signal, wherein the first turn-on signal turns on the first switch of the first transfer gate, and the second turn-on signal turns on the second switch of the first transfer gate, The third turn-on signal turns off the first switch of the second transfer gate, and the fourth turn-on signal turns off the second switch of the second transfer gate, so that the data line connecting the first transfer gate is electrically connected to the common electrode line.

In an embodiment of the invention, the common electrode line includes a first common electrode line and a second common electrode line, and a switcher switches the first common electrode line and the second common electrode line respectively connected to a first voltage and A second voltage, or a common voltage, is connected to a common voltage, wherein the first voltage, the second voltage, or the common voltage is a gamma voltage.

In an embodiment of the present invention, the switch connects the first common electrode line and the second common electrode line to the first voltage and the first according to the reset signal The two voltages, or are commonly connected to a common voltage.

In an embodiment of the invention, the switch connects the first common electrode line and the second common electrode line to the first voltage and the second voltage respectively according to the reset signal and a liquid crystal polarity switching signal (POL), or is connected in common At a common voltage.

According to another aspect of the present invention, a reset method of a display is provided, wherein the display includes at least one source driver for driving a plurality of data lines, and a charge sharing circuit coupled to the source driver, the method comprising: generating a reset signal to reset the display; and initiating the charge sharing circuit to provide a charge discharge path according to the reset signal.

Accordingly, the reset path of the present invention is provided by the charge sharing circuit. In addition to increasing the release charge path, since the added reset path is provided by the charge sharing circuit, no additional reset path is required, and thus This will result in an increase in the overall volume of the flat panel display.

The following description of the preferred embodiments of the invention is in the

1 is a schematic illustration of a flat panel display in accordance with a preferred embodiment of the present invention. It should be noted that only the portion of the flat panel display 100 that is more relevant to the present invention is shown in FIG. 1. The flat panel display 100 actually has other components, such as a gate driver, a timing control circuit, etc., for convenience of explanation. For the sake of this, it will be omitted here.

The flat panel display 100 includes: a source driver 110, a reset device 120 and a display panel 130. A timing controller TCON (not shown) generates various control signals to the source driver 110 and the gate driver (not shown) to control the operation of the source driver 110 and the gate driver (not shown). Under the control of the control signal, a gate driver (not shown) sequentially drives each gate line, and then the source driver 110 outputs the data voltage to the reset device 120 and the display panel 130 through the plurality of data lines 1101 to 110n.

The reset device 120 further includes: a charge sharing circuit 121 and a resetter controller 123. The charge sharing circuit 121 is coupled to the source driver 110, and the reset controller 123 receives a reset signal or a charge sharing signal to control the operation of the charge sharing circuit 121. For example, when a reset signal resets the flat panel display 100, the reset signal is also transmitted to the reset controller 123, and the reset controller 123 activates the charge sharing circuit 121 according to the reset signal to provide A reset path, or a charge discharge path, at which time the charge stored in the liquid crystal capacitor of the display panel 130 can be discharged through the charge sharing circuit 121. Since the reset path of the present case is provided by the inherent circuit, the charge sharing circuit 121, there is no need to additionally set the reset circuit, and therefore, the volume of the transmission channel between the source driver 110 and the display panel 130 can be reduced. And in the embodiment in which the charge sharing circuit 121 is directly constructed in the source driver 110, the overall source driver volume can be greatly reduced.

The charge sharing circuit 121 further includes a plurality of first transfer gates 1211 and a plurality of second transfer gates 1212. The first transmission gate 1211 is coupled between a data line and a first common electrode line V _com1 or a second common electrode line V _com2 , and the second transmission gate 1212 is coupled to two data lines. Between the two data lines are grouped in pairs. For example, taking the data lines 1101, 1102, 1103, and 1104 as an example, the four first transmission gates 1211 are respectively coupled between the data line 1101 and the first common electrode line V _com1 , the data line 1102, and the second common electrode line. Between V _{com2 ,} between the data line 1103 and the first common electrode line V _com1 , and between the data line 1104 and the second common electrode line V _com2 . The two second transmission gates 1212 are respectively coupled between the data lines 1101 and 1102 and between the data lines 1103 and 1104, so that the data lines 1101, 1102, 1103 and 1104 are divided into data lines 1101 and 1102, and data lines. Two groups of 1103 and 1104. In a preferred embodiment, the first transmission gate 1211 and the second transmission 1212 gate have the same circuit structure, and are respectively composed of a first switch 1213 and a second switch 1214 coupled to the first switch 1213. The first switch 1213 is, for example, a P-type transistor switch; and the second switch 1214 is, for example, an N-type transistor switch.

In an embodiment, as shown in FIG. 2A, the first common electrode line _Vcom1 and the second common electrode line _Vcom2 are connected in common to a switch 200. The switch 200 includes at least two switching elements 201 coupled to the first common electrode line V _com1 and the second common electrode line V _{com2 , respectively} . Through the switching of the switching element 201, allowing the first common electrode and a first line V _com1 gamma voltage (Gamma voltage) coupled to the second common electrode line V _com2 may be coupled to a second gamma voltage. Or the first common electrode line V _com1 and the second common electrode line V _{com2 are} coupled together with a first gamma voltage or a second gamma voltage. Alternatively, the first common electrode line V _com1 and the second common electrode line V _{com2 are} commonly coupled to a single voltage Vss. The first gamma voltage and the second gamma voltage are close to the intermediate gamma voltage.

In an embodiment, as shown in FIG. 2B, each switching element 201, They are formed by a P-type transistor 2011 and an n-type transistor 2012, respectively. The P-type transistor 2011 is switched by a control signal A, and the n-type transistor 2012 is switched by a control signal B. Accordingly, when the control signal A is at a high level and the control signal B is at a low level, the switching element 201 is not turned on; conversely, when the control signal A is at a low level and the control signal B is at a high level, the switching element 201 is turned on.

In an embodiment, the conduction state of the switching element 201 can be controlled according to a reset signal. As shown in FIG. 2C, a reset signal generates a control signal A via an inverter, and the control signal A passes through another An inverter generates a control signal B to thereby control the conduction state of the switching element 201.

In another embodiment, the conduction state of the switching element 201 can be controlled according to a reset signal and a liquid crystal polarity switching signal (POL). As shown in FIG. 2D, the reset signal and the liquid crystal polarity switching signal (POL) are transmitted via a The inverse gate generates a control signal A, which in turn generates a control signal B via an inverter, thereby controlling the conduction state of the switching element 201.

Figure 3 is a diagrammatic view of a reset controller in accordance with an embodiment. The reset controller 123 is composed of a NOR gate 1231, a first inverter 1232, a second inverter 1233, and a switch 1234. The inverse gate 1231 receives the reset signal or the charge sharing signal, and generates a first turn-on signal according to the reset signal or the charge sharing signal. The inverter 1232 inverts the first turn-on signal to generate a second turn-on signal. The first open signal and the second open signal are transmitted to the charge sharing circuit 121 to control the first switch 1213 and the second switch 1214 in the first transfer gate 1211 to be turned on during reset or during charge sharing to provide a reset path. Or carry out charge sharing. In addition, the switch 1234 selects a reset signal or charge sharing The signal acts as a third turn-on signal. The inverter 1233 inverts the third turn-on signal to generate a fourth turn-on signal. The third open signal and the fourth open signal are transmitted to the charge sharing circuit 121 to control the first switch 1213 and the second switch 1214 in the second transfer gate 1212 to be turned off during reset, and during charge sharing, the control The first switch 1213 and the second switch 1214 of the second transfer gate 1212 are turned on, so that adjacent data lines 1101 and 1102 are connected in series to provide charge sharing.

In an embodiment, when resetting, the reset signal is a high level signal and the charge sharing signal is a low level signal, when the flat display 100 is reset by a reset signal (reset) The reset signal is transmitted to the reset controller 123, wherein the inverse OR gate 1231 generates a low-order first turn-on signal based on the high-order reset signal. The inverter 1232 inverts the low-order first turn-on signal to generate a high-order second turn-on signal. The first turn-on signal and the second turn-on signal are jointly transmitted to the first transfer gate 1211 of the charge sharing circuit 121, wherein the low-order first turn-on signal controls the P-type first switch 1213 in the first transfer gate 1211 to be turned on, and The high-order second turn-on signal controls the N-type second switch 1214 in the first transfer gate 1211 to be turned on, thereby being reset through the first common electrode line _Vcom1 and the second common electrode line _Vcom2 . In addition, the switch 1234 selects a reset signal and generates a high-order third turn-on signal, and the inverter 1232 inverts the high-order third turn-on signal to generate a low-order fourth turn-on signal. The third open signal and the fourth open signal are jointly transmitted to the second transfer gate 1212 of the charge sharing circuit 121, wherein the third-order high turn signal controls the P-type first switch 1213 in the second transfer gate 1212 to be turned off, and the low order The fourth turn-on signal controls the N-type second switch 1214 in the second transfer gate 1212 to be turned off.

On the other hand, in the charge sharing period, the reset signal is a low level signal, and the charge sharing signal is a high level signal. At this time, the inverse gate 1231 in the reset controller 123 is based on This higher order shared signal produces a low order first turn-on signal. The inverter 1232 inverts the low-order first turn-on signal to generate a high-order second turn-on signal. The first turn-on signal and the second turn-on signal are jointly transmitted to the first transfer gate 1211 of the charge sharing circuit 121, wherein the low-order first turn-on signal controls the P-type first switch 1213 in the first transfer gate 1211 to be turned on, and The high-order second turn-on signal controls the N-type second switch 1214 in the first transfer gate 1211 to be turned on. In addition, the switch 1234 selects a low-order reset signal and generates a low-order third turn-on signal, and the inverter 1232 inverts the low-order third turn-on signal to generate a high-order fourth turn-on signal. The third turn-on signal and the fourth turn-on signal are jointly transmitted to the second transfer gate 1212 of the charge sharing circuit 121, wherein the low-order third turn-on signal controls the P-type first switch 1213 in the second transfer gate 1212 to be turned on, and the high order The fourth turn-on signal controls the N-type second switch 1214 in the second transfer gate 1212 to be turned on, causing charge sharing between the data lines 1101 and 1102 due to the short circuit, and converges to a common state through the first transfer gate 1211. Voltage.

Figure 4 is a diagrammatic view of a reset controller in accordance with another embodiment. The reset controller 123 is composed of an OR gate 1236 and an inverter 1237 coupled to the OR gate 1236. The OR gate 1236 receives a reset signal and a charge sharing signal, and generates a first turn-on signal according to the reset signal or the charge sharing signal. The inverter 1237 inverts the first turn-on signal to generate a second turn-on signal. The first enable signal and the second open signal are transmitted to the charge sharing circuit 121 to control the first transmission during the reset period. The first switch 1213 and the second switch 1214 of the gate 1211 and the second transfer 1212 are turned on to provide a reset path or to provide a charge sharing path during charge sharing.

Figure 5 is a flow chart showing the resetting of a flat panel display in accordance with a preferred embodiment. As shown in FIG. 1 , the flat panel display 100 includes a source driver 110 , a reset device 120 , and a display panel 130 . The reset device 120 further includes: a charge sharing circuit 121 and a resetter controller 123. According to this flow, first in step 201, a reset signal is generated to reset the flat panel display 100. Next, in step 202, the charge sharing circuit 121 is activated according to the reset signal to provide a charge discharge path.

In summary, the present invention activates a charge sharing circuit to provide a reset path when the flat display is turned off, in addition to speeding up the charge release, since the added reset path is an inherent circuit, a charge sharing circuit. Provided, no additional setup reset path is required, so the overall volume of the flat panel display is not increased.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧ flat panel display

110‧‧‧Source Driver

120‧‧‧Reset device

121‧‧‧Charge sharing circuit

123‧‧‧Reset controller

130‧‧‧ display panel

1101~110n‧‧‧ data line

1211‧‧‧First transmission gate

1212‧‧‧Second transmission gate

1213‧‧‧First switch

1214‧‧‧second switch

1221~122n‧‧‧Switch

1231‧‧‧Anti-gate

1232‧‧‧First Inverter

1233‧‧‧Second inverter

200 and 1234‧‧‧Switches

201‧‧‧Switching components

2011‧‧‧P type transistor

2012‧‧‧n type transistor

1236‧‧‧ or gate

1237‧‧‧Inverter

201~202‧‧‧Steps

V _com1 ‧‧‧first common electrode line

V _com2 ‧‧‧second common electrode line

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; Show.

Fig. 2A is a schematic diagram showing a switch for switching the first common electrode line _Vcom1 and the second common electrode line _Vcom2 .

Figure 2B shows a schematic representation of a switching element.

Fig. 2C is a schematic diagram showing the control of the conduction state of the switching element by the reset signal.

Fig. 2D is a schematic diagram showing the control of the conduction state of the switching element by the reset signal and the liquid crystal polarity switching signal (POL).

Figure 3 is a schematic diagram of a reset controller in accordance with an embodiment of the present invention.

Fig. 4 is a schematic view showing a reset controller according to another embodiment of the present invention.

Figure 5 is a flow chart showing the resetting of a flat panel display in accordance with a preferred embodiment.

100‧‧‧ flat panel display

110‧‧‧Source Driver

120‧‧‧Reset device

121‧‧‧Charge sharing circuit

123‧‧‧Reset controller

130‧‧‧ display panel

1101~110n‧‧‧ data line

1211‧‧‧First transmission gate

1212‧‧‧Second transmission gate

1213‧‧‧First switch

1214‧‧‧second switch

Claims (9)

A display reset device, wherein the display includes at least one source driver for driving a plurality of data lines, the reset device comprising: a charge sharing circuit coupled to the source driver, the charge sharing circuit further comprising a plurality of a transmission gate and a plurality of second transmission gates, each of the first transmission gates being coupled between a data line and a common electrode line, each of the second transmission gates being coupled between the two data lines Each of the first transmission gates and each of the second transmission gates further includes a first switch and a second switch, the second switch being coupled to the first switch; and a resetter control The resetter controller includes: a reverse gate, receiving a reset signal and a charge sharing signal, and the inverse gate generates a first turn-on signal according to the reset signal; The first inverter is coupled to the reverse or gate, the first inverter inverts the first turn-on signal to generate a second turn-on signal; a switch receives the reset signal and the charge share signal, according to the Reset signal to generate a Turning on the signal; and a second inverter is coupled to the switch, inverting the third open signal to generate a fourth turn-on signal, wherein when the reset signal resets the display, the reset signal is located at a a first order, the charge sharing signal is located at a second level, the first turn-on signal turns on the first switch of the first transfer gate, and the second turn-on signal turns on the second switch of the first transfer gate, the third The opening signal turns off the first switch of the second transmission gate, and the fourth opening signal turns off the second switch of the second transmission gate, so that the first connection is connected The data line of the transmission gate is electrically connected to the common electrode line, wherein during a charge sharing, the reset signal is located at the second level, the charge sharing signal is located at the first level, and the first opening signal turns on the first transmission a first switch of the gate, the second turn-on signal turns on the second switch of the first transfer gate, the third turn-on signal turns on the first switch of the second transfer gate, and the fourth turn-on signal turns on the second switch The second switch of the transmission gate causes the data lines to generate charge sharing and converge to a common voltage through the first transmission gates. The reset device of claim 1, wherein the common electrode line further comprises a first common electrode line and a second common electrode line, and a switch is coupled to the first common electrode line and the second common electrode line The first common electrode line and the second common electrode line are respectively connected to a first voltage and a second voltage, or are commonly connected to the common voltage. The reset device of claim 2, wherein the first voltage, the second voltage, or the common voltage is a gamma voltage. The reset device of claim 2, wherein the switch connects the first common electrode line and the second common electrode line to the first voltage and the second voltage respectively according to the reset signal, or is connected in common At the common voltage. The reset device of claim 2, wherein the switcher first shares the first common according to the reset signal and a liquid crystal polarity switching signal (POL) The electrode line and the second common electrode line are respectively connected to the first voltage and the second voltage, or are commonly connected to the common voltage. A reset method for a display, wherein the display includes at least one source driver for driving a plurality of data lines, and a charge sharing circuit coupled to the source driver, the charge sharing circuit including a plurality of first transfer gates and a plurality of a second transmission gate, each of the first transmission gates being coupled between a data line and a common electrode line, each of the second transmission gates being coupled between the two data lines, each of the first The transmission gate and each of the second transmission gates further include a first switch and a second switch. The second switch is coupled to the first switch. The method includes: generating a reset signal and sharing a charge Transmitting a first turn-on signal according to the reset signal and the charge share signal through a reverse OR gate; inverting the first turn-on signal to generate a second turn-on signal; generating a third according to the reset signal Turning on the signal; inverting the third turn-on signal to generate a fourth turn-on signal; when the reset signal resets the display, setting the reset signal to be at a first level, the charge-sharing signal is located at a first a first switch that turns on the first switch of the first transfer gate, the second turn-on signal turns on the second switch of the first transfer gate, and the third turn-on signal turns off the second transfer gate a first switch, the fourth open signal turns off the second switch of the second transfer gate, and causes the data line connecting the first transfer gate to be turned on with the common electrode line; and during a charge sharing, setting the weight The signal is in the second place Step, the charge sharing signal is located at the first level, such that the first turn-on signal turns on the first switch of the first transfer gate, and the second turn-on signal turns on the second switch of the first transfer gate, the third The turn-on signal turns on the first switch of the second transfer gate, and the fourth turn-on signal turns on the second switch of the second transfer gate, so that the data lines generate charge sharing and converge to one through the first transfer gates Common voltage. The method of claim 6, wherein the common electrode line comprises a first common electrode line and a second common electrode line, and the switching the first common electrode line and the second common electrode line are respectively connected to a first The voltage and a second voltage are or are commonly connected to the common voltage, wherein the first voltage, the second voltage or the common voltage is a gamma voltage. The method of claim 7, further comprising connecting the first common electrode line and the second common electrode line to the first voltage and the second voltage respectively according to the reset signal, or jointly connected to the common voltage . The method of claim 7, further comprising connecting the first common electrode line and the second common electrode line to the first voltage and the second according to the reset signal and a liquid crystal polarity switching signal (POL) The voltage, or common to the common voltage.