TWI486757B - Power configuring device and method thereof - Google Patents

Power configuring device and method thereof Download PDF

Info

Publication number
TWI486757B
TWI486757B TW098134851A TW98134851A TWI486757B TW I486757 B TWI486757 B TW I486757B TW 098134851 A TW098134851 A TW 098134851A TW 98134851 A TW98134851 A TW 98134851A TW I486757 B TWI486757 B TW I486757B
Authority
TW
Taiwan
Prior art keywords
signal
frequency
reset
frequency signal
built
Prior art date
Application number
TW098134851A
Other languages
Chinese (zh)
Other versions
TW201113693A (en
Inventor
Hung Chang Chen
Hao Yuan Hsiao
Original Assignee
Holtek Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Holtek Semiconductor Inc filed Critical Holtek Semiconductor Inc
Priority to TW098134851A priority Critical patent/TWI486757B/en
Publication of TW201113693A publication Critical patent/TW201113693A/en
Application granted granted Critical
Publication of TWI486757B publication Critical patent/TWI486757B/en

Links

Description

調整功率消耗的裝置及其方法Device and method for adjusting power consumption

本發明係相關於調整功率消耗的裝置及其方法。尤指用於功率放大器、數位/類比轉換器與類比/數位轉換器中的調整功率消耗的裝置及其方法。The present invention relates to an apparatus and method for adjusting power consumption. In particular, devices and methods for adjusting power consumption in power amplifiers, digital/analog converters, and analog/digital converters.

在傳統的電路中,其中一種實現調整功率消耗的方式是如美國專利公開第2007/013628號,判定目前狀態為追蹤或維持(track/hold),在依據判斷的結果,決定要類比/數位轉換器所需供給的電流量,其中耗電量最大的元件為預先放大器(Preamp),故在判定track/hold狀態後將Preamp的偏壓電流關閉,等到track/hold即將結束時再將Preamp打開,以進行資料轉換,這樣可省下track/hold時的功率消耗。In a conventional circuit, one of the ways to achieve adjustment of power consumption is, for example, US Patent Publication No. 2007/013628, which determines that the current state is tracking/holding, and determines the analog/digital conversion according to the result of the judgment. The amount of current required to supply the device, wherein the component that consumes the most power is a preamp, so the bias current of the Preamp is turned off after determining the track/hold state, and the Preamp is turned on when the track/hold is about to end. For data conversion, this saves power consumption in track/hold.

然而這樣的方法僅能省下在track/hold時所消耗的功率,而眾所皆知的是速度與功率消耗間具有正比的關係,因此欲處理高速的訊號時,就必須消耗更多的功率,若處理低速的訊號時,對於消耗功率的需求即可減少,而前述的方法並未將所欲處理的訊號之速度納入考量,無形中在處理低速的訊號時,消耗了不必要的功率。However, such a method can only save the power consumed in the track/hold, and it is well known that there is a proportional relationship between speed and power consumption, so when processing high-speed signals, it must consume more power. If the low-speed signal is processed, the power consumption requirement can be reduced, and the foregoing method does not take into consideration the speed of the signal to be processed, and invisibly consumes unnecessary power when processing the low-speed signal.

而美國專利第6185454號利用偵測數位訊號處理(DSP)輸入訊號的快慢,來改變所使用的電源電壓值,藉以達到降低功率消耗的目的,但其偵測頻率後需再提供多組電源或是改變其他線路特性。U.S. Patent No. 6,185,454 uses the detection of the speed of the digital signal processing (DSP) input signal to change the value of the power supply voltage used, thereby reducing the power consumption, but after the detection frequency, multiple sets of power supply or It is to change other line characteristics.

職是之故,申請人鑑於習知技術中所產生之缺失,經過悉心試驗與研究,並一本鍥而不捨之精神,終構思出本案「調整功率消耗的裝置及其方法」,能夠克服上述缺點,以下為本案之簡要說明。For the sake of the job, the applicant has been able to overcome the above shortcomings in the light of the lack of knowledge in the prior art, through careful experimentation and research, and the spirit of perseverance, and finally conceived the "device and method for adjusting power consumption". The following is a brief description of the case.

本發明提出一種控制功率消耗的方法與裝置,使主電路本身隨著操作速率或是隨著所欲處理的訊號之速度或頻率的不同,調整其所需偏壓電流以提供所需功率,避免浪額外的功率,以改善功率的消耗,且無需提供多組電源或改變其他電路特性。The invention provides a method and device for controlling power consumption, so that the main circuit itself adjusts its required bias current to provide the required power according to the operation rate or the speed or frequency of the signal to be processed, thereby avoiding Additional power is added to improve power consumption without the need to provide multiple sets of power supplies or to change other circuit characteristics.

根據本發明的第一構想,提供一種調整功率消耗的方法,包含下列步驟:(a)提供一系統頻率訊號;(b)產生對應於該系統頻率訊號的一數值;以及(c)依據該數值調整功率消耗。According to a first aspect of the present invention, there is provided a method of adjusting power consumption, comprising the steps of: (a) providing a system frequency signal; (b) generating a value corresponding to the system frequency signal; and (c) determining the value Adjust power consumption.

較佳地,本發明所提供調整功率消耗的方法,其中步驟(b)更包括下列步驟:(b1)提供一內建頻率訊號;以及(b2)偵測該內建頻率訊號的頻率與該系統頻率訊號的頻率兩者間之一比值作為該數值。Preferably, the present invention provides a method for adjusting power consumption, wherein step (b) further comprises the steps of: (b1) providing a built-in frequency signal; and (b2) detecting a frequency of the built-in frequency signal and the system A ratio between the frequencies of the frequency signals is taken as the value.

較佳地,本發明所提供調整功率消耗的方法,其中若該內建頻率訊號的頻率小於該系統頻率訊號的頻率,則該比值為該內建頻率訊號的一期間內,該系統頻率訊號所發生一震盪次數,若該內建頻率訊號的頻率大於該系統頻率訊號的頻率,則該比值為該系統頻率訊號的一期間內,該內建頻率訊號所發生的震盪次數。Preferably, the method for adjusting power consumption is provided by the present invention, wherein if the frequency of the built-in frequency signal is less than the frequency of the system frequency signal, the ratio is the period of the built-in frequency signal, and the system frequency signal is A frequency of occurrence occurs. If the frequency of the built-in frequency signal is greater than the frequency of the system frequency signal, the ratio is the number of oscillations of the built-in frequency signal during a period of the system frequency signal.

較佳地,本發明所提供調整功率消耗的方法,其中該期間是一高電位期間。Preferably, the present invention provides a method of adjusting power consumption wherein the period is a high potential period.

較佳地,本發明所提供調整功率消耗的方法,其中該期間是一低電位期間。Preferably, the present invention provides a method of adjusting power consumption wherein the period is a low potential period.

較佳地,本發明所提供調整功率消耗的方法,其中該期間是一週期。Preferably, the present invention provides a method of adjusting power consumption, wherein the period is a period.

較佳地,本發明所提供調整功率消耗的方法,其中步驟(c)更包括一步驟(c1)依據該數值來產生一電流量,以調整功率消耗。Preferably, the present invention provides a method for adjusting power consumption, wherein step (c) further comprises a step (c1) of generating a current amount according to the value to adjust power consumption.

較佳地,本發明所提供調整功率消耗的方法,其中步驟(c1)是將該數值解碼以產生一控制訊號,並依據該控制訊號來產生該電流量。Preferably, the present invention provides a method for adjusting power consumption, wherein step (c1) decodes the value to generate a control signal, and generates the current amount according to the control signal.

根據本發明的第二構想,提供一種調整功率消耗的裝置,該裝置包括:一頻率偵測器,其接收一系統頻率訊號與一內建頻率訊號,並產生一輸出訊號;以及一偏壓控制器,接收該輸出訊號並藉以調整功率消耗。According to a second aspect of the present invention, an apparatus for adjusting power consumption is provided, the apparatus comprising: a frequency detector that receives a system frequency signal and a built-in frequency signal, and generates an output signal; and a bias control Receive the output signal and adjust the power consumption.

較佳地,本發明所提供調整功率消耗的裝置,其中該頻率偵測器包括:一重置偵測器,其接收該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者,並接收該輸出訊號,且產生一重置訊號;以及一計數器,其接收該重置訊號與一輸入訊號,並產生該輸出訊號。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein the frequency detector includes: a reset detector that receives a lower frequency of the system frequency signal and the built-in frequency signal, And receiving the output signal and generating a reset signal; and a counter receiving the reset signal and an input signal and generating the output signal.

較佳地,本發明所提供調整功率消耗的裝置,其中該輸入訊號為該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者。Preferably, the present invention provides a device for adjusting power consumption, wherein the input signal is the lower of the system frequency signal and the built-in frequency signal.

較佳地,本發明所提供調整功率消耗的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由高電位變為低電位時,該重置偵測器產生該重置訊號以重置該計數器。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein when the output signal is greater than zero, and the lower of the system frequency signal and the built-in frequency signal is changed from a high potential to a low potential, The reset detector generates the reset signal to reset the counter.

較佳地,本發明所提供調整功率消耗的裝置,其中該輸入訊號為一高電位訊號。Preferably, the present invention provides a device for adjusting power consumption, wherein the input signal is a high potential signal.

較佳地,本發明所提供調整功率消耗的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由高電位變為低電位時,該重置偵測器產生該重置訊號使該計數器重置。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein when the output signal is greater than zero, and the lower of the system frequency signal and the built-in frequency signal is changed from a high potential to a low potential, The reset detector generates the reset signal to reset the counter.

較佳地,本發明所提供調整功率消耗的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由低電位變為高電位時,該重置偵測器產生該重置訊號以重置該計數器。Preferably, the apparatus for adjusting power consumption is provided, wherein when the output signal is greater than zero, and the lower frequency of the system frequency signal and the built-in frequency signal is changed from a low level to a high level, The reset detector generates the reset signal to reset the counter.

較佳地,本發明所提供調整功率消耗的裝置,其中該輸入訊號為一低電位訊號。Preferably, the present invention provides a device for adjusting power consumption, wherein the input signal is a low potential signal.

較佳地,本發明所提供調整功率消耗的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由低電位變為高電位時,該重置偵測器產生該重置訊號以重置該計數器。Preferably, the apparatus for adjusting power consumption is provided, wherein when the output signal is greater than zero, and the lower frequency of the system frequency signal and the built-in frequency signal is changed from a low level to a high level, The reset detector generates the reset signal to reset the counter.

較佳地,本發明所提供調整功率消耗的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由高電位變為低電位時,該重置偵測器產生該重置訊號以重置該計數器。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein when the output signal is greater than zero, and the lower of the system frequency signal and the built-in frequency signal is changed from a high potential to a low potential, The reset detector generates the reset signal to reset the counter.

較佳地,本發明所提供調整功率消耗的裝置,其中該系統頻率訊號與該內建頻率訊號兩者中頻率較大者是該計數器的時脈訊號。Preferably, the present invention provides a device for adjusting power consumption, wherein a higher frequency of both the system frequency signal and the built-in frequency signal is a clock signal of the counter.

較佳地,本發明所提供調整功率消耗的裝置,其中該計數器為邊緣觸發計數器。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein the counter is an edge trigger counter.

較佳地,本發明所提供調整功率消耗的裝置,其中該系統頻率訊號的頻率是一功率放大器、一類比/數位轉換器或一數位/類比轉換器的操作頻率。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein the frequency of the system frequency signal is an operating frequency of a power amplifier, an analog/digital converter, or a digital/analog converter.

較佳地,本發明所提供調整功率消耗的裝置,其中該偏壓控制器包括一解碼器用以將該輸出訊號解碼以產生一控制訊號以調整功率消耗。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein the bias controller includes a decoder for decoding the output signal to generate a control signal to adjust power consumption.

較佳地,本發明所提供調整功率消耗的裝置,其中該控制訊號用以控制系統所需的一電流量以調整功率消耗。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein the control signal is used to control a current amount required by the system to adjust power consumption.

根據本發明的第三構想,提供一種偵測頻率的裝置,其用於功率放大器、類比/數位轉換器或數位/類比轉換器,該裝置包括:一頻率偵測器,其接收一系統頻率訊號與一內建頻率訊號,並產生一輸出訊號;以及一偏壓控制器,接收該輸出訊號並藉以調整功率消耗。According to a third aspect of the present invention, a device for detecting a frequency is provided for a power amplifier, an analog/digital converter, or a digital/analog converter, the device comprising: a frequency detector that receives a system frequency signal And a built-in frequency signal, and generate an output signal; and a bias controller that receives the output signal and thereby adjusts power consumption.

較佳地,本發明所提供調整功率消耗的裝置,其中該頻率偵測器包括:一重置偵測器,其接收該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者,並接收該輸出訊號,且產生一重置訊號;以及一計數器,其接收該重置訊號與一輸入訊號,並產生該輸出訊號。Preferably, the present invention provides an apparatus for adjusting power consumption, wherein the frequency detector includes: a reset detector that receives a lower frequency of the system frequency signal and the built-in frequency signal, And receiving the output signal and generating a reset signal; and a counter receiving the reset signal and an input signal and generating the output signal.

本案將可由以下的實施例說明而得到充分瞭解,使得熟習本技藝之人士可以據以完成之,然本案之實施並非可由下列實施案例而被限制其實施型態。其中相同的標號始終代表相同的組件。The present invention will be fully understood by the following examples, so that those skilled in the art can do so. However, the implementation of the present invention may not be limited by the following embodiments. Where the same reference numerals always represent the same components.

請參考第一圖,其係本發明之調整功率消耗裝置1的第一實施例,包括頻率偵測器11、偏壓控制器12與內部高頻振盪器13。其中內部高頻振盪器13產生一內建頻率訊號,頻率偵測器11接收一系統頻率訊號與該內建頻率訊號,該系統頻率訊號為所欲進行功率消調整之系統主電路所運作的操作頻率,且該系統頻率訊號的頻率小於該內建頻率訊號,如第二圖所示。而偏壓控制器12電耦接至頻率偵測器11,並接收頻率偵測器11產生的一輸出訊號,且產生一控制訊號並藉以調整功率消耗。Please refer to the first figure, which is a first embodiment of the power consumption device 1 of the present invention, including a frequency detector 11, a bias controller 12 and an internal high frequency oscillator 13. The internal high frequency oscillator 13 generates a built-in frequency signal, and the frequency detector 11 receives a system frequency signal and the built-in frequency signal, and the system frequency signal is an operation of the system main circuit for which the power consumption adjustment is to be performed. Frequency, and the frequency of the system frequency signal is less than the built-in frequency signal, as shown in the second figure. The bias controller 12 is electrically coupled to the frequency detector 11 and receives an output signal generated by the frequency detector 11 and generates a control signal to adjust the power consumption.

頻率偵測器11包括計數器111與重置偵測器112,其中計數器111具有兩輸入端分別為In端與ck端,In端接收該系統頻率訊號,而ck端接收該內建頻率訊號以作為其時脈訊號。計數器111另具有一Out端產生該輸出訊號並傳送至重置偵測器112與偏壓控制器12。而重置偵測器112接收該系統頻率訊號與該輸出訊號,並產生一重置訊號且傳輸至計數器111。The frequency detector 11 includes a counter 111 and a reset detector 112. The counter 111 has two inputs, an In terminal and a ck terminal. The In terminal receives the system frequency signal, and the ck terminal receives the built-in frequency signal as a Its clock signal. The counter 111 further has an Out terminal for generating the output signal and transmitting to the reset detector 112 and the bias controller 12. The reset detector 112 receives the system frequency signal and the output signal, and generates a reset signal and transmits it to the counter 111.

計數器111可以是正緣觸發或是負緣觸發計數器,在本實施例中,計數器111在In端接收的該系統頻率訊號為高電位時進行計數,在該系統頻率訊號為低電位時停止計數,所計數的次數即該輸出訊號,由Out端輸出。而當該系統頻率訊號由高電位變為低電位(負緣)且該輸出訊號大於零時,重置偵測器112傳送該重置訊號至計數器111表示偵測動作完畢,使計數器111被重置。藉此獲得該系統頻率訊號在高電位期間,內建頻率訊號的震盪次數,以作為該系統頻率訊號的頻率與內建頻率訊號的頻率兩者間的一比值,以用來對應該系統頻率訊號的頻率。The counter 111 can be a positive edge trigger or a negative edge trigger counter. In this embodiment, the counter 111 counts when the system frequency signal received by the In terminal is high, and stops counting when the system frequency signal is low. The number of counts is the output signal, which is output by the Out terminal. When the system frequency signal changes from a high level to a low level (negative edge) and the output signal is greater than zero, the reset detector 112 transmits the reset signal to the counter 111 to indicate that the detecting operation is completed, so that the counter 111 is heavy. Set. Thereby obtaining the oscillation frequency of the built-in frequency signal during the high frequency period of the system frequency signal, as a ratio between the frequency of the system frequency signal and the frequency of the built-in frequency signal, for corresponding to the system frequency signal Frequency of.

偏壓控制器12包括一解碼器(未顯示),當偵測動作完畢時,偏壓控制器12將該輸出訊號解碼獲得一控制訊號,也就是將該輸出訊號對應至不同的控制訊號,使主電路在不同系統頻率下使用不同偏壓電流,以控制主電路偏壓電流的大小來調整其操作頻寬與功率消耗。The bias controller 12 includes a decoder (not shown). When the detecting operation is completed, the bias controller 12 decodes the output signal to obtain a control signal, that is, the output signal is corresponding to different control signals. The main circuit uses different bias currents at different system frequencies to control the magnitude of the main circuit bias current to adjust its operating bandwidth and power consumption.

第三圖是在計數器111的該輸出訊號為三位元(3-bit)的狀況下的一種解碼方式,而該控制訊號為二位元(2-bit)訊號S1 S0 ,其中00、01、10、11分別控制系統主電路使用不同偏壓電流,以使用不同操作頻寬:頻寬1(BW_1)、頻寬2(BW_2)、頻寬3(BW_3)與頻寬4(BW_4)。在第三圖中,該輸出訊號中的000、001欲使用相同偏壓電流,故將其對應至相同控制訊號00;該輸出訊號中的010、011欲使用相同偏壓電流,故將其對應至相同控制訊號01;該輸出訊號中的100、101欲使用相同偏壓電流,故將其對應至相同控制訊號11;及該輸出訊號中的110、111欲使用相同偏壓電流,故將其對應至相同控制訊號11。其對應方式依據系統主電路的進行配置而不限於第三圖所用的對應方式。若偏壓控制器12輸出端為N位元(N-bit),則該控制訊號可有2N 種變化,而可依實際需要對頻寬與功率消耗作最佳化。實現第三圖的對應方式可由本領域技術人士施以變化而不以使用解碼器或上述方式為限。The third figure is a decoding mode in the case where the output signal of the counter 111 is three-bit (3-bit), and the control signal is a two-bit (2-bit) signal S 1 S 0 , where 00, 01, 10, 11 control system main circuit uses different bias currents to use different operating bandwidth: bandwidth 1 (BW_1), bandwidth 2 (BW_2), bandwidth 3 (BW_3) and bandwidth 4 (BW_4) . In the third figure, 000, 001 in the output signal want to use the same bias current, so it corresponds to the same control signal 00; 010, 011 in the output signal want to use the same bias current, so it corresponds to Up to the same control signal 01; 100, 101 of the output signal wants to use the same bias current, so it corresponds to the same control signal 11; and 110, 111 of the output signal wants to use the same bias current, so Corresponding to the same control signal 11. The corresponding manner is configured according to the main circuit of the system and is not limited to the corresponding manner used in the third figure. If the output of the bias controller 12 is N-bit, the control signal can have 2 N variations, and the bandwidth and power consumption can be optimized according to actual needs. The manner in which the third figure is implemented can be varied by those skilled in the art without being limited to the use of the decoder or the above.

第四圖為本發明的第二實施例,其連接方式與第一圖相同,其中不同點在於該系統頻率訊號的頻率大於該內建頻率訊號,如第五圖所示;而以該系統頻率訊號作為計數器111的時脈訊號、計數器111的In端接收該內建頻率訊號。在本實施例中,計數器111在該內建頻率訊號為高電位時進行計數,在該內建頻率訊號為低電位時停止計數,所計數的次數即該輸出訊號。而當該內建頻率訊號由高電位變為低電位(負緣)且Out端的該輸出訊號大於零時,重置偵測器112傳送該重置訊號至計數器111表示偵測動作完畢,並使計數器111被重置。The fourth embodiment is a second embodiment of the present invention, and the connection manner is the same as that of the first figure, wherein the difference is that the frequency of the system frequency signal is greater than the built-in frequency signal, as shown in the fifth figure; The signal is used as the clock signal of the counter 111, and the In terminal of the counter 111 receives the built-in frequency signal. In this embodiment, the counter 111 counts when the built-in frequency signal is high, and stops counting when the built-in frequency signal is low, and the counted number is the output signal. When the built-in frequency signal changes from high potential to low potential (negative edge) and the output signal of the Out terminal is greater than zero, the reset detector 112 transmits the reset signal to the counter 111 to indicate that the detection operation is completed, and The counter 111 is reset.

同樣地,藉此可獲得該內建頻率訊號在高電位期間系統頻率訊號的震盪次數,以作為該內建頻率訊號的頻率與該系統頻率訊號的頻率兩者間的一比值,以用來對應該系統頻率訊號的頻率。當偵測動作完畢時,偏壓控制器12將該輸出訊號解碼獲得一控制訊號,以控制主電路偏壓電流的大小來調整其操作頻寬與功率消耗。Similarly, the number of oscillations of the system frequency signal of the built-in frequency signal during the high potential period can be obtained as a ratio between the frequency of the built-in frequency signal and the frequency of the system frequency signal, so as to be used for The frequency of the system frequency signal should be. When the detecting operation is completed, the bias controller 12 decodes the output signal to obtain a control signal to control the magnitude of the main circuit bias current to adjust its operating bandwidth and power consumption.

又一第三實施例,請參見第六圖(A),其為第一與第二實施例的變化,其中計數器111的In端可以接收該系統頻率訊號、一高電位訊號(1)或一低電位訊號(0),接收該系統頻率訊號時,其動作模式與第一實施例相同。For still another third embodiment, please refer to the sixth figure (A), which is a variation of the first and second embodiments, wherein the In terminal of the counter 111 can receive the system frequency signal, a high potential signal (1) or a The low potential signal (0), when receiving the system frequency signal, has the same operation mode as the first embodiment.

而In端固定接至該高電位訊號時,由於In端一直處於高電位,故計數器111會不斷進行計數的動作,所計數的次數即該輸出訊號。當重置偵測器112接收到該系統頻率訊號的負緣且該輸出訊號大於零時,重置偵測器112送出重置訊號將計數器111重置,藉此獲得該系統頻率訊號的一週期內之內建頻率訊號的震盪次數,以作為該系統頻率訊號的頻率與內建頻率訊號的頻率兩者間的一比值,以用來對應該系統頻率訊號的頻率。When the In terminal is fixedly connected to the high potential signal, since the In terminal is always at a high potential, the counter 111 continuously counts the operation, and the counted number is the output signal. When the reset detector 112 receives the negative edge of the system frequency signal and the output signal is greater than zero, the reset detector 112 sends a reset signal to reset the counter 111, thereby obtaining a cycle of the system frequency signal. The number of oscillations of the built-in frequency signal is used as a ratio between the frequency of the system frequency signal and the frequency of the built-in frequency signal to match the frequency of the system frequency signal.

而當In端固定接至該低電位訊號時,計數器111可被設計為在In端為低電位時進行計數。當重置偵測器112接收到該系統頻率訊號的負緣且該輸出訊號大於零時,重置偵測器112送出重置訊號將計數器111重置,藉此獲得該系統頻率訊號的一週期內之內建頻率訊號的震盪次數,以作為該系統頻率訊號的頻率與內建頻率訊號的頻率兩者間的一比值,以用來對應該系統頻率訊號的頻率。When the In terminal is fixedly connected to the low potential signal, the counter 111 can be designed to count when the In terminal is low. When the reset detector 112 receives the negative edge of the system frequency signal and the output signal is greater than zero, the reset detector 112 sends a reset signal to reset the counter 111, thereby obtaining a cycle of the system frequency signal. The number of oscillations of the built-in frequency signal is used as a ratio between the frequency of the system frequency signal and the frequency of the built-in frequency signal to match the frequency of the system frequency signal.

同樣地,當計數器111被重置時,偏壓控制器12將該輸出訊號解碼獲得一控制訊號,以控制主電路偏壓電流的大小來調整其操作頻寬與功率消耗。Similarly, when the counter 111 is reset, the bias controller 12 decodes the output signal to obtain a control signal to control the magnitude of the main circuit bias current to adjust its operating bandwidth and power consumption.

對本領域技術人士來說,將本實施例中的重置偵測器112傳送重置訊號的條件改為:偵測到該系統頻率訊號的正緣且該輸出訊號大於零,同樣可以達到獲得該系統頻率訊號的一週期內,內建頻率訊號的震盪次數的功效。For the person skilled in the art, the condition that the reset detector 112 in the embodiment transmits the reset signal is changed to: the positive edge of the system frequency signal is detected and the output signal is greater than zero, and the same can be obtained. The effect of the number of oscillations of the built-in frequency signal during the one-week period of the system frequency signal.

而在該系統頻率訊號的頻率大於該內建頻率訊號的狀況下,本實施例中的該系統頻率訊號與內部高頻振盪器13的位置互換,如第六圖(B)。在In端接收該內建頻率訊號的時候,其動作模式與第二實施例相同,而當In端固定接至該高電位或該低電位時,計數器111計數該內建頻率訊號的一週期內,該系統頻率訊號的震盪次數以作為該比值。In the case where the frequency of the system frequency signal is greater than the built-in frequency signal, the system frequency signal in this embodiment is interchanged with the position of the internal high frequency oscillator 13, as shown in the sixth figure (B). When the In terminal receives the built-in frequency signal, the operation mode is the same as that in the second embodiment, and when the In terminal is fixedly connected to the high potential or the low potential, the counter 111 counts the one-time period of the built-in frequency signal. The number of oscillations of the frequency signal of the system is taken as the ratio.

第七圖為對應前述該等實施例的方法流程圖,其包括S1:提供一系統頻率訊號,該系統頻率訊號之頻率即所要控制功率消耗的主電路之頻率;S2:產生對應該系統頻率訊號的一數值,其中該數值為該系統頻率訊號的頻率與一內建頻率訊號的頻率兩者間的一比值;S3:依據該數值產生一控制訊號;S4:依據該控制訊號產生主電路所需電流量。FIG. 7 is a flowchart of a method corresponding to the foregoing embodiments, including S1: providing a system frequency signal, the frequency of the system frequency signal is the frequency of the main circuit for controlling power consumption; S2: generating a corresponding system frequency signal a value, wherein the value is a ratio between a frequency of the system frequency signal and a frequency of a built-in frequency signal; S3: generating a control signal according to the value; S4: generating a main circuit according to the control signal Electricity flow.

本發明可使用於與系統頻率有關連性的電路元件,例如:運算放大器(OPA)、充電泵(Charge Pump)、電壓控制振盪器(VCO),以將其改造為可依其主電路訊號頻率的快慢,控制其電路元件的電器特性,例如耗功率、頻寬、增益、迴轉率等。The present invention can be used for circuit components related to system frequency, such as an operational amplifier (OPA), a charge pump (Charge Pump), a voltage controlled oscillator (VCO), to be modified to be based on its main circuit signal frequency. The speed of control, the electrical characteristics of its circuit components, such as power consumption, bandwidth, gain, slew rate and so on.

總結而言,本案實為一難得一見,值得珍惜的難得發明,惟以上所述者,僅為本發明之最佳實施例而已,當不能以之限定本發明所實施之範圍。即大凡依本發明申請專利範圍所作之均等變化與修飾,皆應仍屬於本發明專利涵蓋之範圍內,謹請貴審查委員明鑑,並祈惠准,是所至禱。In summary, the present invention is a rare and incomprehensible invention, but the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. That is to say, the equivalent changes and modifications made by the applicants in accordance with the scope of the patent application of the present invention should still fall within the scope covered by the patent of the present invention. I would like to ask your review committee to give a clear explanation and pray for the best.

1...調整功率消耗裝置1. . . Adjust power consumption device

11...頻率偵測器11. . . Frequency detector

111...計數器111. . . counter

112...重置偵測器112. . . Reset detector

12...偏壓控制器12. . . Bias controller

13...內部高頻振盪器13. . . Internal high frequency oscillator

S1...提供一系統頻率訊號S1. . . Provide a system frequency signal

S2...產生對應該系統頻率訊號的一數值S2. . . Generate a value corresponding to the system frequency signal

S3...依據該數值產生一控制訊號S3. . . Generate a control signal based on the value

S4...依據該控制訊號產生主電路所需電流量S4. . . The amount of current required to generate the main circuit based on the control signal

第一圖為本發明之第一實施例。The first figure is a first embodiment of the present invention.

第二圖為第一實施例中,內建頻率訊號與系統頻率訊號之示意圖。The second figure is a schematic diagram of the built-in frequency signal and the system frequency signal in the first embodiment.

第三圖為輸出訊號與控制訊號的對應示意圖。The third figure is a corresponding diagram of the output signal and the control signal.

第四圖為本發明之第二實施例。The fourth figure is a second embodiment of the present invention.

第五圖為第二實施例中,內建頻率訊號與系統頻率訊號之示意圖。The fifth figure is a schematic diagram of the built-in frequency signal and the system frequency signal in the second embodiment.

第六圖(A)為本發明之第三實施例。The sixth diagram (A) is a third embodiment of the present invention.

第六圖(B)為本發明之第三實施例的另一實施方式。Figure 6 (B) is another embodiment of the third embodiment of the present invention.

第七圖為本發明之方法流程圖。The seventh figure is a flow chart of the method of the present invention.

1...調整功率消耗裝置1. . . Adjust power consumption device

11...頻率偵測器11. . . Frequency detector

111...計數器111. . . counter

112...重置偵測器112. . . Reset detector

12...偏壓控制器12. . . Bias controller

13...內部高頻振盪器13. . . Internal high frequency oscillator

Claims (21)

一種調整功率消耗的方法,包括下列步驟:(a)提供一系統頻率訊號;(b)提供一內建頻率訊號;(c)偵測該內建頻率訊號的頻率與該系統頻率訊號的頻率兩者間之一比值,其中若該內建頻率訊號的頻率小於該系統頻率訊號的頻率,則該比值為該內建頻率訊號的一期間內,該系統頻率訊號所發生一震盪次數,若該內建頻率訊號的頻率大於該系統頻率訊號的頻率,則該比值為該系統頻率訊號的一期間內,該內建頻率訊號所發生的震盪次數;以及(d)依據該比值調整功率消耗。 A method for adjusting power consumption includes the steps of: (a) providing a system frequency signal; (b) providing a built-in frequency signal; (c) detecting a frequency of the built-in frequency signal and a frequency of the system frequency signal a ratio between the ones, wherein if the frequency of the built-in frequency signal is less than the frequency of the system frequency signal, the ratio is a number of oscillations of the system frequency signal during a period of the built-in frequency signal, if the frequency The frequency of the built-in frequency signal is greater than the frequency of the system frequency signal, and the ratio is the number of oscillations of the built-in frequency signal during a period of the system frequency signal; and (d) the power consumption is adjusted according to the ratio. 如申請專利範圍第1項的方法,其中該期間是一高電位期間。 The method of claim 1, wherein the period is a high potential period. 如申請專利範圍第1項的方法,其中該期間是一低電位期間。 The method of claim 1, wherein the period is a low potential period. 如申請專利範圍第1項的方法,其中該期間是一週期。 The method of claim 1, wherein the period is a period. 如申請專利範圍第1項的方法,其中步驟(c)更包括一步驟(c1)依據該數值來產生一電流量,以調整功率消耗。 The method of claim 1, wherein the step (c) further comprises a step (c1) of generating a current amount according to the value to adjust the power consumption. 如申請專利範圍第5項的方法,其中步驟(c1)是將該數值解碼以產生一控制訊號,並依據該控制訊號來產生該電流量。 The method of claim 5, wherein the step (c1) decodes the value to generate a control signal, and generates the current amount according to the control signal. 一種調整功率消耗的裝置,該裝置包括:一頻率偵測器,其接收一系統頻率訊號與一內建頻率訊號,並產生一輸出訊號;以及 一偏壓控制器,接收該輸出訊號並藉以調整功率消耗;其中該頻率偵測器包括:一重置偵測器,其接收該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者,並接收該輸出訊號,且產生一重置訊號;以及一計數器,其接收該重置訊號與一輸入訊號,並產生該輸出訊號。 A device for adjusting power consumption, the device comprising: a frequency detector that receives a system frequency signal and a built-in frequency signal and generates an output signal; a bias controller that receives the output signal and adjusts power consumption; wherein the frequency detector includes: a reset detector that receives a smaller frequency between the system frequency signal and the built-in frequency signal And receiving the output signal and generating a reset signal; and a counter receiving the reset signal and an input signal and generating the output signal. 如申請專利範圍第7項的裝置,其中該輸入訊號為該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者。 The device of claim 7, wherein the input signal is the lesser of the system frequency signal and the built-in frequency signal. 如申請專利範圍第8項的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由高電位變為低電位時,該重置偵測器產生該重置訊號以重置該計數器。 The device of claim 8, wherein the reset signal is detected when the output signal is greater than zero, and the lower frequency of the system frequency signal and the built-in frequency signal is changed from a high level to a low level. The detector generates the reset signal to reset the counter. 如申請專利範圍第7項的裝置,其中該輸入訊號為一高電位訊號。 The device of claim 7, wherein the input signal is a high potential signal. 如申請專利範圍第10項的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由高電位變為低電位時,該重置偵測器產生該重置訊號使該計數器重置。 The device of claim 10, wherein when the output signal is greater than zero, and the lower frequency of the system frequency signal and the built-in frequency signal changes from a high potential to a low potential, the reset detection The detector generates the reset signal to reset the counter. 如申請專利範圍第10項的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由低電位變為高電位時,該重置偵測器產生該重置訊號以重置該計數器。 The device of claim 10, wherein when the output signal is greater than zero, and the lower frequency of the system frequency signal and the built-in frequency signal changes from a low potential to a high potential, the reset detection The detector generates the reset signal to reset the counter. 如申請專利範圍第7項的裝置,其中該輸入訊號為一低 電位訊號。 For example, the device of claim 7 wherein the input signal is a low Potential signal. 如申請專利範圍第13項的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由低電位變為高電位時,該重置偵測器產生該重置訊號以重置該計數器。 The device of claim 13, wherein the reset signal is changed when the output signal is greater than zero, and the lower frequency of the system frequency signal and the built-in frequency signal is changed from a low level to a high level. The detector generates the reset signal to reset the counter. 如申請專利範圍第13項的裝置,其中當該輸出訊號大於零,且該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者由高電位變為低電位時,該重置偵測器產生該重置訊號以重置該計數器。 The device of claim 13, wherein the reset signal is detected when the output signal is greater than zero, and the frequency of the system frequency signal and the built-in frequency signal is changed from a high level to a low level. The detector generates the reset signal to reset the counter. 如申請專利範圍第7項的裝置,其中該系統頻率訊號與該內建頻率訊號兩者中頻率較大者是該計數器的時脈訊號。 The device of claim 7, wherein a greater frequency of the system frequency signal and the built-in frequency signal is a clock signal of the counter. 如申請專利範圍第7項的裝置,其中該計數器為邊緣觸發計數器。 The device of claim 7, wherein the counter is an edge trigger counter. 如申請專利範圍第7項的裝置,其中該系統頻率訊號的頻率是一功率放大器、一類比/數位轉換器或一數位/類比轉換器的操作頻率。 The device of claim 7, wherein the frequency of the system frequency signal is an operating frequency of a power amplifier, a analog/digital converter or a digital/analog converter. 如申請專利範圍第7項的裝置,其中該偏壓控制器包括一解碼器用以將該輸出訊號解碼以產生一控制訊號以調整功率消耗。 The device of claim 7, wherein the bias controller includes a decoder for decoding the output signal to generate a control signal to adjust power consumption. 如申請專利範圍第19項的裝置,其中該控制訊號用以控制系統所需的一電流量以調整功率消耗。 The device of claim 19, wherein the control signal is used to control a current amount required by the system to adjust power consumption. 一種偵測頻率的裝置,其用於功率放大器、類比/數位轉換器或數位/類比轉換器,該裝置包括:一頻率偵測器,其接收一系統頻率訊號與一內建頻率訊 號,並產生一輸出訊號;以及一偏壓控制器,接收該輸出訊號並藉以調整功率消耗;其中該頻率偵測器包括:一重置偵測器,其接收該系統頻率訊號與該內建頻率訊號兩者之中頻率較小者,並接收該輸出訊號,且產生一重置訊號;以及一計數器,其接收該重置訊號與一輸入訊號,並產生該輸出訊號。 A frequency detecting device for a power amplifier, an analog/digital converter or a digital/analog converter, the device comprising: a frequency detector that receives a system frequency signal and a built-in frequency signal And generating an output signal; and a bias controller for receiving the output signal and adjusting power consumption; wherein the frequency detector comprises: a reset detector that receives the system frequency signal and the built-in The lower of the frequency signals, and receiving the output signal, and generating a reset signal; and a counter that receives the reset signal and an input signal and generates the output signal.
TW098134851A 2009-10-14 2009-10-14 Power configuring device and method thereof TWI486757B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW098134851A TWI486757B (en) 2009-10-14 2009-10-14 Power configuring device and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW098134851A TWI486757B (en) 2009-10-14 2009-10-14 Power configuring device and method thereof

Publications (2)

Publication Number Publication Date
TW201113693A TW201113693A (en) 2011-04-16
TWI486757B true TWI486757B (en) 2015-06-01

Family

ID=44909737

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098134851A TWI486757B (en) 2009-10-14 2009-10-14 Power configuring device and method thereof

Country Status (1)

Country Link
TW (1) TWI486757B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW573242B (en) * 2000-07-24 2004-01-21 Advanced Micro Devices Inc Method and apparatus to provide deterministic power-on voltage in a system having processor-controlled voltage level
TW200529075A (en) * 2003-12-17 2005-09-01 Via Tech Inc Frequency-voltage mechanism for microprocessor power management
US20080169873A1 (en) * 2007-01-17 2008-07-17 Oki Electric Industry Co., Ltd. High frequency signal detection circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW573242B (en) * 2000-07-24 2004-01-21 Advanced Micro Devices Inc Method and apparatus to provide deterministic power-on voltage in a system having processor-controlled voltage level
TW200529075A (en) * 2003-12-17 2005-09-01 Via Tech Inc Frequency-voltage mechanism for microprocessor power management
US20080169873A1 (en) * 2007-01-17 2008-07-17 Oki Electric Industry Co., Ltd. High frequency signal detection circuit

Also Published As

Publication number Publication date
TW201113693A (en) 2011-04-16

Similar Documents

Publication Publication Date Title
US8456136B2 (en) Method and apparatus for battery gauging in portable terminal
TWI463769B (en) Charge pump device
US7616074B2 (en) Low-power fast-startup oscillator with digital feedback control
WO2006127888A3 (en) Data retention device for power-down applications and method
KR20130130728A (en) Crystal oscillator with low-power mode
WO2015165218A1 (en) Voltage comparator
US8907670B2 (en) Metering device and metering method
US20110106992A1 (en) Apparatus and method for scaling dynamic bus clock
WO2022095580A1 (en) Power supply circuit, power supply method, audio power amplifier and integrated circuit
TWI392224B (en) Audio processing chip and audio signal processing method thereof
TWI579686B (en) Electronic device with power controll function
TWI486757B (en) Power configuring device and method thereof
TW200934128A (en) Filter and filtering method
JP2011087451A (en) Dynamic current supplying pump
WO2017016273A1 (en) Accelerator
TWI552529B (en) Demodulation circuit and wireless charging device having the same
TWI449327B (en) Bias current control method and driving circuit for operational amplifier
CN105703731B (en) Automatic gain control circuit for D class audio frequency power amplifier chips
US20210091785A1 (en) Low power always-on microphone using power reduction techniques
TWI749555B (en) Reference voltage generating circuit
TWI457739B (en) Dynamic power control method and circuit thereof
TWI434495B (en) Voltage generation system that can dynamically calibrate time period for enabling the system and method thereof
TW201436453A (en) Bias current control method and driving circuit for operational amplifier
US20130147552A1 (en) Class-d amplifier
US11558706B2 (en) Activity detection