TWI481322B - Circuit board, structural unit thereof and manufacturing method thereof - Google Patents

Description

Circuit board and its structural unit and process

The present application relates to a circuit board, a structural unit thereof, and a manufacturing method thereof, and more particularly to a structural unit, a manufacturing method, and a circuit board formed by using one or more high temperature pressing processes for circuit board fabrication. structure.

One of the conventional methods for fabricating a flexible circuit board is to perform pre-treatment and sputtering on one side surface or opposite side surfaces of an insulating substrate to form a circuit layer by electroless plating or electroplating on an insulating substrate. . However, the steps of this process are complicated and the cost of the sputtering process is high. Most of the current flexible circuit boards are composed of a flexible copper clad laminate (FCCL), an insulating substrate, and an adhesive. Such a flexible circuit board is formed by first etching a flexible copper foil substrate or the like to form a desired wiring. Thereafter, the flexible copper foil substrate and the insulating substrate are subjected to a rapid press-bonding step to bond the flexible copper foil substrate and the insulating substrate to each other by an adhesive.

It should be noted that when manufacturing the aforementioned flexible circuit board, the temperature resistance of each layer, such as the adhesive, is low in temperature resistance, and high temperature and long time cannot be performed. The pressing step. Therefore, the existing flexible circuit boards are mostly single-layer or double-layer circuit structures, and encounter difficulties and limitations when making more layers of circuit structures. In addition, the adhesives conventionally used for flexible circuit boards have a high dielectric constant, which is also disadvantageous for the improvement of line resolution and accumulation.

Although the conventional printed circuit board process can provide a multilayer wiring structure, it uses a glass cloth (Glass Febrics) contained in the FR4 substrate, and has a high dielectric constant. In terms of reduction in thickness, although a staple fiber glass cloth can be used, the fiberglass cloth of such a staple fiber is expensive.

The present application provides a circuit board process that utilizes one or more high temperature bonding processes to achieve rapid and highly reliable multilayer circuit board fabrication.

The board process includes the following steps: First, a core unit and a first stack unit are provided. The core unit includes a first polyimide layer, a first adhesive layer, a second adhesive layer, a first conductive layer and a second conductive layer. The first adhesive layer and the second adhesive layer are respectively disposed on the first surface and the second surface of the first polyimide layer. The first and second conductive layers are respectively disposed on the first and second adhesive layers. The first superimposing unit comprises a second polyimide layer, a third adhesive layer, a fourth adhesive layer and a third conductive layer. The third and fourth adhesive layers are respectively disposed on the third and fourth surfaces of one of the second polyimide layers. The fourth adhesive layer is exposed and faces the first conductive layer, and the third conductive layer is disposed on the third adhesive layer. Thereafter, a first pressing step is performed, and the pressing temperature is higher than 160 ° C, and the first superimposing unit and the core single sheet are pressed together. And bonding the fourth adhesive layer to the first conductive layer.

In an embodiment of the present application, before the first pressing step, further comprising providing a second superimposing unit, comprising a third polyamidamine layer, a fifth adhesive layer, a sixth adhesive layer and a first Four conductive layers. The fifth and sixth adhesive layers are respectively disposed on the fifth and sixth surfaces of one of the third polyimide layers. The sixth adhesive layer is exposed and faces the second conductive layer, and the fourth conductive layer is disposed on the fifth adhesive layer. In addition, during the first pressing step, the first superimposing unit, the second superimposing unit, and the core unit are simultaneously pressed, the fourth adhesive layer is bonded to the first conductive layer, and the sixth adhesive layer is bonded to the first Two conductive layers.

In an embodiment of the present application, after the first pressing step, the first and second solder mask layers may be respectively formed on the third and fourth conductive layers.

In an embodiment of the present application, after the first pressing step, the process further includes providing another first superimposing unit, the fourth adhesive layer of the other first superimposing unit is exposed, and facing the first one The third conductive layer of the superposition unit. Another second superimposing unit is provided, the sixth adhesive layer of the other second superimposing unit is exposed, and faces the fourth conductive layer of the previous second superimposing unit. Then, performing a second pressing step, and the pressing temperature is higher than 160 ° C, pressing all the first superimposing units, the second superimposing unit and the core unit, and bonding the fourth adhesive layer of the other first superimposing unit to The third conductive layer of the first first superimposing unit and the sixth adhesive layer of the other second superimposing unit to the fourth conductive layer of the previous second superimposing unit.

In an embodiment of the present application, after the second pressing step, the third and fourth conductive layers respectively forming a first and a second solder mask layer on the outermost layer may be further included on.

In an embodiment of the present application, the pressing temperature of the first pressing step is between about 160 ° C and 200 ° C.

In an embodiment of the present application, the pressing temperature of the second pressing step is approximately between 160 ° C and 200 ° C.

The present application provides a circuit board that has good process temperature tolerance, is compatible with existing process equipment of printed circuit boards, and has a relatively thin thickness.

The circuit board includes a core unit and a first stacking unit. The core unit includes a first polyimide layer, a first adhesive layer, a second adhesive layer, a first conductive layer and a second conductive layer. The first and second adhesive layers are respectively disposed on the first surface and the second surface of the first polyimide layer. The first and second conductive layers are respectively disposed on the first and second adhesive layers. The first superimposing unit comprises a second polyimide layer, a third adhesive layer, a fourth adhesive layer and a third conductive layer. The second polyamidamine layer has a third and a fourth surface. The third and fourth adhesive layers are respectively disposed on the third and fourth surfaces of the second polyimide layer. A fourth adhesive layer is bonded to the first conductive layer. The third conductive layer is disposed on the third adhesive layer. The glass transition temperatures of the first, second, third, and fourth subbing layers are between about 140 ° C and 160 ° C.

In an embodiment of the present application, the circuit board further includes a second stacking unit including a third polyimide layer, a fifth adhesive layer, a sixth adhesive layer, and a fourth conductive layer. . The fifth and sixth adhesive layers are respectively disposed on the fifth and sixth surfaces of one of the third polyimide layers. The sixth adhesive layer is bonded to the second conductive layer. The fourth conductive layer is disposed on the fifth adhesive layer. The glass transition temperature of the fifth and sixth layers is approximately Between 140 ° C and 160 ° C.

In an embodiment of the present application, the circuit board may further include a first and a second solder mask layer respectively on the third and fourth conductive layers.

In an embodiment of the present application, the circuit board further includes at least another first superimposing unit and at least another second superimposing unit respectively located on the first side and the second side of the core unit. The fourth adhesive layer of the other first superimposing unit is bonded to the third conductive layer of the previous first superimposing unit, and the sixth adhesive layer of the other second superimposing unit is bonded to the fourth conductive layer of the previous second superimposing unit .

In an embodiment of the present application, the circuit board may further include a first and a second solder mask layer respectively on the third and fourth conductive layers of the outermost layer.

In an embodiment of the present application, the first, second, third, and fourth adhesive layers of the circuit board have a dielectric constant of less than about 3.

In an embodiment of the present application, the fifth and sixth adhesive layers of the circuit board have a dielectric constant of less than about 3.

The present application further provides a circuit board which is a soft and hard composite board having good flexibility and process temperature tolerance, and is compatible with the processing equipment of the existing printed circuit board. In addition, this soft and hard composite panel has a much thinner thickness than conventional soft and hard composite panels.

The circuit board includes a first core unit, a second core unit, a third core unit, a seventh adhesive layer, an eighth adhesive layer, a first superimposing unit and a second superimposing unit. The first core unit comprises a first polyimide layer, a first adhesive layer, a second adhesive layer, a first conductive layer and a second conductive layer. The first and second adhesive layers are respectively disposed on the first surface and the second surface of the first polyimide layer. the first And the second conductive layer are respectively disposed on the first and second adhesive layers.

The second core unit is located on a first side of the first core unit. The second core unit comprises a second polyimide layer, a third adhesive layer, a fourth adhesive layer, a third conductive layer and a fourth conductive layer. The third and fourth adhesive layers are respectively disposed on the third and fourth surfaces of one of the second polyimide layers. The third and fourth conductive layers are respectively disposed on the third and fourth adhesive layers, and the fourth conductive layer faces the first conductive layer.

The third core unit is located on a second side of the first core unit. The third core unit comprises a third polyamidamine layer, a fifth adhesive layer, a sixth adhesive layer, a fifth conductive layer and a sixth conductive layer. The fifth and sixth adhesive layers are respectively disposed on the fifth and sixth surfaces of one of the second polyimide layers. The fifth and sixth conductive layers are respectively disposed on the fifth and sixth adhesive layers, and the sixth conductive layer faces the second conductive layer.

In addition, the seventh adhesive layer is disposed between the first and second core units, and the fourth conductive layer is bonded to the first conductive layer by the seventh adhesive layer. The eighth adhesive layer is disposed between the first and third core units, and the sixth conductive layer is bonded to the second conductive layer by the eighth adhesive layer.

The first stacking unit is located on the first side of the first core unit, and the first stacking unit comprises a fourth polyimide layer, a ninth rubber layer, a tenth rubber layer and a seventh conductive layer. The ninth and tenth adhesive layers are respectively disposed on the seventh and eighth surfaces of one of the fourth polyimide layers. The tenth adhesive layer is bonded to the third conductive layer, and the seventh conductive layer is disposed on the ninth adhesive layer.

The second superimposing unit is located on the second side of the first core unit, and the second superimposing unit comprises a fifth polyamidamine layer, an eleventh adhesive layer, a twelfth adhesive layer and an eighth conductive layer. The eleventh and twelfth rubber layers are respectively disposed in the fifth polyamidamine layer A ninth and a tenth surface. The twelfth adhesive layer is bonded to the fifth conductive layer of the third core unit, and the eighth conductive layer is disposed on the eleventh adhesive layer.

In an embodiment of the present application, the circuit board further includes a first and a second solder mask layer respectively on the seventh and eighth conductive layers.

In an embodiment of the present application, the circuit board has a first area, and a portion of the first superimposing unit in the first area is removed, so that the first superimposing unit and the third conductive layer jointly expose the first area A portion of the third layer of glue inside.

In an embodiment of the present application, a second superimposing unit of a portion of the first region of the circuit board is removed, so that the second superimposing unit and the fifth conductive layer together expose a portion of the fifth glue in the first region. Floor. In addition, the circuit board has a thickness in the first region that is less than the thickness of the circuit board in other regions.

In an embodiment of the present application, a portion of the seventh glue layer in the first region of the circuit board is removed, and the seventh glue layer of the removed portion corresponds to the plurality of conductive layers of the first conductive layer. Terminal. A portion of the second core unit in the first region is removed to expose the aforementioned conductive terminals.

In an embodiment of the present application, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and tenthth of the circuit board The dielectric layer has a dielectric constant of less than about 3.

The above-described features and advantages of the present application will become more apparent and understood.

110, 310, 410, 510, 520, 530‧‧‧ core units

120, 320, 330, 420, 430, 470, 480, 550, 560‧ ‧ superimposed units

130‧‧‧joining unit

112, 122, 132, 312, 322, 332, 412, 422, 432, 472, 482, 512, 522, 532, 552, 562‧‧ ‧ polyimide layer

112a, 112b, 122a, 122b, 132a, 132b, 312a, 312b, 412a, 412b, 422a, 422b, 432a, 432b, 472a, 472b, 482a, 482b, 512a, 512b, 522a, 522b, 532a, 532b, 552a, Surface of 552b, 562a, 562b‧‧ ‧ polyimide layer

113, 114, 123, 124, 133, 134, 313, 314, 323, 324, 333, 334, 413, 414, 423, 424, 433, 434, 473, 474, 483, 484, 513, 514, 523, 524, 533, 534, 542, 544, 553, 554, 563, 564 ‧ ‧

115, 116, 126, 315, 316, 326, 336, 415, 416, 426, 436, 476, 486, 515, 516, 525, 526, 535, 536, 556, 566‧‧ ‧ conductive layer

315a, 316a, 326a, 336a, 415a, 416a, 426a, 436a, 476a, 486a, 515a, 516a, 525a, 535a, 556a, 566a‧‧‧ circuit layer

526a, 536a‧‧‧Shield pattern

128‧‧‧ release layer

135, 136‧‧‧ grassroots

210~230‧‧‧Steps

300‧‧‧ four-layer circuit board

340, 440, 592, 594‧‧‧ conductive holes

352, 354, 452, 454, 572, 574‧‧ ‧ welding mask

352a, 354a, 452a, 454a, 572a, 574a‧‧

400‧‧‧Six-layer circuit board

A1‧‧‧ first area

A2‧‧‧Second area

T‧‧‧ conductive terminals

1A-1C respectively illustrate various construction units in accordance with an embodiment of the present application.

2 illustrates a method of fabricating a circuit board in accordance with an embodiment of the present application.

3A-3F illustrate a four-layer circuit board process in accordance with an embodiment of the present application.

4A-4I illustrate a six-layer circuit board process in accordance with an embodiment of the present application.

5A-5I illustrate a circuit board process in accordance with an embodiment of the present application.

The technical solution proposed by the present application comprises a single-layer circuit board, a multi-layer circuit board, a soft and hard composite board, and a construction unit and a manufacturing method for forming the above-mentioned various types of circuit boards. In the following, from the perspective of a structural unit, a plurality of embodiments are used to introduce the technical solution for forming various types of circuit boards.

1A-1C respectively illustrate various construction units in accordance with an embodiment of the present application. Here, in order to facilitate the description of the subsequent process steps, the structural units of FIGS. 1A to 1C are referred to as a core unit, a superimposing unit, and an engaging unit, respectively.

First, the core unit 110 shown in FIG. 1A includes a polyimide layer 112 (polyimide, PI), a first adhesive layer 113, a second adhesive layer 114, a first conductive layer 115, and a second conductive layer 116. The first adhesive layer 113 and the second adhesive layer 114 are respectively located on the first surface 112a and the second surface 112b of the polyimide layer 112. The first conductive layer 115 is located on the first adhesive layer 113. The second conductive layer 116 is located on the second adhesive layer 114.

In addition, the stacking unit 120 shown in FIG. 1B includes a polyimide layer 122, a first adhesive layer 123, a second adhesive layer 124, a conductive layer 126, and a release layer 128. Polyaru The amine layer 122 has a first surface 122a and a second surface 122b. The first adhesive layer 123 and the second adhesive layer 124 are respectively located on the first surface 122a and the second surface 122b of the polyimide layer 122. The conductive layer 126 is located on the first adhesive layer 123. The release layer 128 is located on the second glue layer 124.

In addition, as shown in FIG. 1C, the bonding unit 130 includes a polyimide layer 132, a first adhesive layer 133, a second adhesive layer 134, a first base layer 135, and a second base layer 136. The first adhesive layer 133 and the second adhesive layer 134 are respectively located on the first surface 132a and the second surface 132b of the polyimide layer 132. The first base layer 135 is located on the first adhesive layer 133. The second base layer 136 is located on the second adhesive layer 134.

Furthermore, the aforementioned first glue layers 113, 123, 133 and the second glue layers 114, 124, 134 have, for example, the same material composition, and have a dielectric constant of less than 3, for example between 2.6 and 2.8. Among them, the dielectric constant is measured according to IPC TM650-2.5.5.9 at 1 GHz. Meanwhile, in order to accommodate the subsequent high temperature pressing step, the glass transition temperatures of the first adhesive layers 113, 123, 133 and the second adhesive layers 114, 124, 134 are, for example, between 140 ° C and 160 ° C. As understood by those of ordinary skill in the art, the "glass transition temperature" (Tg) herein can be considered as one of transition temperatures. That is, when the polymer (such as the first adhesive layer 113, 123, 133 and the second adhesive layer 114, 124, 134) is at the glass transition temperature, it will appear from the rubber state exhibited by the higher temperature to the low temperature. The glass is hard and brittle. For example, crystalline plastics have significant glass transition temperatures and latent heat values, while polymers exhibit plastic or rubber state all-glass transition temperatures and temperatures at the time of use. In other words, in The glass transition temperature is, for example, a rubber layer having a temperature greater than or equal to between 140 ° C and 160 ° C, and can withstand a high temperature pressing step of a subsequent temperature of at least 160 ° C or higher.

Even in this embodiment, a polymer having a glass transition temperature of between 140 ° C and 160 ° C may be further selected as the material of the first adhesive layer 113 , 123 , 133 and the second adhesive layer 114 , 124 , 134 . This further ensures a smoother step of the higher temperature (for example between 160 ° C and 200 ° C). Since the process temperature of the high temperature pressing step of the printed circuit board is about 160 ° C, the first adhesive layer 113, 123, 133 and the second adhesive layer 114 having a glass transition temperature of between 140 ° C and 160 ° C are used. 124, 134, it will be ensured that the pressing step of the embodiment is compatible with the high temperature pressing process and equipment of the known printed circuit board, and it is not necessary to develop a new process equipment, and the cost increase can be avoided.

The pressing step in this embodiment and each embodiment is defined below. In more detail, the conventional flexible circuit board uses a quick press process, which is a Roll to Roll device. Compared with the rapid press-bonding process, the pressing step of the present embodiment and the subsequent embodiments is a high-temperature pressing process and apparatus using an existing printed circuit board (that is, a hard board), that is, a one-piece process. Therefore, the process parameters and process equipment of the two are not the same. In terms of process parameters, the pressing time in the pressing step of the present embodiment and the subsequent embodiments is greater than the pressing time of the rapid pressing process used in the conventional flexible board, and the two are approximately one order different. the above. Next, the pressing temperature in the pressing step of the present embodiment and the subsequent embodiments is also larger than the pressing temperature of the rapid pressing process used in the conventional flexible board.

Among the currently known materials, the first adhesive layer 113, 123, 133 and the first For the second adhesive layer 114, 124, 134, for example, a product of the type PE-25F38 supplied by Microcosm Technology Co. Ltd. may be used. This product can provide a glass with a glass transition temperature between 140 ° C and 160 ° C and a dielectric constant of about 2.6-2.8. It is worth mentioning that the dielectric material used in traditional soft boards usually has a dielectric constant greater than 3.

Of course, the foregoing actual product is only used to prove the feasibility of the technical solution of the embodiment, and is not intended to limit the type of glue selected. In accordance with the state of the art, those having ordinary skill in the art, after referring to the disclosure of the present application, may select or develop a material having similar material properties and apply it to the technical solution of the present application.

In addition, according to the roles and functions of the core unit 110, the superimposing unit 120, and the bonding unit 130 in the subsequent circuit board process, the first adhesive layer 113, 123, 133 and the second adhesive layer 114, 124, 134 It may present a cured C-stage state or a semi-cured B-stage state. For example, the first adhesive layer 113 and the second adhesive layer 114 of the core unit 110 are, for example, in a C-stage state after curing. The first adhesive layer 123 of the stacking unit 120 is, for example, a cured C-stage state, and the second adhesive layer 124 is, for example, a semi-cured B-stage state. The first adhesive layer 133 and the second adhesive layer 134 of the bonding unit 130 are, for example, semi-cured B-stage states.

In addition, the materials of the first conductive layer 115, the second conductive layer 116, and the conductive layer 126 are, for example, copper or other suitable conductive materials. In the subsequent circuit board process, the first conductive layer 115, the second conductive layer 116, and the conductive layer 126 may be patterned, for example, as a line, or as a shield layer, a ground layer, a power layer, or the like. Release layer 128 For example, a release paper or the like, which can be removed in a subsequent wiring board process to expose the second adhesive layer 124 in the B-stage state. The material of the first base layer 135 and the second base layer 136 is, for example, a polyethylene terephthalate (PET) substrate or other plastic substrate for supporting the polyimide layer 132 and the B-stage state. The first adhesive layer 133 and the second adhesive layer 134.

Various types of circuit boards can be formed by applying the aforementioned core unit 110, the superimposing unit 120, and the joining unit 130. Specifically, as shown in the process steps of FIG. 2, the present application may first select the core unit 110, the superposition unit 120, and the two or more types of construction units of the same type or different types in the joint unit 130 (step 210). And, a pre-processing is selectively performed on the selected structural unit (step 220). Thereafter, one or more press-bonding steps (step 230) are performed, and the selected structural unit is pressed in an environment having a temperature of, for example, 160 ° C to 200 ° C to cure the B-stage state of the adhesive layer, for example, the superposition unit 120 The second adhesive layer 124 and the first adhesive layer 133 and the second adhesive layer 134 of the bonding unit 130. As such, the plurality of structural units may be joined to each other by a corresponding first adhesive layer 133 or second adhesive layer 124, 134.

The multi-layer circuit board and the process thereof which are implemented by applying the foregoing construction unit and the process steps are further illustrated by a plurality of embodiments.

3A-3F illustrate a four-layer circuit board process in accordance with an embodiment of the present application.

First, as shown in FIG. 3A, a core unit 310 is provided. Here, for example, the core unit 110 of FIG. 1A is selected as the core unit 310 of the present embodiment. The core unit 310 includes a first polyimide layer 312, a first adhesive layer 313, and a second adhesive layer. 314, a first conductive layer 315 and a second conductive layer 316. The first adhesive layer 313 and the second adhesive layer 314 are respectively disposed on the first surface 312a and the second surface 312b of the first polyimide layer 312. The first conductive layer 315 is disposed on the first adhesive layer 313. The second conductive layer 316 is disposed on the second adhesive layer 314.

After the core unit 110 of FIG. 1A is selected as the core unit 310 of the present embodiment, the core unit 310 may also be selected to perform pre-processing as shown in FIG. 2 (step 220). As shown in FIG. 3B, the present embodiment may selectively pattern the first conductive layer 315 and the second conductive layer 316 to form a first wiring layer 315a and a second wiring layer 316a, respectively. In other embodiments, the first conductive layer 315 and the second conductive layer 316 may not be patterned as a signal reference surface, a power supply surface or a ground plane.

On the other hand, as shown in FIG. 3C, a first superimposing unit 320 and a second superimposing unit 330 are respectively provided on opposite sides of the core unit 310. Here, for example, the superimposing unit 120 of FIG. 1B is selected as the first superimposing unit 320 and the second superimposing unit 330 of the present embodiment, wherein the superimposing unit 120 of FIG. 1B is subjected to pre-processing as shown in FIG. 2 (step 220), removing the release layer 128 to expose the second adhesive layer 124 to obtain the first superimposing unit 320 and the second superimposing unit 330 of the embodiment.

The first stacking unit 320 includes a second polyimide layer 322, a third adhesive layer 323, a fourth adhesive layer 324, and a third conductive layer 326. The third adhesive layer 323 and the fourth adhesive layer 324 are respectively disposed on the third surface 322a and the fourth surface 322b of the second polyimide layer 322. The fourth adhesive layer 324 is exposed and faces the first conductive layer 315 (first wiring layer 315a). The third conductive layer 326 is disposed on the third adhesive layer 323.

The second superimposing unit 330 includes a third polyamidamine layer 332, a fifth adhesive layer 333, a sixth adhesive layer 334, and a fourth conductive layer 336. The fifth adhesive layer 333 and the sixth adhesive layer 334 are disposed on the fifth surface 332a and the sixth surface 332b, respectively. And the sixth adhesive layer 334 is exposed and faces the second conductive layer 316 (the second wiring layer 316a). The fourth conductive layer 336 is disposed on the fifth adhesive layer 333.

Then, as shown in FIG. 3D, a pressing step is performed, and the pressing temperature is higher than 160 ° C, and the first stacking unit 320, the core unit 310 and the second stacking unit 330 are pressed together, so that the fourth adhesive layer 324 is bonded to the first A conductive layer 315 (first wiring layer 315a) and a sixth adhesive layer 334 are bonded to the second conductive layer 316 (second wiring layer 316a). In this step, the fourth adhesive layer 324 and the sixth adhesive layer 334 are converted from a semi-cured B-stage state to a solidified C-stage state.

As described above, since the core layer, the superimposing unit, and the bonding layer in the bonding unit of the present application can withstand high temperatures, it can be ensured that the pressing step of the embodiment is compatible with the high temperature pressing process and equipment of the known printed circuit board, New process equipment must be developed to avoid cost increases. Specifically, the pressing temperature of the aforementioned pressing step is approximately between 160 ° C and 200 ° C.

Next, as shown in FIG. 3E, conductive vias 340 are formed through the first stacking unit 320, the core unit 310, and the second stacking unit 330 to electrically connect the third conductive layer 326 and the first wiring layer 315a (the first conductive layer). 315), a second wiring layer 316a (second conductive layer 316) and a fourth conductive layer 336. Also, the third conductive layer 326 and the fourth conductive layer 336 are patterned to form a third wiring layer 326a and a fourth wiring layer 336a, respectively. In other words, the conductive via 340 formed in this embodiment is a guide The plated through holes of the four-layer line such as the third circuit layer 326a, the first circuit layer 315a, the second circuit layer 316a, and the fourth circuit layer 336a.

Of course, in other embodiments, the conductive via 340 may be formed in a portion of the first superimposing unit 320, the core unit 310, and the second superimposing unit 330 by adjusting a process step and a line layout. At least two of the third wiring layer 326a, the first wiring layer 315a, the second wiring layer 316a, and the fourth wiring layer 336a are connected. For example, the conductive vias 340 are formed in the first stacking unit 320 and the core unit 310 to electrically connect the third wiring layer 326a, the first wiring layer 315a, and the second wiring layer 316a. Alternatively, the conductive vias 340 are formed in the first stacking unit 320 to electrically connect the third wiring layer 326a and the first wiring layer 315a.

Next, as shown in FIG. 3F, a first solder mask layer 352 and a second solder mask layer 354 are formed on the third wiring layer 326a and the fourth wiring layer 336a, respectively. The first solder mask layer 352 has one or more openings 352a to expose a portion of the third wiring layer 326a as an external contact. The second shroud layer 354 has one or more openings 354a to expose a portion of the fourth wiring layer 336a as an external contact. Thus, the fabrication of the four-layer wiring board 300 of the present embodiment is substantially completed.

In the case of a conventional flexible circuit board having four layers of wiring, the conventional four-layer flexible circuit board requires two rapid pressing processes for pressing the outermost two wiring layers and a cover layer, for example, a protective film. It is a PET substrate. However, this embodiment requires only one press-fitting step to form a four-layer circuit board. Therefore, it is relatively simple in the process.

4A-4I illustrate a six-layer circuit board process in accordance with an embodiment of the present application.

First, as shown in FIG. 4A, a core unit 410 is provided. Here, for example, the core unit 110 of FIG. 1A is selected as the core unit 410 of the present embodiment. The core unit 410 includes a first polyimide layer 412, a first adhesive layer 413, a second adhesive layer 414, a first conductive layer 415, and a second conductive layer 416. The first adhesive layer 413 and the second adhesive layer 414 are respectively disposed on the first surface 412a and the second surface 412b of the first polyimide layer 412. The first conductive layer 415 is disposed on the first adhesive layer 413. The second conductive layer 416 is disposed on the second adhesive layer 414.

After the core unit 110 of FIG. 1A is selected as the core unit 410 of the present embodiment, the core unit 410 may also be selected to perform pre-processing as shown in FIG. 2 (step 220). As shown in FIG. 4B, the present embodiment may selectively pattern the first conductive layer 415 and the second conductive layer 416 to form a first wiring layer 415a and a second wiring layer 416a, respectively. In other embodiments, the first conductive layer 415 and the second conductive layer 416 may not be patterned as a signal reference plane, a power plane or a ground plane, or the like.

On the other hand, as shown in FIG. 4C, a first superimposing unit 420 and a second superimposing unit 430 are respectively provided on opposite sides of the core unit 410. Here, for example, the superimposing unit 120 of FIG. 1B is selected as the first superimposing unit 420 and the second superimposing unit 430 of the present embodiment, wherein the superimposing unit 120 of FIG. 1B is subjected to pre-processing as shown in FIG. 2 (step 220), removing the release layer 128 to expose the second adhesive layer 124 to obtain the first superimposing unit 420 and the second superimposing unit 430 of the embodiment.

The first stacking unit 420 includes a second polyimide layer 422 and a third layer 423, a fourth adhesive layer 424 and a third conductive layer 426. The third adhesive layer 423 and the fourth adhesive layer 424 are respectively disposed on the third surface 422a and the fourth surface 422b of the second polyimide layer 422. The fourth adhesive layer 424 is exposed and faces the first conductive layer 415 (first wiring layer 415a). The third conductive layer 426 is disposed on the third adhesive layer 423.

The second stacking unit 430 includes a third polyimide layer 432, a fifth adhesive layer 433, a sixth adhesive layer 434, and a fourth conductive layer 436. The fifth adhesive layer 433 and the sixth adhesive layer 434 are disposed on the fifth surface 432a and the sixth surface 432b, respectively. The sixth adhesive layer 434 is exposed and faces the second conductive layer 416 (second wiring layer 416a). The fourth conductive layer 436 is disposed on the fifth adhesive layer 433.

Then, as shown in FIG. 4D, a first pressing step is performed, and the pressing temperature is higher than 160 ° C, and the first superimposing unit 420, the core unit 410 and the second superimposing unit 430 are pressed to join the fourth adhesive layer 424. The first conductive layer 415 (first wiring layer 415a) is bonded to the second conductive layer 416 (second wiring layer 416a). In this step, the fourth adhesive layer 424 and the sixth adhesive layer 434 are transformed from a semi-cured B-stage state to a cured C-stage state. Specifically, the pressing temperature of the aforementioned pressing step is approximately between 160 ° C and 200 ° C.

Next, as shown in FIG. 4E, the embodiment may select the patterned third conductive layer 426 and the fourth conductive layer 436 to form a third wiring layer 426a and a fourth wiring layer 436a, respectively.

Then, as shown in FIG. 4F, another first superimposing unit 470 is provided on the previous first superimposing unit 420, and another second superimposing unit 480 is provided on the previous second superimposing unit 430. Here, for example, the superimposing unit 120 of FIG. 1B is selected for The first superimposing unit 470 and the second superimposing unit 480 of the present embodiment, wherein the superimposing unit 120 of FIG. 1B also needs to remove the release layer 128 via the pre-processing (step 220) as shown in FIG. 2 to expose The first bonding unit 470 and the second superimposing unit 480 of the embodiment can be obtained by the second bonding layer 124.

The first stacking unit 470 includes a second polyimide layer 472, a third adhesive layer 473, a fourth adhesive layer 474, and a third conductive layer 476. The third adhesive layer 473 and the fourth adhesive layer 474 are respectively disposed on the third surface 472a and the fourth surface 472b of the second polyimide layer 472. The fourth adhesive layer 474 is exposed and faces the third wiring layer 426a. The third conductive layer 476 is disposed on the third adhesive layer 473.

The second stacking unit 480 includes a third polyimide layer 482, a fifth adhesive layer 483, a sixth adhesive layer 484, and a fourth conductive layer 486. The fifth adhesive layer 483 and the sixth adhesive layer 484 are respectively disposed on the fifth surface 482a and the sixth surface 482b of the third polyimide layer 482. The sixth adhesive layer 484 is exposed and faces the fourth circuit layer 436a of the previous second stacking unit 430. The fourth conductive layer 486 is disposed on the fifth adhesive layer 483.

Thereafter, as shown in FIG. 4G, a second pressing step is performed, and the pressing temperature is higher than 160 ° C, and the first superimposing unit 470, the first superimposing unit 420, the core unit 410, and the second superimposing unit 430 are pressed. The second stacking unit 480 bonds the fourth adhesive layer 474 to the third conductive layer 426 (third wiring layer 426a), and the sixth adhesive layer 484 is bonded to the fourth conductive layer 436 (fourth wiring layer 436a). In this step, the fourth adhesive layer 474 and the sixth adhesive layer 484 are converted from a semi-cured B-stage state to a solidified C-stage state. Specifically, the pressing temperature of the aforementioned second pressing step is approximately between 160 ° C and 200 ° C.

Next, as shown in FIG. 4H, conductive vias 440 are formed through the first stacking unit 470, the first stacking unit 420, the core unit 410, the second stacking unit 430, and the second stacking unit 480 to electrically connect the third conductive layer. 476, a third circuit layer 426a, a first circuit layer 415a, a second circuit layer 416a, a fourth circuit layer 436a, and a fourth conductive layer 486. Also, the third conductive layer 476 and the fourth conductive layer 486 are patterned to form a third wiring layer 476a and a fourth wiring layer 486a, respectively. In other words, the conductive via 440 formed in this embodiment is a conductive third via layer 476a, a third wiring layer 426a, a first wiring layer 415a, a second wiring layer 416a, a fourth wiring layer 436a, and a fourth wiring layer 486a. Plated through holes for layer lines.

Of course, in other embodiments, the first superimposing unit 470, the first superimposing unit 420, the core unit 410, and the second superimposing unit that form the conductive via 440 in a portion may also be selected by adjusting a process step and a line layout. 430 and the second superimposing unit 480 are electrically connected to the third circuit layer 476a, the third circuit layer 426a, the first circuit layer 415a, the second circuit layer 416a, the fourth circuit layer 436a, and the fourth circuit layer 486a. At least two. For example, the conductive vias 440 are formed in the first stacking unit 470, the first stacking unit 420, and the core unit 410 to electrically connect the third wiring layer 476a, the third wiring layer 426a, the first wiring layer 815a, and the second. Circuit layer 416a. Alternatively, the conductive vias 440 are formed in the first stacking unit 470 and the first stacking unit 420 to electrically connect the third wiring layer 476a, the third wiring layer 426a, and the first wiring layer 415a.

Next, as shown in FIG. 4I, a first solder mask layer 452 and a second solder mask layer 454 are formed on the third wiring layer 476a and the fourth wiring layer 486a, respectively. First welding The cover layer 452 has one or more openings 452a to expose a portion of the third wiring layer 476a as an external contact. The second shroud layer 454 has one or more openings 454a to expose a portion of the fourth wiring layer 486a as an external contact. Thus, the fabrication of the six-layer wiring board 400 of the present embodiment is substantially completed.

Based on the foregoing various embodiments, one can press one or more of the superimposing unit of FIG. 1B to one side or opposite sides of the core unit 110 of FIG. 1A by one or more pressing processes to form various Multi-layer circuit board. Therefore, the present application is not limited to the four-layer wiring board 300 shown in FIG. 3F and the six-layer wiring board 400 shown in FIG. 4I.

For example, after the second pressing step shown in FIG. 4G, another first superimposing unit and another second superimposing unit may be separately provided on the first superimposing unit 470 and the second superimposing unit 480, and pressed. The other pressing step is performed at a temperature higher than 160 ° C, and the newly added first superimposing unit is joined to the previous first superimposing unit 470, and the newly added second superimposing unit is joined to the previous second superimposing unit. 480 on. In addition, patterning of the conductive layer and fabrication of the conductive vias may be selected to form an eight-layer wiring board.

Alternatively, the above steps may be repeated to form a plurality of layers of even-numbered wiring boards. I will not repeat them here.

The technical solution of the present application can be further used to fabricate a circuit board structure similar to a soft and hard composite board. In other words, the aforementioned core unit 110, the superimposing unit 120, and the joining unit 130 can be applied to form the wiring board of the present embodiment.

5A-5I illustrate a circuit board process in accordance with an embodiment of the present application.

First, as shown in FIG. 5A, a first core unit 510, a second core unit 520, and a third core unit 530 are provided. Here, for example, the core unit 110 of FIG. 1A is selected as the first core unit 510, the second core unit 520, and the third core unit 530 of the present embodiment. The second core unit 520 and the third core unit 530 are respectively located at two sides of the first core unit 510.

The first core unit 510 includes a first polyimide layer 512, a first adhesive layer 513, a second adhesive layer 514, a first conductive layer 515, and a second conductive layer 516. The first adhesive layer 513 and the second adhesive layer 514 are disposed on the first surface 512a and the second surface 512b, respectively. The first conductive layer 515 is disposed on the first adhesive layer 513. The second conductive layer 516 is disposed on the second adhesive layer 514.

The second core unit 520 includes a second polyimide layer 522, a third adhesive layer 523, a fourth adhesive layer 524, a third conductive layer 525, and a fourth conductive layer 526. The third adhesive layer 523 and the fourth adhesive layer 524 are respectively disposed on the third surface 522a and the fourth surface 522b of the second polyimide layer 522. The third conductive layer 525 is disposed on the third adhesive layer 523. The fourth conductive layer 526 is disposed on the fourth adhesive layer 524 and faces the first conductive layer 515.

The third core unit 530 includes a third polyimide layer 532, a fifth adhesive layer 533, a sixth adhesive layer 534, a fifth conductive layer 535, and a sixth conductive layer 536. The fifth adhesive layer 533 and the sixth adhesive layer 534 are disposed on the fifth surface 532a and the sixth surface 532b, respectively. The fifth conductive layer 535 is disposed on the fifth adhesive layer 533. The sixth conductive layer 536 is disposed on the sixth adhesive layer 534 and faces the second conductive layer 516.

The core unit 110 of FIG. 1A is selected as the first core of the embodiment. After the unit 510, the second core unit 520, and the third core unit 530, the first core unit 510, the second core unit 520, and the third core unit 530 may also be selected to perform pre-processing as shown in FIG. 2 (step 220). ). In this embodiment, the first conductive layer 515 and the second conductive layer 516 of the first core unit 510 may be patterned to form a first circuit layer 515a and a second circuit layer 516a, respectively. At the same time, a first conductive via 592 is formed in the first core unit 510 to electrically connect the first wiring layer 515a (the first conductive layer 515) and the second wiring layer 516a (the second conductive layer 516). In addition, the fourth conductive layer 526 of the second core unit 520 and the sixth conductive layer 536 of the third core unit 530 may also be selected to form the shield patterns 526a and 536a, respectively. Of course, in other embodiments, the conductive layer of each core unit may be patterned or not patterned to be a different component such as a circuit layer, a signal reference surface, a power supply surface, or a ground plane.

Next, as shown in FIG. 5C, a seventh adhesive layer 542 is provided between the first core unit 510 and the second core unit 520, and an eighth adhesive layer 544 is provided between the first core unit 510 and the third core unit 530. . Here, the seventh adhesive layer 542 and the eighth adhesive layer 544 are in a semi-cured B-stage state, and the material thereof is, for example, the foregoing first adhesive layer 513, second adhesive layer 514, third adhesive layer 523, and fourth adhesive layer 524. The fifth adhesive layer 533 and the sixth adhesive layer 534 are the same, and are not described herein again.

Then, as shown in FIG. 5D, a first pressing step is performed, and the pressing temperature is higher than 160 ° C, and the first core unit 510, the second core unit 520 and the third core unit 530 are pressed together, so that the fourth conductive layer 526 is borrowed. Bonded to the first conductive layer 515 by the seventh adhesive layer 542, and the sixth conductive layer 536 is bonded to the second conductive layer by the eighth adhesive layer 544 516. In this step, the seventh adhesive layer 542 and the eighth adhesive layer 544 are converted from a semi-cured B-stage state to a solidified C-stage state. Specifically, the pressing temperature of the first pressing step of the present embodiment is approximately between 160 ° C and 200 ° C.

Next, as shown in FIG. 5E, the third conductive layer 525 of the second core unit 520 and the fifth conductive layer 535 of the third core unit 530 may be selected and patterned. Here, for example, the third conductive layer 525 and the fifth conductive layer 535 in the first region A1 are removed, and the remaining third conductive layer 525 and fifth conductive layer 535 are formed into a third wiring layer 525a and a fifth, respectively. Circuit layer 535a.

Then, as shown in FIG. 5F, the first superimposing unit 550 and the second superimposing unit 560 are respectively provided on opposite sides of the first core unit 510. Here, for example, the superimposing unit 120 of FIG. 1B is selected as the first superimposing unit 550 and the second superimposing unit 560 of the present embodiment, wherein the superimposing unit 120 of FIG. 1B is subjected to pre-processing as shown in FIG. 2 (step 220), removing the release layer 128 to expose the second adhesive layer 124 to obtain the first superimposing unit 550 and the second superimposing unit 560 of the embodiment.

The first superimposing unit 550 includes a fourth polyamidamine layer 552, a ninth subbing layer 553, a tenth subbing layer 554, and a seventh conductive layer 556. The ninth adhesive layer 553 and the tenth adhesive layer 554 are respectively disposed on the seventh surface 552a and the eighth surface 552b of the fourth polyimide layer 552. The tenth adhesive layer 554 is exposed and faces the third conductive layer 525. The seventh conductive layer 556 is disposed on the ninth adhesive layer 553.

The second superimposing unit 560 includes a fifth polyamidamine layer 562, an eleventh adhesive layer 563, a twelfth adhesive layer 564, and an eighth conductive layer 566. The eleventh adhesive layer 563 and the twelfth adhesive layer 564 are respectively disposed on the ninth surface 562a of the fifth polyamidamine layer 562 and the first Ten on the surface 562b. The twelfth adhesive layer 564 is exposed and faces the fifth conductive layer 535. The eighth conductive layer 566 is disposed on the eleventh adhesive layer 563.

Next, as shown in FIG. 5G, a second pressing step is performed, and the pressing temperature is higher than 160 ° C, and the first superimposing unit 550, the second superimposing unit 560, the first core unit 510, and the second core unit 520 are pressed. The third core unit 530 is bonded to the third conductive layer 525 and the twelfth adhesive layer 564 is bonded to the fifth conductive layer 535. In this step, the tenth adhesive layer 554 and the twelfth adhesive layer 564 are transformed from a semi-cured B-stage state to a solidified C-stage state.

In this embodiment, the first superimposing unit 550 in the first area A1 may be removed before the second pressing step, so that the first superimposing unit 550 is after being pressed to the second core unit 520 and the third conductive unit. Layer 525 collectively exposes third glue layer 523 within first region A1. In addition, the second superimposing unit 560 in the first area A1 may be removed before the second pressing step, so that the second superimposing unit 560 is exposed together with the fifth conductive layer 535 after being pressed to the third core unit 530. The fifth glue layer 533 in the first area A1. Specifically, the pressing temperature of the second pressing step of the present embodiment is approximately between 160 ° C and 200 ° C.

Then, as shown in FIG. 5H, the present embodiment may select the seventh conductive layer 556 of the first superimposing unit 550 and the eighth conductive layer 566 of the second superimposing unit 560 to form a seventh wiring layer 556a and an eighth, respectively. Circuit layer 566a. In addition, the second conductive via 594 can also be formed in at least part of the first superimposing unit 550, the second core unit 520, the first core unit 510, the third core unit 530, and the second superimposing unit 560. Electrically connecting the seventh conductive layer 556, the first At least two of the third conductive layer 525, the fourth conductive layer 526, the first conductive layer 515, the second conductive layer 516, the sixth conductive layer 536, the fifth conductive layer 535, and the eighth conductive layer 566. Here, for example, the second conductive via 594 is penetrated through the first stacking unit 550, the second core unit 520, the first core unit 510, the third core unit 530, and the second stacking unit 560 to electrically connect the seventh conductive layer. 556. The third conductive layer 525, the fourth conductive layer 526, the first conductive layer 515, the second conductive layer 516, the sixth conductive layer 536, the fifth conductive layer 535, and the eighth conductive layer 566.

In addition, the embodiment further selects, for example, laser cutting to remove a portion of the second core unit 520 and a portion of the seventh adhesive layer 542 in the first region A1 to expose a portion of the first conductive layer 515a. As a plurality of conductive terminals T. Of course, we can also choose to remove the seventh glue layer 542 in the first area A1 before the first pressing step of FIG. 13D. The present application does not limit the point in time at which the seventh subbing layer 542 is removed.

Thereafter, as shown in FIG. 5I, a first solder mask layer 572 is formed on the seventh conductive layer 556 (seventh wiring layer 556a), and a second solder mask layer 574 is formed on the eighth conductive layer 566 (eighth wiring layer 566a). )on. The first solder mask layer 572 has one or more openings 572a to expose a portion of the seventh wiring layer 556a as an external contact. The second shroud layer 574 has one or more openings 574a to expose a portion of the eighth wiring layer 566a as an external contact.

Thus, the fabrication of the circuit board 500 is substantially completed. The wiring board 500 obtained by the process according to the present embodiment can be divided into a first region A1 having a small thickness and a second region A2 having a relatively thick thickness. The portion of the circuit board 500 may have a flexible property like a flexible circuit board due to its thin thickness, and is externally connected by the conductive terminal T. Pick up. In addition, the thickness of the portion of the second region A2 of the wiring board 500 is thick, and a wiring structure of more layers can be formed by repeatedly joining a plurality of superimposing units, thereby providing a wiring layout space equivalent to a known printed wiring board. With elasticity. In other words, the circuit board proposed in this embodiment integrates the advantages of the known printed circuit board (hard board) and the flexible circuit board (soft board) at the same time, and the circuit board can be completed by the same process, so the process is simple and fast. And can reduce production costs.

In the case of a conventional six-layer soft and hard board, a quick press-fitting process is required for the flexible circuit board portion to press a cover layer, for example, a PET substrate. For the portion of a conventional printed circuit board, two press-bonding processes are required to form another four-layer line.

However, in the present embodiment, only two second pressing steps are required to form a wiring board having six wiring layers. Therefore, the process of this embodiment is relatively fast and simple.

The following is a comparison of various embodiments of the present application with conventional printed circuit boards.

Referring to Table 1, the thickness of the circuit board formed by the present application is thinner than that of the conventional printed circuit board. In more detail, the thickness of the four-layer wiring board of the present application is only 41.2% of the thickness of the conventional four-layer printed circuit board. The thickness of the ten-layer circuit board of the present application Only 74.6% of the thickness of a traditional ten-layer printed circuit board. The thickness of the six-layer soft and hard board of the present application is only 68.9% of the thickness of the conventional six-layer soft and hard board.

Compared with the conventional printed circuit board, the FR4 substrate has a high dielectric constant. The present application uses a polyimide layer as a substrate and a high temperature resistant rubber material, and has a dielectric constant of less than about 3. Therefore, the present application has The electrical characteristics of the board are preferred.

Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and refinements without departing from the spirit and scope of the present application. The scope of protection of this application is subject to the definition of the scope of the patent application.

300‧‧‧ four-layer circuit board

310‧‧‧ core unit

320, 330‧‧‧ superimposed unit

312, 322, 332‧‧ ‧ polyimide layer

313, 314, 323, 324, 333, 334‧‧ ‧ layers

315a, 316a, 326a, 336a‧‧‧ circuit layer

340‧‧‧ conductive holes

352, 354‧‧‧ welding cover

352a, 354a‧‧

Claims (20)

A circuit board process includes: providing a core unit, the core unit comprising: a first polyimide layer having two opposite first and a second surface; and a first adhesive layer disposed on the first a second adhesive layer disposed on the second surface; a first conductive layer disposed on the first adhesive layer; and a second conductive layer disposed on the second adhesive layer; a first superimposing unit, and the first superimposing unit comprises: a second polyamidamine layer having two opposite ones of the third and a fourth surface; a third adhesive layer disposed on the third surface; a fourth adhesive layer disposed on the fourth surface and facing the first conductive layer; and a third conductive layer disposed on the third adhesive layer; and performing a first pressing step, and the pressing temperature is high Pressing the first stacking unit and the core unit at 160 ° C to bond the fourth adhesive layer of the first stacking unit to the first conductive layer. The circuit board process of claim 1, wherein before the first pressing step, the circuit board process further comprises: providing a second superimposing unit, and the second superimposing unit comprises: a third polyamidamine layer having two opposite fifth and sixth surfaces; a fifth adhesive layer disposed on the fifth surface; a sixth adhesive layer disposed on the sixth surface And facing the second conductive layer; and a fourth conductive layer disposed on the fifth adhesive layer, wherein during the performing the first pressing step, simultaneously pressing the first superimposing unit and the second superimposing layer And the core unit, the fourth adhesive layer is bonded to the first conductive layer, and the sixth adhesive layer is bonded to the second conductive layer. The circuit board process of claim 2, wherein after the first pressing step, the circuit board process further comprises: forming a first solder mask layer on the third conductive layer; and forming a first A second solder mask layer is on the fourth conductive layer. The circuit board process of claim 2, wherein after the first pressing step, the circuit board process further comprises: providing another first superimposing unit, wherein the first one of the other first superimposing units The fourth adhesive layer is exposed, and faces the third conductive layer of the first first superimposing unit; and another second superimposing unit is provided, wherein the sixth adhesive layer of the other second superimposing unit is exposed, and faces the front second a fourth conductive layer of the superimposing unit; and performing a second pressing step, and the pressing temperature is higher than 160 ° C, pressing all of the first superimposing unit, the second superimposing unit and the core unit to make the other first The fourth adhesive layer of the stacking unit is bonded to the third conductive layer of the previous first stacked unit and the The sixth adhesive layer of the other second superimposing unit to the fourth conductive layer of the previous second superimposing unit. The circuit board process of claim 4, wherein after the second pressing step, the circuit board process further comprises: forming a first solder mask layer on the third conductive layer of the outermost layer; Forming a second solder mask layer on the fourth conductive layer of the outermost layer. The circuit board process of claim 4, wherein the second pressing step has a pressing temperature of between about 160 ° C and 200 ° C. The circuit board process of claim 1, wherein the first pressing step has a pressing temperature of between about 160 ° C and 200 ° C. A circuit board comprising: a core unit comprising: a first polyamidamine layer having two opposite first and a second surface; a first adhesive layer disposed on the first surface; a second adhesive layer disposed on the second surface; a first conductive layer disposed on the first adhesive layer; and a second conductive layer disposed on the second adhesive layer; and a first superimposing unit, Disposed on a first side of the core unit, and the first superimposing unit comprises: a second polyamidamine layer having two opposite ones of the third and a fourth surface; a third adhesive layer disposed on the third surface; a fourth adhesive layer disposed on the fourth surface and bonded to the first conductive layer; and a third conductive layer disposed on the third adhesive On the layer, wherein the first, the second, the third and the fourth adhesive layer have a glass transition temperature of between about 140 ° C and 160 ° C. The circuit board of claim 8, further comprising: a second superimposing unit located on a second side of the core unit, the second superimposing unit comprising: a third polyamidamine layer having two a fifth and a sixth surface; a fifth adhesive layer disposed on the fifth surface; a sixth adhesive layer disposed on the sixth surface and bonded to the second conductive layer, wherein the The fifth and the sixth adhesive layer have a glass transition temperature of between about 140 ° C and 160 ° C; and a fourth conductive layer disposed on the fifth adhesive layer. The circuit board of claim 9, further comprising: a first solder mask layer on the third conductive layer; and a second solder mask layer on the fourth conductive layer. The circuit board of claim 9, further comprising: at least another first superimposing unit located on the first side of the core unit, wherein the fourth adhesive layer of the other first superimposing unit is coupled to The first one of the first superimposing units a third conductive layer; and at least another second superimposing unit located on the second side of the core unit, wherein the sixth adhesive layer of the other second superimposing unit is bonded to the fourth of the previous second superimposing unit Conductive layer. The circuit board of claim 11, further comprising: a first solder mask layer on the third conductive layer on the outermost layer; and a second solder mask layer on the outermost layer of the fourth conductive layer On the floor. The circuit board of claim 9, wherein the fifth and the sixth adhesive layer have a dielectric constant of less than about 3. The circuit board of claim 8, wherein the first, the second, the third and the fourth adhesive layer have a dielectric constant of less than about 3. A circuit board comprising: a first core unit comprising: a first polyamidamine layer having two opposite first and a second surface; a first adhesive layer disposed on the first surface; a second adhesive layer disposed on the second surface; a first conductive layer disposed on the first adhesive layer; and a second conductive layer disposed on the second adhesive layer; a second core unit Located on a first side of the first core unit, the second core unit includes: a second polyamidamine layer having two opposite ones, a third and a fourth table a third adhesive layer disposed on the third surface; a fourth adhesive layer disposed on the fourth surface; a third conductive layer disposed on the third adhesive layer; and a fourth conductive layer a layer disposed on the fourth adhesive layer, the fourth conductive layer facing the first conductive layer; a third core unit located on a second side of the first core unit, the third core unit comprising: a first a third polyimide layer having two opposite fifth and sixth surfaces; a fifth adhesive layer disposed on the fifth surface; a sixth adhesive layer disposed on the sixth surface; a fifth conductive layer disposed on the fifth adhesive layer; and a sixth conductive layer disposed on the sixth adhesive layer, the sixth conductive layer facing the second conductive layer; a seventh adhesive layer, wherein the first conductive layer The fourth conductive layer is bonded to the first conductive layer by the seventh adhesive layer; an eighth adhesive layer, wherein the sixth conductive layer is bonded to the second conductive layer by the eighth adhesive layer; Located on the first side of the first core unit, the first stacking unit comprises: a fourth polyamidamine layer having two One seventh and an eighth table a ninth adhesive layer disposed on the seventh surface; a tenth adhesive layer disposed on the eighth surface, the tenth adhesive layer bonded to the third conductive layer; and a seventh conductive layer, Arranging on the ninth rubber layer; and a second superimposing unit on the second side of the first core unit, the second superimposing unit comprising: a fifth polyamidamine layer having two opposite ones a tenth and a tenth surface; an eleventh adhesive layer disposed on the ninth surface; a twelfth adhesive layer disposed on the tenth surface, the twelfth adhesive layer bonded to the fifth conductive layer And an eighth conductive layer disposed on the eleventh rubber layer, wherein the first, the second, the third, the fourth, the fifth, the sixth, the seventh, the eighth The glass transition temperature of the ninth, the tenth, the eleventh and the twelfth rubber layer is between 140 ° C and 160 ° C. The circuit board of claim 15, further comprising: a first solder mask layer on the seventh conductive layer; and a second solder mask layer on the eighth conductive layer. The circuit board of claim 15, wherein the circuit board has a first area, and the first superimposing unit of the part of the first area is removed, so that the first superimposing unit and the first The three conductive layers collectively expose the first region A portion of the third layer of glue. The circuit board of claim 17, wherein the second superimposing unit of the portion in the first region is removed, so that the second superimposing unit and the fifth conductive layer together expose the first region A portion of the fifth adhesive layer, and the circuit board has a thickness in the first region that is less than a thickness of the circuit board in other regions. The circuit board of claim 18, wherein a portion of the seventh adhesive layer in the first region is removed, and the removed seventh adhesive layer corresponds to the first conductive layer And a plurality of conductive terminals, wherein a portion of the second core unit in the first region is removed to expose the conductive terminals. The circuit board of claim 15, wherein the first, the second, the third, the fourth, the fifth, the sixth, the seventh, the eighth, the ninth, The tenth, the eleventh and the twelfth sublayer have a dielectric constant of less than about 3.