TWI462115B - Memory apparatus and negative bit-line signal generating apparatus - Google Patents

Description

Memory device and negative bit line signal generating device thereof

The present invention relates to a memory device, and more particularly to a negative bit line signal generating device for a memory device.

With the advancement of electronic technology, electronic products have become an indispensable tool in people's daily lives. Memory devices used to record information in electronic products have also become an important part of this.

Taking Static Random Access Memory (SRAM) as an example, in the case where the operating voltage received by the electronic device is getting lower and lower, and the access speed is getting faster and faster, in the case of static random access When the memory is accessed, in order to increase the voltage difference between the bit line and the word line, a negative bit line signal that reduces the negative bit line signal to below the zero voltage level The technology was then put forward.

Conventional negative bit line signal generation techniques often occur at high operating voltages, which in turn produce negative bit line signals with larger absolute values of voltage. As a result, the voltage difference between the gate and the source of the transistor receiving the bit line signal and the word line signal is excessively large. Under long-term use, this transistor may be damaged and cause leakage or malfunction. It also causes a decrease in the reliability of the static random access memory.

The present invention provides a negative bit line signal generating device that provides a negative bit line signal of a stable voltage level under different operating voltages of different sizes.

The invention provides a memory device, which belongs to a negative bit line signal generating device, which can provide a negative voltage line signal with a stable voltage level under different operating voltages of different sizes.

The invention provides a negative bit line signal generating device, which comprises a pre-charging channel, a discharging channel and a capacitor. The precharge channel is coupled between the operating voltage and the negative push terminal, controlled by the voltage push enable signal to charge the negative push terminal during the first time interval. The discharge channel is coupled between the negative push terminal and the reference voltage, and provides a negative push end discharge path in the second time interval according to the voltage push enable signal and the voltage push termination signal. One end of the capacitor is coupled to the negative push terminal, and the other end is coupled to the bit line to generate a negative bit line signal. The first time interval and the second time interval do not overlap, the operating voltage is greater than the reference voltage, and the time length of the second time interval is opposite to the magnitude of the operating voltage.

The present invention further provides a memory device having a plurality of bit lines and including a plurality of negative bit line signal generating devices, wherein each negative bit line signal generating device includes a precharge channel, a discharge channel, and a capacitor . The precharge channel is coupled between the operating voltage and the negative push terminal, controlled by the voltage push enable signal to charge the negative push terminal during the first time interval. The discharge channel is coupled between the negative push terminal and the reference voltage, and provides a negative push end discharge path in the second time interval according to the voltage push enable signal and the voltage push termination signal. One end of the capacitor is coupled to the negative push terminal, and the other end is coupled to the corresponding connected bit line to generate a negative bit line signal. The first time interval and the second time interval do not overlap, the operating voltage is greater than the reference voltage, and the time length of the second time interval is opposite to the magnitude of the operating voltage.

Based on the above, in the negative bit line signal generating device of the present invention, the discharge channel changes the resistance value provided by the discharge channel according to the voltage pushing termination signal, so that the negative position generated by the operating voltage of different magnitudes can be made. The voltage level of the line signal does not change significantly. As a result, the phenomenon of an excessively low negative bit line signal caused by a high operating voltage can be avoided, that is, the destruction of electronic components due to an excessively low negative bit line signal will also be possible. Effectively eliminates and improves the reliability of the memory device.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a negative bit line signal generating apparatus 100 according to an embodiment of the present invention. The negative bit line signal generating device 100 includes a precharge channel 110, a discharge channel 120, and a capacitor C _bst . The pre-charging channel 110 is coupled between the operating voltage VCC and the negative driving terminal NBST. The pre-charging channel 110 further receives the voltage boost enable signal BSTEN and is controlled by the voltage boost enable signal BSTEN to be negative in the first time interval. Push the endpoint NBST to charge. The discharge channel 120 is coupled between the negative push terminal NBST and the reference voltage GND. The discharge channel 120 receives the voltage push enable signal BSTEN and the voltage push termination signal BSTEND, and provides a reference voltage according to the voltage push enable signal BSTEN and the voltage push termination signal BSTEND in a second time interval that does not overlap with the first time interval. GND to negative push terminal NBST, causing negative push terminal NBST to discharge. In the present embodiment, the reference voltage GND is, for example, a ground voltage, and the voltage level of the reference voltage GND is smaller than the voltage level of the operating voltage VCC.

One end of the capacitor C _BST is coupled to the negative end push NBST, and the other end is coupled to the bit line BL and a negative bit line signal in the bit line NSBL.

In the present embodiment, the pre-charging channel 110 is constructed by a pull-up transistor MP, wherein the control terminal (eg, the gate) of the pull-up transistor MP receives the voltage boost enable signal BSTEN, and its first end (eg, source) The pole or the drain receives the operating voltage VCC, and the second end (eg, the drain or the source) is coupled to the negative push terminal NBST. The discharge channel 120 is formed by connecting two switches constructed by the transistors M1 and M2 in series. Wherein, the gate receiving voltage of the transistor M1 pushes the enable signal BSTEN, and the gate of the transistor M2 receives the voltage pushing termination signal BSTEND.

Please refer to FIG. 1 and FIG. 2 simultaneously, wherein FIG. 2 is a waveform diagram of the negative bit line signal generating apparatus 100 of FIG. In the first time interval T1, the voltage push enable signal BSTEN is a low level signal (for example, equal to the ground voltage), and the voltage push end signal BSTEND is a high level signal with respect to the voltage push enable signal BSTEN. At this time, the pull-up transistor MP is turned on and the negative capacitor terminal C _bst NBST push operation is charged to a voltage equal to VCC. Then entering the second time interval T2, the voltage push enable signal BSTEN is turned into a high level signal, and the pull-up transistor MP is turned off, and the transistors M1 and M2 are both turned on. In this case, the discharge channel 120 causes the ground voltage GND to be coupled to the negative push terminal NBST through the transistors M1 and M2. In contrast, the voltage on the bit line BL is pulled downward due to the boost effect generated by the capacitance C _bst , and accordingly the negative bit line signal NSBL is generated.

Note here that the voltage of the negative bit line signal NSBL can be obtained according to the following mathematical formula (1):

NSBL=-(VCC-V0)*C _bst /(C _bst +C _b1 ) (1)

Wherein, V0 is a voltage value that can be lowered by the negative push terminal NBST in the second time interval T2, and C _b1 is a capacitance value on the bit line BL.

It is to be noted that V0 in the mathematical formula (1) can be changed by controlling the length of time of the discharge channel 120 in the second time interval T2. Briefly, if the discharge channel 120 is shorter in the second time interval T2, the value of V0 will be a relatively high voltage. In contrast, if the discharge channel 120 is longer in the second time interval T2, then V0 The value will be a relatively low voltage (closer to the reference voltage GND). Therefore, it can be easily understood that when the voltage value of the operating voltage VCC changes, the negative bit line signal generating apparatus 100 of the present embodiment can change the value of V0 by controlling the length of the second time interval T2, and maintains The size of the negative bit line signal NSBL does not vary too much. Simply put, the length of the on-time of the transistor M2 is controlled by the voltage push termination signal BSTEND.

Referring to FIG. 3, FIG. 3 is a schematic diagram of a negative bit line signal generating apparatus 300 according to another embodiment of the present invention. The negative bit line signal generating device 300 further includes a voltage push termination signal generating circuit 330 in addition to the precharge channel 310, the discharge channel 320, and the capacitor C _bst . The voltage push termination signal generating circuit 330 is coupled to the precharge channel 310 and the discharge channel 320. The voltage push termination signal generating circuit 330 receives the voltage push enable signal BSTEN and generates a voltage push termination signal BSTEND in accordance with a voltage boost enable signal BSTEN equal to the operating voltage VCC in the second time interval.

Note that in the embodiment illustrated in FIG. 3, the voltage push termination signal generating circuit 330 includes transistors M3, M4 and a control signal generating circuit 331. The control terminal (gate) of the transistor M3 receives the voltage boost enable signal BSTEN, the first end (source/drain) is coupled to the operating voltage VCC, and the second end (drain/source) generates a voltage boost The signal BSTEND is terminated. The first end (source/drain) of the transistor M4 is coupled to the second end of the transistor M3, and the second end (drain/source) of the transistor M4 is coupled to the reference voltage GND, and its control terminal (gate) The pole is coupled to the control signal generating circuit 331 to receive the control signal PBST. The control signal generating circuit 331 is coupled to the operating voltage VCC and the reference voltage GND, and generates a control signal PBST according to the operating voltage VCC, wherein in the present embodiment, the control signal generating circuit 331 divides the operating voltage VCC to generate a control. Signal PBST.

The control signal generating circuit 331 includes capacitors C1 and C2 and a transistor DM1. The capacitors C1 and C2 are connected in series between the output of the inverter INV2 and the reference voltage GND. In the second time interval, the voltage boost enable signal BSTEN is equal to the operating voltage VCC, and therefore, the output of the inverter INV2 is also equal to the operating voltage VCC. The capacitors C1 and C2 divide the output of the inverter INV2 (operation voltage VCC) and generate a control signal PBST. Here, the voltage level of the control signal PBST can be obtained according to the capacitance ratio of the capacitors C1 and C2.

Please note that when the operating voltage VCC is a lower voltage, the voltage level of the control signal PBST will be close to the threshold voltage of the transistor M4. At this time, the discharge current that the transistor M4 can provide will be small and the voltage will be pushed. The voltage drop of the termination signal BSTEND is slowed down. Therefore, the length of time of the second time interval can be lengthened, and the voltage on the negative push terminal NBST can be lowered to a voltage level close to the reference voltage GND before the transistor M2 is turned off. Conversely, when the operating voltage VCC is a higher voltage, the voltage of the control signal PBST is boosted. At this time, the discharge current supplied by the transistor M4 is greater than the discharge current that the transistors M1 and M2 can provide. Therefore, the voltage push termination signal BSTEND can be quickly reduced to be equal to the reference voltage GND, and the discharge time (second time interval) at which the negative push terminal NBST discharges through the transistor M2 is shortened, so that the negative push terminal NBST The voltage is not too low to avoid excessively low negative bit line signal NSBL.

The control terminal of the transistor DM1 receives the reverse signal of the voltage boost enable signal BSTEN through the inverter INV1. The first end is coupled to the coupling point of the capacitor C1 and the capacitor C2, and the second end thereof is coupled to the reference voltage GND. . In the first time interval, the transistor DM1 is turned on in response to the inverted signal of the received voltage pushing enable signal BSTEN, and the capacitors C1 and C2 can pass through the transistor DM1 to release the stored charge therein. In this way, it can be ensured that the capacitors C1 and C2 have no residual charge before entering the second time interval.

Referring to FIG. 4A, FIG. 4A is a schematic diagram of a negative bit line signal generating apparatus 400 according to still another embodiment of the present invention. The negative bit line signal generating device 400 includes a precharge channel 410, a discharge channel 420, and a capacitor C _bst , and further includes a voltage push termination signal generating circuit 430. The voltage push termination signal generating circuit 430 is coupled to the precharge channel 410 and the discharge channel 420.

In the present embodiment, the voltage push termination signal generating circuit 430 includes transistors M3, M4 and a control signal generating circuit 431. Unlike the previous embodiment, the control signal generating circuit 431 steps down the operating voltage VCC and generates a control signal PBST. The control signal generating circuit 431 includes transistors M5, M6, and M7. The first end of the transistor M5 receives the operating voltage VCC, and the control terminal receives the reverse signal of the voltage pushing enable signal BSTEN, and the second end is coupled to the second end. The first end of the transistor M6. Moreover, the control end of the transistor M6 is coupled to the operating voltage VCC, and the second end thereof is coupled to the first end of the transistor M7. The second end of the transistor M7 is coupled to the reference voltage GND and its control terminal receives the reverse signal of the voltage boost enable signal BSTEN together with the control terminal of the transistor M5.

Note here that the transistor M6 is used as a step-down element, and the control signal PBST is equal to the operating voltage VCC minus the threshold voltage value of the transistor M6 in the second time interval. This stepped down control signal PBST is a length of time during which the discharge capacity of the transistor M4 can be increased or decreased as the operating voltage VCC rises or falls, and the second time interval is shortened or extended. That is to say, when the operating voltage VCC rises, the length of time in the second time interval is shortened, and when the operating voltage VCC decreases, the length of time in the second time interval increases. In this way, the negative bit line signal NSBL on the bit line BL can be maintained at a relatively stable voltage level, so as not to vary greatly with the level of the operating voltage VCC.

Please refer to FIG. 4B. FIG. 4B illustrates another embodiment of the negative bit line signal generating apparatus 400 according to the embodiment of the present invention. In the present embodiment, the transistor M6 of FIG. 4A can be replaced by the diode D1, and the diode D1 is used as the step-down element.

Referring to FIG. 5, FIG. 5 is a schematic diagram of a negative bit line signal generating apparatus 500 according to a further embodiment of the present invention. The negative bit line signal generating device 500 includes a precharge channel 510, a discharge channel 520, and a capacitor C _bst , and further includes a voltage push termination signal generating circuit 530. The voltage push termination signal generating circuit 530 is coupled to the precharge channel 510 and the discharge channel 520.

In the present embodiment, the voltage push termination signal generating circuit 530 includes an inverter INV0 and transistors M3 to M5. The output end of the inverter INV0 generates a voltage push termination signal BSTEND, the first end of the transistor M3 is coupled to the operating voltage VCC, the second end is coupled to the input end of the inverter INV0, and the control end is coupled to the power The first end of the crystal M4. The second end of the transistor M4 is coupled to the negative push terminal NBST, and the control terminal receives the reference voltage GND. The control end of the transistor M5 is coupled to the output end of the inverter INV1, and receives the reverse signal of the voltage boost enable signal BSTEN. The first end and the second end are respectively coupled to the second end of the transistor M3. And the reference voltage GND.

In the overall operation, during the first time interval, the negative push terminal NBST is precharged to be equal to the operating voltage VCC, and the voltage on the control terminal of the transistor M3 is equal to the operating voltage through the transmission channel provided by the transistor M4. VCC subtracts the threshold voltage of transistor M4. When the operating voltage VCC is a low level voltage, the reaction speed of the path formed by the transistor M3 and the inverter INV0 is insufficient to quickly turn off the transistor M2, that is, the second time interval is extended. Conversely, when the operating voltage VCC is a high level voltage, the reaction speed of the path formed by the transistor M3 and the inverter INV0 will be correspondingly increased, and therefore, the transistor M2 will be quickly turned off. That is, the second time interval will be shortened.

In this way, the second time interval is adaptively adjusted corresponding to the high or low operating voltage. The negative bit line signal NSBL on the bit line BL can be maintained at a relatively stable voltage level, so as not to vary greatly with the operating voltage VCC.

In addition, the transistor M5 is used to provide the input reference voltage GND of the inverter INV0 in the first time interval.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a memory device 600 according to an embodiment of the invention. The memory device 600 may be a static random access memory, and the memory device 600 includes a plurality of memory cells 601 to 60M and a plurality of negative bit line signal generating devices 610 to 61N. The negative bit line signal generating devices 610~61N are respectively coupled to the bit lines BL1~BLN and BL1B~BLNB connected to the memory cells 601~60M. The negative bit line signal generating devices 610 to 61N can be implemented by any of the negative bit line signal generating devices 100 to 500 illustrated in FIGS. 1 to 5 described above. The implementation details of the negative bit line signal generating devices 100 to 500 are described in detail in the foregoing embodiments, and the description thereof will not be repeated here.

In summary, the present invention adjusts the length of the second time interval of the discharge operation provided by the discharge channel according to the magnitude of the operating voltage. The level of the operating voltage can be matched with the time when the negative bit line signal is pulled low. In this way, the degree of the negative bit line signal being pulled down can be controlled, and the voltage level of the negative bit line signal generated by the negative bit line signal generating device can be effectively stabilized without operating voltage. The change, while the big change.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 300, 400, 500, 610~61N. . . Negative bit line signal generating device

110, 310, 410, 510. . . Precharge channel

120, 320, 420, 520. . . Discharge channel

330, 430, 530. . . Voltage push termination signal generation circuit

331, 431, 531. . . Control signal generation circuit

600. . . Memory device

601~60M. . . Memory cell

C1, C2, C _bst . . . capacitance

VCC. . . Operating voltage

BSTEN. . . Voltage boost enable signal

NBST. . . Negative push endpoint

BSTEND. . . Voltage push termination signal

BL, BL1~BLN, BL1B~BLNB. . . Bit line

NSBL. . . Negative bit line signal

MP, M1~M7. . . Transistor

GND. . . Reference voltage

T1, T2. . . Time interval

PBST. . . control signal

INV0~INV2. . . Inverter

D1. . . Dipole

FIG. 1 is a schematic diagram of a negative bit line signal generating apparatus 100 according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of the negative bit line signal generating apparatus 100 of FIG. 1.

FIG. 3 is a schematic diagram of a negative bit line signal generating apparatus 300 according to another embodiment of the present invention.

FIG. 4A is a schematic diagram of a negative bit line signal generating apparatus 400 according to still another embodiment of the present invention.

FIG. 4B illustrates another embodiment of a negative bit line signal generating apparatus 400 in accordance with an embodiment of the present invention.

FIG. 5 is a schematic diagram of a negative bit line signal generating apparatus 500 according to a further embodiment of the present invention.

FIG. 6 is a schematic diagram of a memory device 600 according to an embodiment of the invention.

100. . . Negative bit line signal generating device

110. . . Precharge channel

120. . . Discharge channel

C _bst . . . capacitance

VCC. . . Operating voltage

BSTEN. . . Voltage boost enable signal

NBST. . . Negative push endpoint

BSTEND. . . Voltage push termination signal

BL. . . Bit line

NSBL. . . Negative bit line signal

MP, M1, M2. . . Transistor

GND. . . Reference voltage

Claims (18)

A negative bit line signal generating device includes: a pre-charging channel coupled between an operating voltage and a negative driving terminal, controlled by a voltage boosting enable signal to push the negative in a first time interval The end point is charged; a discharge channel is coupled between the negative push terminal and a reference voltage, and according to the voltage push enable signal and a voltage push termination signal to provide the negative push end point in a second time interval a discharge path; and a capacitor having one end coupled to the negative push terminal and the other end coupled to the one bit line to generate the negative bit line signal, wherein the first time interval and the second time interval are not Overlapping, the operating voltage is greater than the reference voltage, and the length of time of the second time interval is opposite to the magnitude of the operating voltage. The negative bit line signal generating device of claim 1, wherein the discharge channel comprises: a first discharge switch, the first end of which is coupled to the negative push end, the first discharge switch receives the The voltage boosting enable signal is controlled by the voltage boost enable signal; and a second discharge switch is serially connected between the second end of the first discharge switch and the reference voltage, receiving the voltage push termination signal, and Controlled by this voltage pushes the termination signal. The negative bit line signal generating device of claim 2, wherein the first discharge switch and the second discharge switch are both a transistor switch. The negative bit line signal generating device of claim 1, wherein the pre-charging channel comprises: a pull-up transistor having a control end, a first end and a second end, wherein the control end receives the voltage boost The enable signal has a first end receiving the operating voltage and a second end coupled to the discharge channel. The negative bit line signal generating device of claim 1, wherein in the first time interval, the precharge channel provides the operating voltage to charge the negative push terminal on the capacitor. The negative bit line signal generating device of claim 1, wherein in the second time interval, the discharge channel supplies the reference voltage to the negative push terminal, and the capacitor is not coupled to the negative Pushing the voltage drop at the other end of the endpoint to generate the negative bit line signal. The negative bit line signal generating device of claim 1, further comprising: a voltage push termination signal generating circuit coupled to the precharge channel and the discharge channel, receiving the voltage boost enable signal, and In the second time interval, the voltage push termination signal is generated according to the voltage boost enable signal equal to the operating voltage. The negative bit line signal generating device of claim 7, wherein the voltage pushing termination signal generating circuit comprises: a first transistor having a control end, a first end and a second end, the control end receiving The voltage push enable signal has a first end coupled to the operating voltage and a second end generating the voltage push termination signal; a second transistor having a control end, a first end, and a second end, the first The second end of the first transistor is coupled to the second end, and the second end is coupled to the reference voltage; and a control signal generating circuit is coupled to the operating voltage, the reference voltage, and the control end of the second transistor The control signal generating circuit generates a control signal according to the operating voltage and provides the control signal to the control end of the second transistor. The negative bit line signal generating device of claim 8, wherein the control signal generating circuit divides the operating voltage to generate the control signal, the control signal generating circuit comprising: a first capacitor, Receiving the operating voltage at one end and generating the control signal at the other end; a second capacitor connected in series between the end point of the first capacitor generating the control signal and the reference voltage; and a third transistor having a control end, The first end and the second end, the control end receives the reverse signal of the voltage boost enable signal, the first end is coupled to the coupling point of the first capacitor and the second capacitor, and the second end is coupled To the reference voltage. The negative bit line signal generating device of claim 8, wherein the control signal generating circuit steps down the operating voltage and generates the control signal, the control signal generating circuit comprising: a third power a crystal having a first end, a second end, and a control end, the first end of which receives the operating voltage, the control end receives the reverse signal of the voltage boost enable signal; and a fourth transistor having a first end, a second end and a control end, the first end of which is coupled to the second end of the third transistor, the control end receives the operating voltage, the second end generates the control signal; and a fifth transistor has a first end The first end of the fourth transistor is coupled to the second end of the fourth transistor, the second end of the second transistor is coupled to the reference voltage, and the control end is coupled to the control of the third transistor end. The negative bit line signal generating device of claim 8, wherein the control signal generating circuit steps down the operating voltage and generates the control signal, the control signal generating circuit comprising: a third power a crystal having a first end, a second end, and a control end, the first end of which receives the operating voltage, the control end receives the reverse signal of the voltage boost enable signal; and a diode coupled to the second electrode a second end of the triode; and a fourth transistor having a first end, a second end, and a control end, the first end of which is coupled to the cathode of the diode, and the second end of which is coupled to the reference The control end of the voltage is coupled to the control end of the third transistor. The negative bit line signal generating device of claim 7, wherein the voltage push termination signal generating circuit comprises: an inverter, the output terminal generates the voltage pushing termination signal; and a first transistor having a first end, a second end, and a control end, the first end of which is coupled to the operating voltage, the second end of which is coupled to the input end of the inverter; and a second transistor having a first end and a second end And the first end of the second transistor is coupled to the control end of the first transistor, the second end of the second transistor is coupled to the negative push terminal, and the control end of the second transistor receives the reference And a third transistor having a first end, a second end, and a control end, wherein the control end receives the reverse signal of the voltage push enable signal, and the second end receives the reference voltage, and the first end is coupled Connect to the input of the inverter. A memory device having a plurality of bit line lines, the memory device comprising: a plurality of negative bit line signal generating devices respectively coupled to the bit lines, wherein each of the negative bit line signal generating devices comprises: a precharge channel coupled between an operating voltage and a negative push terminal, controlled by a voltage boost enable signal to charge the negative push terminal in a first time interval; a discharge channel coupled to The negative push terminal and a reference voltage are respectively provided according to the voltage boost enable signal and a voltage push termination signal to provide the negative push terminal-discharge path in a second time interval; and a capacitor coupled to one end of the capacitor The negative driving terminal is coupled to the corresponding bit line to generate the negative bit line signal, wherein the first time interval and the second time interval do not overlap, and the operating voltage is greater than the The reference voltage, and the length of time of the second time interval is opposite to the magnitude of the operating voltage. The memory device of claim 13, wherein the discharge channel comprises: a first discharge switch, the first end of which is coupled to the negative push terminal, receives the voltage boost enable signal, and is controlled And driving the enable signal; and a second discharge switch connected between the second end of the first discharge switch and the reference voltage, receiving the voltage push termination signal, and controlled by the voltage to push the termination signal. The memory device of claim 12, wherein the first discharge switch and the second discharge switch are both transistor switches. The memory device of claim 13, wherein the pre-charging channel comprises: a pull-up transistor having a control end, a first end and a second end, the control end receiving the voltage boost enable signal, The first end receives the operating voltage, and the second end is coupled to the discharge channel. The memory device of claim 13, wherein in the first time interval, the pre-charge channel provides the operating voltage to charge the negative push terminal on the capacitor. The memory device of claim 13, wherein in the second time interval, the discharge channel provides the reference voltage to the negative push terminal, and the capacitor is not coupled to the negative push terminal The voltage at the other end drops to produce the negative bit line signal.