TWI461712B - A parallel test switching device, a parallel test system and a parallel test method - Google Patents

A parallel test switching device, a parallel test system and a parallel test method Download PDF

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TWI461712B
TWI461712B TW098102230A TW98102230A TWI461712B TW I461712 B TWI461712 B TW I461712B TW 098102230 A TW098102230 A TW 098102230A TW 98102230 A TW98102230 A TW 98102230A TW I461712 B TWI461712 B TW I461712B
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test
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parallel test
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TW201028702A (en
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Fu Tai Chen
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King Yuan Electronics Co Ltd
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平行測試轉換裝置、平行測試系統以及平行測試之方法 Parallel test conversion device, parallel test system, and parallel test method

本發明提供一種平行測試轉換裝置、平行測試系統以及平行測試方法,特別是有關一種應用於開放式測試系統而實行平行測試的平行測試轉換裝置、平行測試系統以及平行測試方法。 The invention provides a parallel test conversion device, a parallel test system and a parallel test method, in particular to a parallel test conversion device, a parallel test system and a parallel test method which are applied to an open test system and perform parallel test.

現行用於半導體測試的測試機台所採用的測試系統與方式一般分為兩種,一為使用圖形介面(GUI)的測試系統,其所使用的測試程式已經內建於該系統中,使用者並無法對其加以修改或是編寫,即所謂的封閉式的測試系統;另一種則是開放給使用者進行測試程式或是測試韌體碼(code)編寫的系統,再依使用者所編寫的測試程式或是測試韌體碼對半導體元件進行測試,即所謂的開放式的測試系統。 The test systems and methods used in the current testing machines for semiconductor testing are generally divided into two types. One is a test system using a graphical interface (GUI), and the test program used is already built in the system, and the user It can't be modified or written, so-called closed test system; the other is open to the user to test the program or test the firmware code (the code) system, and then according to the user's test The program or test firmware code tests the semiconductor components, the so-called open test system.

由於半導體元件普及與多元化,越來越多的種類的半導體元件被發展出來,因此,測試機台往往需要對各種不同的半導體元件進行測試,而需要對不同的半導體元件使用不同的測試程式。因此,使用圖形介面(GUI)的測試系統此一封閉式系統顯然不敷使用,而開放式的測試系統使用上的比重則日益增加。然而,大多數的開放式的測試系統只能提供單一半導體元件的測試,在同一時間內僅能對一個半導體元件進行測試,需等前一 個半導體元件為測試完畢之前,才會對下一個半導體元件進行測試,即所謂的循序測試(Serial Test),但是並無法在同一時間對多個半導體元件同時進行測試,即所謂的平行測試(Parallel Test)。因此,一般所使用的開放式測試系統因為僅能進行循序測試,而無法像封閉式的測試系統一樣可以同時對多個半導體元件進行測試,即進行平行測試,所以開放式測試系統相比於封閉式測試系統導致測試效能大幅地的下滑。 Due to the popularity and diversification of semiconductor components, more and more types of semiconductor components have been developed. Therefore, test benches often require testing of various semiconductor components, and different test programs are required for different semiconductor components. Therefore, a closed system using a graphical interface (GUI) is clearly inadequate, and the use of open test systems is increasing. However, most open test systems can only provide testing of a single semiconductor component, and only one semiconductor component can be tested at the same time. The semiconductor component is tested before the test is completed, the so-called serial test, but it is not possible to test multiple semiconductor components at the same time, so-called parallel test (Parallel) Test). Therefore, the open test system generally used can only perform sequential testing, and can not test multiple semiconductor components at the same time as a closed test system, that is, parallel test, so the open test system is closed compared to the closed test system. Test systems have led to a significant decline in test performance.

然而,若要強行以現行的開放式系統實施平行測試,額外增加一前編譯器(pre-compiler)來處理同時對多個半導體元件進行平行測試時所產生的資料與訊號傳遞的問題,而用以管理測試流程。但是,為了能夠應付使用者所撰寫的各種測試程式或是測試韌體碼,並且考慮各種測試流程與狀態,造成所需的前編譯器是很龐大與複雜的,在開發上是很費時與困難的,並且在維護上有著龐大的負擔,因此,使得整個開放式測試系統同樣變得複雜而不易維護,所以使得整個測試成本大幅的增加。 However, if you want to enforce parallel testing with the current open system, add a pre-compiler to handle the problem of data and signal transmission when parallel testing multiple semiconductor components simultaneously. To manage the testing process. However, in order to be able to cope with various test programs written by users or to test firmware codes, and to consider various test processes and states, the required pre-compilers are very large and complicated, which is very time consuming and difficult to develop. And there is a huge burden on maintenance, so the entire open test system is also complicated and not easy to maintain, so the overall test cost is greatly increased.

其次,此一使用前編譯器的開放式測試系統,在平行測試進行時,每一半導體元件所採用記載有半導體元件引腳(device pin)與測試通道(device channel)之間對應關係的對應表皆為同一個並且為固定的,因此,導致測試機台所使用的測試載板(load board)與探針卡(probe card)上的走線設計受到限制,並且因此無法使平行測試中的每一半導體元件都獲得最短與最佳的資料與訊號傳遞路徑,導致開放式測試系統的訊號品質不良。舉例來說,在以使用前編譯器的開放式測試系統進行平行測試時,每一測試區域(site)分別對應並使用固定的測試通道,例如第一測試區域使用編號1-10的測試通道,而第二測試區域使用編號11-20的測試通道,由於每一測試區域都使用同一對應表,所以當第一測試區域中的半導體元件的引腳分別對應編 號1-4的測試通道進行測試,使得第二測試區域中的半導體元件的引腳僅能對應編號11-14的測試通道進行測試,而無法依據不同的測試載板或是探針卡上的走線設計進行變更,更無法使每一測試區域內的半導體元件對應不同的測試通道,而獲得最短與最佳的資料與訊號傳遞路徑。 Secondly, in the open test system using the pre-compiler, when parallel testing is performed, a correspondence table describing the correspondence between the semiconductor device pin and the device channel is used for each semiconductor component. They are all the same and fixed, so the design of the traces on the test board and the probe card used by the test machine is limited, and therefore it is impossible to make each of the parallel tests Semiconductor components get the shortest and best data and signal transmission paths, resulting in poor signal quality in open test systems. For example, in parallel testing with an open test system using a pre-compiler, each test site corresponds to and uses a fixed test channel, for example, the first test area uses a test channel numbered 1-10. The second test area uses the test channel numbered 11-20. Since each test area uses the same correspondence table, the pins of the semiconductor components in the first test area are respectively corresponding. The test channels of No. 1-4 are tested so that the pins of the semiconductor components in the second test area can only be tested corresponding to the test channels numbered 11-14, and cannot be based on different test carriers or probe cards. The trace design is changed, and the semiconductor components in each test area cannot be matched to different test channels to obtain the shortest and best data and signal transmission paths.

因此,亟需要一種平行測試系統、平行測試轉換裝置與平行測試方法,使開放式測試系統可以在循序測試與平行測試等測試模式進行切換,而在同一測試系統中提供循序測試與平行測試,並且無需使用龐大而複雜的前編譯器,更可以使平行測試中每一半導體元件的引腳分別對應最佳的測試通道,而使其獲得最短與最佳的資料與訊號傳遞路徑,進而導致測試成本的降低以及測試效能的增加。 Therefore, there is a need for a parallel test system, a parallel test conversion device, and a parallel test method, so that an open test system can be switched between test modes such as sequential test and parallel test, and sequential test and parallel test are provided in the same test system, and No need to use a large and complicated pre-compiler, it can make the pins of each semiconductor component in parallel test correspond to the best test channel, so that the shortest and best data and signal transmission path can be obtained, which leads to the test cost. The reduction and the increase in test performance.

本發明之一目的為提供一種平行測試轉換裝置,可以適用於各種開放式的測試系統,而用以做為循序測試與平行測試等測試模式切換的簡單裝置,而使開放使用者編寫測試程式的開放式測試系統可以藉由一簡單的裝置進行循序測試與平行測試之間的切換,並且同時提供平行測試中的每一半導體元件最佳的資料與訊號傳遞路徑,進而降低測試成本以及增加測試效能。 An object of the present invention is to provide a parallel test conversion device which can be applied to various open test systems, and is used as a simple device for switching test modes such as sequential test and parallel test, and enables an open user to write a test program. The open test system can switch between sequential test and parallel test by a simple device, and at the same time provide the best data and signal transmission path for each semiconductor component in parallel test, thereby reducing test cost and increasing test efficiency. .

本發明之另一目的為提供一種平行測試系統,可以對使用者所編寫的測試程式進行平行測試,而無需使用龐大而複雜的前編譯器,並提供平行測試中的每一半導體元件最佳的資料與訊號傳遞路徑,進而降低測試成本以及增加測試效能。 Another object of the present invention is to provide a parallel test system capable of parallel testing of test programs written by a user without using a large and complicated pre-compiler and providing optimum for each semiconductor component in parallel testing. Data and signal delivery paths, which in turn reduce test costs and increase test performance.

本發明之又一目的為提供一種平行測試方法,可以在開放式測試系統中,將使用者所編寫的測試程式轉換為平行測試流程,而同時對數個半導體元件同時進行測試,並提供每一每一半導體元件最佳的資料與訊號傳遞路徑,進而降低測試成本以及增加測試效能。 It is still another object of the present invention to provide a parallel test method for converting a test program written by a user into a parallel test flow in an open test system while simultaneously testing a plurality of semiconductor components and providing each The best data and signal transmission path for a semiconductor component reduces test costs and increases test performance.

根據上述目的,本發明提供一種平行測試轉換裝置,其包含一平行測試執行與結束控制單元、一平行測試資料擷取存放單元以及一循序測試執行與結束控制單元。其中,平行測試執行與結束控制單元,用以將測試流程轉換成平行測試而對多個半導體元件進行平行測試,並且控制該平行測試的開始、執行與結束,而平行測試資料擷取存放單元,則用以將平行測試後所得到的資料進行擷取與存放,而供後續測試進行資料的運算與判斷。其次,循序測試執行與結束控制單元,則用以將測試流程由平行測試轉換成循序測試而進行測試,並且控制該循序測試的開始、執行與結束。此平行測試轉換裝置以簡單組成元件構建,而提供開放式測試系統進行循序測試與平行測試之間的切換,而可以在開放式測試系統中進行循序測試與平行測試兩種模式的測試,並且處理同時對多個半導體元件進行平行測試時所產生的資料與訊號傳遞的問題,而提供每一半導體元件最佳的資料與訊號傳遞路徑,而降低測試成本以及增加測試效能。 In accordance with the above objects, the present invention provides a parallel test conversion apparatus including a parallel test execution and end control unit, a parallel test data capture storage unit, and a sequential test execution and end control unit. Wherein, a parallel test execution and end control unit is configured to convert the test flow into a parallel test to perform parallel testing on the plurality of semiconductor components, and control the start, execution and end of the parallel test, and the parallel test data captures the storage unit, It is used to capture and store the data obtained after the parallel test, and to perform the calculation and judgment of the data for subsequent tests. Secondly, the sequential test execution and end control unit is used to test the test flow from parallel test to sequential test, and control the start, execution and end of the sequential test. The parallel test conversion device is constructed with simple components, and an open test system is provided for switching between sequential test and parallel test, and the test can be performed in both the sequential test and the parallel test in the open test system, and processed. At the same time, the data and signal transmission problems generated by parallel testing of multiple semiconductor components provide the best data and signal transmission path for each semiconductor component, thereby reducing the test cost and increasing the test performance.

根據上述目的,本發明提供一種平行測試系統,其不但可以進行循序測試,更可以進行平行測試,其包含一用以控制半導體元件之測試之流程與運作的測試控制裝置、一用以進行循序測試與平行測試之間的切換的平行測試轉換裝置、以及一用以接受該測試控制裝置所提供之測試指令與該平行測試轉換裝置所提供之測試模式而執行測試的測試執行裝置。此一平行測試系統藉由一簡單的平行測試轉換裝置,例如一巨集指令等,而可以將使 用者所所編寫的測試程式或測試韌體碼,以平行測試流程而同時對數個半導體元件進行測試,並提供每一半導體元件最佳的資料與訊號傳遞路徑,而降低測試成本以及增加測試效能。 In accordance with the above objects, the present invention provides a parallel test system that not only performs sequential testing, but also performs parallel testing, including a test control device for controlling the flow and operation of testing of semiconductor components, and a test for sequencing. A parallel test conversion device for switching between parallel tests and a test execution device for performing a test by accepting a test command provided by the test control device and a test mode provided by the parallel test conversion device. This parallel test system can be made by a simple parallel test conversion device, such as a macro instruction Test program or test firmware code written by the user to test several semiconductor components simultaneously in parallel test process, and provide the best data and signal transmission path for each semiconductor component, reducing test cost and increasing test efficiency .

根據上述目的,本發明提供一種平行測試方法,而對使用者所編寫的測試程式進行平行測試。首先,開始執行一使用者編寫之測試程式,再依此測試程式建立一測試流程,接著,將此測試流程轉換成一對多個半導體元件進行同步測試的測試流程。然後,開始執行平行測試,並且收集平行測試所量測之資料與測試結果,最後,待所有半導體元件測試完畢後,即結束平行測試。此一行測試方法藉由簡單的步驟,例如一執行平行測試執行與結束巨集指令等,而將使用者所所編寫的測試程式或測試韌體碼以平行測試流程執行,並提供每一半導體元件最佳的資料與訊號傳遞路徑,而降低測試成本以及增加測試效能。 In accordance with the above objects, the present invention provides a parallel test method in which a test program written by a user is tested in parallel. First, a test program written by a user is started, and then a test flow is established according to the test program. Then, the test flow is converted into a test process in which a plurality of semiconductor components are synchronously tested. Then, the parallel test is started, and the data measured by the parallel test and the test result are collected. Finally, after all the semiconductor components are tested, the parallel test is ended. This one-line test method performs a parallel test flow and provides each semiconductor component by a simple step, such as performing a parallel test execution and ending a macro instruction, etc., and executing a test program or test firmware code written by the user in a parallel test flow. The best data and signal delivery path reduces test costs and increases test performance.

因此,本發明對比先前技術之功效在於提供一種應用於開放式測試系統而實行平行測試的平行測試轉換裝置、平行測試系統以及平行測試方法,以一簡單的平行測試轉換裝置或是巨集指令取代龐大複雜的前編譯器,即可以將使用者所編寫的測試程式或是測試韌體碼以一簡單的平行測試轉換裝置或步驟,例如一巨集指令或是執行巨集指令步驟等,取代複雜而龐大並且開發困難的前編寫器,而將循序測試流程轉換成平行測試流程,進而將降低測試成本與增加測試效率。 Therefore, the present invention is compared with the prior art in that it provides a parallel test conversion device, a parallel test system, and a parallel test method for parallel testing in an open test system, and is replaced by a simple parallel test conversion device or a macro instruction. A large and complex pre-compiler that replaces the complexity of a user-written test program or test firmware code with a simple parallel test conversion device or step, such as a macro instruction or a macro instruction step. The large and difficult to develop pre-writers, and the sequential test process into a parallel test process, which will reduce the cost of testing and increase the efficiency of testing.

另外,本發明對比先前技術之另一功效在於,提供一種平行測試轉換裝置、平行測試系統以及平行測試方法,其根據每一半導體之位置與狀態提供不同的對應表,而使每一半導體元件引腳對應到最佳的測試通道,藉此因應不同的測試載板或探針卡而提供最佳的資料與訊號傳遞路徑,並減 少對測試載板或探針卡上走線設計的限制。 In addition, another effect of the present invention over the prior art is to provide a parallel test conversion device, a parallel test system, and a parallel test method, which provide different correspondence tables according to the position and state of each semiconductor, and lead each semiconductor component. The foot corresponds to the best test channel, which provides the best data and signal transmission path for different test carriers or probe cards, and reduces Less restrictions on the design of the traces on the test carrier or probe card.

10、10’‧‧‧平行測試系統 10, 10'‧‧‧ parallel test system

20、20’‧‧‧測試控制裝置 20, 20'‧‧‧ test control device

30‧‧‧平行測試轉換裝置 30‧‧‧Parallel test conversion device

40‧‧‧測試執行裝置 40‧‧‧Test actuator

32‧‧‧平行測試執行與結束控制單元 32‧‧‧Parallel Test Execution and End Control Unit

33‧‧‧平行測試資料擷取存放單元 33‧‧‧Parallel test data capture storage unit

34‧‧‧循序測試執行與結束控制單元 34‧‧‧Sequential test execution and end control unit

35‧‧‧同步測試旗號單元 35‧‧‧Synchronized test flag unit

36‧‧‧測試通道自動展延單元 36‧‧‧Test channel automatic extension unit

37‧‧‧量測資料存放單元 37‧‧‧Measurement data storage unit

300‧‧‧開始執行使用者編寫的測試程式步驟 300‧‧‧Starting the execution of user-written test program steps

302‧‧‧依測試程式建立一測試流程步驟 302‧‧‧Create a test procedure step according to the test program

304‧‧‧將測試流程轉換成平行測試流程步驟 304‧‧‧Convert the test process into a parallel test process step

306‧‧‧執行平行測試流程步驟 306‧‧‧ Perform parallel test process steps

308‧‧‧收集平行測試流程所量測之資料與測試結果步驟 308‧‧‧Collect the data and test results steps measured by the parallel test process

310‧‧‧結束平行測試流程步驟 310‧‧‧ End Parallel Test Process Steps

第一A圖係為本發明一實施例之平行測試系統的簡單示意圖。 The first A diagram is a simplified schematic diagram of a parallel test system in accordance with an embodiment of the present invention.

第一B圖係為本發明另一實施例之平行測試系統的簡單示意圖。 The first B diagram is a simplified schematic diagram of a parallel test system according to another embodiment of the present invention.

第二圖係為本發明另一實施例之平行測試轉換裝置的簡單示意圖。 The second figure is a simplified schematic diagram of a parallel test conversion device according to another embodiment of the present invention.

第三圖係為本發明一實施例之平行測試方法的流程圖。 The third figure is a flow chart of a parallel test method according to an embodiment of the present invention.

本發明的一些實施例詳細描述如下。然而,除了該詳細描述外,本發明還可以廣泛地在其他的實施例施行。亦即,本發明的範圍不受已提出之實施例的限制,而以本發明提出之申請專利範圍為準。其次,當本發明之實施例圖示中的各元件或結構以單一元件或結構描述說明時,不應以此作為有限定的認知,即如下之說明未特別強調數目上的限制時本發明之精神與應用範圍可推及多數個元件或結構並存的結構與方法上。再者,在本說明書中,各元件之不同部分並沒有完全依照尺寸繪圖,某些尺度與其他相關尺度相比或有被誇張或是簡化,以提供更清楚的描述以增進對本發明的理解。而本發明所沿用的現有技藝,在此僅做重點式的引用,以助本發明的闡述。 Some embodiments of the invention are described in detail below. However, the present invention may be widely practiced in other embodiments in addition to the detailed description. That is, the scope of the present invention is not limited by the embodiments of the present invention, and the scope of the patent application proposed by the present invention shall prevail. In the following, when the elements or structures in the embodiments of the present invention are described in terms of a single element or structure, the present invention should not be construed as limited. The spirit and scope of application can be derived from the structure and method in which many components or structures coexist. In addition, in the present specification, the various parts of the elements are not drawn in full accordance with the dimensions, and some dimensions may be exaggerated or simplified compared to other related dimensions to provide a clearer description to enhance the understanding of the present invention. The prior art of the present invention, which is used in the prior art, is only referred to herein by reference.

參照第一A圖,為本發明之一實施例的平行測試系統10的簡單示意圖,平行測試系統10包含一用以控制半導體元件測試之流程與運作的測 試控制裝置20、一用以進行循序測試與平行測試之間切換的平行測試轉換裝置30、以及一用以執行半導體元件測試的測試執行裝置40。其中,測試執行裝置40依據測試控制裝置20所提供的測試指令與測試程式以及平行測試轉換裝置30所提供的測試模式,而對半導體元件進行測試。 Referring to FIG. 1A, a simplified schematic diagram of a parallel test system 10 according to an embodiment of the present invention, the parallel test system 10 includes a test for controlling the flow and operation of semiconductor component testing. The test control device 20, a parallel test conversion device 30 for switching between the sequential test and the parallel test, and a test execution device 40 for performing semiconductor component testing. The test execution device 40 tests the semiconductor component according to the test command provided by the test control device 20 and the test program and the test mode provided by the parallel test conversion device 30.

測試控制裝置20更包含一測試程式平台(圖中未示),用以供使用者編寫測試程式或是測試韌體碼,而這些測試程式或是測試韌體碼一般是以C程式語言編寫的,但並不以此為限,而是可以依測試程式的需求或是測試機台的種類而採取適合的程式語言進行編寫。另外,測試控制裝置20依據使用者在測試程式平台上編寫的測試程式或測試韌體碼,建立一符合此測試程式(或測試韌體碼)的測試流程。 The test control device 20 further includes a test program platform (not shown) for the user to write test programs or test firmware codes, and the test programs or test firmware codes are generally written in a C programming language. However, it is not limited to this, but can be written in a suitable programming language depending on the requirements of the test program or the type of test machine. In addition, the test control device 20 establishes a test flow conforming to the test program (or test firmware code) according to the test program or the test firmware code written by the user on the test program platform.

平行測試轉換裝置30則提供循序測試(Serial Test)與平行測試(Parallel Test)兩種測試模式,以及提供此兩種測試模式之間的切換。參照第二圖,平行測試轉換裝置30係由一平行測試執行與結束控制單元32、一平行測試資料擷取存放單元33以及一循序測試執行與結束控制單元34所組成。其中,平行測試執行與結束控制單元32,用以將測試控制裝置20依照使用者所編寫的測試程式所建立的測試流程,轉換成一可以同時測試數個半導體元件的平行測試。平行測試資料擷取存放單元33,則用以擷取與存放平行測試中每一半導體元件的測試結果與量測資料,以供後續測試流程進行資料的運算與判斷,即進行每一半導體元件之量測資料的運算與後續測試是否繼續的判斷依據。循序測試執行與結束控制單元34,則是用以將測試流程由平行測試轉換成在同一時間僅對單一半導體元件進行測試的循序測試,並且控制循序測試的開始、執行與結束。 The parallel test conversion device 30 provides two test modes, a sequential test and a parallel test (Parallel Test), and provides switching between the two test modes. Referring to the second figure, the parallel test conversion device 30 is composed of a parallel test execution and end control unit 32, a parallel test data capture storage unit 33, and a sequential test execution and end control unit 34. The parallel test execution and end control unit 32 is configured to convert the test control device 20 into a parallel test capable of simultaneously testing a plurality of semiconductor components according to a test flow established by a test program written by a user. The parallel test data capture storage unit 33 is used for capturing and storing the test results and measurement data of each semiconductor component in the parallel test for the subsequent test process to perform data calculation and judgment, that is, performing each semiconductor component. The basis for judging whether the operation of the measurement data and the subsequent test continue. The sequential test execution and end control unit 34 is used to convert the test flow from the parallel test to a sequential test that tests only a single semiconductor component at the same time, and controls the start, execution, and end of the sequential test.

另外,平行測試轉換裝置30具有一同步測試旗號單元35,用以 依據當時測試狀態、測試流程或是測試結果,而對一或多個半導體元件設定同步測試旗號,而標示與決定那些半導體元件要進行同步測試,即標示與決定要進行循序測試或平行測試的半導體元件。 In addition, the parallel test conversion device 30 has a synchronous test flag unit 35 for According to the test state, test flow or test result at that time, a synchronous test flag is set for one or more semiconductor components, and the semiconductor device is marked and determined to be synchronously tested, that is, the semiconductor that marks and determines the sequential test or the parallel test is determined. element.

其次,平行測試轉換裝置30還具有一測試通道自動展延單元36,用以將測試流程中的測試項目展延並對應至所有設定有同步測試旗號的半導體元件的測試通道(device channel)以進行平行測試。其中,測試通道自動展延單元36包含數個不同的對應表,每一對應表皆記載一半導體元件的各個引腳(pin)與各個測試通道(device channel)之間的對應關係,並且每一對應表所記載之對應關係皆不相同,使得進行每一半導體元件依其位置與狀態找到合適的對應表,使得每一引腳可以與對應之測試通道形成最佳的或是最短的訊號傳遞路徑,或是可以配合所使用之測試載板或是探針卡上的走線設計,而降低對測試載板或是探針卡上走線設計的限制。 Secondly, the parallel test conversion device 30 further has a test channel automatic extension unit 36 for extending the test items in the test flow and corresponding to the device channels of all the semiconductor components set with the synchronous test flag. Parallel testing. The test channel automatic extension unit 36 includes a plurality of different correspondence tables, and each correspondence table records a correspondence between each pin of a semiconductor component and each test channel, and each Corresponding relationships in the correspondence table are different, so that each semiconductor component finds a suitable correspondence table according to its position and state, so that each pin can form an optimal or shortest signal transmission path with the corresponding test channel. Or it can be used with the test carrier board used or the trace design on the probe card to reduce the restrictions on the test carrier or the design of the trace on the probe card.

再者,平行測試轉換裝置30還具有一量測資料存放單元37,用以在平行測試之中或之後,將每一半導體元件之測試結果與量測資料進行存放。在量測資料存放單元37包含數個資料存取區(圖中未示),每一資料存取區對應一半導體元件,而儲存所對應之半導體元件之量測資料與測試結果。 Furthermore, the parallel test conversion device 30 further has a measurement data storage unit 37 for storing the test results and measurement data of each semiconductor component during or after the parallel test. The measurement data storage unit 37 includes a plurality of data access areas (not shown), each of which corresponds to a semiconductor component, and stores measurement data and test results of the corresponding semiconductor components.

在本實施例中,在平行測試系統10中,平行測試轉換裝置30係介於測試控制裝置20與測試執行裝置40之間,而做為測試控制裝置20所建立之測試流程與測試執行裝置40所執行之測試流程之間的轉換,並且測試控制裝置20與平行測試轉換裝置30為分離的兩裝置。但是,在其他如第一B圖所示之實施例中,平行測試系統10’中的平行測試轉換裝置30係為測試控制裝置20’的一部份,而設置於測試控制裝置20’中。 In the present embodiment, in the parallel test system 10, the parallel test conversion device 30 is interposed between the test control device 20 and the test execution device 40, and the test flow and test execution device 40 established as the test control device 20 The conversion between the test runs performed, and the test control device 20 and the parallel test conversion device 30 are separate devices. However, in other embodiments as shown in Fig. B, the parallel test conversion device 30 in the parallel test system 10' is part of the test control device 20' and is disposed in the test control device 20'.

前述平行測試系統10與10’之運作方式如下:在使用者於測試控制裝置20或20’編寫好測試程式或是測試韌體碼之後,測試控制裝置20或20’會依測試程式或是測試韌體碼建立一對單一半導體元件進行測試的測試流程,並將其傳送至平行測試轉換裝置30中,而同時測試控制裝置20或20’會直接對測試執行裝置40或是經由平行測試轉換裝置30對測試執行裝置40下達執行測試指令。 The parallel test systems 10 and 10' operate as follows: after the user writes the test program or tests the firmware code on the test control device 20 or 20', the test control device 20 or 20' will follow the test program or test. The firmware code establishes a test flow for testing a pair of single semiconductor components and transmits them to the parallel test conversion device 30, while the test control device 20 or 20' directly passes the test execution device 40 or via a parallel test conversion device. 30 pairs of test execution devices 40 issue test instructions.

接著,平行測試轉換裝置30中的平行測試執行與結束控制單元32會將此一測試流程自動轉換成一平行測試流程,而同步測試旗號單元35則設定同步測試旗號於每一半導體元件或是設定於需要進行平行測試的半導體元件,而做為進行同步測試之半導體的標示。平行測試執行與結束控制單元32則藉由此一同步測試旗號的設定來選定與標示那些半導體元件要進行平行測試。 Then, the parallel test execution and end control unit 32 in the parallel test conversion device 30 automatically converts this test flow into a parallel test flow, and the synchronous test flag unit 35 sets the synchronous test flag to each semiconductor component or is set to Semiconductor components that require parallel testing are used as labels for semiconductors for simultaneous testing. The parallel test execution and end control unit 32 selects and performs parallel testing of those semiconductor components by the setting of the synchronization test flag.

然後,測試通道自動展延單元36會將測試流程中測試項目自動展延,而使每一設定有同步測試旗號的半導體元件的測試通道對應這些測試項目,並且每一設定有同步測試旗號的半導體元件依照各個不同的對應表,而使其每一引腳皆對應一可以配合測試載板或是探針卡上的走線設計並獲得最短與最佳的訊號傳遞途徑的測試通道。因此,本發明之平行測試系統10與10’不會受限於測試載板或是探針卡上的走線設計,或是對測試載板或是探針卡上的走線設計造成限制,而可以是適用於各種測試載板與探針卡,甚至靈活地運用各個測試通道配合測試載板與探針卡上的走線,而獲得可以縮短測試訊號的傳遞途徑,進而得到較佳的信號品質。 Then, the test channel automatic extension unit 36 automatically extends the test items in the test flow, so that the test channels of the semiconductor components each having the synchronous test flag are corresponding to the test items, and each semiconductor having the synchronous test flag is set. The components are each according to a different correspondence table, so that each pin corresponds to a test channel that can be matched with the trace design on the test carrier or the probe card to obtain the shortest and best signal transmission path. Therefore, the parallel test systems 10 and 10' of the present invention are not limited by the trace design on the test carrier or probe card, or the design of the trace on the test carrier or probe card. It can be applied to various test carriers and probe cards, and even flexibly use each test channel to match the traces on the test carrier and the probe card, thereby obtaining a transmission path that can shorten the test signal, thereby obtaining a better signal. quality.

接著,測試執行裝置40依據測試控制裝置20或20’提供之測試指令以及平行測試轉換裝置30提供之測試模式,以測試通道自動展延單 元36所展延對應的測試通道對數個設定有同步測試旗號的半導體元件同時進行測試,而未設定同步測試旗號的半導體元件則同步進行測試。在平行測試的同時或是之後,量測資料存放單元37分別收集每一半導體元件的量測資料與測試結果,並將其分別儲存於每一半導體元件對應的資料存取區,即每一半導體元件個別專屬的資料存取區中。 Next, the test execution device 40 tests the channel automatic extension according to the test command provided by the test control device 20 or 20' and the test mode provided by the parallel test conversion device 30. The test channel corresponding to the extension of the element 36 is simultaneously tested on a plurality of semiconductor elements set with the synchronous test flag, and the semiconductor elements not set with the synchronous test flag are simultaneously tested. Simultaneously or after the parallel test, the measurement data storage unit 37 separately collects the measurement data and the test result of each semiconductor component, and stores them in the data access area corresponding to each semiconductor component, that is, each semiconductor. The individual data access areas of the components are unique.

待平行測試完畢後,平行測試資料擷取存放單元33則會擷取每一半導體元件的量測資料與測試結果進行運算與判斷,而決定每一半導體元件是否進行下一項目的測試、後續的測試流程或步驟、或者是否進行測試分枝。舉例來說,若平行測試資料擷取存放單元33擷取之半導體元件的量測資料與測試結果符合測試程式所設定的臨界值,例如超過某一特定電壓或電流,則進行對該半導體元件進行測試分枝,或是若藉由一半導體元件的量測資料與測試結果而判斷該半導體元件為一劣品,則停止後續測試流程或是測試項目。 After the parallel test is completed, the parallel test data capture storage unit 33 retrieves the measurement data of each semiconductor component and the test result, and determines whether each semiconductor component performs the test of the next item, and subsequent. Test the process or steps, or whether to test the branches. For example, if the measurement data of the semiconductor component captured by the parallel test data capture unit 33 and the test result meet the threshold set by the test program, for example, exceed a certain voltage or current, the semiconductor component is subjected to the semiconductor component. The test branch, or if the semiconductor component is judged to be inferior by the measurement data of the semiconductor component and the test result, the subsequent test process or test item is stopped.

等到所有的平行測試都完成後,若還需要進行循序測試,測試控制裝置20或20’則傳遞循序測試指令給平行測試轉換裝置30與測試執行裝置40。在測試控制裝置20或20’接收到循序測試指令後,同步測試旗號單元35會對半導體元件重新設定一同步測試旗號,但是在同一時間內僅對一個半導體元件設定同步測試旗號,亦即在一個半導體元件完成測試前,不會設定同步測試旗號於另一個半導體元件,因此,測試執行裝置40在同一時間只會對同一個半導體元件進行測試。當然,本發明之平行測試系統10與10’也可以依照測試需求,而在一開始測試之時就進行上述之循序測試。 After all of the parallel tests are completed, if a sequential test is required, the test control device 20 or 20' passes the sequential test command to the parallel test conversion device 30 and the test execution device 40. After the test control device 20 or 20' receives the sequential test command, the synchronous test flag unit 35 resets a synchronous test flag to the semiconductor component, but sets a synchronous test flag for only one semiconductor component at a time, that is, in one Before the semiconductor component is tested, the synchronous test flag is not set to another semiconductor component, and therefore, the test actuator 40 will only test the same semiconductor component at the same time. Of course, the parallel test systems 10 and 10' of the present invention can also perform the above-described sequential tests at the beginning of the test in accordance with the test requirements.

另外,本發明之平行測試執行與結束控制單元32中可以包含一簡單的平行測試巨集指令來控制平行測試的開始、執行、與結束,以及 收集平行測試的量測資料與測試結果,例如:MacroParallelTestStart()//平行測試開始 In addition, the parallel test execution and end control unit 32 of the present invention may include a simple parallel test macro instruction to control the start, execution, and end of the parallel test, and Collect the measurement data and test results of the parallel test, for example: MacroParallelTestStart()//parallel test begins

//User’s Test Item 1//使用者的測試程式 //User’s Test Item 1//user's test program

MacroGetTestData_1()//取得資料 MacroGetTestData_1 () / / get information

//User’s Test Item 2//使用者的測試程式 //User’s Test Item 2//user's test program

MacroGetTestData_2()//取得資料 MacroGetTestData_2 () / / get information

MacroParallelTestEnd()//平行測試結束 MacroParallelTestEnd()//parallel test ends

其中,User’s Test Item 1與User’s Test Item 2分別為使用者編寫的測試程式中的不同的測試項目,在本實施例中雖然只有兩個項目,但並不以此為限,而是可以一測試需求而增減。 Among them, User's Test Item 1 and User's Test Item 2 are different test items in the test program written by the user respectively. Although there are only two items in this embodiment, it is not limited thereto, but can be tested. Increase or decrease in demand.

再者,本發明之循序測試執行與結束控制單元34中,也可以包含一簡單的循序測試巨集指令來控制循序測試的開始、執行、與結束,以及循序測試的量測資料的運算,例如:MacroSerialTestStart()//循序測試開始 Furthermore, the sequential test execution and end control unit 34 of the present invention may also include a simple sequential test macro instruction to control the start, execution, and end of the sequential test, and the operation of the measured data of the sequential test, for example, :MacroSerialTestStart()//Sequential test begins

//User’s Operation//取得資料後的運算 //User’s Operation// operation after getting the data

MacroSerialTestEnd()//循序測試結束 MacroSerialTestEnd () / / end of the test

因此,根據上述實施例,本發明之平行測試系統不但可以對使用者所編寫的測試程式循序測試,更可以進行平行測試,而以一簡單的平行測試轉換裝置習知龐大複雜且不易開發與維護的前編譯器,並提供平行測試中的每一半導體元件最佳的資料與訊號傳遞路徑,藉此降低測試成本以及增加測試效能。 Therefore, according to the above embodiment, the parallel test system of the present invention can not only test the test program written by the user, but also perform parallel test, and the simple parallel test conversion device is complicated and difficult to develop and maintain. The pre-compiler provides the best data and signal transfer path for each semiconductor component in parallel testing, thereby reducing test costs and increasing test performance.

另外,本發明更提供一種平行測試轉換裝置可以是用於各種開放式測試系統,而進行循序測試與平行測試之間的切換,而使各種開放式測試系統不但可以進行循序測試,更可以進行平行測試,而縮短測試時間,並增加測試效能。此平行測試轉換裝置之組成如第二圖所示,其已於前文描述,因此,在此不再贅述。 In addition, the present invention further provides a parallel test conversion device which can be used for various open test systems to perform switching between sequential test and parallel test, so that various open test systems can not only perform sequential test, but also parallel. Test, shorten test time and increase test performance. The composition of the parallel test conversion device is as shown in the second figure, which has been described above, and therefore will not be described herein.

其次,本發明更提供一種平行測試方式,可以在一開放式測試系統中進行平行測試,而不需要任何龐大且複雜的前編譯器。參照第三圖,其為本發明之一實施例之平行測試方法的流程圖。首先,在使用者編寫一測試程式或是測試韌體碼於測試機台後,測試機台會開始執行此測試程式或是測試韌體碼(步驟300)。其中,此測試程式或是測試韌體碼係以C程式語言編寫的,但並不以此為限,而是可以依測試程式的需求或是測試機台的種類而採取適合的程式語言進行編寫,並且此測試程式包含有多項測試項目。 Secondly, the present invention further provides a parallel test method that allows parallel testing in an open test system without the need for any large and complex pre-compilers. Referring to the third figure, it is a flow chart of a parallel test method according to an embodiment of the present invention. First, after the user writes a test program or tests the firmware code on the test machine, the test machine will start executing the test program or test the firmware code (step 300). The test program or the test firmware code is written in the C programming language, but it is not limited thereto, but can be written in a suitable programming language according to the requirements of the test program or the type of the test machine. And this test program contains several test items.

接著,測試機台會依此測試程式建立一對單一半導體元件進行測試的測試流程(步驟302),而此測試流程包含有測試程式中的各項測試項目。然後,再將此測試流程進行轉換,而轉換成一可以同時對多個半導體元件進行測試的平行測試流程(步驟304),而後,開始執行此平行測試流程而對多個半導體元件進行同步測試(步驟306)。接著,在執行平行測試流程的同時或是之後,收集參與平行測試的每一半導體元件的量測資料與測試結 果(步驟308),然後,在每一半導體元件都完成測試後,結束此平行測試流程(步驟310)。 Then, the test machine will establish a test process for testing a pair of single semiconductor components according to the test program (step 302), and the test process includes various test items in the test program. Then, the test flow is converted, and converted into a parallel test flow that can simultaneously test a plurality of semiconductor components (step 304), and then the parallel test process is started to perform synchronous test on a plurality of semiconductor components (steps) 306). Next, at the same time as or after the parallel test process is performed, the measurement data and test knots of each semiconductor component participating in the parallel test are collected. (Step 308), then, after each semiconductor component has completed testing, the parallel test flow is ended (step 310).

另外,此平行測試方法更包含一同步測試旗號設定步驟,在測試流程轉換成平行測試流程步驟中(步驟304),更包含一同步測試旗號設定步驟,而設定同步測試旗號於需要進行同步測試的半導體元件,藉此標示或選定進行平測試的半導體元件。再者,測試流程轉換成平行測試流程步驟中(步驟304)還包含一測試通道展延步驟,用以將各項測試項目展延並對應至所有設定有同步測試旗號的半導體元件的測試通道(device channel),而使每一設定有同步測試旗號的半導體元件可以對應實施各種測試項目,而進行平行測試。 In addition, the parallel test method further includes a synchronization test flag setting step, in the step of converting the test flow into the parallel test flow (step 304), further including a synchronization test flag setting step, and setting the synchronization test flag to be required for the synchronization test. A semiconductor component whereby the semiconductor component subjected to the flat test is marked or selected. Furthermore, the conversion of the test flow into the parallel test flow step (step 304) further includes a test channel extension step for extending the test items and corresponding to the test channels of all the semiconductor components set with the synchronous test flag ( Device channel), and each semiconductor component with a synchronous test flag can be tested in parallel for various test items.

測試通道展延步驟則包含一提供對應表步驟,使得每一設定有同步測試旗號的半導體元件依照各個不同的對應表,而使每一引腳皆對應一可以配合測試載板或是探針卡上的走線設計並獲得最短與最佳的訊號傳遞途徑的測試通道。每一對應表記載每一半導體元件的各個引腳(pin)與各個測試通道之間的對應關係,而提供每一半導體元件最短與最佳的測試訊號傳遞途徑進行來平行測試。因此,使得本發明之平行測試方法不但不會受限於測試載板或是探針卡上的走線設計,或是對測試載板或是探針卡上的走線設計造成限制,甚至靈活地運用各個測試通道配合測試載板與探針卡上的走線,而獲得可以縮短測試訊號的傳遞途徑,進而得到較佳的信號品質。 The test channel extension step includes a step of providing a correspondence table, so that each semiconductor component having a synchronous test flag is set according to each different correspondence table, so that each pin corresponds to one can cooperate with the test carrier or the probe card. The traces on the design and the test channel for the shortest and best signal transmission path. Each correspondence table records the correspondence between each pin of each semiconductor component and each test channel, and provides the shortest and best test signal transmission path for each semiconductor component to be tested in parallel. Therefore, the parallel test method of the present invention is not limited to the design of the trace on the test carrier or the probe card, or the design of the trace on the test carrier or the probe card, or even flexible. The test channel is used to match the traces on the test board and the probe card, so that the transmission path of the test signal can be shortened, thereby obtaining better signal quality.

另外,收集參與平行測試的每一半導體元件的量測資料與測試結果的步驟(步驟308)更包含一提供提供資料存放區步驟,用以提供每一設定有同步測試旗號的半導體元件對應之資料存放區,即提供每一進行平行測試的半導體元件個別專屬的資料存放區。其次,收集參與平行測試的每一半 導體元件的量測資料與測試結果的步驟(步驟308)還包含一資料存放步驟,而將每一半導體元件的量測資料與測試結果存放至對應的資料存放區。 In addition, the step of collecting the measurement data and the test result of each semiconductor component participating in the parallel test (step 308) further comprises providing a data storage area step for providing data corresponding to each semiconductor component set with the synchronous test flag. The storage area is a separate data storage area for each semiconductor component that is tested in parallel. Second, collect each half of the parallel test The step of measuring the measurement data and the test result of the conductor element (step 308) further comprises a data storage step, and storing the measurement data and the test result of each semiconductor component in the corresponding data storage area.

本發明之平行測試方法更包含一運算與判斷步驟,其由每一半導體元件對應的專屬資料存放區擷取此半導體元件的量測資料與測試結果而進行運算與判斷,並依照使用者編寫之測試程式所提供之規格,判斷每一半導體元件之測試狀態,而判定每一半導體元件是否要進行後續測試或進行測試分枝。再者,本發明之平行測試方法更包含一重新設定同步測試旗號步驟,而重新對需要進行後續測試或進行測試分枝的半導體元件重新進行同步測試旗號設定,而標示與選定需要進行後續測試或進行測試分枝的半導體元件。 The parallel test method of the present invention further comprises an operation and a judgment step, which is performed by the measurement data and the test result of the semiconductor component by the dedicated data storage area corresponding to each semiconductor component, and is calculated and judged according to the user. The specifications provided by the test program determine the test state of each semiconductor component, and determine whether each semiconductor component is to be subjected to subsequent testing or test branching. Furthermore, the parallel test method of the present invention further includes a step of resetting the synchronization test flag, and re-synchronizing the test component flag for the semiconductor component that needs to be subjected to subsequent testing or test branching, and the marking and selection require subsequent testing or A semiconductor component that is tested for branching.

另外,本發明之平行測試方法可以藉由一簡單的平行測試巨集指令,來控制平行測試的開始、執行、與結束,以及收集平行測試的量測資料與測試結果,此一平行測試巨集指令已於前文描述,因此,在此不再贅述。 In addition, the parallel test method of the present invention can control the start, execution, and end of the parallel test by a simple parallel test macro instruction, and collect the measurement data and the test result of the parallel test. This parallel test macro The instructions have been described above and therefore will not be described here.

此平行測試方法更可以在完成平行測試,接著進行循序測試,其包含一循序測試步驟,用以進行循序測試,並且也包含一單一同步測試旗號設定步驟,用以在同一時間內,僅對一半導體元件設定同步測試旗號,而標示或選定進行循序測試之半導體元件而進行測試。此循序測試步驟可以藉由一簡單的循序測試巨集指令,來控制循序測試的開始、執行、與結束,以及以及循序測試的量測資料的運算,此一循序測試巨集指令已於前文描述,因此,在此不再贅述。 The parallel test method can further complete the parallel test, and then perform a sequential test, which includes a sequential test step for performing the sequential test, and also includes a single synchronous test flag setting step for only one at the same time. The semiconductor component sets the synchronization test flag and tests or selects the semiconductor component for sequential testing. The sequential test step can control the start, execution, and end of the sequential test, and the operation of the measured data of the sequential test by a simple sequential test macro instruction, which is described in the foregoing. Therefore, it will not be described here.

因此,本發明所提供應用於開放式測試系統而實行平行測試的 平行測試轉換裝置、平行測試系統以及平行測試方法,可以將使用者所編寫的測試程式或是測試韌體碼以一簡單的平行測試轉換裝置或步驟,例如一巨集指令或是執行巨集指令步驟等,取代複雜而龐大並且開發困難的前編寫器,而將循序測試流程轉換成平行測試流程,進而將降低測試成本與增加測試效率。另外,本發明可以根據每一半導體之位置與狀態提供不同的對應表,而使每一半導體元件引腳對應到最佳的測試通道,藉此因應不同的測試載板或探針卡而提供最佳的資料與訊號傳遞路徑,並減少對測試載板或探針卡上走線設計的限制。 Therefore, the present invention provides parallel testing using an open test system. The parallel test conversion device, the parallel test system, and the parallel test method can convert the test program written by the user or the test firmware code into a simple parallel test conversion device or step, such as a macro instruction or a macro instruction. Steps, etc., replace complex and large and difficult to develop pre-writers, and convert the sequential test process into a parallel test process, which will reduce test costs and increase test efficiency. In addition, the present invention can provide different correspondence tables according to the position and state of each semiconductor, so that each semiconductor component pin corresponds to an optimal test channel, thereby providing the most for different test carriers or probe cards. Good data and signal transmission paths and reduce the restrictions on the design of the traces on the test carrier or probe card.

30‧‧‧平行測試轉換裝置 30‧‧‧Parallel test conversion device

32‧‧‧平行測試執行與結束控制單元 32‧‧‧Parallel Test Execution and End Control Unit

33‧‧‧平行測試資料擷取存放單元 33‧‧‧Parallel test data capture storage unit

34‧‧‧循序測試執行與結束控制單元 34‧‧‧Sequential test execution and end control unit

35‧‧‧同步測試旗號單元 35‧‧‧Synchronized test flag unit

36‧‧‧測試通道自動展延單元 36‧‧‧Test channel automatic extension unit

37‧‧‧量測資料存放單元 37‧‧‧Measurement data storage unit

Claims (33)

一種平行測試轉換裝置,用以提供循序測試(Serial Test)與平行測試(Parallel Test)兩種測試模式,以及提供該循序測試模式與該平行測試模式之間的轉換,其包含:一平行測試執行與結束控制單元,用以將測試流程由一同一時間僅對單一半導體元件進行測試的循序測試流程轉換成一可以同時對多個半導體元件進行平行測試流程,而提供該平行測試模式以進行平行測試,並且控制該平行測試的開始、執行與結束;一平行測試資料擷取存放單元,用以將平行測試後所得到的資料進行擷取與存放,而供後續測試流程進行資料的運算與判斷;一同步測試旗號單元,用以依據當時測試狀態、測試流程或測試結果而設定同步測試旗號,而決定要對那些半導體元件進行同步測試;以及一循序測試執行與結束控制單元,用以將測試流程由該平行測試流程重新轉換成該循序測試流程,而提供該循序測試模式以進行循序測試,並且控制該循序測試的開始、執行與結束,其中,該平行測試執行與結束控制單元、該平行測試資料擷取存放單元、以及該循序測試執行與結束控制單元分別與該同步測試旗號單元連接,並且該平行測試執行與結束控制單元、該平行測試資料擷取存放單元、以及該循序測試執行與結束控制單元經由該同步測試旗號單元而彼此連接。 A parallel test conversion device for providing two test modes, a sequential test and a parallel test (Parallel Test), and providing a conversion between the sequential test mode and the parallel test mode, comprising: a parallel test execution And an end control unit for converting the test flow from a sequential test flow that tests only a single semiconductor component at the same time into a parallel test process for simultaneously performing a plurality of semiconductor components, and providing the parallel test mode for parallel testing, And controlling the start, execution and end of the parallel test; a parallel test data capture storage unit for extracting and storing the data obtained after the parallel test, and performing calculation and judgment of the data for the subsequent test process; Synchronous test flag unit for setting the synchronous test flag according to the current test state, test flow or test result, and determining to perform synchronous test on those semiconductor components; and a sequential test execution and termination control unit for using the test flow by The parallel test flow is reconverted to the sequence Testing the process, providing the sequential test mode for performing a sequential test, and controlling the start, execution, and end of the sequential test, wherein the parallel test execution and end control unit, the parallel test data capture storage unit, and the sequential test The execution and end control unit is respectively connected to the synchronous test flag unit, and the parallel test execution and end control unit, the parallel test data capture storage unit, and the sequential test execution and end control unit are mutually connected via the synchronous test flag unit connection. 如申請專利範圍第1項所述之平行測試轉換裝置,其中該平行測試執行與結束控制單元藉由該同步測試旗號而選定對那些半導體元件進行同步測試。 The parallel test conversion device of claim 1, wherein the parallel test execution and end control unit selects to perform synchronous testing on those semiconductor components by the synchronization test flag. 如申請專利範圍第1項所述之平行測試轉換裝置,其中該同步測試旗號單元在進行完平行測試後或是需要對半導體元件進行循序測試時,會依 測試流程或結果而在同一時間內,僅對一半導體元件設定同步測試旗號,而使循序測試執行與結束控制單元依該同步測試旗號控制循序測試的執行。 The parallel test conversion device according to claim 1, wherein the synchronous test flag unit is subjected to parallel test or needs to perform sequential test on the semiconductor component. The test flow or result, at the same time, only sets a synchronous test flag for a semiconductor component, and causes the sequential test execution and end control unit to control the execution of the sequential test according to the synchronous test flag. 如申請專利範圍第1項所述之平行測試轉換裝置,其中更包含一測試通道自動展延單元,用以將測試流程中的測試項目展延並對應至所有設定有同步測試旗號的半導體元件的測試通道(device channel)以進行平行測試。 The parallel test conversion device of claim 1, further comprising a test channel automatic extension unit for extending the test items in the test flow and corresponding to all semiconductor components set with the synchronous test flag. Test channel for parallel testing. 如申請專利範圍第4項所述之平行測試轉換裝置,其中該測試通道自動展延單元更包含數個對應表,每一對應表皆記載一半導體元件的各個引腳(pin)與各個測試通道(device channel)之間的對應關係。 The parallel test conversion device of claim 4, wherein the test channel automatic extension unit further comprises a plurality of correspondence tables, each of which records each pin of the semiconductor component and each test channel. Correspondence between (device channels). 如申請專利範圍第4項所述之平行測試轉換裝置,其中更包含一量測資料存放單元,用以在平行測試後,將每一半導體元件之測試結果與量測資料進行存放。 The parallel test conversion device of claim 4, further comprising a measurement data storage unit for storing the test result and the measurement data of each semiconductor component after the parallel test. 如申請專利範圍第6項所述之平行測試轉換裝置,其中更包含數個資料存取區,其中每一該資料存取區對應一半導體元件,而用以存放所對應之半導體元件的測試結果與量測資料。 The parallel test conversion device of claim 6, further comprising a plurality of data access areas, wherein each of the data access areas corresponds to a semiconductor component for storing test results of the corresponding semiconductor component And measurement data. 如申請專利範圍第7項所述之平行測試轉換裝置,其中該平行測試資料擷取存放單元藉由擷取每一半導體元件的個別資料存放區內的測試資料與結果,經由運算與判定而決定那些半導體元件需要進行後續測試或是測試分枝。 The parallel test conversion device of claim 7, wherein the parallel test data capture unit determines the test data and the result in the individual data storage area of each semiconductor component by operation and determination. Those semiconductor components require subsequent testing or test branching. 一種平行測試系統,具有循序測試(Serial Test)與平行測試(Parallel Test)兩種測試模式,而可以在該循序測試模式與該平行測試模式之間轉換,其包含:一測試控制裝置,用以控制半導體元件測試之流程與運作;一平行測試轉換裝置,用以提供該循序測試(Serial Test)與該平行測 試(Parallel Test)兩種測試模式,以及提供該循序測試模式與該平行測試模式之間的轉換,該平行測試轉換裝置包含:一平行測試執行與結束控制單元,用以將測試流程由一同一時間僅對單一半導體元件進行測試的循序測試流程轉換成一可以同時對多個半導體元件進行平行測試流程,而提供該平行測試模式以進行平行測試,並且控制該平行測試的開始、執行與結束;一平行測試資料擷取存放單元,用以將平行測試後所得到的資料進行擷取與存放,而供後續測試流程進行資料的運算與判斷;一同步測試旗號單元,用以依據當時測試狀態、測試流程或測試結果而設定同步測試旗號,而決定要對那些半導體元件進行同步測試;一循序測試執行與結束控制單元,用以將測試流程由該平行測試流程重新轉換成該循序測試流程,而提供該循序測試模式以進行循序測試,並且控制該循序測試的開始、執行與結束,其中,該平行測試執行與結束控制單元、該平行測試資料擷取存放單元、以及該循序測試執行與結束控制單元分別與該同步測試旗號單元連接,並且該平行測試執行與結束控制單元、該平行測試資料擷取存放單元、以及該循序測試執行與結束控制單元經由該同步測試旗號單元而彼此連接,該平行測試轉換裝置設置於該測試控制裝置與該測試執行裝置之間,但該平行測試轉換裝置與該測試控制裝置為分離的兩裝置,或是該平行測試轉換裝置設置於該測試控制裝置,而為該測試控制裝置的一部份;以及一測試執行裝置,用以接受該測試控制裝置所提供之測試指令與該平行測試轉換裝置所提供之測試模式,並根據該測試指令與該測試模式執行測試。 A parallel test system, which has two test modes, a sequential test and a parallel test (Parallel Test), and can be switched between the sequential test mode and the parallel test mode, and includes: a test control device for Controlling the flow and operation of the semiconductor component test; a parallel test conversion device for providing the serial test and the parallel test Parallel Test two test modes, and providing a conversion between the sequential test mode and the parallel test mode, the parallel test conversion device includes: a parallel test execution and end control unit for using the same test flow The sequential test flow for testing only a single semiconductor component is converted into a parallel test flow for a plurality of semiconductor components simultaneously, and the parallel test mode is provided for parallel testing, and the start, execution and end of the parallel test are controlled; The parallel test data capture unit is used to capture and store the data obtained after the parallel test, and the data is calculated and judged by the subsequent test process; a synchronous test flag unit is used to test the state according to the test state at the time. Setting the synchronization test flag for the process or test result, and deciding to perform synchronous testing on those semiconductor components; a sequential test execution and termination control unit for reconverting the test flow from the parallel test flow to the sequential test flow, and providing The sequential test mode for sequential testing And controlling the start, execution and end of the sequential test, wherein the parallel test execution and end control unit, the parallel test data capture storage unit, and the sequential test execution and end control unit are respectively connected to the synchronous test flag unit And the parallel test execution and end control unit, the parallel test data capture storage unit, and the sequential test execution and end control unit are connected to each other via the synchronous test flag unit, and the parallel test conversion device is disposed on the test control device And the test execution device, but the parallel test conversion device and the test control device are separate devices, or the parallel test conversion device is disposed in the test control device as part of the test control device; And a test execution device for accepting the test command provided by the test control device and the test mode provided by the parallel test conversion device, and performing the test according to the test command and the test mode. 如申請專利範圍第9項所述之平行測試系統,其中該測試控制裝 置更包含一測試程式平台,用以供使用者撰寫測試程式或是韌體碼(code)。 The parallel test system of claim 9, wherein the test control device The device also includes a test program platform for the user to write a test program or a firmware code. 如申請專利範圍第10項所述之平行測試系統,其中該測試程式平台係為C語言測試程式平台,而該測試程式或是韌體碼(code)則是以C語言撰寫。 For example, the parallel test system described in claim 10, wherein the test program platform is a C language test program platform, and the test program or firmware code is written in C language. 如申請專利範圍第9項所述之平行測試系統,其中該平行測試轉換裝置所提供之測試模式包含循序測試模式與平行測試模式兩種。 The parallel test system of claim 9, wherein the test mode provided by the parallel test conversion device comprises two types: a sequential test mode and a parallel test mode. 如申請專利範圍第9項所述之平行測試系統,其中該平行測試執行與結束控制單元藉由該同步測試旗號而選定對那些半導體元件進行同步測試,並且通知該測試執行裝置對設定有同步測試旗號的半導體元件進行平行測試。 The parallel test system of claim 9, wherein the parallel test execution and end control unit selects to perform synchronous test on the semiconductor components by the synchronous test flag, and notifies the test execution device that the set is synchronized. The semiconductor components of the flag are tested in parallel. 如申請專利範圍第9項所述之平行測試系統,其中該同步測試旗號單元在進行完平行測試後或是需要對半導體元件進行循序測試時,會依測試流程或結果而在同一時間內,僅對一半導體元件設定同步測試旗號,而使循序測試執行與結束控制單元依該同步測試旗號控制循序測試的執行,並通知該進行測試執行裝置循序測試。 The parallel test system of claim 9, wherein the synchronous test flag unit, after performing the parallel test or when the semiconductor component needs to be sequentially tested, is in accordance with the test flow or the result at the same time, only A synchronization test flag is set for a semiconductor component, and the sequential test execution and termination control unit controls the execution of the sequential test according to the synchronization test flag, and notifies the test execution device to perform the sequential test. 如申請專利範圍第9項所述之平行測試系統,其中更包含一測試通道自動展延單元,用以將該測試流程中的測試項目展延並對應至所有設定有同步測試旗號的半導體元件的測試通道(device channel)以進行平行測試。 The parallel test system of claim 9, further comprising a test channel automatic extension unit for extending the test item in the test flow and corresponding to all semiconductor components set with the synchronous test flag. Test channel for parallel testing. 如申請專利範圍第15項所述之平行測試系統,其中該測試通道自動展延單元更包含數個對應表,每一對應表皆記載一半導體元件的各個引腳(pin)與各個測試通道(device channel)之間的對應關係。 The parallel test system of claim 15, wherein the test channel automatic extension unit further comprises a plurality of correspondence tables, each of which records each pin of the semiconductor component and each test channel ( Correspondence between device channels). 如申請專利範圍第15項所述之平行測試系統,其中更包含一量測資料存放單元,用以在平行測試後,將每一半導體元件之測試結果與量測資料進行存放。 The parallel test system of claim 15 further includes a measurement data storage unit for storing the test result and the measurement data of each semiconductor component after the parallel test. 如申請專利範圍第17項所述之平行測試系統,其中更包含數個資料存取區,其中每一該資料存取區對應一半導體元件,而用以存放所對應之半導體元件的測試結果與量測資料。 The parallel test system of claim 17, further comprising a plurality of data access areas, wherein each of the data access areas corresponds to a semiconductor component, and the test result for storing the corresponding semiconductor component is Measurement data. 如申請專利範圍第18項所述之平行測試系統,其中該平行測試資料擷取存放單元藉由擷取每一半導體元件的個別資料存放區內的測試資料與結果,經由運算與判定而決定,那些半導體元件需要進行後續測試或是測試分枝。 The parallel test system of claim 18, wherein the parallel test data capture unit determines the test data and the result in the individual data storage area of each semiconductor component by calculation and determination. Those semiconductor components require subsequent testing or test branching. 一種平行測試方法,可以在循序測試模式與平行測試模式之間轉換測試模式,包含:一測試機台開始執行一使用者所編寫的測試程式;該測試機台依該測試程式建立一對單一半導體元件進行測試的測試流程;藉由一平行測試轉換裝置而將該測試流程轉換成一對多個半導體元件進行同步測試的平行測試流程,其中,該平行測試轉換裝置用以提供循序測試(Serial Test)與平行測試(Parallel Test)兩種測試模式,以及提供該循序測試模式與該平行測試模式之間的轉換,其包含:一平行測試執行與結束控制單元,用以將測試流程由一同一時間僅對單一半導體元件進行測試的循序測試流程轉換成一可以同時對多個半導體元件進行平行測試流程,而提供該平行測試模式以進行平行測試,並且控制該平行測試的開始、執行與結束;一平行測試資料擷取存放單元,用以將平行測試後所得到的資料進行擷取與存放,而供後續測試流程進行資料的運算與判斷;一同步測試旗號單元,用以依據當時測試狀態、測試流程或測試結果而設定同步測試旗號,而決定要對那些半導體元件進行同步測試;一循序測試執行與結束控制單元,用以將測試流程由該平行測試流程 重新轉換成該循序測試流程,而提供該循序測試模式以進行循序測試,並且控制該循序測試的開始、執行與結束,其中,該平行測試執行與結束控制單元、該平行測試資料擷取存放單元、以及該循序測試執行與結束控制單元分別與該同步測試旗號單元連接,並且該平行測試執行與結束控制單元、該平行測試資料擷取存放單元、以及該循序測試執行與結束控制單元經由該同步測試旗號單元而彼此連接;執行該平行測試流程;收集該平行測試流程所量測之資料與測試結果;以及結束平行測試流程。 A parallel test method for switching a test mode between a sequential test mode and a parallel test mode, comprising: a test machine starts executing a test program written by a user; the test machine establishes a pair of single semiconductors according to the test program a test flow in which the component is tested; a parallel test flow in which the test flow is converted into a pair of semiconductor components for simultaneous testing by a parallel test conversion device, wherein the parallel test conversion device is used to provide a serial test (Serial Test) And Parallel Test two test modes, and providing a conversion between the sequential test mode and the parallel test mode, comprising: a parallel test execution and end control unit for using the test process by a same time only The sequential test flow for testing a single semiconductor component is converted into a parallel test process for simultaneously performing a plurality of semiconductor components, and the parallel test mode is provided for parallel testing, and the start, execution and end of the parallel test are controlled; a parallel test Data capture unit for flattening The data obtained after the test is taken and stored, and the data is calculated and judged by the subsequent test process; a synchronous test flag unit is used to set the synchronous test flag according to the current test state, test flow or test result, and Decided to perform synchronous testing on those semiconductor components; a sequential test execution and termination control unit to pass the test flow from the parallel test flow Re-converting to the sequential test process, providing the sequential test mode for performing a sequential test, and controlling the start, execution, and end of the sequential test, wherein the parallel test execution and end control unit, the parallel test data capture storage unit And the sequential test execution and end control unit are respectively connected to the synchronous test flag unit, and the parallel test execution and end control unit, the parallel test data capture storage unit, and the sequential test execution and end control unit are synchronized via the synchronization test Test the flag unit and connect to each other; perform the parallel test process; collect the data and test results measured by the parallel test process; and end the parallel test process. 如申請專利範圍第20項所述之平行測試方法,其中更包含一撰寫該測試程式於測試機台步驟。 For example, the parallel test method described in claim 20 of the patent application further includes a step of writing the test program on the test machine. 如申請專利範圍第21項所述之平行測試方法,其中該測試程式係以C語言撰寫而成。 For example, the parallel test method described in claim 21, wherein the test program is written in C language. 如申請專利範圍第20項所述之平行測試方法,其中更包含一同步測試旗號設定步驟,用以設定同步測試旗號於需要進行同步測試的半導體元件,藉此標示或選定進行平測試的半導體元件。 The parallel test method as claimed in claim 20, further comprising a synchronization test flag setting step for setting a synchronization test flag to the semiconductor component that needs to be synchronously tested, thereby marking or selecting the semiconductor component for performing the flat test. . 如申請專利範圍第23項所述之平行測試方法,其中該測試流程更包含各項測試項目。 For example, the parallel test method described in claim 23, wherein the test process further includes various test items. 如申請專利範圍第24項所述之平行測試方法,其中更包含一測試通道展延步驟,用以將該等測試項目展延並對應至所有設定有同步測試旗號的半導體元件的測試通道(device channel),而進行平行測試。 The parallel test method as described in claim 24, further comprising a test channel extension step for extending the test items and corresponding to all test channels of the semiconductor component set with the synchronous test flag (device) Channel), and parallel testing. 如申請專利範圍第25項所述之平行測試方法,其中該測試通道展延步驟更包含一提供對應表步驟,用以提供每一進行平行測試之半導體元件個別對應的對應表。 The parallel test method of claim 25, wherein the test channel extending step further comprises a step of providing a correspondence table for providing a corresponding correspondence table of each semiconductor component for parallel testing. 如申請專利範圍第26項所述之平行測試方法,其中每一該對應表記載每一該半導體元件的引腳(pin)對應之測試通道,而提供每一該半導體元件最短與最佳的測試訊號傳遞途徑進行平行測試。 The parallel test method according to claim 26, wherein each of the correspondence tables records a test channel corresponding to a pin of each of the semiconductor components, and provides the shortest and best test of each of the semiconductor components. The signal transmission path is tested in parallel. 如申請專利範圍第25項所述之平行測試方法,其中更包含一提供資料存放區步驟,用以提供每一該半導體元件對應之資料存放區。 The parallel test method of claim 25, further comprising a data storage area step for providing a data storage area corresponding to each of the semiconductor elements. 如申請專利範圍第28項所述之平行測試方法,其中更包含一資料存放步驟,用以將每一該半導體元件所量測之資料與測試結果存放至對應之該資料存放區。 The parallel test method of claim 28, further comprising a data storage step for storing the data and test results measured by each of the semiconductor components in the corresponding data storage area. 如申請專利範圍第29項所述之平行測試方法,其中更包含一運算與判斷步驟,用以擷取每一該資料存放區的量測資料與測試結果進行運算與判斷,而判定每一該半導體元件是否進行後續測試或進行測試分枝。 The parallel test method as claimed in claim 29, further comprising an operation and a judgment step, which are used for calculating and judging the measurement data and the test result of each of the data storage areas, and determining each of the Whether the semiconductor component is subjected to subsequent testing or test branching. 如申請專利範圍第30項所述之平行測試方法,其中更包含一重新設定同步測試旗號步驟,重新對需要進行後續測試或進行測試分枝的每一該半導體元件重新進行同步測試旗號設定。 The parallel test method of claim 30, further comprising the step of resetting the synchronization test flag, and re-synchronizing the test flag for each of the semiconductor components that need to be tested or tested. 如申請專利範圍第20項所述之平行測試方法,其中更包含一循序測試步驟,用以進行循序測試。 The parallel test method as described in claim 20, further comprising a sequential test step for performing the sequential test. 如申請專利範圍第32項所述之平行測試方法,其中該循序測試步驟包含一單一同步測試旗號設定步驟,用以在同一時間內,僅對一半導體元件設定同步測試旗號,而標示或選定進行循序測試之半導體元件。 The parallel test method of claim 32, wherein the sequential test step comprises a single synchronous test flag setting step for setting a synchronization test flag for only one semiconductor component at the same time, and marking or selecting Sequentially tested semiconductor components.
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