TWI460654B - Data storage device and method for managing blocks of a flash memory - Google Patents

Data storage device and method for managing blocks of a flash memory Download PDF

Info

Publication number
TWI460654B
TWI460654B TW102103260A TW102103260A TWI460654B TW I460654 B TWI460654 B TW I460654B TW 102103260 A TW102103260 A TW 102103260A TW 102103260 A TW102103260 A TW 102103260A TW I460654 B TWI460654 B TW I460654B
Authority
TW
Taiwan
Prior art keywords
blocks
block
data
spare
controller
Prior art date
Application number
TW102103260A
Other languages
Chinese (zh)
Other versions
TW201349096A (en
Inventor
Chang Kai Cheng
Yen Hung Lin
Original Assignee
Silicon Motion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US13/474,801 priority Critical patent/US9116792B2/en
Application filed by Silicon Motion Inc filed Critical Silicon Motion Inc
Publication of TW201349096A publication Critical patent/TW201349096A/en
Application granted granted Critical
Publication of TWI460654B publication Critical patent/TWI460654B/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7205Cleaning, compaction, garbage collection, erase control
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7211Wear leveling

Description

Data storage device and block management method for flash memory

The present invention relates to a flash memory, and more particularly to a block management method for a flash memory.

Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. Flash memory is suitable for the storage and transmission of general data, mainly used in memory cards, USB flash memory, solid-state drives and similar products. For example, devices that apply flash memory include personal computers, personal digital assistants (PDAs), digital audio players, digital cameras, mobile phones, video games, and the like. In addition to being non-volatile, flash memory also provides fast read times like dynamic random access memory (dynamic RAM), although not as fast as static random access memory (static RAM) or read only Memory (ROM). Due to the large demand for non-volatile, solid-state storage devices, the current flash memory price is much lower than the byte-programmable electronic erasable rewritable read-only memory (EEPROM). And has become the mainstream memory type.

Therefore, there is a need for a suitable flash memory management method for improving the performance of flash memory.

It is an object of the present invention to provide a block management method for flash memory for improving the performance of a flash memory.

The invention provides a data storage device comprising a flash memory and a controller. The flash memory includes a spare block pool and a data block pool, the spare block pool includes a plurality of spare blocks, and the data block pool includes a plurality of data blocks. The controller determines a minimum erasure number from the erasure times of the spare block and the data block, and adds a minimum erased number to a second difference value to obtain a forbidden threshold value, and compares the erased block of the spare block. The number of times and the imprisonment threshold are used to obtain a plurality of imprisonment blocks with the number of erasures greater than the imprisonment threshold, limit the imprisonment block to a prison cell, and avoid using the imprisonment block as one of the data to be written. Piece.

The invention also provides a block management method for flash memory, wherein a data storage device comprises a flash memory and a controller, the flash memory body comprises a spare block pool and a data block pool, and the spare area The block pool includes a plurality of spare blocks and the data block pool includes a plurality of data blocks, and the block management method of the flash memory includes determining, by the controller, a minimum number of erasures from the spare blocks and the number of erases of the data blocks. The minimum number of erasures is added to the second difference value by the controller to obtain a threshold of imprisonment; the number of erasures of the spare block and the imprisonment threshold are compared via the controller to obtain an erasure number greater than imprisonment The imprisonment block of the critical value; the imprisonment block is restricted to one imprisonment pool in the spare block pool; and the imprisonment block is avoided as the current data block to be written by the controller.

100,800‧‧‧ data storage device

102, 802‧‧ ‧ controller

104‧‧‧Flash memory

120‧‧‧ Imprisonment pool

110, 812, 822, 832‧‧‧ spare block pool

130, 814, 824, 834‧‧‧ data block pool

111~11n‧‧‧ spare block

121~12k‧‧‧ Imprisonment block

131~13m‧‧‧data block

300‧‧‧ current data block

301~30x‧‧‧page

311~314, D5‧‧‧Information

WL_TH1‧‧‧First difference

WL_TH2‧‧‧second difference

Blocks 502, 503, 504‧‧

601, 602, 603, 604, 701, 701'‧‧‧ source data blocks

610, 711, 711’ ‧ ‧ end of the spare block

D1, D2, D3, D4‧‧‧ valid data

810, 820, 830‧‧‧ flash memory area

Figure 1 is a schematic illustration of a data storage device in accordance with the present invention.

Figure 2 is a flow chart of a block management method for flash memory according to the present invention.

Figure 3 is a schematic diagram of the current data block in accordance with the present invention.

Figure 4 is a flow diagram of a method for obtaining spare blocks from a pool of data blocks in accordance with the present invention.

Figure 5 is a schematic diagram of the calculation of imprisonment thresholds and popular thresholds in accordance with the present invention.

Figure 6 is a schematic illustration of a data merging procedure in accordance with the present invention.

Figure 7 is a schematic illustration of a wear leveling procedure in accordance with the present invention.

Figure 8 is another schematic view of a data storage device in accordance with the present invention.

Figure 9 is a flow chart of a block management method for a plurality of memory regions in accordance with the present invention.

The following description is the best mode for carrying out the invention. It will be appreciated by those skilled in the art that a number of changes, substitutions and substitutions can be made without departing from the spirit and scope of the invention. The scope of the invention is determined by the scope of the appended claims.

1 is a block diagram of a data storage device 100 of the present invention. In an embodiment, the data storage device 100 includes a controller 102 and a flash memory 104. Flash memory 104 includes a plurality of blocks for storing data. In one embodiment, the flash memory 104 includes a spare block pool 110 and a data block pool 130. The spare block pool 110 includes a plurality of spare blocks 111-11n for storing invalid data. The data block pool 130 includes a plurality of data blocks 131 to 13m for storing data. In a In an embodiment, the data storage device 100 is coupled to a host. The controller 102 manages the blocks within the flash memory 104 in accordance with instructions sent by the host. The flash memory 104 specifies a block based on a physical address, and the host designates a block based on the logical address. Therefore, the controller 102 must convert a logical address sent by the host into a physical address. In an embodiment, the controller 102 records the correspondence between the logical address of the block and the physical address in the address mapping table.

Each data block 131~13m includes a plurality of pages. When a material is stored in a page of a data block, the page is called a data page. When the page has a corresponding logical address, the page is called a valid page. In an embodiment, the controller 102 individually calculates the total number of valid pages of each of the data blocks 131~13m to obtain a valid page number, and records the effective page number of the data blocks 131~13m. Go to an effective quantity table. In addition, the number of times the block is erased is referred to as the number of erases of the block. In one embodiment, the controller 102 also records the number of erases of all blocks in the flash memory 104 in an erasure count table.

2 is a flow diagram of a method 200 for managing blocks of flash memory 104 in accordance with the present invention. When the host sends the target data to be written to the data storage device 100, the controller receives the target data (step 202), and then writes the target data to the current data block (step 204). Referring to FIG. 3, FIG. 3 is a schematic diagram of one of the current data blocks 300 in the flash memory 104. The current data block 300 includes a plurality of pages. The current data block 300 can be used to store data pages corresponding to different logical addresses. For example, the data 311 stored in the page 301 corresponds to the logical address L1, the data 312 stored in the page 302 corresponds to the logical address L2, and the data stored in the page 303 corresponds to the data 313. Go to the logical address L3.

After the target material is written to the current data block, the controller 102 then determines if the current data block is full (step 206). In an embodiment, when the programming page currently programmed by the controller 102 is the last page of the current data block, the controller 102 determines that the current data block is full, and then the controller 102 is based on the current data. The information of the block updates the plural data table (step 208). In an embodiment, the updated data tables include a one-bit link list and a valid page number table. Since the data stored in the pages of the current data block respectively correspond to different logical addresses, the controller 102 must write the paged physical address of the current data block and the logical address stored in the data. The mapping relationship to the address link table. In addition, when the host deletes or updates a page break, the page break will be marked as invalid page break. Controller 102 must calculate the total number of valid pages in a block to determine the number of valid pages in the block and write the number of valid pages to the effective page number table. After more data is deleted and/or updated again, the pages stored in some of the data blocks in the data block pool 130 will not have a valid page, and their effective page number will be set to zero. Thereafter, the data blocks with zero effective page number will be set as spare blocks and moved from the data block pool 130 to the spare block pool 110 (step 210). Step 210 will be explained in more detail in FIG. The controller 102 continues to retrieve a spare block from the spare block pool 110 and assigns the spare block to the current data block for receiving new data sent by the host (step 212).

Figure 5 is a schematic diagram of the calculation of a jail threshold value and a hot threshold value in accordance with the present invention. All blocks in the flash memory 104 have an erasure count. When the controller 102 sets a block as a spare block and places the block in the spare block pool, the number of erases of the block is increased once. The minimum number of erases of the block of flash memory 104 will increase over time, and in some cases, the block with the least number of erases will change. Therefore, based on the change in the number of erases of all blocks in the flash memory 104, the controller 102 frequently determines the minimum number of erases. As shown in FIG. 5, after the minimum number of erases is determined, the controller 102 adds the first difference WL_TH1 to the minimum erase count to obtain a hot threshold, and adds the second error WL_TH2. The minimum number of erasures is taken to obtain a imprisonment threshold. In an embodiment, the first difference WL_TH1 is smaller than the second difference WL_TH2. Here, the second difference WL_TH2 is greater than the first difference WL_TH1, so the imprisonment threshold will be greater than the popularity threshold. When the number of erasures of a block is greater than the popularity threshold, the controller 102 determines the block as a hot block. When the number of erasures of a block is greater than the imprisonment threshold, the controller 102 determines the block as a block of imprisonment and places the block of imprisonment in the jail pool shown in FIG. 120. For example, blocks 502, 503, and 504 shown in FIG. 5 have erase times greater than the imprisonment threshold and are therefore placed in jail cell 120. Although the imprisonment blocks 121~12k are also spare blocks, when the controller 102 is to retrieve a new spare block for storing data from the spare block pool 110, the controller 102 does not retrieve the jail block. Therefore, unless the imprisonment block is released in the future, the number of erasures of the imprisonment block will not be increased.

FIG. 4 is a flow diagram of a method 400 of obtaining spare blocks from a data block pool 130. Method 400 includes the method of performing the method shown in FIG. The detailed steps of step 210 in 200. First, the controller 102 determines the minimum number of erasures from one of the erasure times of the block of the flash memory 104, and calculates a detention threshold based on the minimum number of erasures. After updating the imprisonment threshold, the number of erasures in some of the imprisonment blocks 121-12k in the imprisonment pool 120 will be less than the updated imprisonment threshold. Therefore, the controller 102 compares the erasure times of the imprisonment blocks 121~12k in the imprisonment pool 120 with the imprisonment threshold, and when the number of erasures of the imprisonment blocks 121~12k is less than the imprisonment threshold, the controller 102 will The imprisonment block is released to the spare block pool 110 (step 402).

Some of the data blocks 131~13m in the data block pool 130 do not have valid data and the effective page number is zero. Therefore, in step 404, the controller 102 searches for any target blocks in the data block pool 130 that have a valid number of pages of zero, and then proceeds to step 406 to place the target blocks into the spare block pool 110 and Add one to the number of erasures for these target blocks. In step 408, the controller 102 will determine if any of the target blocks have been erased more than the imprisonment threshold. If the result of the decision in step 408 is YES, then step 412 is entered. In step 412, the controller 102 places the target block with the number of erases greater than the imprisonment threshold to the imprisonment pool 120. If the result of the determination in step 408 is no, the process proceeds to step 410. In step 410, the controller 102 will determine if any of the target blocks have been erased more than the popularity threshold. If the decision in step 410 is YES, then step 414 is entered. In step 414, the controller 102 determines that the target block is a hot block and adds the number of target blocks determined to be the hot block to the number of hot blocks.

Refer to Figure 2. In step 204, the process proceeds to step 206 after the target material is written to the current data block. In step 206, the controller 102 It will determine whether the current data block is full. If the result of the determination in step 206 is no, the process proceeds to step 214. In step 214, the controller 102 determines if the currently stylized page break is the first page of the current data block. If the decision result is yes, then go to step 216. For example, if the currently stylized page of the controller is the page 301 shown in FIG. 3, and the page 301 is the first page of the current data block 300, the controller 102 determines whether the number of spare blocks is smaller than a spare area. The block number threshold (step 216). The number of spare blocks is the total number of spare blocks in the spare block pool 110. In an embodiment, the threshold number of spare blocks is 15. Assuming that a spare block is obtained from the spare block pool and erased as a new current data block, the total number of spare blocks in the spare block pool will be one less. In step 216, when the number of spare blocks is less than the threshold number of spare blocks, then step 218 is entered. In step 218, the controller 102 sets a data movement information required for a data merge procedure to initiate a data merge procedure for increasing the number of spare blocks.

In an embodiment, the data movement information used to initiate the data merge program includes a physical address having a plurality of source data blocks to be merged data and a destination spare block to be written into the merged data. The physical address. The controller 102 selects a plurality of data blocks having the smallest effective page number from the data block pool 130 as the source data block, and obtains a spare block as the destination spare block. Figure 6 is a schematic illustration of a data merge procedure in accordance with the present invention. When the data merge process begins, four source material blocks 601, 602, 603, and 604 having the least significant page number are selected from the data block pool 130, and the destination spare block 610 is selected from the spare pool. The controller 102 then erases the destination spare block 610 and sources the source data. The valid data D1, D2, D3, and D4 of blocks 601, 602, 603, and 604 are combined in a RAM (not shown) to obtain a merged material (D1+D2+D3+D4). The controller 102 writes the merged material (D1+D2+D3+D4) to the destination spare block 610. Finally, the controller 102 places the source data blocks 601, 602, 603, and 604 into the spare block pool 110, and places the destination spare block 610 written to the merged data (D1+D2+D3+D4) to the data. Block pool 130. Therefore, after the data merge process is performed, the total number of spare blocks in the spare block pool will increase by three.

Refer to Figure 2. When the currently programmed page break is the first page of the current data block (step 214), and the number of spare blocks is greater than the spare block number threshold (step 216), the controller 102 will determine if the number of hot blocks is greater than Zero (step 220). The number of hot blocks is the total number of hot blocks in the spare block pool that have erase times greater than the popularity threshold. Because the hot blocks have a high number of erasures, if the spare block pool 110 includes a large number of hot blocks, the controller 102 must retrieve the hot blocks from the spare block pool 110 and A data block with a minimum number of erases performs a wear-level process. Therefore, when the number of spare blocks is greater than the threshold value of the spare blocks and the number of hot blocks is greater than zero (step 220), the controller 102 sets the data movement information for the wear leveling program to start the wear leveling program, so that the hotspot The number of blocks is reduced (step 222).

In an embodiment, the data movement information used to initiate the wear leveling program includes a physical address of at least one source data block of the data to be copied and a physical address of at least one destination spare block for writing the data. When there are multiple hot blocks in the spare block pool 110, the controller 102 determines the heat The gate block is the spare block for these destinations. Since the data stored in the data block having the low erase count has a low update probability, the controller 102 selects a plurality of data blocks having a low erase count from the data block pool 130 as the source data block. Figure 7 is a schematic illustration of a wear leveling procedure in accordance with the present invention. When the wear leveling procedure begins, the source data block 701 having the smallest number of erases is selected from the data block pool 130 and the destination spare block 711 is selected from the spare block pool 110. Next, the controller 102 erases the destination spare block 711 and writes the copied material D5 to the destination spare block 711'. Then, the source data block 701' having the low erase count is placed in the spare block pool 110, and the destination spare block 711' from the spare block pool 110 having the high erase count is placed in the data area. Block pool 130. Therefore, after the wear leveling procedure is performed, the total number of hot blocks in the spare block pool 110 will be reduced by one.

Refer to Figure 2. When the current stylized page written by the target data is not the first page of the current data block (step 214), the controller 102 determines whether the data transfer information is set (step 224). If the data transfer information for the data merge program or the wear leveling program has been set, the controller 102 moves the data merge program or the wear level balance program of the information execution portion according to the data in a limited time interval (step 226). The limited time interval is determined by the criteria required for data transfer between the host and the data storage device 104. For example, after the host sends a write command and sends the target data to the controller 102, the host must receive response information about the execution in a limited time interval of 100 milliseconds to 300 milliseconds, and the controller 102 can only Perform data merge procedures or wear leveling procedures in a limited time interval.

Controller 102 will merge data due to limited time intervals The operation of the data movement in the program or the wear leveling program is cut into a plurality of data moving programs. When a new target data is written to the current stylized page (step 204), if the currently stylized page is not the first page of the current data block (step 214), then it is used in a limited time interval. One of the plurality of operating procedures for the data merge procedure or the data transfer of the wear leveling program will be executed. For example, as shown in FIG. 6, when the data transfer information for the data merge program is set (step 224), the controller 102 proceeds from the source material blocks 601, 602, 603, and 604 in a limited time interval. The plurality of target pages having valid data are selected, and the valid data is copied from the target page to the destination spare block 610. For example, as shown in FIG. 7, when the data movement information for the wear leveling program is set (step 224), the controller 102 selects the plurality of target pages from the source data block 701 in a limited time interval. And the data is copied from the target page to the destination spare block 711. After several new write commands are executed, the data transfer operation for the data merge program or the wear leveling program is also completed.

Figure 8 is a block diagram of a data storage device 800 of the switchable memory region of the present invention. The data storage device 800 includes a controller 802 and a plurality of flash memory regions 810, 820, and 830. In one embodiment, flash memory regions 810, 820, and 830 are respectively different flash memory chips. For example, the flash memory region 810 is a flash memory having a single-bit per cell (SLC), and the flash memory region 820 has a second-order memory cell (MLC). The flash memory and flash memory area 830 is a flash memory having a third bit cell (TLC). In another embodiment, the flash memory regions 810, 820, and 830 are A number of memory partitions within a single flash memory. Each of the flash memory regions 810, 820, and 830 includes a spare block pool and a data block pool. The controller 802 independently manages the blocks located in each of the flash memory regions 810, 820, and 830. For example, the controller 802 performs a data merge procedure or a wear leveling procedure between the spare block pool and the data chunk pool of a single flash memory area. When performing block management, the controller 802 does not exchange data of blocks of a flash memory area with data of other flash memory areas.

Figure 9 is a flow diagram of a method 900 for managing memory regions 810, 820, and 830 in accordance with the present invention. First, the controller 802 receives the target data from the host (step 902). Then, the controller 802 determines a target memory region for writing the target data from the plurality of flash memory regions 810, 820, and 830 (step 904). Then, the controller 802 sets a physical address range parameter according to the target memory area (step 906). In an embodiment, the physical address range parameter includes a start address parameter and an end address parameter, and the controller 802 sets the start address parameter to a start address of the target memory area, and sets the end address. The parameter is the end address of the target memory area. Controller 802 then sets a spare block pool parameter based on the target memory region (step 908). In one embodiment, controller 802 records the physical address of the spare block in the spare block pool of the target memory region into the spare block pool parameter. Controller 802 then writes the target data into the current data block of the target memory region (step 910).

The controller 802 performs a data merge process on the plurality of blocks of the target memory region according to steps 206-226 in the method 200 shown in FIG. Is the wear leveling program. In other words, the controller 802 performs a data merge process on a plurality of data blocks in the data block pool of the target memory region (step 912), or a plurality of spare blocks in the spare block pool of the target memory region. A wear leveling procedure is performed between the plurality of data blocks in the data block pool of the target memory area (step 914). The data merge process in step 912 or the data move information in the wear leveling process in step 914 is the same as that shown in step 218 or 222, and is performed in the data merge process in step 912 or in step 914. The wear leveling procedure is also the same as step 226. Therefore, the controller 802 can independently manage the blocks within the target memory area without simultaneously managing the blocks in other flash memory areas.

100‧‧‧ data storage device

110‧‧‧Reserved block pool

102‧‧‧ Controller

104‧‧‧Flash memory

120‧‧‧ Imprisonment pool

130‧‧‧Data Pool

111~11n‧‧‧ spare block

121~12k‧‧‧ Imprisonment block

131~13m‧‧‧data block

Claims (16)

  1. A data storage device comprising: a flash memory, comprising a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks; And a controller determining a minimum erasure number from the plurality of erasure times of the spare blocks and the data blocks, and adding a second difference value to obtain a imprisonment threshold And comparing the number of erasures of the spare blocks with the imprisonment threshold to obtain a plurality of imprisonment blocks having a number of erasures greater than the imprisonment threshold, and restricting the imprisonment blocks to a jail cell, And avoid using these imprisonment blocks as the current data block for one of the data to be written.
  2. The data storage device of claim 1, wherein the controller adds the first erasure number to a first difference value to obtain a hot threshold value, and compares the number of erasures of the spare blocks. And the hot threshold value is used to obtain a plurality of hot blocks having a erased number greater than the hot threshold, and the number of the hot blocks is calculated to obtain a number of hot blocks, and when the number of the hot blocks is greater than At zero hour, a wear leveling procedure is performed between the data blocks in the data block pool and the hot blocks.
  3. The data storage device of claim 2, wherein the second difference is greater than the first difference.
  4. The data storage device of claim 2, wherein when the controller executes the wear leveling program, the controller selects a plurality of the minimum number of erasures from the data blocks of the data block pool. Target data area Blocking, selecting, from the hot blocks of the spare block pool, a plurality of target spare blocks having a maximum number of erasures, and moving the data stored in the target data blocks to the target spare blocks. The data located in the target data blocks is erased, the target spare blocks are placed in the data block pool, and the target data blocks are placed in the spare block pool.
  5. The data storage device of claim 2, wherein the controller frequently updates the minimum erasure times and the imprisonment threshold according to changes in the spare blocks and the number of erasures of the data blocks. Value, and when the imprisonment threshold is changed, the controller releases the imprisonment block from the imprisonment pool into the hot blocks.
  6. The data storage device of claim 1, wherein the controller searches for the at least one target block having a valid number of pages of zero in the data blocks in the data block pool.
  7. The data storage device of claim 6, wherein after the number of erasures of the target block is increased, if the number of erasures of the target block is greater than the imprisonment threshold, the controller will cause The target block becomes the imprisonment block, and the target block is placed in the imprisonment pool.
  8. The data storage device of claim 6, wherein after the erasing number of the target block is increased, if the erasure number of the target block is greater than a hot threshold, the controller will cause The target block becomes a hot block and adds one to the number of hot blocks.
  9. A block management method for flash memory, wherein a data storage device comprises a flash memory and a controller, the flash memory body comprising a spare block pool and a data block pool, the spare block pool Including multiple spare areas And the data block pool includes a plurality of data blocks, and the block management method of the flash memory includes: determining, by the controller, a minimum of the plurality of erasure times of the spare blocks and the data blocks The number of erasures; the minimum number of erasures is added to the second difference value by the controller to obtain a forbidden threshold; and the number of erasures of the spare blocks is compared with the imprisonment threshold via the controller a value for obtaining a plurality of imprisonment blocks having a number of erasures greater than the imprisonment threshold; limiting the imprisonment block to a jail cell in the spare block pool; and avoiding using the imprisonment block as soon The controller writes one of the current data blocks of the data.
  10. The block management method of the flash memory according to claim 9 further includes: adding, by the controller, the minimum erasure number to a first difference value to obtain a hot threshold value; The controller compares the number of erasures of the spare blocks with the popularity threshold to obtain a plurality of hot blocks having an erased number greater than the hot threshold; and calculating the number of the hot blocks via the controller For obtaining a number of hot blocks; and when the number of the hot blocks is greater than zero, performing a wear level balancing between the data blocks in the data block pool and the hot blocks via the controller program.
  11. The method for managing a block of a flash memory according to claim 10, wherein the second difference is greater than the first difference.
  12. The method for managing a block of a flash memory according to claim 10, wherein the step of executing the wear leveling process comprises: selecting, from the data blocks of the data block pool, a minimum number of erasures. a plurality of target data blocks; selecting, from the hot blocks of the spare block pool, a plurality of target spare blocks having a maximum number of erasures; and moving data stored in the target data blocks to the target spares Blocking; erasing data located in the target data blocks; placing the target spare blocks into the data block pool; and placing the target data blocks into the spare block pool.
  13. The method for managing a block of a flash memory according to claim 10, further comprising: frequently updating the number of erase times according to the spare blocks and the number of erases of the hot blocks; The minimum number of erasures and the imprisonment threshold; and when the imprisonment threshold is changed, the imprisonment blocks in the imprisonment pool are released into the hot blocks via the controller.
  14. The block management method of the flash memory according to claim 9 further includes: searching, by the controller, the data blocks in the data block pool to have a valid page number of zero At least one target block; The target block is placed into the spare block pool via the controller; and the number of erasures of the target block is increased by one.
  15. The method for managing a block of a flash memory according to claim 14 further includes: after the number of erasures of the target block is increased, when the number of erasures of the target block is greater than the imprisonment threshold When the value is reached, the controller determines the target block as the imprisonment block and places the target block into the imprisonment pool.
  16. The method for managing a block of a flash memory according to claim 14 further includes: after the number of erasures of the target block is increased, when the number of erasures of the target block is greater than a critical value of the hot zone When the value is reached, the controller determines the target block as a hot zone block and increments the number of hot zone blocks by one.
TW102103260A 2012-05-18 2013-01-29 Data storage device and method for managing blocks of a flash memory TWI460654B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/474,801 US9116792B2 (en) 2012-05-18 2012-05-18 Data storage device and method for flash block management

Publications (2)

Publication Number Publication Date
TW201349096A TW201349096A (en) 2013-12-01
TWI460654B true TWI460654B (en) 2014-11-11

Family

ID=49582277

Family Applications (6)

Application Number Title Priority Date Filing Date
TW102103258A TW201349101A (en) 2012-05-18 2013-01-29 Data storage device and method for managing blocks of a flash memory
TW102103259A TWI590150B (en) 2012-05-18 2013-01-29 Data storage device and method for managing blocks of a flash memory
TW102103260A TWI460654B (en) 2012-05-18 2013-01-29 Data storage device and method for managing blocks of a flash memory
TW102103441A TW201349098A (en) 2012-05-18 2013-01-30 Data storage device and method for managing blocks of a flash memory
TW102103442A TWI489373B (en) 2012-05-18 2013-01-30 Data storage device and method for managing blocks of a flash memory
TW102103440A TWI514260B (en) 2012-05-18 2013-01-30 Data storage device and method for managing blocks of a flash memory

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW102103258A TW201349101A (en) 2012-05-18 2013-01-29 Data storage device and method for managing blocks of a flash memory
TW102103259A TWI590150B (en) 2012-05-18 2013-01-29 Data storage device and method for managing blocks of a flash memory

Family Applications After (3)

Application Number Title Priority Date Filing Date
TW102103441A TW201349098A (en) 2012-05-18 2013-01-30 Data storage device and method for managing blocks of a flash memory
TW102103442A TWI489373B (en) 2012-05-18 2013-01-30 Data storage device and method for managing blocks of a flash memory
TW102103440A TWI514260B (en) 2012-05-18 2013-01-30 Data storage device and method for managing blocks of a flash memory

Country Status (3)

Country Link
US (6) US9116792B2 (en)
CN (6) CN103425597B (en)
TW (6) TW201349101A (en)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010125574A1 (en) * 2009-04-27 2010-11-04 Kamlesh Gandhi Description
KR102067029B1 (en) * 2012-12-13 2020-01-16 삼성전자주식회사 Semiconductor memory devices and memory systems
US10417123B1 (en) * 2013-05-16 2019-09-17 Western Digital Technologies, Inc. Systems and methods for improving garbage collection and wear leveling performance in data storage systems
KR102164630B1 (en) * 2013-06-28 2020-10-12 삼성전자주식회사 Memory controller, and operation method of the memory controller
US9235486B1 (en) * 2013-09-30 2016-01-12 Symantec Corporation Techniques for spare storage pool management
US9329992B2 (en) * 2013-12-04 2016-05-03 Silicon Motion, Inc. Data storage device and flash memory control method
CN103631538B (en) * 2013-12-05 2017-04-05 华为技术有限公司 Cold and hot data identification threshold value calculation, device and system
CN103761193B (en) * 2013-12-17 2016-09-14 记忆科技(深圳)有限公司 The method and system that suppression logical page (LPAGE) fragment produces
CN103823640B (en) * 2014-03-03 2017-12-01 山西科泰航天防务技术股份有限公司 A kind of high efficiency storage method of flash storage
TWI516922B (en) * 2014-03-12 2016-01-11 慧榮科技股份有限公司 Data storage device and flash memory garbage collection method
CN105468538B (en) * 2014-09-12 2018-11-06 华为技术有限公司 A kind of internal memory migration method and apparatus
CN105489246B (en) * 2014-09-16 2018-10-19 华邦电子股份有限公司 NOR flash memory and its method for repairing and mending
US9740425B2 (en) * 2014-12-16 2017-08-22 Sandisk Technologies Llc Tag-based wear leveling for a data storage device
KR20170010136A (en) * 2015-07-15 2017-01-26 에스케이하이닉스 주식회사 Memory system and operating method of memory system
TWI585770B (en) * 2015-08-11 2017-06-01 群聯電子股份有限公司 Memory management method, memory control circuit unit and memory storage device
KR20170027927A (en) * 2015-09-02 2017-03-13 삼성전자주식회사 Method for operating storage device managing wear level depending on reuse period
TWI561985B (en) * 2015-10-22 2016-12-11 Silicon Motion Inc Data storage device and data maintenance method thereof
US9983963B2 (en) * 2015-11-09 2018-05-29 Alibaba Group Holding Limited System and method for exploiting hard disk drive capacity reserve and extending operating life thereof
US10387329B2 (en) * 2016-02-10 2019-08-20 Google Llc Profiling cache replacement
US20170277629A1 (en) * 2016-03-25 2017-09-28 Alibaba Group Holding Limited Extending the useful lifespan of nonvolatile memory
TWI614605B (en) * 2016-03-31 2018-02-11 慧榮科技股份有限公司 Data storage device and data maintenance method thereof
TWI590051B (en) 2016-06-21 2017-07-01 慧榮科技股份有限公司 Data storage device and data maintenance method thereof
TWI615710B (en) * 2016-12-14 2018-02-21 群聯電子股份有限公司 Memory management method, memory storage device and memory control circuit unit
KR20180076425A (en) * 2016-12-27 2018-07-06 에스케이하이닉스 주식회사 Controller and operating method of controller
US10380028B2 (en) * 2016-12-30 2019-08-13 Western Digital Technologies, Inc. Recovery of validity data for a data storage system
CN108877863B (en) * 2017-05-16 2020-08-04 华邦电子股份有限公司 Flash memory storage device and operation method thereof
CN108089994A (en) * 2018-01-04 2018-05-29 威盛电子股份有限公司 Storage device and data save method
CN108563397A (en) 2018-01-04 2018-09-21 威盛电子股份有限公司 Storage device and data save method
US20200026436A1 (en) * 2018-07-17 2020-01-23 Silicon Motion Inc. Flash controllers, methods, and corresponding storage devices capable of rapidly/fast generating or updating contents of valid page count table
US10795576B2 (en) 2018-11-01 2020-10-06 Micron Technology, Inc. Data relocation in memory
CN109669889A (en) * 2018-12-24 2019-04-23 青岛方寸微电子科技有限公司 A kind of light-type Nor Flash flash memory control method and device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956473A (en) * 1996-11-25 1999-09-21 Macronix International Co., Ltd. Method and system for managing a flash memory mass storage system
US20050204187A1 (en) * 2004-03-11 2005-09-15 Lee Charles C. System and method for managing blocks in flash memory
US20110161564A1 (en) * 2009-12-30 2011-06-30 Phison Electronics Corp. Block management and data writing method, and flash memory storage system and controller using the same

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8027194B2 (en) * 1988-06-13 2011-09-27 Samsung Electronics Co., Ltd. Memory system and method of accessing a semiconductor memory device
US20080195798A1 (en) * 2000-01-06 2008-08-14 Super Talent Electronics, Inc. Non-Volatile Memory Based Computer Systems and Methods Thereof
US20080082736A1 (en) * 2004-03-11 2008-04-03 Chow David Q Managing bad blocks in various flash memory cells for electronic data flash card
US8959280B2 (en) * 2008-06-18 2015-02-17 Super Talent Technology, Corp. Super-endurance solid-state drive with endurance translation layer (ETL) and diversion of temp files for reduced flash wear
JP4812192B2 (en) * 2001-07-27 2011-11-09 パナソニック株式会社 Flash memory device and method for merging data stored therein
US6895464B2 (en) * 2002-06-03 2005-05-17 Honeywell International Inc. Flash memory management system and method utilizing multiple block list windows
US6973531B1 (en) * 2002-10-28 2005-12-06 Sandisk Corporation Tracking the most frequently erased blocks in non-volatile memory systems
US7254668B1 (en) * 2002-10-28 2007-08-07 Sandisk Corporation Method and apparatus for grouping pages within a block
US7035967B2 (en) * 2002-10-28 2006-04-25 Sandisk Corporation Maintaining an average erase count in a non-volatile storage system
US6985992B1 (en) 2002-10-28 2006-01-10 Sandisk Corporation Wear-leveling in non-volatile storage systems
US20050120265A1 (en) 2003-12-02 2005-06-02 Pline Steven L. Data storage system with error correction code and replaceable defective memory
US7409489B2 (en) * 2005-08-03 2008-08-05 Sandisk Corporation Scheduling of reclaim operations in non-volatile memory
US7853749B2 (en) * 2005-09-01 2010-12-14 Cypress Semiconductor Corporation Flash drive fast wear leveling
US7594087B2 (en) * 2006-01-19 2009-09-22 Sigmatel, Inc. System and method for writing data to and erasing data from non-volatile memory
US7653778B2 (en) * 2006-05-08 2010-01-26 Siliconsystems, Inc. Systems and methods for measuring the useful life of solid-state storage devices
JP4700562B2 (en) 2006-05-18 2011-06-15 株式会社バッファロー Data storage device and data storage method
US7953954B2 (en) * 2007-01-26 2011-05-31 Micron Technology, Inc. Flash storage partial page caching
CN101281492B (en) * 2007-04-04 2011-02-02 扬智科技股份有限公司 Method for recovering comparison table of flash memory
US7689762B2 (en) 2007-05-03 2010-03-30 Atmel Corporation Storage device wear leveling
KR100857761B1 (en) * 2007-06-14 2008-09-10 삼성전자주식회사 Memory system performing wear levelling and write method thereof
TWI366828B (en) * 2007-09-27 2012-06-21 Phison Electronics Corp Wear leveling method and controller using the same
CN101409108B (en) * 2007-10-09 2011-04-13 群联电子股份有限公司 Average abrasion method and controller using the same
US8122179B2 (en) * 2007-12-14 2012-02-21 Silicon Motion, Inc. Memory apparatus and method of evenly using the blocks of a flash memory
KR101454817B1 (en) * 2008-01-11 2014-10-30 삼성전자주식회사 Semiconductor memory devices and wear leveling methods thereof
JP4675985B2 (en) * 2008-03-01 2011-04-27 株式会社東芝 Memory system
CN101566969B (en) * 2008-04-21 2011-05-18 群联电子股份有限公司 Method and controller capable of enhancing management efficiency of nonvolatile storage
US8275928B2 (en) * 2008-05-15 2012-09-25 Silicon Motion, Inc. Memory module and method for performing wear-leveling of memory module using remapping, link, and spare area tables
US8843691B2 (en) * 2008-06-25 2014-09-23 Stec, Inc. Prioritized erasure of data blocks in a flash storage device
TWI389125B (en) * 2008-07-18 2013-03-11 A Data Technology Co Ltd Memory storage device and control method thereof
US8140739B2 (en) * 2008-08-08 2012-03-20 Imation Corp. Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table
US8219781B2 (en) * 2008-11-06 2012-07-10 Silicon Motion Inc. Method for managing a memory apparatus, and associated memory apparatus thereof
TWI413931B (en) 2009-01-15 2013-11-01 Phison Electronics Corp Data accessing method for flash memory, and storage system and controller system thereof
US20100235605A1 (en) * 2009-02-13 2010-09-16 Nir Perry Enhancement of storage life expectancy by bad block management
TWI409819B (en) * 2009-03-03 2013-09-21 Silicon Motion Inc Method of evenly using a plurality of blocks of a flash memory, and associated memory device and controller thereof
KR101586047B1 (en) * 2009-03-25 2016-01-18 삼성전자주식회사 Nonvolatile memory device and program methods for the same
US8412909B2 (en) * 2009-04-08 2013-04-02 Samsung Electronics Co., Ltd. Defining and changing spare space and user space in a storage apparatus
KR101571693B1 (en) * 2009-04-15 2015-11-26 삼성전자주식회사 Non-volatile semiconductor memory controller for processing one request first before completing another request Memory system having the same and Method there-of
TWI399643B (en) 2009-12-31 2013-06-21 Phison Electronics Corp Flash memory storage system and controller and data writing method thereof
US8402203B2 (en) * 2009-12-31 2013-03-19 Seagate Technology Llc Systems and methods for storing data in a multi-level cell solid state storage device
JP2011198433A (en) * 2010-03-23 2011-10-06 Toshiba Corp Memory system
KR20120002760A (en) * 2010-07-01 2012-01-09 삼성전자주식회사 Data recording method and data recoding device for improving operation reliability of nand flash memory
CN102298555B (en) * 2011-08-22 2016-04-27 宜兴市华星特种陶瓷科技有限公司 Based on the modularization flash management system of NAND technology
TWI454911B (en) * 2011-10-12 2014-10-01 Phison Electronics Corp Data writing method, memory controller and memory storage apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956473A (en) * 1996-11-25 1999-09-21 Macronix International Co., Ltd. Method and system for managing a flash memory mass storage system
US20050204187A1 (en) * 2004-03-11 2005-09-15 Lee Charles C. System and method for managing blocks in flash memory
US20110161564A1 (en) * 2009-12-30 2011-06-30 Phison Electronics Corp. Block management and data writing method, and flash memory storage system and controller using the same

Also Published As

Publication number Publication date
TWI514260B (en) 2015-12-21
CN103425595B (en) 2017-03-01
US9223691B2 (en) 2015-12-29
US20130311705A1 (en) 2013-11-21
CN103425599A (en) 2013-12-04
US20130311701A1 (en) 2013-11-21
TWI590150B (en) 2017-07-01
TWI489373B (en) 2015-06-21
TW201349097A (en) 2013-12-01
US20130311703A1 (en) 2013-11-21
TW201349096A (en) 2013-12-01
US20130311704A1 (en) 2013-11-21
TW201349098A (en) 2013-12-01
CN103425597A (en) 2013-12-04
US20130311702A1 (en) 2013-11-21
CN103425588B (en) 2017-03-01
CN103425597B (en) 2016-04-06
CN103425588A (en) 2013-12-04
CN103425598A (en) 2013-12-04
CN103425598B (en) 2017-04-19
CN103425595A (en) 2013-12-04
US20130311698A1 (en) 2013-11-21
TW201349099A (en) 2013-12-01
TW201349101A (en) 2013-12-01
US9600408B2 (en) 2017-03-21
TW201349095A (en) 2013-12-01
CN103425596A (en) 2013-12-04
US9104549B2 (en) 2015-08-11
US9116792B2 (en) 2015-08-25

Similar Documents

Publication Publication Date Title
US9075740B2 (en) Memory system
US10754769B2 (en) Memory system having persistent garbage collection
JP6568387B2 (en) Storage controller and storage device
KR102042889B1 (en) Detection of read disturbances on non-volatile memories through counting of read accesses within divisions of the memory
US9176864B2 (en) Non-volatile memory and method having block management with hot/cold data sorting
US20180260317A1 (en) Method for managing the copying and storing of data in garbage collection, memory storage device and memory control circuit unit using the same
CN103425595B (en) Data memory device and the block management method of flash memory
US10732855B2 (en) Storage system having a host that manages physical data locations of a storage device
US9141528B2 (en) Tracking and handling of super-hot data in non-volatile memory systems
US10296453B2 (en) Memory controller, non-volatile memory system, and method of operating the same
US9021190B2 (en) Memory system
JP2014116031A (en) Electronic system with memory device
TWI463315B (en) Data storage apparatus and method for data storage
TWI437439B (en) Method for performing block management using dynamic threshold, and associated memory device and controller thereof
US8244960B2 (en) Non-volatile memory and method with write cache partition management methods
US8656256B2 (en) Apparatus and method for multi-mode operation of a flash memory device
US9021185B2 (en) Memory controller and methods for enhancing write performance of a flash device
US8094500B2 (en) Non-volatile memory and method with write cache partitioning
US7797481B2 (en) Method and apparatus for flash memory wear-leveling using logical groups
US9448868B2 (en) Data storing method, memory control circuit unit and memory storage apparatus
US8296498B2 (en) Method and system for virtual fast access non-volatile RAM
US8700840B2 (en) Nonvolatile memory with write cache having flush/eviction methods
KR101907059B1 (en) Method for block management for non-volatile memory device and system for the same
TWI393140B (en) Methods of storing data in a non-volatile memory
US7552272B2 (en) Automated wear leveling in non-volatile storage systems