TWI456721B - 導線架及其製造方法及受光發光裝置 - Google Patents

導線架及其製造方法及受光發光裝置 Download PDF

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Publication number
TWI456721B
TWI456721B TW097146604A TW97146604A TWI456721B TW I456721 B TWI456721 B TW I456721B TW 097146604 A TW097146604 A TW 097146604A TW 97146604 A TW97146604 A TW 97146604A TW I456721 B TWI456721 B TW I456721B
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Taiwan
Prior art keywords
reflective layer
light
layer
base material
lead frame
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TW097146604A
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English (en)
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TW200939440A (en
Inventor
Tadashi Kawanobe
Yuichi Ohnuma
Mamoru Mita
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Sh Prec Co Ltd
Mamoru Mita
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Publication of TW200939440A publication Critical patent/TW200939440A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)

Claims (8)

  1. 一種導線架，其特徵在於，該導線架具有：基體材料；反射層，係形成在該基體材料的一部分上並含有Ag，而對規定波長的光顯示規定的反射率；以及特性維持層，係覆蓋該反射層，且設置在該反射層上及未設有該反射層之該基體材料上，藉由將該反射層由外部隔絕而維持對該反射層之該規定波長的光顯示規定的反射率的特性，且具有透過該規定之波長之光之厚度為0.0001μ m~0.05μ m而形成的Au薄膜。
  2. 如申請專利範圍第1項所述的導線架，其中，該特性維持層係防止該反射層的該反射率的降低之同時，能透過由外部來之被該反射層反射之所述光。
  3. 一種發光裝置，具有導線架及發光元件，其中該導線架含有：基體材料；反射層，係形成在該基體材料之一部份上並含有Ag，而對規定波長的光顯示規定之反射率；以及特性維持層，係覆蓋該反射層，且設置在該反射層上以及未設有該反射層之該基體材料上，藉由將反射層由外部隔絶而維持對該反射層之該規定波長的光顯示規定的反射率之特性，且具有透過該規定之波長而形成的Au薄膜；其中該發光元件係搭載在該特性維持層上；該特性維持層係在將該發光元件搭載在該導線架之步驟，藉由以構成該反射層之Ag以及構成該Au薄膜之Au之相互擴散之合金化，而形成與該反射層一體化的厚度者。
  4. 一種導線架，係搭載半導體發光元件，係包含有： 基體材料；反射層，係形成在該基體材料之一部份上並含有Ag，而對規定波長的光顯示規定之反射率；以及特性維持層，係覆蓋該反射層，且設置在該反射層上及未設有該反射層之該基體材料上，藉由將反射層由外部隔絶而維持對該反射層之該規定波長的光顯示之特性，且具有透過該規定之波長而形成的Au薄膜；其中該特性維持層包含該Au薄膜以及在該Au薄膜與該反射層之間形成的合金層。
  5. 如申請專利範圍第1項或第2項所述之導線架，其中該特性維持層具有：與半導體元件接觸之元件搭載區域以及在該元件搭載區域外側形成的外部區域；該元件搭載區域係與該反射層上之一部份對應而形成者。
  6. 如申請專利範圍第5項所述之導線架，其中該特性維持層係該搭載區域與該外部區域形成為一體者。
  7. 一種導線架之製造方法，具有形成反射層之步驟及形成特性維持層之步驟，該形成反射層之步驟，係形成反射層，該反射層係形成在一基體材料之一部份上並含有Ag，而對規定波長的光顯示規定的反射率；該形成特性維持層之步驟，係形成特性維持層，該特性維持層係覆蓋該反射層，且設置在該反射層上及未設有該反射層之該 基體材料上，藉由將該反射層由外部隔絶而維持對該反射層之該規定波長的光顯示規定的反射率的特性，且具有透過該規定波長的光之厚度為0.0001μm~0.05μm而形成的Au薄膜。
  8. 一種發光裝置，具備有：半導體發光元件搭載用導線架、發光元件以及密封部件；其中該半導體發光元件搭載用導線架含有：基體材料；反射層，係形成在該基體材料之一部份上並含有Ag，而對規定波長的光顯示規定的反射率；以及特性維持層，係覆蓋該反射層，且設置在該反射層上以及未設有該反射層之該基體材料上，藉由將該反射層由外部隔絶而維持對該反射層之該規定之波長的光顯示規定的反射率之特性，且具有透過該規定波長的光之厚度為0.0001μm~0.05μm而形成的Au薄膜；其中該發光元件係搭載於該元件搭載區域；該密封部件係密封該發光元件。
TW097146604A 2007-12-03 2008-12-01 導線架及其製造方法及受光發光裝置 TWI456721B (zh)

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JP2007311975A JP4758976B2 (ja) 2007-12-03 2007-12-03 半導体発光素子搭載用リードフレーム及びその製造方法並びに発光装置

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KR20090057915A (ko) 2009-06-08
CN101452904A (zh) 2009-06-10
TW200939440A (en) 2009-09-16
JP2009135355A (ja) 2009-06-18
US20090141498A1 (en) 2009-06-04
KR101457489B1 (ko) 2014-11-07
US7888697B2 (en) 2011-02-15
CN101452904B (zh) 2013-05-08
JP4758976B2 (ja) 2011-08-31

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