TWI453837B - Semiconductor package with nonconductive layer and manufacturing method thereof - Google Patents

Description

Semiconductor package having non-conductive layer and method of manufacturing the same

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package in which the electrical contacts are completely covered and a method of fabricating the same.

A conventional semiconductor structure includes a substrate, a plurality of electrical contacts, and a protective layer. The protective layer covers a portion of the electrical contacts such that the exposed portions of the electrical contacts are electrically contacted to an external circuit. In order to increase the area of electrical contact, the exposed portion of the electrical contact usually includes the end face and most of the side faces, that is, the electrical contacts are almost entirely exposed to the atmosphere.

However, the exposed parts of the electrical contacts are directly affected by the atmospheric environment. For example, after the semiconductor structure is fabricated, it is usually placed in the inventory for a long period of time, so that the exposed electrical contacts in the semiconductor structure are easily oxidized.

In addition, the material of the conventional electrical contact is gold (Au). Although gold has good oxidation resistance, the price of the semiconductor structure cannot be lowered because the price of gold is too expensive.

The present invention relates to a semiconductor package and a method of fabricating the same, in which the electrical contacts of the semiconductor package are completely covered without being exposed, in which case the electrical contacts can be made of materials having low or even no anti-oxidation effects. It can reduce the manufacturing cost of the semiconductor package.

According to an embodiment of the present invention, a method of fabricating a semiconductor package is provided. The manufacturing method includes the following steps. Providing a substrate comprising a plurality of wafers; forming a plurality of conductive pillars adjacent to the active surfaces of the wafers; forming a non-conductive layer completely covering the conductive pillars; and singulating the substrates.

In accordance with another embodiment of the present invention, a semiconductor package is presented. The semiconductor package includes a wafer, a plurality of conductive pillars, and a non-conductive layer. The wafer has an active surface. The conductive posts are disposed adjacent to the active surface of the wafer. The non-conductive layer covers the active surface and completely covers the conductive pillars.

In accordance with yet another embodiment of the present invention, a semiconductor package is presented. The semiconductor package includes a wafer, a plurality of conductive pillars, a non-conductive layer, and a cladding layer. The wafer has an active surface. The conductive pillars are disposed adjacent to the active surface of the wafer, and each of the conductive pillars has an end surface and a side surface. The non-conductive layer covers the active surface and covers the sides of the conductive pillars to expose the end faces of the conductive pillars. The cladding covers the end faces of the respective conductive columns.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Referring to FIG. 1A, a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention is shown. A semiconductor package 100 includes a die 110, a plurality of conductive pillars 112, and a nonconductive layer 120.

Wafer 110 has an active surface 110u. The conductive pillars 112 are disposed adjacent to the active surface 110u of the wafer 110, and the material thereof includes copper (Cu) or aluminum (Al). The conductive post 112 acts as an input/output (I/O) contact.

The non-conductive layer 120 is disposed adjacent to the active surface 110u of the wafer 110 and completely encases the conductive pillars 112 and covers the active surface 110u. In this embodiment, the non-conductive layer 120 directly contacts and completely covers the side surface 112s and the end surface 112u of the conductive pillar 112. The side 120s of the non-conductive layer 120 is aligned with the side 110s of the wafer 110, for example, coplanar. The material of the non-conductive layer 120 may be, for example, a thermosetting resin having a B-stage characteristic.

The non-conductive layer 120 having the B-stage characteristics can be softened by heating, and can also swell in the liquid, but cannot be completely dissolved and melted. In addition, its appearance is semi-solid (for example, jelly-like colloid), with a certain degree of stability does not easily adhere to other objects, but has not yet reached a fully solidified phase (that is, phase C). When the semiconductor package 100 is mounted to an external component by surface mount technology (SMT), the non-conductive layer 120 can be extruded to expose the surface of the conductive pillar 112 to electrically connect the conductive pillar to the external component (described in detail later). .

The color of the non-conductive layer 120 is translucent, and an element covered by the non-conductive layer 120, such as the conductive pillars 112, can be optically detected from above. This facilitates the positioning of the wafer 110 during the singulation process.

Since the non-conductive layer 120 completely covers the conductive pillars 112, corrosion and oxidation of the conductive pillars can be prevented, and electron migration between the adjacent two conductive pillars 112 can also be prevented during the operation of the semiconductor package 100.

Referring to Fig. 1B, an enlarged schematic view of a portion 1B' in Fig. 1A is shown. The wafer 110 further includes at least one pad 116 and a passvation layer 113. A pad 116 is formed on the active surface 110u of the wafer 110. The protective layer 113 covers the pad 116 and has at least one opening 113a, and the pad 116 is exposed from the corresponding opening 113a. A polyimine layer (PI layer) 114 is selectively formed on the active surface 110u. The polyimide layer 114 covers the protective layer 113 and has at least one opening 114a, and the pads 116 are exposed from the corresponding openings 113a and 114a. An under bump metallurgy (UBM) 115 is formed in the corresponding closed cells 113a and 114a and electrically contacts the pads 116 through the openings 113a and 114a. The material of the bottom bump metal 115 may be selected from the group consisting of titanium, copper, tungsten, and combinations thereof. For example, in one embodiment, the bottom bump metal 115 includes a copper layer and a titanium layer; or, the bottom bump metal 115 may include a titanium tungsten oxide layer and a copper layer. A conductive pillar 112 is formed on the bottom bump metal 115. The side 112s of the conductive post 112 are substantially aligned with the side 115s of the bottom bump metal 115, such as being coplanar.

Please refer to FIGS. 2A-2E for a manufacturing flow diagram of a semiconductor package in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a substrate 111 is provided, which is, for example, a wafer having at least one plurality of wafers 110. A plurality of conductive pillars 112 are formed, wherein the conductive pillars 112 are disposed adjacent to the active surface 110u of the wafer 110. The method of forming the conductive pillars 112 can be, for example, electroplating, sputtering, or other metal patterning methods.

As shown in FIG. 2B, for example, the grinding method can be used to thin the substrate 111 from the back surface 111b of the substrate 111 (the back surface 111b is shown in FIG. 2A). Prior to thinning, an abrasive tape (not shown) may be attached to the opposite side of the thinned surface, for example, attached to the active surface 110u. In this way, the substrate 111 can be firmly adhered to a grinding stage through the abrasive tape, so that the substrate 111 does not arbitrarily shake during the grinding process. Further, in the case where the thickness of the substrate 111 is appropriate, the thinning step may be omitted.

As shown in FIG. 2C, the conductive pillars 112 may be planarized by, for example, mechanical grinding or chemical polishing, such that the end faces 112u of the conductive pillars 112 are substantially aligned, for example, coplanar. In the case where the semiconductor package 100 is mounted to an external component using, for example, an anisotropic conductive paste, since the anisotropic conductive paste electrically connects the conductive pillars 112 of the semiconductor package 100 to external components by using conductive particles having substantially the same size, any two The tolerance of the height difference of the conductive pillars is small, and it is preferable that the height difference of any two of the conductive pillars 112 in the single wafer 110 is less than 2 μm, and the flatness of the end surface 112u of the single conductive pillar is less than 2 μm. In addition, if the flatness can be controlled during the formation of the conductive pillar process, the planarization step can also be omitted.

As shown in FIG. 2D, the non-conductive layer 120 is formed to completely cover the conductive pillars 112. The non-conductive layer 120 can be formed using, for example, a Non-Conductive Paste (NCP) or a Non-Conductive Film (NCF). When a non-conductive paste is used, it may be applied to the surface of the substrate 111 by, for example, spinning, spraying, or roller coating, and then added to be matured to convert the non-conductive paste to the B-stage. Non-conductive layer 120. When a non-conductive film is used, the non-conductive layer 120 may be formed on the surface of the substrate 111 by, for example, lamination.

As shown in FIG. 2E, the substrate 111 is singulating (the substrate 111 is shown in FIG. 2D). For example, the substrate 111 and the non-conductive layer 120 may be diced using, for example, a laser or a tool to form at least one semiconductor package 100. The semiconductor package 100 is, for example, a drive wafer. Since the conductive pillars 112 are covered by the non-conductive layer 120, corrosion and oxidation can be avoided.

In summary, the conductive pillars 112 of the semiconductor package 100 can be completely protected by the non-conductive layer 120 before the semiconductor package 100 is bonded to the external components. In addition, when the semiconductor package 100 needs to be bonded to an external substrate, the semiconductor package 100 can be easily bonded to an external component by transforming the properties of the non-conductive layer 120. The process of bonding the semiconductor package 100 to an external component is further described below.

Please refer to FIGS. 3A to 3C , which are schematic diagrams showing the process of mounting the semiconductor package of FIG. 1A to an external component. A glass substrate in which the semiconductor package 100 is bonded to a display panel will be described as an example.

As shown in FIG. 3A, in a COG (Chip-on-Glass) process such as a flat panel display device, a glass substrate 140 is provided, wherein the glass substrate 140 includes at least one contact 141 disposed on a surface thereof, and a material of the contact 141. For example, it is Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The anisotropic conductive paste 130 is disposed on the surface of the glass substrate 140 and covers the contact 141. The anisotropic conductive paste 130 includes a plurality of conductive particles 131. Then, the semiconductor package 100 is adsorbed by suction (not shown), for example, an adsorption semiconductor package. The back side of 100 faces the anisotropic conductive paste 130 with a non-conductive layer 120.

As shown in FIG. 3B, heat H and pressure P are applied to the back surface of the semiconductor package 100 to cause the anisotropic conductive paste 130 to be pressed against the non-conductive layer 120. Since the non-conductive layer 120 can be softened by heating in a B-stage characteristic, and temporarily converted to the A stage after being heated, that is, in an early stage of the reaction of the thermosetting resin, the material can still be melted and dissolved in a solvent or a fluid, and its appearance is liquid. . The non-conductive layer 120 transformed to the A stage has good plasticity, and under the action of the pressure P, it can be redistributed so that the conductive particles 131 can be easily squeezed out of the non-conductive layer 120 in the A-stage and then contacted with the conductive column. 112.

As shown in FIG. 3C, after the conductive particles 131 are squeezed out of the non-conductive layer 120 in the A-stage, the conductive particles 131 can be substantially and electrically contacted to the conductive pillars 112 to electrically connect the conductive pillars 112. And contact 141. The heating is then continued until the non-conductive layer 120 is fully cured to the C stage, that is, the final stage of the thermosetting resin reaction, the material cannot be melted and dissolved, and its appearance assumes a solid state.

In the case where the end faces 112u of the conductive pillars 112 are substantially coplanar, the spacing between the conductive pillars 112 and the contacts 141 is substantially equal, so that the conductive particles 131 located therebetween are substantially compressed by the same amount, thereby ensuring each electrical connection. Both maintain a certain quality, which allows the process to be stably controlled and the electrical quality of the semiconductor package 100 and the glass substrate 140 to be good.

Although the above description is based on the application of the semiconductor package 100 to the display panel field, the application of the semiconductor package 100 of the embodiment of the present invention is not limited to the display panel, and can be applied to any field in which the semiconductor package 100 is required to be used.

Referring to FIG. 4, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown. The semiconductor package 200 includes a wafer 110, a plurality of conductive pillars 112, a non-conductive layer 120, and a cladding layer. The non-conductive layer 120 covers the active surface 110u and covers the side 112s of each of the conductive pillars 112, and exposes the end surface 112u of each of the conductive pillars 112. The cladding layer is, for example, an oxidation resistant conductive layer 250 that covers the end face 112u of the conductive pillar 112. Since the conductive pillars 112 are covered by the non-conductive layer 120 and the conductive layer 250, corrosion and oxidation can be avoided.

Please refer to FIGS. 5A to 5C for a manufacturing flow chart of the semiconductor package of FIG. 4.

As shown in FIG. 5A, after the conductive pillars 112 are formed (as shown in FIG. 2A) and the non-conductive layer 120 is formed to cover the conductive pillars 112 (as shown in FIG. 2D), for example, mechanical grinding or chemical grinding may be employed. In a manner, the non-conductive layer 120 and the conductive pillars 112 are planarized such that the upper surface 120u of the non-conductive layer 120 and the end surface 112u of each of the conductive pillars 112 are substantially aligned, for example, coplanar.

In this embodiment, the planarization step of FIG. 2C may be performed after the non-conductive layer 120 covers the conductive pillars 112; or, after the conductive pillars 112 are formed, a planarization step may be performed, and the conductive pillars are covered by the non-conductive layer 120. After 112, the planarization step can be performed again.

Moreover, in an embodiment, the conductive pillars 112 may not be ground during the planarization of the non-conductive layer 120. For example, in the process of planarizing the non-conductive layer 120, as long as the end surface 112u of the conductive pillar 112 is exposed from the non-conductive layer 120, the planarization action can be stopped, so that the conductive pillar 112 or the grinding to a small amount can be omitted. Conductive column 112.

As shown in FIG. 5B, the conductive layer 250 is formed to cover the end faces 112u of the respective conductive pillars 112. Preferably, but not limited to, the conductive layer 250 is an oxidation resistant layer. The conductive layer 250 is, for example, a surface finish, and the material thereof may be selected from the group consisting of gold (Au), palladium (Pd), tin (Sn), silver (Ag), and combinations thereof. In another embodiment, the conductive layer 250 can also be an Organic Solderability Preservative (OSP) or a plasma treated layer.

During the formation of the conductive layer 250, chemical vapor deposition, electroless plating, electrolytic plating, printing, spin coating, spray coating, sputtering, or vacuum deposition may be utilized. form. In another embodiment, the conductive layer 250 can be selectively formed by a patterning method, such as photolithography, chemical etching, laser drilling, or mechanical drilling. Mechanical drilling.

As shown in FIG. 5C, the substrate 111 is singulated (the substrate 111 is shown in FIG. 5B). For example, the substrate 111 and the non-conductive layer 120 may be diced, for example, by a laser or a cutter, to form at least one semiconductor package 200. The semiconductor package 200 is, for example, a drive wafer. Since the conductive pillars 112 are covered by the non-conductive layer 120 and the conductive layer 250, corrosion and oxidation can be avoided.

Referring to FIG. 6, a cross-sectional view of a semiconductor package in accordance with still another embodiment of the present invention is shown. The semiconductor package 300 includes a wafer 110, a plurality of conductive pillars 112, a non-conductive layer 120, and a cladding layer. The cladding layer is, for example, an oxidation resistant conductive layer 350. In this embodiment, the conductive layer 350 completely covers the conductive pillars 112, wherein the non-conductive layer 120 completely covers the conductive layer 350. Since the conductive pillars 112 are covered by the conductive layer 250, corrosion and oxidation can be avoided.

Please refer to FIGS. 7A-7C for a manufacturing flow diagram of the semiconductor package of FIG. 6.

As shown in FIG. 7A, the conductive layer 350 is formed to completely cover the respective conductive pillars 112. The material and formation method of the conductive layer 350 of FIG. 7A are similar to those of the conductive layer 250, and thus will not be described again.

The conductive layer 350 covers the side 112s of the conductive pillars 112. This prevents the semiconductor package 300 (shown in FIG. 7C) from undergoing electron transfer between adjacent two conductive pillars 112 during operation.

As shown in FIG. 7B, the non-conductive layer 120 is formed to completely cover the conductive pillars 112 and the conductive layer 350.

As shown in Fig. 7C, the singulated substrate 111 (the substrate 111 is shown in Fig. 7B). For example, the substrate 111 and the non-conductive layer 120 may be diced using, for example, a laser or a tool to form at least one semiconductor package 300.

In one embodiment, prior to the formation of the conductive layer 350 of FIG. 7A, the conductive pillars 112 may be planarized such that each of the conductive pillars 112 forms a planarized upper surface. After planarization, the conductive layer 350 forms a planarized upper surface 350u, and the planarized upper surface 350u of each conductive layer 350 is aligned in real values, for example, coplanar; then, the non-conductive layer 120 is formed to completely cover the planarized conductive Layer 350; Then, the substrate 111 and the non-conductive layer 120 are diced to form at least one semiconductor package.

Referring to FIG. 8, a cross-sectional view of a semiconductor package in accordance with still another embodiment of the present invention is shown. The semiconductor package 400 includes a wafer 110, a plurality of conductive pillars 112, a non-conductive layer 120, and a cladding layer. The cladding layer is, for example, an oxidation resistant conductive layer 350. The conductive layer 350 covers the side 112s of each of the conductive pillars 112, and the non-conductive layer 120 directly contacts and completely covers the end surface 112u of the conductive pillar 112. Since the conductive pillars 112 are covered by the non-conductive layer 120 and the conductive layer 350, corrosion and oxidation can be avoided.

Please refer to FIGS. 9A to 9C for a manufacturing flow chart of the semiconductor package of FIG. 8.

As shown in FIG. 9A, after the conductive layer 350 of FIG. 9A is formed, the conductive layer 350 and the conductive pillars 112 may be planarized such that the upper surface 350u of the conductive layer 350 and the end surface 112u of the conductive pillar 112 are substantially aligned, for example, Coplanar.

In another embodiment, the conductive layer 350 of FIG. 9A may also be replaced with an insulating layer such as parylene. The p-xylene layer can be formed, for example, by chemical vapor deposition (CVD). Further, the cladding layer covering the conductive pillars 112 in this embodiment (FIG. 9A) may be a conductive layer or an insulating layer covering the side 112s or the end surface 112u of the conductive pillars 112.

As shown in FIG. 9B, the non-conductive layer 120 is formed to completely cover the planarized conductive layer 350 and the conductive pillars 112.

As shown in Fig. 9C, the substrate 111 is singulated (the substrate 111 is shown in Fig. 9B). For example, the substrate 111 and the non-conductive layer 120 may be diced using, for example, a laser or a tool to form at least one semiconductor package 400.

In summary, the conductive pillars 112 may be covered by at least one of the non-conductive layer 120 and a conductive layer (eg, the conductive layer 250 or 350). For example, the non-conductive layer 120 may completely cover at least a portion of the conductive pillars 112; or, the non-conductive layer 120 may indirectly cover at least a portion of the conductive pillars 112 via the conductive layer. Alternatively, the conductive layer can selectively coat at least a portion of the conductive pillars 112.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400. . . Semiconductor package

110. . . Wafer

110u. . . Active surface

111. . . Substrate

111b. . . back

112. . . Conductive column

112u. . . End face

110s, 112s, 115s, 120s. . . side

113. . . The protective layer

113a, 114a‧‧‧ openings

114‧‧‧Polyimide layer

115‧‧‧Bottom bump metal

116‧‧‧ pads

120‧‧‧non-conductive layer

120u, 350u‧‧‧ upper surface

130‧‧‧ anisotropic conductive adhesive

131‧‧‧ conductive particles

140‧‧‧ glass substrate

141‧‧‧Contacts

250, 350‧‧‧ conductive layer

P‧‧‧ pressure

H‧‧‧heat

1A is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

Fig. 1B is an enlarged schematic view showing a portion 1B' in Fig. 1A.

2A to 2E are views showing a manufacturing process of a semiconductor package in accordance with an embodiment of the present invention.

3A to 3C are schematic views showing a process of mounting the semiconductor package of FIG. 1A to an external component.

4 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

5A to 5C are views showing a manufacturing flow chart of the semiconductor package of FIG. 4.

6 is a cross-sectional view of a semiconductor package in accordance with still another embodiment of the present invention.

7A to 7C are views showing a manufacturing flow chart of the semiconductor package of Fig. 6.

8 is a cross-sectional view of a semiconductor package in accordance with still another embodiment of the present invention.

9A to 9C are views showing a manufacturing flow chart of the semiconductor package of Fig. 8.

100. . . Semiconductor package

110. . . Wafer

110s, 112s, 120s. . . side

110u. . . Active surface

112. . . Conductive column

112u. . . End face

120. . . Non-conductive layer

Claims (20)

A method of fabricating a semiconductor package, comprising: providing a substrate, the substrate comprising a plurality of wafers; forming a plurality of conductive pillars adjacent to an active surface of each of the wafers; forming a non-conductive layer to completely encapsulate the conductive pillars; and singularizing Singulating the substrate. The manufacturing method according to claim 1, wherein the non-conductive layer is a thermosetting resin. The manufacturing method according to claim 2, wherein the thermosetting resin is in a B-stage. The manufacturing method of claim 1, wherein before the step of forming the non-conductive layer, the manufacturing method further comprises: planarizing the conductive pillars. The manufacturing method of claim 1, further comprising: planarizing the non-conductive layer to expose one end surface of each of the conductive pillars; and forming a conductive layer covering the end faces of each of the conductive pillars. The manufacturing method according to claim 5, wherein the material of the conductive layer is selected from the group consisting of gold, palladium, tin, silver, and combinations thereof. The manufacturing method of claim 1, further comprising: forming a conductive layer to completely cover each of the conductive pillars; in the step of forming the non-conductive layer, the non-conductive layer completely covering the conductive pillars and the Conductive layer. The manufacturing method described in claim 1 of the patent application further includes: A pair of parylene layers are formed to completely coat each of the conductive pillars. The manufacturing method of claim 1, wherein the wafer further has a back surface opposite to the active surface, and the manufacturing method further comprises: thinning the substrate from the back surface of the substrate. A semiconductor package comprising: a wafer having an active surface; a plurality of conductive pillars disposed adjacent to the active surface of the wafer; and a non-conductive layer completely encasing the conductive pillars. The semiconductor package of claim 10, wherein each of the conductive pillars has a side surface and an end surface, and the non-conductive layer directly contacts and completely covers the side surface and the end surface of each of the conductive pillars. The semiconductor package of claim 10, wherein the non-conductive layer is a thermosetting resin. The semiconductor package of claim 12, wherein the thermosetting resin is in the B stage. The semiconductor package of claim 10, further comprising: a conductive layer completely covering the conductive pillars, wherein the non-conductive layer completely covers the conductive layer. The semiconductor package of claim 10, wherein each of the conductive pillars has a side surface and an end surface, and further includes: a conductive layer covering the side of each of the conductive pillars, the non-conductive layer directly contacting and completely covering The end faces of each of the conductive columns are covered. The semiconductor package of claim 10, wherein The sides of the non-conductive layer are substantially aligned with the sides of the wafer. The semiconductor package of claim 10, wherein each of the conductive pillars has a side surface and an end surface, and further includes: a cladding layer covering the side of each of the conductive pillars, the non-conductive layer being in direct contact and completely The end surface of each of the conductive pillars is coated, wherein the material of the cladding layer comprises para-xylene. A semiconductor package comprising: a wafer having an active surface; a plurality of conductive pillars disposed adjacent to the active surface of the wafer, each of the conductive pillars having an end surface and a side surface; and a non-conductive layer covering each of the conductive pillars The side surface and the end surface of each of the conductive pillars are exposed; and a cladding layer covering the end surface of each of the conductive pillars. The semiconductor package of claim 18, wherein the cladding layer is an oxidation resistant conductive layer. The semiconductor package of claim 18, wherein the cladding layer is an oxidation resistant conductive layer, the cladding layer further covering the side surface of each of the conductive pillars.