TWI449479B - Method for manufacturing circuit - Google Patents

Method for manufacturing circuit Download PDF

Info

Publication number
TWI449479B
TWI449479B TW101140496A TW101140496A TWI449479B TW I449479 B TWI449479 B TW I449479B TW 101140496 A TW101140496 A TW 101140496A TW 101140496 A TW101140496 A TW 101140496A TW I449479 B TWI449479 B TW I449479B
Authority
TW
Taiwan
Prior art keywords
layer
protective layer
patterned protective
film layer
circuit
Prior art date
Application number
TW101140496A
Other languages
Chinese (zh)
Other versions
TW201419965A (en
Inventor
Li Chieh Hsu
Hsiao Wen Kuo
Wei Chuan Chen
Original Assignee
Rtr Tech Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rtr Tech Technology Co Ltd filed Critical Rtr Tech Technology Co Ltd
Priority to TW101140496A priority Critical patent/TWI449479B/en
Publication of TW201419965A publication Critical patent/TW201419965A/en
Application granted granted Critical
Publication of TWI449479B publication Critical patent/TWI449479B/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof

Description

線路之製造方法Line manufacturing method

本發明係有關於一種線路之製造方法,尤指一種藉由增加保護層或施壓於保護層而使之覆蓋導電層之手段,以避免蝕刻過程中的過度蝕刻,進而獲得精準線路圖案之線路製造方法。The invention relates to a method for manufacturing a circuit, in particular to a method for covering a conductive layer by adding a protective layer or pressing a protective layer to avoid excessive etching during etching, thereby obtaining a circuit of a precise circuit pattern. Production method.

目前資訊產品中,例如手機、電腦以及導航通訊裝置,對於印刷電路板或觸控面板的需求逐漸提高,相對地對面板之線路的精確度以及良率的要求也提高許多,以往傳統的電路板係採用印刷蝕刻阻劑之方法製造電路之線路及圖案,但由於電子產品之尺寸逐漸微小化與精細化,目前電路多採用壓膜或塗布光阻層,經過曝光顯影後,再以蝕刻作出電路板,而在前述之製造過程中,蝕刻過程係最不易控制且容易因過度浸蝕造成線路圖案精準度差或產生蝕刻斷線,降低良率。In current information products, such as mobile phones, computers, and navigation communication devices, the demand for printed circuit boards or touch panels is gradually increasing, and the accuracy and yield requirements of the lines of the panels are relatively improved. Conventional circuit boards have been used. The circuit and pattern of the circuit are manufactured by the method of printing etch resist. However, due to the gradual miniaturization and refinement of the electronic product, the current circuit uses a film or a photoresist layer, and after exposure and development, the circuit is made by etching. The board, while in the aforementioned manufacturing process, the etching process is the most difficult to control and is prone to poor accuracy of the line pattern or etch-off due to excessive etching, reducing the yield.

線路圖案化之製造過程包括於基板上形成導電薄膜層,再對基板上之導電薄膜層進行蝕刻。目前蝕刻的方式有兩種,分別為濕式蝕刻與乾式蝕刻,其中製造圖案化之習知手段係採用兩道蝕刻製程,而二次蝕刻的結果常會造成線路圖案化之線路尺寸較原預定為小,且破壞導電薄膜層之導電性。並且由於導電薄膜層大多為結晶型氧化物所組成,其蝕刻速率與穩定性不易控制,易造成蝕刻不均、產品良率降低以及增加製造成本等缺點。The circuit patterning manufacturing process includes forming a conductive thin film layer on the substrate, and etching the conductive thin film layer on the substrate. At present, there are two kinds of etching methods, namely wet etching and dry etching, wherein the conventional method of manufacturing patterning adopts two etching processes, and the result of secondary etching often causes the line patterning to be larger than originally planned. It is small and destroys the conductivity of the conductive film layer. Moreover, since the conductive thin film layer is mostly composed of a crystalline oxide, the etching rate and stability thereof are not easily controlled, and it is easy to cause defects such as uneven etching, a decrease in product yield, and an increase in manufacturing cost.

綜上所述,對於線路之製造過程中所產生之蝕刻缺點,目前未有一良好方案可控制前述線路圖案化之精準度,仍待進一步地研究並加以解決。In summary, there is currently no good solution for controlling the etching defects in the manufacturing process of the circuit, and the accuracy of the above-mentioned circuit patterning is still to be further studied and solved.

本發明揭露一種於導電薄膜層表面施加保護層之方法,使導電薄膜層在蝕刻過程中受到保護而可保持預定圖案化之線路,達到精準、高良率的圖案化線路,解決線路蝕刻過程中之過度側蝕的問題為本發明之目的。The invention discloses a method for applying a protective layer on the surface of a conductive thin film layer, so that the conductive thin film layer is protected during the etching process to maintain a predetermined patterning line, to achieve a precise and high-yield patterned circuit, and to solve the line etching process. The problem of excessive side erosion is the object of the present invention.

本發明係有關於一種線路之製造方法,其包括下列步驟:提供一基板,基板上依順序形成第一導電薄膜層以及第二導電薄膜層。於基板之第二導電薄膜層上形成第一圖案化保護層,蝕刻第二導電薄膜層至露出局部之第一導電薄膜層。形成第二圖案化保護層於第一圖案化保護層之上,並使第二圖案化保護層覆蓋第二導電薄膜層之側面。以及蝕刻第一導電薄膜層。The present invention relates to a method of manufacturing a wiring comprising the steps of: providing a substrate on which a first conductive thin film layer and a second conductive thin film layer are sequentially formed. Forming a first patterned protective layer on the second conductive thin film layer of the substrate, and etching the second conductive thin film layer to expose the local first conductive thin film layer. Forming a second patterned protective layer over the first patterned protective layer and covering the side of the second conductive thin film layer with the second patterned protective layer. And etching the first conductive film layer.

較佳為,其形成第二圖案化保護層於第一圖案化保護層上之方法,更包括:形成光阻層於第一圖案化保護層上,曝光光阻層,以及顯影光阻層。Preferably, the method for forming the second patterned protective layer on the first patterned protective layer further comprises: forming a photoresist layer on the first patterned protective layer, exposing the photoresist layer, and developing the photoresist layer.

較佳為,形成第一圖案化保護層及第二圖案化保護層之方法,可藉由光阻微影法、網版印刷法、噴塗法、旋轉塗布法或狹縫式塗布法來形成。Preferably, the method of forming the first patterned protective layer and the second patterned protective layer can be formed by a photoresist lithography method, a screen printing method, a spray coating method, a spin coating method, or a slit coating method.

較佳為,第一圖案化保護層及第二圖案化保護層可為乾膜光阻層、液態光阻層、聚合物層或油墨層。Preferably, the first patterned protective layer and the second patterned protective layer may be a dry film photoresist layer, a liquid photoresist layer, a polymer layer or an ink layer.

較佳為,第二圖案化保護層更覆蓋於第一導電薄膜層之部分表面、第二導電薄膜層之側面及第一圖案化保護層之表面。Preferably, the second patterned protective layer covers a portion of the surface of the first conductive film layer, the side of the second conductive film layer, and the surface of the first patterned protective layer.

較佳為,基板可為聚酯(PET)、聚醯胺(PE)、用於電路板(PCB)之樹脂、矽、玻璃、塑膠、金屬或陶瓷。Preferably, the substrate may be polyester (PET), polyamine (PE), resin for circuit boards (PCB), tantalum, glass, plastic, metal or ceramic.

另一方面,本發明進一步地提供另一種線路之製造方法,其包括下列步驟:提供一基板,基板上依順序形成第一導電薄膜層以及第二導電薄膜層。形成第一圖案化保護層於第二導電薄膜層之上,蝕刻第二導電薄膜層至露出局部至第一導電薄膜層。對第一圖案化保護層施加壓力,令第一圖案化保護層覆蓋於第二導電薄膜層之側面。以及對第一導電薄膜層進行蝕刻。In another aspect, the present invention further provides a method of fabricating another circuit comprising the steps of: providing a substrate on which a first conductive thin film layer and a second conductive thin film layer are sequentially formed. Forming a first patterned protective layer over the second conductive thin film layer, etching the second conductive thin film layer to expose a portion to the first conductive thin film layer. Apply pressure to the first patterned protective layer such that the first patterned protective layer covers the side of the second conductive thin film layer. And etching the first conductive film layer.

較佳為,第一圖案化保護層之表面積係大於第二導電薄膜層之表面積。Preferably, the surface area of the first patterned protective layer is greater than the surface area of the second conductive thin film layer.

較佳為,第一圖案化保護層可為乾膜光阻層、液態光阻層、聚合物層或油墨層。Preferably, the first patterned protective layer can be a dry film photoresist layer, a liquid photoresist layer, a polymer layer or an ink layer.

較佳為,對第一圖案化保護層施加壓力之方法可為熱壓法或輥壓法。Preferably, the method of applying pressure to the first patterned protective layer may be a hot pressing method or a rolling method.

較佳為,基板可為聚酯(PET)、聚醯胺(PE)、用於電路板之樹脂、矽、玻璃、塑膠、金屬或陶瓷。Preferably, the substrate may be polyester (PET), polyamine (PE), resin for circuit boards, tantalum, glass, plastic, metal or ceramic.

以下參考實施例及申請專利範圍而揭述本發明之例示具體實施例。在此所揭述的例示具體實施例之各種修改、調整或變化因所揭示而對熟悉本技術領域之人士為顯而易知。應了解,所有此種依據本發明之教示且經此教示而改進此技術的修改、調整或變化均視為在本發明之範圍與精髓內。Illustrative embodiments of the invention are described below with reference to the examples and claims. Various modifications, adaptations, and variations of the exemplary embodiments disclosed herein will be apparent to those skilled in the art. It is to be understood that all such modifications, adaptations, and variations of the present invention are intended to be within the scope and spirit of the invention.

本發明提供一種觸控面板之製造方法,其具體實施例之詳細步驟請參見圖1a至圖1d。The invention provides a method for manufacturing a touch panel. For detailed steps of the specific embodiment, please refer to FIG. 1a to FIG. 1d.

如圖1a所示,本發明提供一基板1,基板1之表面上依次塗布有第一導電薄膜層2以及第二導電薄膜層3,其中基板1例如可為聚酯(PET)、聚醯胺(PE)、用於電路板(PCB)之樹脂、矽、玻璃、強化玻璃、聚碳酸酯(PC)、聚甲基丙烯酸甲酯(PMMA)、塑膠、金屬或陶瓷,以及第一導電薄膜層2及第二導電薄膜層3。其中,第一導電薄膜層2例如可為金屬氧化物、氧化銦錫(indium tin oxide,ITO)、氧化銦鋅(indium zinc oxide,IZO)、氧化鎘錫(cadmium tin oxide,CTO)、氧化鋁鋅(aluminum zinc oxide,AZO)、氧化銦鋅錫(indium tin zinc oxide,ITZO)、氧化鋅(zinc oxide)、氧化鎘(cadmium oxide)、氧化鉿(hafnium oxide,HfO)、氧化銦鎵鋅(indium gallium zinc oxide,InGaZnO)、氧化銦鎵鋅鎂(indium gallium zinc magnesium oxide,InGaZnMgO)、氧化銦鎵鎂(indium gallium magnesium oxide,InGaMgO)或氧化銦鎵鋁(indium gallium aluminum oxide,InGaAlO)等所組成。第二導電薄膜層3例如可為至少一層導電金屬層,或者多層導電金屬層,其材質可為銅合金、鋁合金、金、銀、鋁、銅、鉬等導電金屬或導電合金。多層導電金屬層之結構,例如可為鉬層/鋁層/鉬層之堆疊結構,或者可為選自銅合金、鋁合金、金、銀、鋁、銅、鉬等導電金屬或導電合金之一種或多種材質而堆疊之多層導電金屬層結構。As shown in FIG. 1a, the present invention provides a substrate 1 on which a first conductive film layer 2 and a second conductive film layer 3 are sequentially coated, wherein the substrate 1 can be, for example, polyester (PET) or polyamine. (PE), resin for circuit board (PCB), tantalum, glass, tempered glass, polycarbonate (PC), polymethyl methacrylate (PMMA), plastic, metal or ceramic, and first conductive film layer 2 and a second conductive film layer 3. The first conductive thin film layer 2 may be, for example, a metal oxide, indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), or aluminum oxide. Aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide, cadmium oxide, hafnium oxide (HfO), indium gallium zinc oxide ( Indium gallium zinc oxide, InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO) or indium gallium aluminum oxide (InGaAlO) composition. The second conductive thin film layer 3 may be, for example, at least one conductive metal layer or a plurality of conductive metal layers, and the material thereof may be a conductive metal or a conductive alloy such as a copper alloy, an aluminum alloy, gold, silver, aluminum, copper, or molybdenum. The structure of the multi-layer conductive metal layer may be, for example, a stacked structure of a molybdenum layer/aluminum layer/molybdenum layer, or may be a conductive metal or a conductive alloy selected from the group consisting of copper alloy, aluminum alloy, gold, silver, aluminum, copper, molybdenum, and the like. A multi-layer conductive metal layer structure stacked with a plurality of materials.

接著,於基板1之第二導電薄膜層3表面形成第一圖案化保護層4,其中第一圖案化保護層4可為固態光阻、乾膜光阻、液態光阻劑或光阻膠等物質所組成。另外,第一圖案化保護層4可藉由熱壓乾膜光阻、網版印刷法、噴塗法、旋轉塗布法或狹縫式塗布法所形成。接著,以特定圖案的光罩6對第一圖案化保護層4進行曝光顯影以圖案化(請參見圖1b所示)。其中圖案化的製程大致是藉由微影製程(photolithography)而達成,微影製程包括光阻塗佈(photoresist coating)、軟烘烤(soft baking)、光罩對準(mask aligning)、曝光(exposure)、曝光後烘烤(post-exposure)、光阻顯影(developing photoresist)與硬烘烤(hard baking)等。繼之,對第二導電薄膜層3進行蝕刻,蝕刻至第一導電薄膜層2之局部表面露出為止。另外,於本發明之具體實施例中,第一圖案化保護層4可為任一具有保護被覆功能之塗布層所替代,例如可為金屬層、乾膜光阻層、液態光阻層、聚合物層、黏著劑層或油墨層。Next, a first patterned protective layer 4 is formed on the surface of the second conductive thin film layer 3 of the substrate 1. The first patterned protective layer 4 may be a solid photoresist, a dry film photoresist, a liquid photoresist or a photoresist. Composed of substances. In addition, the first patterned protective layer 4 can be formed by a hot press dry film photoresist, a screen printing method, a spray coating method, a spin coating method, or a slit coating method. Next, the first patterned protective layer 4 is subjected to exposure development to be patterned with a mask 6 of a specific pattern (see FIG. 1b). The patterning process is generally achieved by photolithography, which includes photoresist coating, soft baking, mask aligning, and exposure ( Exposure), post-exposure, developing photoresist, and hard baking. Next, the second conductive thin film layer 3 is etched and etched until the partial surface of the first conductive thin film layer 2 is exposed. In addition, in a specific embodiment of the present invention, the first patterned protective layer 4 may be replaced by any coating layer having a protective coating function, such as a metal layer, a dry film photoresist layer, a liquid photoresist layer, and a polymerization. a layer of matter, an adhesive layer or an ink layer.

請參見圖1c所示,對經蝕刻之第二導電薄膜層3以及第一圖案化保護層4塗布第二圖案化保護層5,令第二圖案化保護層5覆蓋於第一導電薄膜層2之部分表面、第二導電薄膜層3之側面,以及第一圖案化保護層4之表面,以保護已形成圖案化之第二導電薄膜層3。Referring to FIG. 1c, the second patterned protective layer 5 is coated on the etched second conductive film layer 3 and the first patterned protective layer 4, and the second patterned protective layer 5 is covered on the first conductive film layer 2. A portion of the surface, a side of the second conductive film layer 3, and a surface of the first patterned protective layer 4 to protect the patterned second conductive film layer 3.

如圖1d所示,對第一導電薄膜層2進行蝕刻,由於第二導電薄膜層3之側面,已為第二圖案化保護層所被覆,因此於第一導電薄膜層2之蝕刻過程中,第二導電薄膜層 3可維持預定之圖案化線路而不被侵蝕,待第一導電薄膜層2蝕刻完成後,去除第一圖案化保護層4以及第二圖案化保護層5,獲得一精準圖案化線路之基板1。As shown in FIG. 1d, the first conductive thin film layer 2 is etched. Since the side surface of the second conductive thin film layer 3 has been covered by the second patterned protective layer, during the etching process of the first conductive thin film layer 2, Second conductive film layer 3, the predetermined patterned circuit can be maintained without being eroded. After the first conductive thin film layer 2 is etched, the first patterned protective layer 4 and the second patterned protective layer 5 are removed to obtain a substrate 1 of a precise patterned circuit. .

進一步地,本發明更提供另一種線路之製造方法,其具體實施例之詳細步驟請參見圖2a至圖2e。Further, the present invention further provides a manufacturing method of another circuit. For detailed steps of the specific embodiment, please refer to FIG. 2a to FIG. 2e.

請參見圖2a所示,如前述之具有第一導電薄膜層2以及第二導電薄膜層3之基板1,藉由特定之光罩圖案形成第一圖案化保護層4於第二導電薄膜層3之表面,藉由曝光顯影,且蝕刻第一圖案化保護層4及第二導電薄膜層3予以圖案化,此道蝕刻至露出第一導電薄膜層2之表面為止。其中,上述之圖案化製程大致是藉由微影製程(photolithography)而達成,微影製程包括光阻塗佈(photoresist coating)、軟烘烤(soft baking)、光罩對準(mask aligning)、曝光(exposure)、曝光後烘烤(post-exposure)、光阻顯影(developing photoresist)與硬烘烤(hard baking)等。Referring to FIG. 2a, the substrate 1 having the first conductive film layer 2 and the second conductive film layer 3 is formed by forming a first patterned protective layer 4 on the second conductive film layer 3 by using a specific mask pattern. The surface is patterned by exposure and etching, and the first patterned protective layer 4 and the second conductive thin film layer 3 are patterned, and the etching is performed until the surface of the first conductive thin film layer 2 is exposed. Wherein, the above-mentioned patterning process is substantially achieved by photolithography, which includes photoresist coating, soft baking, mask aligning, Exposure, post-exposure, developing photoresist, and hard baking.

請參見圖2b所示,進一步地蝕刻第二導電薄膜層3,令第二導電薄膜層3至預定之尺寸大小,使第一圖案化保護層4之表面積大於第二導電薄膜層3之表面積。Referring to FIG. 2b, the second conductive thin film layer 3 is further etched to a predetermined size so that the surface area of the first patterned protective layer 4 is larger than the surface area of the second conductive thin film layer 3.

請參見圖2c所示,對第一圖案化保護層4施加壓力,例如藉由熱壓法或輥壓法進行,使第一圖案化保護層4向下方延展,進而被覆第二導電薄膜層3之側面,達到保護第二導電薄膜層3之功效。Referring to FIG. 2c, pressure is applied to the first patterned protective layer 4, for example, by hot pressing or rolling, so that the first patterned protective layer 4 is extended downward, and then the second conductive thin film layer 3 is coated. On the side, the effect of protecting the second conductive film layer 3 is achieved.

如圖2d所示,接著進行第二道蝕刻工法,對第一導電薄膜層2進行蝕刻,由於第二導電薄膜層3已獲得第一 圖案化保護層4覆蓋,因此於第一導電薄膜層2之蝕刻過程中,第二導電薄膜層3可保持預定之線路圖案。As shown in FIG. 2d, a second etching process is then performed to etch the first conductive thin film layer 2, since the second conductive thin film layer 3 has obtained the first The patterned protective layer 4 is covered, so that during the etching of the first conductive thin film layer 2, the second conductive thin film layer 3 can maintain a predetermined wiring pattern.

請參見圖2d及2e所示,待蝕刻且圖案化之第一導電薄膜層2完成蝕刻後,去除第一圖案化保護層4後,獲得精確之圖案化線路之基板1。Referring to FIGS. 2d and 2e, after the first conductive thin film layer 2 to be etched and patterned is etched, the first patterned protective layer 4 is removed, and the substrate 1 of the precise patterned circuit is obtained.

本發明之線路之製造方法具有連續性生產特性,且本發明之基板為具可撓性的基板,因此前述之該等步驟係均採用捲對捲(roll-to-roll)製程,以達到高效能、低成本之優點。其中,可撓式基板材質為低位相差材料,例如可為三醋酸纖維素(TAC)、聚甲基丙烯酸甲酯(PMMA)等,但不限於此。The manufacturing method of the circuit of the present invention has continuous production characteristics, and the substrate of the present invention is a flexible substrate, so the aforementioned steps are all performed by a roll-to-roll process to achieve high efficiency. The advantages of energy and low cost. The material of the flexible substrate is a low phase difference material, and may be, for example, cellulose triacetate (TAC) or polymethyl methacrylate (PMMA), but is not limited thereto.

藉由本發明之線路之製造方法,可有效改善線路因過度蝕刻而造成精確度低或導電性遭破壞等缺點,藉由兩道圖案化保護層或對圖案化保護層施加壓力令其被覆導電薄膜層之表面等手段,達到保護導電薄膜層之功效。By the manufacturing method of the circuit of the present invention, the defects of low precision or electrical conductivity caused by excessive etching can be effectively improved, and the conductive film is coated by applying pressure to the patterned protective layer or applying pressure to the patterned protective layer. The surface of the layer and the like achieve the effect of protecting the conductive film layer.

1‧‧‧基板1‧‧‧Substrate

2‧‧‧第一導電薄膜層2‧‧‧First conductive film layer

3‧‧‧第二導電薄膜層3‧‧‧Second conductive film layer

4‧‧‧第一圖案化保護層4‧‧‧First patterned protective layer

5‧‧‧第二圖案化保護層5‧‧‧Second patterned protective layer

6‧‧‧光罩6‧‧‧Photomask

圖1a 係本發明之第一圖案化保護層之示意圖。Figure 1a is a schematic illustration of a first patterned protective layer of the present invention.

圖1b 係本發明之蝕刻第二導電薄膜層示意圖。Figure 1b is a schematic view of the etched second conductive thin film layer of the present invention.

圖1c 係本發明之形成第二圖案化保護層之示意圖。Figure 1c is a schematic illustration of the formation of a second patterned protective layer of the present invention.

圖1d 係本發明之蝕刻具有第二圖案化保護層之第一導電薄膜層之示意圖。Figure 1d is a schematic illustration of the etching of a first conductive thin film layer having a second patterned protective layer of the present invention.

圖2a 係本發明之蝕刻第一圖案化保護層以及第二導電薄膜層之示意圖。2a is a schematic view of etching the first patterned protective layer and the second conductive thin film layer of the present invention.

圖2b 係蝕刻第二導電薄膜層之示意圖。Figure 2b is a schematic view of etching a second conductive thin film layer.

圖2c 係對第一圖案化保護層施加壓力被覆第二導電薄膜層之示意圖。2c is a schematic view showing pressure applied to the first patterned protective layer to coat the second conductive thin film layer.

圖2d 係對第一導電薄膜層進行蝕刻示意圖。Figure 2d is a schematic view showing etching of the first conductive film layer.

圖2e 係本發明蝕刻完成之基板的示意圖。Figure 2e is a schematic illustration of an etched substrate of the present invention.

1‧‧‧基板1‧‧‧Substrate

2‧‧‧第一導電薄膜層2‧‧‧First conductive film layer

3‧‧‧第二導電薄膜層3‧‧‧Second conductive film layer

4‧‧‧第一圖案化保護層4‧‧‧First patterned protective layer

5‧‧‧第二圖案化保護層5‧‧‧Second patterned protective layer

6‧‧‧光罩6‧‧‧Photomask

Claims (11)

一種線路之製造方法,其包括下列步驟:提供一基板,該基板上依順序形成一第一導電薄膜層以及一第二導電薄膜層;於該基板之該第二導電薄膜層上形成一第一圖案化保護層;蝕刻該第二導電薄膜層至露出局部之該第一導電薄膜層;形成一第二圖案化保護層於該第一圖案化保護層之上,並使該第二圖案化保護層覆蓋該第二導電薄膜層之側面;以及蝕刻該第一導電薄膜層。A method for manufacturing a circuit, comprising the steps of: providing a substrate on which a first conductive film layer and a second conductive film layer are sequentially formed; and forming a first on the second conductive film layer of the substrate Patterning a protective layer; etching the second conductive thin film layer to expose a portion of the first conductive thin film layer; forming a second patterned protective layer over the first patterned protective layer, and allowing the second patterned protection layer a layer covering a side of the second conductive film layer; and etching the first conductive film layer. 如申請專利範圍第1項之線路之製造方法,其中,形成該第二圖案化保護層於該第一圖案化保護層上之步驟,更包括:形成一光阻層於該第一圖案化保護層上;曝光該光阻層;以及顯影該光阻層。The method of manufacturing the circuit of the first aspect of the invention, wherein the step of forming the second patterned protective layer on the first patterned protective layer further comprises: forming a photoresist layer on the first patterned protection On the layer; exposing the photoresist layer; and developing the photoresist layer. 如申請專利範圍第1項之線路之製造方法,其中,形成該第一圖案化保護層及第二圖案化保護層可為以光阻微影法、網版印刷法、噴塗法、旋轉塗布法或狹縫式塗布法所形成。The method for manufacturing a circuit according to claim 1, wherein the first patterned protective layer and the second patterned protective layer are formed by photoresist lithography, screen printing, spray coating, and spin coating. Or formed by a slit coating method. 如申請專利範圍第1項之線路之製造方法,其中該第一圖案化保護層及該第二圖案化保護層可為乾膜光阻層、液態光阻層、聚合物層或油墨層。The method of manufacturing the circuit of claim 1, wherein the first patterned protective layer and the second patterned protective layer are a dry film photoresist layer, a liquid photoresist layer, a polymer layer or an ink layer. 如申請專利範圍第1項之線路之製造方法,其中該第二圖案化保護層係覆蓋於該第一導電薄膜層之部分表面、該第二導電薄膜層之側面及該第一圖案化保護層之表面。The method of manufacturing the circuit of claim 1, wherein the second patterned protective layer covers a portion of the surface of the first conductive film layer, a side of the second conductive film layer, and the first patterned protective layer. The surface. 如申請專利範圍第1至5項中任一項之線路之製造方法,其中該基板可為聚酯(PET)、聚醯胺(PE)、用於電路板(PCB)之樹脂、矽、玻璃、塑膠、金屬或陶瓷。The method of manufacturing a circuit according to any one of claims 1 to 5, wherein the substrate is a polyester (PET), a polyamide (PE), a resin for a circuit board (PCB), a crucible, and a glass. , plastic, metal or ceramic. 一種線路之製造方法,其包括下列步驟:提供一基板,該基板上依順序形成一第一導電薄膜層以及一第二導電薄膜層;形成一第一圖案化保護層於該第二導電薄膜層之上;蝕刻該第二導電薄膜層至露出局部至該第一導電薄膜層;對該第一圖案化保護層施加壓力,令該第一圖案化保護層覆蓋於該第二導電薄膜層之側面;以及對該第一導電薄膜層進行蝕刻。A method for manufacturing a circuit, comprising the steps of: providing a substrate on which a first conductive film layer and a second conductive film layer are sequentially formed; forming a first patterned protective layer on the second conductive film layer Etching the second conductive film layer to expose a portion to the first conductive film layer; applying pressure to the first patterned protective layer, so that the first patterned protective layer covers the side of the second conductive film layer And etching the first conductive film layer. 如申請專利範圍第7項之線路之製造方法,其中該第一圖案化保護層之表面積係大於該第二導電薄膜層之表面積。The method of manufacturing the circuit of claim 7, wherein the first patterned protective layer has a surface area greater than a surface area of the second conductive thin film layer. 如申請專利範圍第7項之線路之製造方法,其中該第一圖案化保護層可為乾膜光阻層、液態光阻層、聚合物層或油墨層。The method of manufacturing the circuit of claim 7, wherein the first patterned protective layer can be a dry film photoresist layer, a liquid photoresist layer, a polymer layer or an ink layer. 如申請專利範圍第7項之線路之製造方法,其中對該第一圖案化保護層施加壓力之方法可為熱壓法或輥壓法來執行。The method of manufacturing the circuit of claim 7, wherein the method of applying pressure to the first patterned protective layer is performed by a hot press method or a roll press method. 如申請專利範圍第7至10項中任一項之線路之製造方法,其中該基板可為聚酯(PET)、聚醯胺(PE)、用於電路板(PCB)之樹脂、矽、玻璃、塑膠、金屬或陶瓷。The method of manufacturing a circuit according to any one of claims 7 to 10, wherein the substrate is a polyester (PET), a polyamide (PE), a resin for a circuit board (PCB), a crucible, and a glass. , plastic, metal or ceramic.
TW101140496A 2012-11-01 2012-11-01 Method for manufacturing circuit TWI449479B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW101140496A TWI449479B (en) 2012-11-01 2012-11-01 Method for manufacturing circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101140496A TWI449479B (en) 2012-11-01 2012-11-01 Method for manufacturing circuit
CN201310495279.0A CN103811333A (en) 2012-11-01 2013-10-21 Line manufacturing method

Publications (2)

Publication Number Publication Date
TW201419965A TW201419965A (en) 2014-05-16
TWI449479B true TWI449479B (en) 2014-08-11

Family

ID=50707943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101140496A TWI449479B (en) 2012-11-01 2012-11-01 Method for manufacturing circuit

Country Status (2)

Country Link
CN (1) CN103811333A (en)
TW (1) TWI449479B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016070933A1 (en) * 2014-11-07 2016-05-12 Applied Materials, Inc. Layer system for use in a touch screen panel, method for manufacturing a layer system for use in a touch screen panel, and touch screen panel
CN104378923A (en) * 2014-11-14 2015-02-25 江门崇达电路技术有限公司 Printed circuit board etching method
CN104360443A (en) * 2014-11-14 2015-02-18 四川飞阳科技有限公司 Etching method
CN108966515B (en) * 2018-08-10 2021-02-26 鹤山市中富兴业电路有限公司 Printed circuit board etching factor 6.0 process
TWI708537B (en) * 2019-08-26 2020-10-21 健鼎科技股份有限公司 Method for producing circuit patterns
CN113064306A (en) * 2021-03-16 2021-07-02 昆山龙腾光电股份有限公司 Manufacturing method of substrate structure, substrate structure and display panel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201216799A (en) * 2010-10-14 2012-04-16 Young Fast Optoelectronics Co Manufacturing method of touch sensor pattern and signal conductor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100703985B1 (en) * 2006-02-17 2007-04-09 삼성전자주식회사 Method for fabricating semiconductor device
US7842558B2 (en) * 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
JP4308862B2 (en) * 2007-03-05 2009-08-05 日東電工株式会社 Wiring circuit board and manufacturing method thereof
CN101308809A (en) * 2007-05-17 2008-11-19 力晶半导体股份有限公司 Manufacture method of aluminum conductive wire
CN102088002B (en) * 2009-12-02 2013-12-04 旺宏电子股份有限公司 Method for manufacturing memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201216799A (en) * 2010-10-14 2012-04-16 Young Fast Optoelectronics Co Manufacturing method of touch sensor pattern and signal conductor

Also Published As

Publication number Publication date
TW201419965A (en) 2014-05-16
CN103811333A (en) 2014-05-21

Similar Documents

Publication Publication Date Title
TWI449479B (en) Method for manufacturing circuit
JP5486019B2 (en) Conductive pattern and manufacturing method thereof
JP6437574B2 (en) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE
JP2014027317A (en) Method of manufacturing printed circuit board
WO2014166150A1 (en) Touch panel and manufacturing method thereof and display device
US9551937B2 (en) Graphene sensor and method of fabricating the same and touch-sensitive display device
US20150029411A1 (en) Touch panel, conductive film and method for manufacturing the same
TWM586818U (en) Touch sensing panel
TW201712513A (en) Film touch sensor and method for manufacturing the same
TWI482223B (en) Method for manufacturing touch panel
EP2711972A1 (en) Method for manufacturing pattern structure
CN101998770A (en) Method for manufacturing etched film resistance circuit board manufacturing method
US8227175B2 (en) Method for smoothing printed circuit boards
CN108305881B (en) Array substrate, manufacturing method thereof, display panel and display device
CN107107603B (en) Method for manufacturing cliche for offset printing and cliche for offset printing
US20140096693A1 (en) Apparatus of forming pattern, method of manufacturing the same, and method of forming the same
KR100798738B1 (en) Method for fabricating fine pattern in semiconductor device
JP4808824B1 (en) Method for manufacturing pattern structure
CN105206621A (en) Pattern composition method, array substrate and display device
JP2010040424A (en) Method of manufacturing touch sensor
US20210200378A1 (en) Touch panel and manufacturing method thereof
WO2020147322A1 (en) Method for manufacturing conductive film, and conductive film
TWI619415B (en) Method for making printed circuit board by semi-additive method
JP2009117784A (en) Polymer film patterning method
KR101250422B1 (en) High Definition Printing Plate of Liquid Crystal Display and Method for Manufacture using the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees