TWI447897B - Lateral transient voltage suppressor for low-voltage application - Google Patents

Description

Transient transient voltage suppressor with low operating voltage

The present invention relates to a lateral transient voltage suppressor, and more particularly to a lateral operating voltage suppressor having a low operating voltage.

Since the components of the integrated circuit (IC) have been miniaturized to the nanometer size, they are easily damaged by the impact of electrostatic discharge (ESD), and some electronic products, such as notebook computers or mobile phones, are made lighter than before. Short, the ability to withstand ESD shocks is even lower. For these electronic products, if the protection is not protected by an appropriate ESD protection device, the electronic product is easily affected by the ESD, and the electronic product is restarted, and even the hardware is damaged and cannot be recovered. Currently, all electronic products are required to pass the ESD test requirements of the IEC 61000-4-2 standard. For ESD problems in electronic products, the use of Transient Voltage Suppressor (TVS) is a more effective solution to allow ESD energy to be quickly released through TVS, preventing electronic products from being damaged by ESD. The working principle of TVS is as shown in Fig. 1. On the printed circuit board (PCB), the transient voltage suppressor 10 is connected in parallel to protect the device 12. When the ESD condition occurs, the transient voltage suppressor 10 is triggered instantaneously. The transient voltage suppressor 10 can also provide a low resistance path for discharging the transient ESD current, allowing the energy of the ESD transient current to be released through the transient voltage suppressor 10.

For advanced interface applications such as Ethernet, Low Voltage Differential Signaling (LVDS), etc., the signal swing range or power supply voltage is less than 2.5 volts. 2 is a prior art lateral transient voltage suppressor having a Zener diode 14, wherein the turn-on voltage of the transient voltage suppressor depends on the breakdown voltage of the Zener diode 14. However, the Zener breakdown voltage of a conventional transient voltage suppressor is about 6-10 volts, which is higher than the breakdown voltage of the component to be protected. When an electrostatic discharge (ESD) event occurs, the component to be protected will collapse and be damaged before the transient voltage suppressor turns on. Therefore, the turn-on voltage of the transient voltage suppressor must be reduced to apply to applications less than 2.5 volts.

In the prior art, the way to reduce the breakdown voltage is to adjust the doping concentration of the p-n junction of the Zener diode 14. However, if the trim breakdown voltage is about 3 volts, a very large leakage current will occur due to the heavily doped concentration of the p-n junction. In Fig. 3, a Zener diode of Vcc and ground potential GND is replaced by a plurality of diodes 16 connected in series. The forward voltage of each diode 16 is about 0.7 volts, so when there are n diodes 16 connected in series, the turn-on voltage of the transient voltage suppressor is n x 0.7 volts. However, as can be seen from FIGS. 4 and 5, the P-type substrate 20 and each of the N-type well regions 22 constitute a parasitic PNP transistor 18, so that the more the number of transistors connected in series with each other, the parasitic PNP The higher the leakage current generated by the transistor. This phenomenon is the Darlington effect. In Figure 3, the turn-on voltage caused by the series connection of n diodes 16 is lower than n × 0.7 volts, and the maximum leakage current in the complementary MOS process is affected by the Darlington effect. Will also be produced.

Accordingly, the present invention has been made in view of the above problems, and proposes a lateral operating voltage suppressor with a low operating voltage to solve the problems caused by the prior art.

The main object of the present invention is to provide a lateral transient voltage suppressor which is connected to a substrate and uses a deep trench isolation structure to isolate each doped well region for low voltage operation applications and avoids extremely high Leakage current.

To achieve the above objective, the present invention provides a lateral operating voltage suppressor with a low operating voltage, comprising an N-type heavily doped substrate and at least two clamp diode structures, each clamping diode structure being horizontally disposed. In the N-type heavily doped substrate, and comprising a clamping well region in the N-type heavily doped substrate, a first and a second heavily doped region, and the first and second heavily doped regions are mutually phased Shaped. In addition, a plurality of deep trench isolation structures are located in the N-type heavily doped substrate, and the depth of each deep trench isolation structure is greater than the depth of the clamp well region to isolate each clamp well region.

For a better understanding and understanding of the structural features and the achievable effects of the present invention, please refer to the preferred embodiment and the detailed description.

Please refer to Fig. 6 and Fig. 7, and Fig. 7 is an equivalent circuit diagram of Fig. 6. The present invention comprises an N-type heavily doped substrate 24, at least two clamped diode structures 26 and a plurality of deep trench isolation structures 28 of dielectric material, wherein each clamped diode structure 26 is horizontally disposed at N The type is heavily doped in the substrate 24 and adjacent to each other. The N-type heavily doped substrate 24 is used to avoid the latch-up effect. In the first embodiment, the number of clamped diode structures 26 is exemplified by five, and the clamped diode structure 26 is a semiconductor structure of the diodes 30. Each of the clamped diode structures 26 further includes a clamp well region 32 disposed in the N-type heavily doped substrate 24, and a first and second heavily doped regions 34, 36 are located in the clamp well In area 32. In addition, in the semiconductor doping type, it is not N-type or P-type. The first and second heavily doped regions 34, 36 are mutually dissimilar, and each of the clamping well regions 32 is connected in series with each other through the first and second heavily doped regions 34, 36. In the first embodiment, the clamp well region 32, the first and second heavily doped regions 34, 36 are respectively exemplified by a P-type clamp well region, a P-type, and an N-type heavily doped region. The first clamp well zone 32 is considered the leftmost clamp well zone 32 and the last clamp well zone 32 is considered the rightmost clamp well zone 32. The first heavily doped region 34 of the first clamp well region 32 is connected to a high voltage Vcc, and the second heavily doped region 36 of the last clamp well region 32 is connected as a low voltage ground potential, so that all first, The second heavily doped regions 34, 36 are all biased. In addition, the N-type heavily doped substrate 24 is floating or connected to the voltage Vcc to avoid leakage current generation.

The deep trench isolation structure 28 is located in the N-type heavily doped substrate 24, and the depth of the deep trench isolation structure 28 is deeper than the depth of each clamp well region 32. A deep trench isolation structure 28 adjacent thereto is disposed adjacent to the adjacent clamp well region 32, such that the deep trench isolation structure 28 can isolate each clamp well region 32.

When the suppressor is biased, an electrostatic discharge (ESD) current flows through the clamp well region 32 in a lateral path, and the Darlington effect does not occur in the clamped diode structure 26. In general, when five diodes are connected in series, the turn-on voltage is approximately 3.5 volts, which is suitable for 2.5 volt applications. For lower operating voltages, such as 1.8 volts, the number of diodes 30 in series can be reduced. Therefore, the present invention can avoid extremely large leakage currents for applications with low operating voltages.

The first embodiment can also be displayed in another doping type. When the clamp well region 32 is an N-type clamp well region, the first and second heavily doped regions 34, 36 are respectively N-type, P-type heavily doped regions. In addition, the first heavily doped region 34 of the first clamp well region 32 is connected as a low voltage ground potential, and the second heavily doped region 36 of the last clamp well region 32 is connected to the high voltage Vcc to make all the first The second heavily doped regions 34, 36 are all biased.

The second embodiment will be described below. Please refer to FIG. 8 and FIG. 9. FIG. 9 is an equivalent circuit diagram of FIG. 8, and FIG. 9 is a multi-channel transient voltage suppressor. The second embodiment differs from the first embodiment in that the second embodiment has at least one diode series structure 38 disposed horizontally in the N-type heavily doped substrate 24 and adjacent to the clamped diode structure 26. In this example, the number of diode series structures 38 is exemplified by four. The diode series structure 38 is not only adjacent to the clamped diode structure 26, but also adjacent to each other. Each of the diode series structures 38 includes a first and second well regions 40, 46, and a third and fourth heavily doped regions 42, 44 are located in the first well region 40, a fifth and sixth The heavily doped regions 48, 50 are located in the second well region 46. In addition, a first diode 52 is formed by the first well region 40, the third and fourth heavily doped regions 42, 44, and a second diode 54 is formed by the second well region 46, fifth, and sixth. The heavily doped regions 48, 50 are formed.

The first well region 40 is located in the N-type heavily doped substrate 24, and the first well region 40 is of the same type as the clamp well region 32. The third and fourth heavily doped regions 42, 44, which are further located in the first well region 40, are mutually different. The third heavily doped region 42 is of the same type as the first well region 40, and the fourth heavily doped region 44 is of the same type as the second well region 46. In the second embodiment, the first well region 40, the third and fourth heavily doped regions 42, 44 are exemplified by a P-type well region, a P-type heavily doped region, and an N-type heavily doped region, respectively.

The second well region 46 located in the N-type heavily doped substrate 24 is adjacent to the first well region 40, and the fifth and sixth heavily doped regions 48, 50 are located in the second well region 46 and are mutually phased. The profiled, second well zone 46 is also distinct from the first well zone 40. The fifth heavily doped region 48 and the third heavily doped region 42 are of the same type, and the sixth heavily doped region 50 and the fourth heavily doped region 44 are of the same type, and the fourth heavily doped region 44 and the fifth heavily doped region are the same. 48 is mutually different, the first heavily doped region 34 is of the same type as the fifth heavily doped region 48, and the second heavily doped region 36 is of the same type as the sixth heavily doped region 50. In the second embodiment, the second well region 46, the fifth and sixth heavily doped regions 48, 50 are respectively exemplified by an N-type well region, a P-type heavily doped region, and an N-type heavily doped region. As described above, the first heavily doped region 34 is a P-type heavily doped region, the second heavily doped region 36 is an N-type heavily doped region, and the fourth and fifth heavily doped regions 44, 48 are all connected. To an input/output pin (I/O pin).

The first heavily doped region 34 of the first clamp well region 32 is connected to each of the sixth heavily doped regions 50 by a high voltage Vcc. The second heavily doped region 36 of the last clamp well region 32 is coupled to each of the third heavily doped regions 42 as a low voltage ground potential to bias all heavily doped regions. In addition, the N-type heavily doped substrate 24 is floating or connected to the voltage Vcc to avoid leakage current generation.

The deep trench isolation structure 28 is also deeper than the depths of the first and second well regions 40,46. A deep trench isolation structure 28 between the adjacent diode-series structures 38 is adjacent thereto. A deep trench isolation structure 28 is provided in the diode cascade structure 38 and its most adjacent clamp well region 32, the three being adjacent to one another. A deep trench isolation structure 28 is disposed between adjacent first and second well regions 40, 46, and the three are also adjacent to one another. Thus, the deep trench isolation structure 28 can isolate the clamp well regions 32, the first and second well regions 40, 46 and each of the diode series structures 38 adjacent to each other.

As in the first embodiment, when the suppressor is biased, the electrostatic discharge current flows through the clamp well region 32, the first and second well regions 40, 46 in a lateral path, and the Darlington effect does not occur at Clamped diode structure 26. Therefore, this suppressor can be applied to applications with low operating voltages.

The second embodiment can also be represented by another doping type. When the clamp well region 32 is an N-type clamp well region, the first and second heavily doped regions 34 and 36 are respectively N-type and P-type heavily doped regions, and the first and second well regions 40 and 46 respectively For the N-type and P-type well regions, the third and fourth heavily doped regions 42, 44 are respectively N-type and P-type heavily doped regions, and the fifth and sixth heavily doped regions 48 and 50 are respectively N-type, P-type heavily doped region. For the voltage connection relationship, the first heavily doped region 34 of the first clamp well region 32 is connected to each of the sixth heavily doped regions 50 as a low voltage ground potential. The second heavily doped region 36 of the last clamp well region 32 is coupled to each of the third heavily doped regions 42 by a high voltage Vcc such that all heavily doped regions are biased.

In summary, the deep trench isolation structure disposed in the substrate allows each well region to be independent, thereby making the present invention suitable for low operating voltage applications.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally varied and modified. All should be included in the scope of the patent application of the present invention.

10. . . Transient voltage suppressor

12. . . To protect the device

14. . . Zener diode

16. . . Dipole

18. . . PNP transistor

20. . . P-type substrate

twenty two. . . N type well area

twenty four. . . N-type heavily doped substrate

26. . . Clamped diode structure

28. . . Deep trench isolation structure

30. . . Dipole

32. . . Clamping well area

34. . . First heavily doped region

36. . . Second heavily doped region

38. . . Diode connected structure

40. . . First well area

42. . . Third heavily doped region

44. . . Fourth heavily doped region

46. . . Second well area

48. . . Fifth heavily doped region

50. . . Sixth heavily doped region

Figure 1 is a block diagram of a prior art transient voltage suppressor coupled to a device to be protected.

Figure 2 is a schematic diagram of a prior art transient voltage suppressor with a Zener diode between high voltage and low voltage.

Figure 3 is a schematic diagram of a prior art transient voltage suppressor with a high voltage and low voltage complex diode.

Figure 4 is a cross-sectional view showing the structure of a plurality of transistors in series in the prior art.

Figure 5 is a circuit diagram of a prior art plurality of transistors in series.

Figure 6 is a cross-sectional view showing the structure of the first embodiment of the present invention.

Figure 7 is a circuit diagram showing a first embodiment of the present invention.

Figure 8 is a cross-sectional view showing the structure of a second embodiment of the present invention.

Figure 9 is a circuit diagram showing a second embodiment of the present invention.

twenty four. . . N-type heavily doped substrate

26. . . Clamped diode structure

28. . . Deep trench isolation structure

32. . . Clamping well area

34. . . First heavily doped region

36. . . Second heavily doped region

Claims (16)

A lateral operating voltage suppressor with low operating voltage, comprising: an N-type heavily doped substrate; at least two clamping diode structures disposed horizontally in the N-type heavily doped substrate, each of the clamping The diode structure comprises: a clamp well region, located in the N-type heavily doped substrate, and a first and second heavily doped regions are located in the clamp well region, the first and second heavily doped The hetero-regions are mutually different; and the plurality of deep trench isolation structures have a depth greater than a depth of the clamp well region and are shallower than a bottom depth of the N-type heavily doped substrate, and the deep trench isolation structures are located at the N-type The heavily doped substrate is isolated to isolate each of the clamp well regions. The lateral transient voltage suppressor of the low operating voltage as described in claim 1 further includes at least one diode serial structure, which is disposed in the N-type heavily doped substrate and is coupled to the clamp The diode structure is adjacent to each other, and the diode serial structure further comprises: a first well region located in the N-type heavily doped substrate, and a third and fourth heavily doped regions are located in the first well region The first well region is of the same type as the clamp well region, the third and fourth heavily doped regions are mutually different; and a second well region adjacent to the first well region and located In the N-type heavily doped substrate, the first and second well regions are mutually different, and a fifth and sixth heavily doped regions are located in the second well region, and the fifth and sixth heavily doped regions The regions are mutually different, and the fourth and fifth heavily doped regions are mutually different and interconnected, and the depth of the deep trench isolation structure is greater than the first and second well regions to isolate the adjacent ones 1. The second well zone and the adjacent clamp well zone. A lateral transient voltage suppressor having a low operating voltage as described in claim 2, wherein The fourth and fifth heavily doped regions of the diode series structure are connected to a pin (I/O pin). The transverse transient voltage suppressor of the low operating voltage as described in claim 2, wherein, when the plurality of diodes are connected in series, the diodes are horizontally disposed on the N-type In the doped substrate, the deep trench isolation structures also isolate each of the diodes in series. a lateral operating voltage suppressor having a low operating voltage as described in claim 2, wherein the third heavily doped region is of the same type as the first well region, the fourth heavily doped region and the second well region In the same type, the fifth and third heavily doped regions are of the same type, the sixth and fourth heavily doped regions are of the same type, and the first and fifth heavily doped regions are of the same type, and the second and sixth heavily doped regions are doped. The area is the same type. The transverse transient voltage suppressor with low operating voltage as described in claim 2, wherein the first well region and the clamp well region are respectively a P-type well region and a P-type clamp well region, the first The Erjing District is an N-type well area. a lateral operating voltage suppressor having a low operating voltage as described in claim 6 wherein the third heavily doped region is connected to a low voltage of the second heavily doped region of the last clamping well region, The sixth heavily doped region is coupled to the first heavily doped region of the first clamp well region to a high voltage such that the first and second heavily doped regions are biased. The transverse transient voltage suppressor with low operating voltage as described in claim 2, wherein the first well region and the clamp well region are respectively an N-type well region and an N-type clamp well region, the first The Erjing District is a P-type well area. a lateral operating voltage suppressor having a low operating voltage as described in claim 8 wherein the third heavily doped region is connected to a high voltage of the second heavily doped region of the last clamping well region, The sixth heavily doped region is connected to the first heavily doped region of the first clamping well region and is low-powered Pressing, the first and second heavily doped regions are all biased. A lateral transient voltage suppressor having a low operating voltage as described in claim 7 wherein the low voltage is a ground potential. A lateral transient voltage suppressor having a low operating voltage as described in claim 9 wherein the low voltage is a ground potential. A lateral operating voltage suppressor having a low operating voltage as described in claim 7 wherein the N-type heavily doped substrate is floating or connected to the high voltage. A lateral operating voltage suppressor having a low operating voltage as described in claim 9 wherein the N-type heavily doped substrate is floating or connected to the high voltage. A lateral operating voltage suppressor having a low operating voltage as described in claim 1, wherein each of the clamping well regions is connected in series with each other through the first and second heavily doped regions. The transverse transient voltage suppressor with low operating voltage as described in claim 2, wherein the first well region, the second well region and the clamp well region are adjacent to the deep trenches adjacent thereto The isolation structure is adjacent. The lateral transient voltage suppressor of the low operating voltage as described in claim 1, wherein the deep trench isolation structure is made of a dielectric material.