TWI439864B - 包括階層式交叉開關之裝置及其操作方法 - Google Patents

包括階層式交叉開關之裝置及其操作方法 Download PDF

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Publication number
TWI439864B
TWI439864B TW095129809A TW95129809A TWI439864B TW I439864 B TWI439864 B TW I439864B TW 095129809 A TW095129809 A TW 095129809A TW 95129809 A TW95129809 A TW 95129809A TW I439864 B TWI439864 B TW I439864B
Authority
TW
Taiwan
Prior art keywords
agent
agents
data
interconnect
communication path
Prior art date
Application number
TW095129809A
Other languages
English (en)
Chinese (zh)
Other versions
TW200809517A (en
Inventor
Sridhar P Subramanian
James B Keller
George Kong Yiu
Ruchi Wadhawan
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of TW200809517A publication Critical patent/TW200809517A/zh
Application granted granted Critical
Publication of TWI439864B publication Critical patent/TWI439864B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
TW095129809A 2005-08-11 2006-08-14 包括階層式交叉開關之裝置及其操作方法 TWI439864B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/201,573 US7269682B2 (en) 2005-08-11 2005-08-11 Segmented interconnect for connecting multiple agents in a system

Publications (2)

Publication Number Publication Date
TW200809517A TW200809517A (en) 2008-02-16
TWI439864B true TWI439864B (zh) 2014-06-01

Family

ID=37670651

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095129809A TWI439864B (zh) 2005-08-11 2006-08-14 包括階層式交叉開關之裝置及其操作方法

Country Status (8)

Country Link
US (2) US7269682B2 (https=)
EP (1) EP1922628B1 (https=)
JP (1) JP5356024B2 (https=)
CN (1) CN101326505B (https=)
AT (1) ATE443893T1 (https=)
DE (1) DE602006009408D1 (https=)
TW (1) TWI439864B (https=)
WO (1) WO2007022019A2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
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US7269682B2 (en) 2005-08-11 2007-09-11 P.A. Semi, Inc. Segmented interconnect for connecting multiple agents in a system
US7779189B2 (en) * 2008-02-21 2010-08-17 International Business Machines Corporation Method, system, and computer program product for pipeline arbitration
JP2010165175A (ja) 2009-01-15 2010-07-29 Internatl Business Mach Corp <Ibm> バスの使用権を制御する装置および方法
US9514074B2 (en) 2009-02-13 2016-12-06 The Regents Of The University Of Michigan Single cycle arbitration within an interconnect
US8787368B2 (en) * 2010-12-07 2014-07-22 Advanced Micro Devices, Inc. Crossbar switch with primary and secondary pickers
CN104412246B (zh) * 2012-07-02 2017-05-31 马维尔以色列(M.I.S.L.)有限公司 用于从存储器到处理客户端提供复制数据的系统和方法
ITMI20121800A1 (it) * 2012-10-24 2014-04-25 St Microelectronics Srl Dispositivo e relativo metodo per la scrittura/lettura di un registro di memoria condiviso da una pluralità di periferiche.
TWI617920B (zh) * 2013-07-12 2018-03-11 密西根大學董事會 單循環仲裁

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US5081575A (en) * 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
US5452231A (en) 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
JPH07123252B2 (ja) * 1991-11-27 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション ネットワーク用スイッチングシステム
US5524235A (en) * 1994-10-14 1996-06-04 Compaq Computer Corporation System for arbitrating access to memory with dynamic priority assignment
US5887146A (en) 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
US6195335B1 (en) 1997-06-27 2001-02-27 International Business Machines Corporation Data switch
US6343081B1 (en) * 1997-12-30 2002-01-29 International Business Machines Corporation Method and apparatus for managing contention in a self-routing switching architecture in a port expansion mode
EP0938212A1 (en) * 1998-02-19 1999-08-25 International Business Machines Corporation Process and system of flow control for a switching system
US6157989A (en) * 1998-06-03 2000-12-05 Motorola, Inc. Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system
US6604230B1 (en) 1999-02-09 2003-08-05 The Governing Counsel Of The University Of Toronto Multi-logic device systems having partial crossbar and direct interconnection architectures
US6374319B1 (en) * 1999-06-22 2002-04-16 Philips Electronics North America Corporation Flag-controlled arbitration of requesting agents
US6460174B1 (en) 1999-10-01 2002-10-01 Stmicroelectronics, Ltd. Methods and models for use in designing an integrated circuit
US6601126B1 (en) * 2000-01-20 2003-07-29 Palmchip Corporation Chip-core framework for systems-on-a-chip
US6769046B2 (en) 2000-02-14 2004-07-27 Palmchip Corporation System-resource router
US6665760B1 (en) * 2000-09-29 2003-12-16 Rockwell Automation Technologies, Inc. Group shifting and level shifting rotational arbiter system
JP2002169787A (ja) * 2000-11-30 2002-06-14 Matsushita Electric Ind Co Ltd 複数のプロセッサ部を含む半導体装置
US7096292B2 (en) 2001-02-28 2006-08-22 Cavium Acquisition Corp. On-chip inter-subsystem communication
US7203202B2 (en) * 2001-10-31 2007-04-10 Polytechnic University Arbitration using dual round robin matching with exhaustive service of winning virtual output queue
US6954811B2 (en) * 2002-07-19 2005-10-11 Calix Networks, Inc. Arbiter for an input buffered communication switch
US20040223454A1 (en) * 2003-05-07 2004-11-11 Richard Schober Method and system for maintaining TBS consistency between a flow control unit and central arbiter in an interconnect device
JP2005070497A (ja) * 2003-08-26 2005-03-17 Canon Inc 現像装置及び画像形成装置
US7199607B2 (en) * 2004-12-22 2007-04-03 Infineon Technologies Ag Pin multiplexing
US7275121B1 (en) * 2005-04-05 2007-09-25 Nvidia Corporation System and method for hardware assisted resource sharing
US7269682B2 (en) 2005-08-11 2007-09-11 P.A. Semi, Inc. Segmented interconnect for connecting multiple agents in a system

Also Published As

Publication number Publication date
CN101326505A (zh) 2008-12-17
JP5356024B2 (ja) 2013-12-04
US20070038796A1 (en) 2007-02-15
EP1922628A2 (en) 2008-05-21
DE602006009408D1 (https=) 2009-11-05
ATE443893T1 (de) 2009-10-15
JP2009505241A (ja) 2009-02-05
US7426601B2 (en) 2008-09-16
EP1922628B1 (en) 2009-09-23
WO2007022019A2 (en) 2007-02-22
TW200809517A (en) 2008-02-16
US20070271402A1 (en) 2007-11-22
US7269682B2 (en) 2007-09-11
CN101326505B (zh) 2011-06-01
WO2007022019A3 (en) 2007-05-31

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