TWI423232B - Driving circuit and display device using the same - Google Patents

Description

Driving circuit and display device using same

SUMMARY OF THE INVENTION The present invention relates to a display device for use in a drive circuit, and more particularly to a drive circuit that can control the drive channels it contains at an appropriate timing.

A liquid crystal display (LCD) is a flat panel display including a display panel, a timing controller, a plurality of source drivers, and a plurality of gate drivers. A plurality of pixel units arranged in an array are disposed on the display panel, and each of the pixel units is coupled to a corresponding data line and a corresponding scan line thereof. The timing controller outputs the video data to the plurality of source drivers, and converts the video data to the data driving signal via the source driver. The timing controller also controls the gate controller to sequentially enable the scan line, and controls the source driver to transmit the data drive signal to the pixel unit via the data line to display the picture when the scan line is enabled.

In general, in order to prevent the liquid crystal from being polarized by the residual charge, a data driving signal of opposite polarity is usually used to drive the pixel unit at the same position in two consecutive pictures. For the same picture, adjacent pixel units are also driven by data driving signals of opposite polarity to avoid crosstalk affecting display quality. However, when polarity inversion is performed, if the switching frequency of the positive and negative polarities is not fast enough, the human eye can easily perceive the flickering of the screen. Therefore, a source of point-to-point Reduced Swing Differential Signaling has been proposed. The pole driver has a plurality of driving channels controlled by the timing controller, and each driving channel can receive the video data of one of the two data paths to increase the operating frequency of the source driver. Wherein, each driving channel needs to set a corresponding data mode, and the video data is obtained from the corresponding data path by appropriate timing control.

However, the number of source drivers required in a liquid crystal display device increases as the resolution of the display panel increases, which is limited by the panel layout space. These source drivers may be disposed at different positions on the display panel, for example, above or below. At this time, the drive channels of different source drivers may be connected at both ends of the same data line. If the drive channels at both ends of the same data line have different data mode settings, or have a mismatched data mode, the incorrect data mode setting will cause the drive channel to fail to obtain the correct video data from the corresponding data path.

In view of the above, the present invention provides a driving circuit and a display device using the same, wherein the driving channels connected to both ends of the same data line can be connected from the same bus by the timing control of the displacement register in each source driver. Get the right information to drive the display panel.

The invention provides a driving circuit suitable for driving a display panel having a plurality of data channels. The driving circuit includes a first source driver and a second source driver. The first source driver has m first driving channels, and the first to nth first driving channels drive the first to nth data channels. Each of the first driving channels operates in the first mode according to the first preset mode sequence Or the second mode. The first source driver includes a plurality of first displacement registers and a plurality of second displacement registers. The first displacement register respectively corresponds to the first driving channel, and the first displacement register corresponding to the first driving channel of the first mode transmits the first starting pulse one by one to the first driving channel with the first mode, So that the first driving channel with the first mode can be driven. The second displacement register respectively corresponds to the first driving channel, and the second displacement register corresponding to the first driving channel of the second mode transmits the second starting pulse one by one to the first driving channel with the second mode, So that the first driving channel with the second mode can be driven.

In the above, the second source driver has m second driving channels, and the mth to the (m-n+1)th second driving channels drive the 1st to nth data channels. Each of the second driving channels operates in the first mode or the second mode according to the second preset mode sequence. The second source driver includes a plurality of third displacement registers and a plurality of fourth displacement registers. The third displacement register respectively corresponds to the second driving channel, and the third displacement register corresponding to the second driving channel of the second mode transmits the first starting pulse to the second driving channel with the second mode one by one, So that the second drive channel with the second mode can be driven. The fourth displacement register respectively corresponds to the second driving channel, and the fourth displacement register corresponding to the second driving channel of the first mode transmits the second starting pulse one by one to the second driving channel with the first mode, So that the second drive channel having the first mode can be driven, where m and n are positive integers and m≧n.

The present invention further provides a display device including a display panel having a plurality of data channels and the above-described driving circuit.

In the above driving circuit and display device, in one embodiment of the present invention, the first source driver further includes a plurality of first displacement multiplexers, a plurality of first data multiplexers, and a plurality of first latches. Each first multiplexer selects a first start pulse outputted by the corresponding first shift register or a second start pulse outputted by the corresponding second shift register according to the displacement control signal. Each of the first data multiplexers selects the data on the first bus or the data on the second bus according to the data control signal. Each of the first latches is enabled to operate according to a start pulse output by the corresponding first shift multiplexer, and latches the data output by the corresponding first data multiplexer.

In the above driving circuit and display device, in one embodiment of the present invention, the second source driver further includes a plurality of second displacement multiplexers, a plurality of second data multiplexers, and a plurality of second latches. Each of the second shift multiplexers selects a first start pulse outputted by the corresponding third shift register or a second start pulse outputted by the corresponding fourth shift register according to the displacement control signal. Each of the second data multiplexers selects the data on the first bus or the data on the second bus according to the data control signal. Each of the second latches is enabled to operate according to a start pulse outputted by the corresponding second shift multiplexer, and latches the data output by the corresponding second data multiplexer.

The invention uses the first source driver to drive the n data channels on the display panel in a forward direction, and uses the second source driver to reversely drive the n data channels on the display panel. Through the timing control of the output pulse of the displacement register in each source driver, it is ensured that the driving channels of different source drivers timely acquire the correct data from the same bus to drive the same data channel, and avoid the driving channel data mode. The error caused by the match works.

The above described features and advantages of the present invention will be more apparent from the following description.

Embodiments of the present invention will be described in detail below with reference to the drawings, and the same reference numerals will be used to refer to the same or like parts.

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention. Referring to FIG. 1 , a display device 100 , such as a liquid crystal display, includes a driving circuit and a display panel 130 . The display panel 130 has n pixel units 131 on each of the scan lines S ₁ -S _P , and the n pixel units 131 is connected to the data channels D ₁ ~ D _{n respectively} , for example: n=12. The drive circuit includes source drivers 110 and 120. The source drivers 110 and 120 each have m drive channels CH ₁ ~CH _m (eg, m=12), where m and n are positive integers and m is greater than or equal to n.

Limited to the panel layout space, the source drivers 110 and 120 may be disposed on different sides of the display panel 130, such as the upper side and the lower side. When the scan lines S ₁ -S _{P are} sequentially enabled, the source drivers 110 and 120 are responsible for driving the pixel units 131 on the upper half display panel 130 and the lower half display panel, respectively. For example, when the scan lines S ₁ enabled, the source driver drive channel 110 CH ₁ to CH _n drive the display panel data channel D 130 of _{from 1} to D _n, and when the scan line S _P enabled, the source The drive channels CH _m to CH _{m-n+1 of the} pole driver 120 drive the data channels D ₁ to D _{n of the} display panel 130, respectively.

In this embodiment, the source drivers 110 and 120 are, for example, point-to-point Reduced Swing Differential Signaling source drivers, which can simultaneously receive video data from two data paths. To increase the operating frequency of the source driver. In each of the source drivers 110 and 120, each of the driving channels CH ₁ to CH _m may be set to a first mode or a second mode, thereby receiving data from the first bus bar or the second bus bar, wherein the first mode and the first mode The two modes are respectively referred to as A mode and B mode. In general, each of the source drivers 110 and 120 has three transmission modes, namely, AAAA, AABB, and ABAB types. In the AAAA type, the drive channels CH ₁ ~CH _m sequentially receive data from the same bus. In the AABB type, each of the two driving channels CH ₁ to CH _m is a group, and the adjacent two groups receive data from the first bus bar and the second bus bar, respectively. In the ABAB type, adjacent drive channels CH ₁ -CH _m receive data from the first bus bar and the second bus bar, respectively.

Referring to FIG. 1, it is assumed that each of the source drivers 110 and 120 has 4i driving channels, that is, m=4i (for example, i=3), where i is a positive integer. For the AABB type, according to the preset mode sequences SEQ1 and SEQ2, the (4k+1)th drive channel CH _4k+1 and the (4k+2)th drive channel CH _{4k+2 of} each of the source drivers 110 and 120 (Example: CH ₁ , CH ₂ , CH ₅ , CH ₆ ) operates in A mode, and the (4k+3)th drive channels CH _4k+3 and (4k+4) of each of the source drivers 110 and 120 Drive channel CH _4k+4 (eg, CH ₃ , CH ₄ , CH ₇ , CH ₈ ) operates in B mode, where k is a non-negative integer. Since the source drivers 110 and 120 are disposed on different sides of the display panel 130, the modes of the driving channels CH ₁₂ to CH ₁ in the source driver 120 are different from those in the source driver 110 for the data channels D ₁ to D ₁₂ , respectively. Channel CH ₁ to CH ₁₂ . In short, the drive channels of different source drivers are located on both ends of the same data channel and will have different modes.

In order to ensure that the driving channels of different source drivers can obtain the correct data from the same bus to drive the same data channel, in this embodiment, the driving circuit further includes a mode control unit 140 according to the preset mode of the source drivers 110 and 120. The sequence generates the displacement control signal CON1 and the data control signal CON2 to control the source drivers 110 and 120 to be driven by appropriate start pulses and to obtain data on the bus. In addition, the source driver 110 includes two shift register groups 111 and 112, which respectively transmit the first start pulse ASTH and the second start pulse BSTH, so that the drive channels CH ₁ -CH _{m of the} energy source driver 110 operate. Similarly, the source driver 120 includes two shift register groups 121 and 122 that respectively transmit the first start pulse ASTH and the second start pulse BSTH, so that the drive channels CH ₁ -CH _{m of the} energy source driver 120 operate.

The source driver 110 is taken as an example for description. FIG. 2A is a timing diagram of the shift register groups 111 and 112 illustrated in FIG. 1 according to an embodiment of the invention. Referring to FIG. 1, the shift register group 111 includes a plurality of shift registers ASR ₁ ~ ASR ₁₂ corresponding to the drive channels CH ₁ -CH _{12 respectively} , and the shift register 112 includes a plurality of shift registers BSR ₁ ~ BSR ₁₂ corresponds to the drive channels CH ₁ ~CH _{12 respectively} . The number of the shift registers included in the shift register groups 111 and 112 may be the same as the number of the drive channels of the source driver 110 or the number of data channels of the display panel 130, and is not limited thereto. When the number of the shift registers is the same as the number of data channels of the display panel 130, and the number of drive channels is more than the number of data channels, the start pulse outputted by the shift register groups 111 and 112 can be switched to the additional multiplexer to Used to drive the drive channel of the data channel.

Referring to FIG. 2A, in the source driver 110, the shift registers ASR ₁ , ASR ₂ , and ASR corresponding to the drive channels CH ₁ , CH ₂ , CH ₅ , CH ₆ , CH ₉ , and CH ₁₀ operating in the A mode are operated. ₅ , ASR ₆ , ASR ₉ , ASR ₁₀ pass the first start pulse ASTH one by one to the drive channels CH ₁ , CH ₂ , CH ₅ , CH ₆ , CH ₉ , CH ₁₀ operating in the A mode, so as to drive the A mode Drive channels CH ₁ , CH ₂ , CH ₅ , CH ₆ , CH ₉ , CH ₁₀ . Moreover, the shift registers BSR ₃ , BSR ₄ , BSR ₇ , BSR ₈ , BSR ₁₁ , BSR ₁₂ corresponding to the drive channels CH ₃ , CH ₄ , CH ₇ , CH ₈ , CH ₁₁ , CH ₁₂ operating in the B mode are operated. Passing the second start pulse BSTH one by one to the drive channels CH ₃ , CH ₄ , CH ₇ , CH ₈ , CH ₁₁ , CH ₁₂ operating in the B mode, so as to drive the drive channels CH ₃ , CH ₄ , CH with the B mode ₇ , CH ₈ , CH ₁₁ , CH ₁₂ . In FIG. 2A, the two driving channels of the source driver 110 (for example, CH ₁ and CH ₃ ) can be simultaneously driven to acquire data from different bus bars, thereby increasing the operating frequency thereof. In addition, each of the drive channels CH ₁ -CH _{12 of the} source driver 110 is controlled by the displacement control signal CON1 to select an appropriate start pulse, and is controlled by the data control signal CON2 to select the data on the appropriate bus bar.

In order to improve the versatility of the source driver, the source driver is designed to conform to the application of the display panel 130. The source driver 120 of the embodiment includes two displacement register groups 121 and 122, wherein the displacement is temporarily suspended. The start pulse timing outputted by the register group 121 corresponding to the drive channels CH ₁₂ to CH ₁ is the same as the start pulse timing outputted by the corresponding drive channels CH ₁ to CH _{12 of} the shift register group 112, and the shift register group 122 corresponds to the drive. The timing of the start pulse outputted by the channels CH ₁₂ to CH ₁ is the same as the start pulse timing of the corresponding drive channels CH ₁ to CH _{12 of} the shift register group 111. Thereby, the drive channels CH ₁ -CH ₁₂ in the source driver 120 can be controlled by appropriate timing.

FIG. 2B is a timing diagram of the shift register groups 121 and 122 illustrated in FIG. 1 according to an embodiment of the present invention. Referring to FIG. 1, in the source driver 120, the shift register group 121 includes a plurality of shift registers CSR ₁ -CSR ₁₂ corresponding to the drive channels CH ₁ -CH ₁₂ , respectively, and the shift register 122 includes a plurality of displacements. The registers DSR ₁ ~ DSR ₁₂ correspond to the drive channels CH ₁ ~ CH _{12 , respectively} . Referring to FIG. 2B, in the source driver 120, the shift registers CSR ₁₂ , CSR ₁₁ , and CSR corresponding to the drive channels CH ₁₂ , CH ₁₁ , CH ₈ , CH ₇ , CH ₄ , and CH ₃ operating in the B mode are operated. _8. CSR ₇ , CSR ₄ , and CSR ₃ pass the first start pulse ASTH one by one to the drive channels CH ₁₂ , CH ₁₁ , CH ₈ , CH ₇ , CH ₄ , and CH ₃ operating in the B mode, so that the drive mode B can be driven. Drive channels CH ₁₂ , CH ₁₁ , CH ₈ , CH ₇ , CH ₄ , CH ₃ . Moreover, the shift registers DSR ₁₀ , DSR ₉ , DSR ₆ , DSR ₅ , DSR ₂ , DSR ₁ corresponding to the drive channels CH ₁₀ , CH ₉ , CH ₆ , CH ₅ , CH ₂ , CH ₁ operating in the A mode are operated. Passing the second start pulse BSTH one by one to the drive channels CH ₁₀ , CH ₉ , CH ₆ , CH ₅ , CH ₂ , CH ₁ operating in the A mode, so as to drive the drive channels CH ₁₀ , CH ₉ , CH with the A mode ₆ , CH ₅ , CH ₂ , CH ₁ . In FIG. 2B, the two drive channels of the source driver 120 (eg, CH ₁₂ and CH ₁₀ ) can be simultaneously driven to acquire data from different bus bars, thereby increasing the operating frequency thereof. In addition, each of the drive channels CH ₁ -CH _{12 of the} source driver 120 is controlled by the displacement control signal CON1 to select an appropriate start pulse, and is controlled by the data control signal CON2 to select the data on the appropriate bus bar.

3 is a circuit diagram of source drivers 110 and 120 of FIG. 1 in accordance with an embodiment of the present invention. Referring to FIG. 3, the source driver 110 includes a shift register group 111 and 112, a shift multiplexer group 113, a data multiplexer group 114, and a data latch group 115. The shift multiplexer group 113 includes a plurality of shift multiplexers MUX1, and each shift multiplexer MUX1 is controlled by the displacement control signal CON1 to select the start of the output of the corresponding shift register in the shift register group 111 or 112. pulse. The data multiplexer group 114 includes a plurality of data multiplexers MUX2, and each data multiplexer MUX2 is controlled by the data control signal CON2 to select data on the first bus BUS1 or the second bus BUS2. The data latch group 115 includes a plurality of data latches DL1, and each data latch DL1 is controlled to operate by a start pulse outputted by the corresponding shift multiplexer MUX1 to latch the corresponding data multiplexer. The data output by MUX2.

Similarly, the source driver 120 includes shift register groups 121 and 122, a shift multiplexer group 123, a data multiplexer group 124, and a data latch group 125. The shift multiplexer group 123 includes a plurality of shift multiplexers MUX3, and each shift multiplexer MUX3 is controlled by the displacement control signal CON1 to select the start of the output of the corresponding shift register in the shift register group 121 or 122. pulse. The data multiplexer group 124 includes a plurality of data multiplexers MUX4, and each data multiplexer MUX4 is controlled by the data control signal CON2 to select data on the first bus BUS1 or the second bus BUS2. data The latch group 125 includes a plurality of data latches DL2, and each data latch DL2 is controlled to operate by a start pulse outputted by the corresponding shift multiplexer MUX3 to latch the corresponding data multiplexer The data output by MUX4.

It is worth mentioning that the source drivers 110 and 120 further include a digital analog converter to convert the data on the bus bar to an analog voltage, and an output buffer to enhance and buffer components such as an analog voltage. Those skilled in the art should understand the operation of these elements, and therefore the connections between these elements are not described.

Referring to FIG. 1 and FIG. 3, for the drive channels CH _4k+1 and CH _{4k+2 having the} A mode in the source driver 110, the mode control unit 140 controls the corresponding signals via the displacement control signal CON1 and the data control signal CON2. Each of the displacement multiplexers MUX1 of the drive channel selects a first start pulse ASTH outputted by the corresponding shift register in the shift register group 111, and controls each data multiplexer MUX2 corresponding to the drive channels to select the first bus Information on BUS1. Conversely, for the drive channels CH _4k+3 and CH _{4k+4 having the} B mode in the source driver 110, the mode control unit 140 controls the displacements corresponding to the drive channels via the displacement control signal CON1 and the data control signal CON2. The multiplexer MUX1 selects the second start pulse BSTH outputted by the corresponding shift register in the shift register group 112, and controls each data multiplexer MUX2 corresponding to the drive channels to select the data on the second bus BUS2.

Referring to FIG. 1 and FIG. 3, for the drive channels CH _4k+1 and CH _{4k+2 of the} A mode in the source driver 120, the mode control unit 140 controls the corresponding signals via the displacement control signal CON1 and the data control signal CON2. Each of the displacement multiplexers MUX3 of the drive channel selects a second start pulse BSTH outputted by the corresponding shift register in the shift register group 122, and controls each data multiplexer MUX4 corresponding to the drive channels to select the second bus Information on BUS2. Conversely, for the drive channels CH _4k+3 and CH _{4k+4 having the} B mode in the source driver 120, the mode control unit 140 controls the displacements corresponding to the drive channels via the displacement control signal CON1 and the data control signal CON2. The multiplexer MUX3 selects the first start pulse ASTH outputted by the corresponding shift register in the shift register group 121, and controls each data multiplexer MUX4 corresponding to the drive channels to select the data on the first bus BUS1.

4 is a circuit diagram of source drivers 110 and 120 of FIG. 1 in accordance with an embodiment of the present invention. Referring to FIG. 4, the source driver 120 further includes a switch 126 that can exchange data on the first bus BUS1 with data on the second bus BUS2. At this time, for the drive channels CH _4k+1 and CH _{4k+2 having the} A mode in the source driver 120, the mode control unit 140 controls the displacement multiplexers MUX3 corresponding to the drive channels to select the displacement register group 122. Corresponding to the second start pulse BSTH outputted by the shift register, and controlling each data multiplexer MUX3 of the drive channels to select the data of the first bus BUS1. Moreover, for the drive channels CH _4k+3 and CH _{4k+4 having the} B mode in the source driver 120, the mode control unit 140 controls the shift multiplexers MUX3 corresponding to the drive channels to select the shift register group 121. Corresponding to the first start pulse ASTH outputted by the shift register, and controlling each data multiplexer MUX4 corresponding to the drive channels to select the data on the second bus BUS2. Thereby, the manner in which the mode control unit 140 controls the data multiplexer MUX4 in the source driver 120 is similar to the manner in which the data multiplexer MUX2 in the source driver 110 is controlled.

Please refer to FIG. 1. In another embodiment of the present invention, for the ABAB type, according to the preset mode sequences SEQ3 and SEQ4, the (2k+1)th driving channels of each of the source drivers 110 and 120 (for example: CH ₁ , CH ₃ , CH ₅ , CH ₇ ) operate in the A mode, and the (2k+2)th drive channels of each of the source drivers 110 and 120 (eg, CH ₂ , CH ₄ , CH ₆ , CH ₈ ) Operate in B mode. FIG. 5A is another timing diagram of the shift register groups 111 and 112 illustrated in FIG. 1 according to an embodiment of the invention. Referring to FIG. 5A, in the source driver 110, the shift registers ASR ₁ , ASR ₃ , ... corresponding to the drive channels CH ₁ , CH ₃ , . . . , CH ₉ , CH _{11 of} the A mode are operated. The ASR ₉ and the ASR _{11 respectively} transmit the first start pulse ASTH to the drive channels CH ₁ , CH ₃ , ..., CH ₉ , CH ₁₁ operating in the A mode, so as to drive the drive channel CH ₁ having the A mode, CH ₃ ,..., CH ₉ , CH ₁₁ . Further, the shift registers BSR ₂ , BSR ₄ , ..., BSR ₁₀ , and BSR ₁₂ corresponding to the drive channels CH ₂ , CH ₄ , ..., CH ₁₀ , and CH ₁₂ operating in the B mode are transmitted one by one. BSTH two start pulse to B-mode operation of the drive channel _{CH 2, CH 4, ...,} CH 10, CH 12, so that the drive can be driven with the B-mode channel _{CH 2, CH 4, ...,} CH 10, CH ₁₂ .

Referring to FIG. 3, for the drive channel CH _{2k+1 having the} A mode in the source driver 110, the mode control unit 140 controls the corresponding shift multiplexer MUX1 corresponding to the drive channels to select the corresponding one of the shift register groups 111. The first start pulse ASTH outputted by the shift register is controlled, and each data multiplexer MUX2 corresponding to the drive channels is controlled to select the data on the first bus BUS1. For the drive channel CH _2k+2 with the B mode in the source driver 110, the mode control unit 140 controls each of the displacement multiplexers MUX1 corresponding to the drive channels to select the corresponding displacement register in the shift register group 112. The second start pulse BSTH is output, and each data multiplexer MUX2 corresponding to the drive channels is controlled to select data on the second bus BUS.

FIG. 5B is another timing diagram of the shift register groups 111 and 112 illustrated in FIG. 1 according to an embodiment of the invention. Referring to FIG. 5B, in the source driver 120, the shift registers CSR ₁₂ , CSR ₁₀ , ... corresponding to the drive channels CH ₁₂ , CH ₁₀ , ..., CH ₄ , CH ₂ in the B mode are operated. , CSR ₄ , CSR ₂ pass the first start pulse ASTH one by one to the drive channels CH ₁₂ , CH ₁₀ , ..., CH ₄ , CH ₂ operating in the B mode, so as to drive the drive channel CH ₁₂ with the B mode, CH ₁₀ , ..., CH ₄ , CH ₂ . Moreover, the shift registers DSR ₁₁ , DSR ₉ , ..., DSR ₃ , and DSR ₁ corresponding to the drive channels CH ₁₁ , CH ₉ , ..., CH ₃ , and CH ₁ operating in the A mode are transmitted one by one. Two start pulse BSTH to the drive channels CH ₁₁ , CH ₉ , ..., CH ₃ , CH ₁ operating in the A mode, so as to drive the drive channels CH ₁₁ , CH ₉ , ..., CH ₃ with the A mode, CH ₁ .

Referring to FIG. 3, for the drive channel CH _{2k+1 having the} A mode in the source driver 120, the mode control unit 440 controls the corresponding shift multiplexer MUX3 corresponding to the drive channels to select the corresponding one of the shift register groups 122. The second start pulse BSTH outputted by the shift register is controlled, and each data multiplexer MUX4 corresponding to the drive channels is controlled to select the data on the second bus BUS2. For the drive channel CH _2k+2 with the B mode in the source driver 120, the mode control unit 440 controls each of the displacement multiplexers MUX3 corresponding to the drive channels to select the corresponding displacement register in the displacement register group 121. The first start pulse ASTH is output, and each data multiplexer MUX4 corresponding to the drive channels is controlled to select the data on the first bus BUS1.

The source driver 120 of the above embodiment controls the drive channels CH ₁ to CH _{m of the} source driver 120 to operate in a timely manner via the start pulses of the two shift register groups 121 and 122. The mode control unit 140 provides a control signal to control each drive channel CH ₁ ~CH _{m to} select the start pulse and the data on the bus. On the other hand, for the AABB type, the mode setting of the drive channels CH ₁ ~CH _m in the source driver 120 can also be changed via appropriate circuit design. For example, each set of four drive channels, for example: CH ₁ ~CH ₄ , changes the preset mode sequence AABB to BBAA, that is, the (4k+3)th drive channel CH in the source driver 120. _4k+3 and (4k+4)th drive channels CH _{4k+4 are} changed to operate in A mode, and (4k+1)th drive channel CH _4k+1 and (4k+2)th drive channel CH _{4k +2} changed to operate in A mode. However, in the case of a number of drive channels other than 4 integers, this way of changing the preset mode sequence will cause a malfunction.

FIG. 6 is a schematic diagram of a display device according to an embodiment of the invention. Referring to FIG. 6, it is assumed that each of the source drivers 610 and 620 has 4i+2 driving channels, that is, m=4i+2 (for example, i=3). According to the preset mode sequence SEQ5, the (4k+1)th drive channel CH _4k+1 and the (4i+2)th drive channel CH _{4k+2 of the} source driver 610 (eg, CH ₁ , CH ₂ , CH _{5 )} , CH ₆ ) operates in the A mode, and the (4k+3)th drive channel CH _4k+3 and the (4k+4)th drive channel CH _{4k+4 of the} source driver 610 (eg, CH ₃ , CH _{4 )} , CH ₇ , CH ₈ ) operate in B mode. In addition, according to the preset mode sequence SEQ6, the (4k+3)th drive channel CH _4k+3 and the (4i+4)th drive channel CH _{4k+4 of the} source driver 620 (eg, CH ₃ , CH ₄ , CH ₇ , CH ₈ ) operate in the A mode, and the (4k+1)th drive channel CH _4k+1 and the (4k+4)th drive channel CH _{4k+2 of the} source driver 610 (eg CH ₁ , CH ₂ , CH ₅ , CH ₆ ) operate in B mode.

Similar to the embodiment of FIG. 1 and FIG. 2A, the source driver 610, the operation mode of drive channel A _{CH 1, CH 2, CH 5} , CH 6, ..., 14 corresponding to the CH _13, CH displacement The registers ASR ₁ , ASR ₂ , ASR ₅ , ASR ₆ , ..., ASR ₁₃ , ASR ₁₄ pass the first start pulse ASTH one by one to the drive channels CH ₁ , CH ₂ , CH ₅ , CH operating in the A mode ₆ , ..., CH ₁₃ , CH ₁₄ . Moreover, the shift registers BSR ₃ , BSR ₄ , BSR ₇ , BSR ₈ , which correspond to the drive channels CH ₃ , CH ₄ , CH ₇ , CH ₈ , ..., CH ₁₁ , CH _{12 of} the B mode are operated. The BSR ₁₁ and the BSR ₁₂ pass the second start pulse BSTH one by one to the drive channels CH ₃ , CH ₄ , CH ₇ , CH ₈ , ..., CH ₁₁ , CH ₁₂ operating in the B mode.

Similar to FIG. 1 and FIG. 2B of the above embodiment, in the source driver 620, the displacement corresponding to the drive channels CH ₁₄ , CH ₁₃ , CH ₁₀ , CH ₉ , ..., CH ₂ , CH ₁ operating in the B mode is operated. The register CSR ₁₄ , CSR ₁₃ , CSR ₁₀ , CSR ₉ , ..., CSR ₂ , CSR ₁ pass the first start pulse ASTH one by one to the drive channels CH ₁₄ , CH ₁₃ , CH ₁₀ , CH operating in the B mode ₉ , ..., CH ₂ , CH ₁ . Moreover, the shift registers DSR ₁₂ , DSR ₁₁ , DSR ₈ , DSR ₇ , which correspond to the drive channels CH ₁₂ , CH ₁₁ , CH ₈ , CH ₇ , ..., CH ₄ , CH _{3 of} the A mode are operated. The DSR ₄ and the DSR ₃ pass the second start pulse BSTH one by one to the drive channels CH ₁₂ , CH ₁₁ , CH ₈ , CH ₇ , ..., CH ₄ , CH ₃ operating in the A mode.

The above embodiment uses the display panel 130 as an example, and the n pixel units 131 on each scan line are respectively connected to the data channels D ₁ -D _n to explain the operation of the source drivers 110, 120, 610 and 620 of the embodiment. However, the driving circuit taught in the embodiment can also be applied to a Z-type conversion display panel.

FIG. 7 is a schematic diagram of a display device according to an embodiment of the invention. Referring to FIG. 7, the display panel 730 has n pixel units 731 on each of the scan lines S ₁ to S _P , and the n pixel units 731 on the scan lines S ₁ to S _P are respectively connected to the data channels D ₁ to D _n . And n pixel units 731 on the other scan lines S ₁ to S _P are respectively connected to the data channels D ₂ to D _n+1 , where n is, for example, 12. When the scan line S _{1 is} enabled, the drive channels CH ₁ to CH _{n of the} source driver 710 respectively drive the data channels D ₁ to D _{n of the} display panel 730 , and when the scan line S _{2 is} enabled, the source driver 710 The drive channels CH ₂ to CH _n+1 drive the data channels D ₂ to D _{n+1 of the} display panel 730, respectively. On the other hand, when the scan line S _P When enabled, the source driver 720 drives through the channel CH _m CH _{m-n + 1,} respectively, to drive the display panel 730 of the data channel D ₁ to D _n, and when the scan line S _{P- 1} is enabled, the source driver 720 drives the channel CH _m-1 CH _mn to drive the display panel 730 of the data channel D ₂ to D _{n + 1.} Here, the invention is not limited to the order of scan line enabling.

In FIG. 7 of the embodiment of the present invention, a start pulse is transmitted to the additional multiplexer (not shown) between each of the shift register groups and the drive channels CH ₁ to CH _m during different scans. The drive channel used. For example, the source driver 710, the scan period of the scan lines S ₁ can be activated, the shift register 712 and multiplexer 711 sets the start pulse is transmitted to the drive channel CH ₁ to CH _n, and via in During the scan of the scan line S ₂ enable, the shift register groups 711 and 712 pass the start pulse to the drive channels CH ₂ to CH _n+1 via the multiplexer. Further, the source driver 720, the scan period of the scan lines S _P enabled, the shift register 722 and multiplexer 721 sets the start pulse is transmitted to the drive channel CH _m to CH _{m-n + 1} through, And during the scan of the scan line S _P-1 enable, the shift register groups 721 and 722 pass the start pulse to the drive channels CH _m-1 to CH _mn via the multiplexer.

In summary, the two source drivers of the above embodiment are designed according to the panel layout, one of which drives the data channels on the display panel in the drive channels CH ₁ to CH _n and the other drives the channels CH _m to CH _{m . -n+1} drives the data channel on the display panel in reverse. In order to ensure the correctness of the data transmission to the drive channels of the source drivers, the two shift register groups included in each source driver generate appropriate timing control according to the preset mode sequence, so as to enable the drive channel operation in a timely manner. Get the right information from the bus.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 600, 700‧‧‧ display devices

110, 120, 610, 620, 710, 720‧‧‧ source drivers

111~112, 121~122, 611~612, 621~622, 711~712, 721~722‧‧‧ Displacement register group

126‧‧‧Switch

130, 730‧‧‧ display panel

131, 731‧‧ ‧ pixel unit

140, 740‧‧‧ mode control unit

ASR ₁ ~ASR ₁₂ , BSR ₁ ~BSR ₁₂ , CSR ₁ ~CSR ₁₂ , DSR ₁ ~DSR ₁₂ ‧‧‧Displacement register

ASTH‧‧‧First start pulse

BSTH‧‧‧second start pulse

CH ₁ ~CH ₁₄ ‧‧‧ drive channel

CON1, CON2‧‧‧ control signals

D ₁ ~D ₁₃ ‧‧‧ data channel

DL1, DL2‧‧‧Latch

MUX1, MUX3‧‧‧ Displacement multiplexer

MUX2, MUX4‧‧‧ data multiplexer

DL1, DL2‧‧‧Latch

BUS1, BUS2‧‧‧ busbar

SEQ1~6‧‧‧ Preset pattern sequence

S ₁ ~S _P ‧‧‧ scan line

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.

2A and 2B are timing diagrams of the shift register group illustrated in FIG. 1 according to an embodiment of the invention.

3 is a circuit diagram of the source driver of FIG. 1 in accordance with an embodiment of the present invention.

4 is a circuit diagram of the source driver of FIG. 1 in accordance with an embodiment of the present invention.

5A and 5B are another timing diagram of the shift register group illustrated in FIG. 1 according to an embodiment of the invention.

6 and 7 are schematic diagrams of a display device according to an embodiment of the invention.

100‧‧‧LCD display

110, 120‧‧‧ source drive

111, 112, 121, 122‧‧‧ Displacement register group

130‧‧‧ display panel

131‧‧‧pixel unit

140‧‧‧Mode Control Unit

ASR ₁ ~ASR ₁₂ , BSR ₁ ~BSR ₁ , CSR ₁ ~CSR ₁ , DSR ₁ ~DSR ₁₂ ‧‧‧Displacement register

ASTH‧‧‧First start pulse

BSTH‧‧‧second start pulse

CH ₁ ~CH ₁₂ ‧‧‧ drive channel

CON1, CON2‧‧‧ control signals

D ₁ ~D ₁₂ ‧‧‧ data channel

SEQ1, SEQ2‧‧‧ Preset pattern sequence

S ₁ ~S _P ‧‧‧ scan line

Claims (23)

A driving circuit, configured to drive a display panel having a plurality of data channels, comprising: a first source driver having m first driving channels for driving the display panel, during a first scanning period, the first one to The nth first driving channel drives the first to the nth data channels, wherein each of the first driving channels operates in a first mode or a second mode according to a first preset mode sequence, The first source driver includes: a plurality of first displacement registers respectively corresponding to the first driving channels, and the first displacement registers corresponding to the first driving channels of the first mode Passing a first start pulse one by one to enable driving the first driving channels having the first mode; and a plurality of second shift registers respectively corresponding to the first driving channels and operating in the second mode The second displacement registers corresponding to the first driving channels respectively transmit a second starting pulse to enable driving the first driving channels having the second mode; and a second source driver, With m number The driving channel drives the display panel. During a second scanning period, the mth to the (m-n+1)th second driving channels drive the first to the nth data channels, wherein each of the The second driving channel is operated in the first mode or the second mode according to a second preset mode sequence, and the second source driver comprises: a plurality of third displacement registers respectively corresponding to the second driving channels, And the third shift registers corresponding to the second driving channels of the second mode transmit the first start pulse one by one to enable driving The second driving channels having the second mode; and the plurality of fourth displacement registers respectively corresponding to the second driving channels, and the second driving channels operating in the first mode are corresponding to the The fourth shift register transfers the second start pulse one by one to enable driving the second drive channels having the first mode, where m and n are positive integers, and m≧n. The driving circuit of claim 1, wherein the first source driver further comprises: a plurality of first displacement multiplexers, each of the first displacement multiplexers selecting the corresponding one according to a displacement control signal The first start pulse output by the first displacement register or the second start pulse output by the second displacement register; a plurality of first data multiplexers, each of the first data multiplexers Selecting data on a first bus bar or data on a second bus bar according to a data control signal; and a plurality of first latches, each of the first latches multiplexing according to the corresponding first displacement The start pulse outputted by the device is enabled to operate, and the latch corresponds to the data output by the first data multiplexer. The driving circuit of claim 2, wherein the second source driver further comprises: a plurality of second displacement multiplexers, each of the second displacement multiplexers selecting the corresponding one according to the displacement control signal The first start pulse output by the third displacement register or the second start pulse output by the fourth displacement register; a plurality of second data multiplexers, each of the second data multiplexers selecting data on the first bus bar or data on the second bus bar according to the data control signal; and a plurality of second latchers Each of the second latches is enabled to operate according to a start pulse outputted by the corresponding second shift multiplexer, and latches the data corresponding to the first output. The driving circuit of claim 3, further comprising: a mode control unit, generating the displacement control signal and the data control signal according to the first preset mode sequence and the second preset mode sequence. The driving circuit of claim 4, wherein the mode control unit controls each of the first displacement multiplexers and each of the first data corresponding to each of the first driving channels of the first mode Selecting the first start pulse and the data on the first bus bar, respectively, and controlling each of the first displacement multiplexers corresponding to each of the first driving channels of the second mode and each of the first The data multiplexer selects the second start pulse and the data on the second bus. The driving circuit of claim 4, wherein the mode control unit controls each of the second displacement multiplexers and the second data corresponding to each of the second driving channels of the first mode Selecting the second start pulse and the data on the second bus, respectively, and controlling each of the second shift multiplexers and the second corresponding to each of the second drive channels of the second mode The data multiplexer selects the first start pulse and the data on the first bus. a driving circuit as described in claim 4, wherein the The two-source driver further includes: an exchanger for exchanging data on the first bus bar with data on the second bus bar, wherein the mode control unit controls operations in each of the first modes Each of the second shift multiplexers corresponding to the two driving channels and each of the second data multiplexers respectively select the second starting pulse and the data on the first bus bar, and the control operation is in each of the second modes. Each of the second shift multiplexers and the second data multiplexers corresponding to the second driving channel respectively select the data of the first start pulse and the second bus bar. The driving circuit of claim 4, wherein the (2k+1)th first driving channel operates in the first mode according to the first preset mode sequence, and the (2k+2)th first The driving channel operates in the second mode, and according to the second preset mode sequence, the (2k+1)th second driving channel operates in the second mode, and the (2k+2)th second driving channel operates in In the first mode, k is a non-negative integer. The driving circuit of claim 4, wherein the (4k+1)th first driving channel and the (4k+2)th first driving channel operate according to the first preset mode sequence In one mode, the (4k+3)th and the (4k+4)th first driving channels operate in the second mode, and the (4k+1)th and the (4k+) according to the second preset mode sequence 2) The second driving channel operates in the first mode, the (4k+3)th and the (4k+4)th second driving channels operate in the second mode, and k is a non-negative integer. The driving circuit of claim 4, wherein the (4k+1)th first driving channel and the first according to the first preset mode sequence (4k+2) first driving channels operate in the first mode, the (4k+3)th and the (4k+4)th first driving channels operate in the second mode, and according to the second preset The (4k+3)th and the (4k+4)th second driving channels of the mode sequence operate in the first mode, and the (4k+1)th and (4k+2)th second driving channels operate in the In the second mode, k is a non-negative integer and (m=4i+2), and i is a positive integer. A display device includes: a display panel having a plurality of data channels; a first source driver having m first driving channels for driving the display panel, the first to the nth during a first scanning period The first driving channel drives the first to the nth data channels, wherein each of the first driving channels operates in a first mode or a second mode according to a first preset mode sequence, the first source The pole driver includes: a plurality of first displacement registers respectively corresponding to the first driving channels, and the first displacement registers corresponding to the first driving channels of the first mode are respectively transmitted one by one a first start pulse to enable driving the first driving channels having the first mode; and a plurality of second displacement registers respectively corresponding to the first driving channels and operating in the second mode The second displacement register corresponding to the first driving channel transmits a second starting pulse one by one to enable driving the first driving channels having the second mode; and a second source driver having m Second drive channel Moving the display panel, the first to the mth second driving channels drive the nth to the first data channel during a second scanning period, wherein each of the second driving channels is based on a second pre- Setting a pattern sequence to operate in the first mode or In the second mode, the second source driver includes: a plurality of third displacement registers respectively corresponding to the second driving channels, and the second driving channels operating in the second mode are corresponding to the second driving channels The third shift register transmits the first start pulse one by one to enable driving the second drive channels having the second mode; and the plurality of fourth shift registers respectively corresponding to the second drive channels, and The fourth shift register corresponding to the second driving channels corresponding to the second driving channels of the first mode transmits the second driving pulse one by one to enable driving the second driving channels having the first mode, where m and n Is a positive integer and m≧n. The display device of claim 11, wherein the first source driver further comprises: a plurality of first displacement multiplexers, each of the first displacement multiplexers selecting the corresponding one according to a displacement control signal The first start pulse output by the first displacement register or the second start pulse output by the second displacement register; a plurality of first data multiplexers, each of the first data multiplexers Selecting data on a first bus bar or data on a second bus bar according to a data control signal; and a plurality of first latches, each of the first latches multiplexing according to the corresponding first displacement The start pulse outputted by the device is enabled to operate, and the latch corresponds to the data output by the first data multiplexer. The display device of claim 12, wherein the second source driver further comprises: a plurality of second displacement multiplexers, each of the second displacement multiplexers selecting the first start pulse corresponding to the third displacement register or the corresponding fourth displacement temporary storage according to the displacement control signal The second start pulse outputted by the device; the plurality of second data multiplexers, each of the second data multiplexers selecting the data on the first bus bar or the second bus bar according to the data control signal And a plurality of second latches, each of the second latches being enabled to operate according to a start pulse outputted by the corresponding second shift multiplexer, the latch corresponding to the first outputted data. The display device of claim 13, further comprising: a mode control unit, configured to generate the displacement control signal and the data control signal according to the first preset mode sequence and the second preset mode sequence. The display device of claim 14, wherein the mode control unit controls each of the first displacement multiplexers and each of the first data corresponding to each of the first driving channels of the first mode Selecting the first start pulse and the data on the first bus bar, respectively, and controlling each of the first displacement multiplexers corresponding to each of the first driving channels of the second mode and each of the first The data multiplexer selects the second start pulse and the data on the second bus. The display device of claim 14, wherein the mode control unit controls each of the second displacement multiplexers and each of the second data corresponding to each of the second driving channels of the first mode Separator Selecting the second start pulse and the data on the second bus, and controlling the second shift multiplexer corresponding to each of the second drive channels in the second mode and each of the second data multiplexing The device selects the first start pulse and the data on the first bus. The display device of claim 14, wherein the second source driver further comprises: an exchanger for exchanging data on the first bus bar with data on the second bus bar, The mode control unit controls the second shift multiplexer and the second data multiplexer corresponding to each of the second drive channels of the first mode to select the second start pulse and the first Selecting the first start pulse and the control data in each of the second shift multiplexers and the second data multiplexers corresponding to the second drive channels of the second mode Information on the second bus. The display device of claim 14, wherein the (2k+1)th first driving channel operates in the first mode according to the first preset mode sequence, and the (2k+2)th first The driving channel operates in the second mode, and according to the second preset mode sequence, the (2k+1)th second driving channel operates in the second mode, and the (2k+2)th second driving channel operates In this first mode, k is a non-negative integer. The display device of claim 14, wherein the (4k+1)th first driving channel and the (4k+2)th first driving channel operate according to the first preset mode sequence a mode, the (4k+3)th and the (4k+4)th first driving channels operate in the second mode, and according to the second The (4k+1)th and (4k+2)th second driving channels of the preset mode sequence operate in the first mode, and the (4k+3)th and (4k+4)th second driving channels operate. In this second mode, k is a non-negative integer. The display device of claim 14, wherein the (4k+1)th first driving channel and the (4k+2)th first driving channel operate according to the first preset mode sequence In a mode, the (4k+3)th and the (4k+4)th first driving channels operate in the second mode, and the (4k+3)th and the (4k+) according to the second preset mode sequence 4) a second driving channel operates in the first mode, the (4k+1)th and the (4k+2)th second driving channels operate in the second mode, k is a non-negative integer, and (m=4i +2), i is a positive integer. The display device of claim 11, wherein the display panel has a plurality of scan lines, and each of the scan lines is configured with n pixel units coupled to the first to the nth data channels. The display device of claim 11, wherein the display panel has a plurality of scan lines, and the scan lines are respectively configured with n pixel units coupled to the first to the nth data channels respectively And the other one of the scan lines is configured with n pixel units respectively coupled to the second to the n+1th data channels. The display device of claim 22, wherein the second to the n+1th first driving channels drive the second to the n+1th data channel during a third scanning period And during a fourth scan period, the m-1th to the (mn)th second driving channels drive the second to the n+1th data channel.