TWI418888B - Display panel and alignment method and operation method thereof and color filter substrate - Google Patents

Display panel and alignment method and operation method thereof and color filter substrate Download PDF

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Publication number
TWI418888B
TWI418888B TW98144311A TW98144311A TWI418888B TW I418888 B TWI418888 B TW I418888B TW 98144311 A TW98144311 A TW 98144311A TW 98144311 A TW98144311 A TW 98144311A TW I418888 B TWI418888 B TW I418888B
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Taiwan
Prior art keywords
substrate
electrode layer
display panel
layer
electrode
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TW98144311A
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Chinese (zh)
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TW201122643A (en
Inventor
Cheng Han Tsao
Te Wei Chan
Chung Yi Chiu
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Au Optronics Corp
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Publication of TWI418888B publication Critical patent/TWI418888B/en

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Description

Display panel, alignment method and operation method thereof, and color filter base board

The invention relates to a display panel and an alignment method and an operation method thereof, and particularly relates to a display panel using a Ployd Stabilized Alignment (PSA) technology, and an alignment method and an operation method thereof.

In the development of displays, with the advancement of optoelectronic technology and semiconductor manufacturing technology, liquid crystal displays with superior features such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

The liquid crystal display comprises a backlight module and a liquid crystal display panel, and the conventional liquid crystal display panel is composed of two substrates and a liquid crystal layer filled between the two substrates. In general, in the manufacturing process of a liquid crystal display panel, an alignment film is formed on both substrates to have a specific arrangement of liquid crystal molecules. It is conventional to form an alignment film by first applying an alignment material and then performing an alignment process on the alignment material. The alignment process can be divided into a contact alignment process and a non-contact alignment process. Although the non-contact alignment process can solve the problems of electrostatic problems caused by contact friction alignment and particle contamination, it often causes insufficient anchoring energy of the alignment surface. However, if the anchoring energy of the alignment surface is insufficient, the display quality of the liquid crystal display panel will often be poor.

In order to solve the above problems, a technique of Ployd Stabilized Alignment (PSA) has been proposed. This technology is It is to incorporate a suitable concentration of monomer in the liquid crystal material and to oscillate uniformly. Next, the mixed liquid crystal material is placed on a heater and heated to reach an isotropic state. Then, when the liquid crystal mixture is cooled to room temperature of 25 ° C, the liquid crystal mixture returns to the nematic state. At this time, the liquid crystal mixture was injected into the liquid crystal cell and a voltage was applied. When a voltage is applied to stabilize the alignment of the liquid crystal molecules, the monomer compound is polymerized by ultraviolet light or heating to form a polymer layer, thereby achieving the purpose of stable alignment.

Generally, in the liquid crystal display panel of the PSA, alignment slits are formed in the pixel electrodes of the pixel structure to cause the liquid crystal molecules to have a specific alignment direction. The more the alignment slits in the pixel electrode, the more precisely the alignment of the liquid crystal molecules can be controlled. However, the more the area occupied by the alignment slits, the more the display mura phenomenon, which is mainly due to the alignment slit. The lithography process results in inconsistent slit widths. In more detail, in the lithography etching process of the alignment slit, the boundary between the optical lens groups of the exposure device tends to be inconsistent because the exposure conditions at the place and the exposure conditions at the non-junction are not completely identical, thus causing the The slit width at the point is inconsistent with the width of the other slits. As a result, the brightness of the display panel at these two places is different, resulting in display mura problems.

The invention provides a display panel and a color filter substrate which can be used for the display panel, which can reduce the display panel which is conventionally used by the PSA technology, and the display panel is inconsistent due to the width of the alignment slit formed in the pixel electrode. Uneven problem.

The invention provides an alignment method of a display panel, which is different from the conventional PSA alignment method.

The invention provides a method for operating a display panel, which has better transmittance than a conventional display panel using PSA technology.

The present invention provides a display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes a plurality of pixel structures. The second substrate is located opposite to the first substrate, wherein the second substrate comprises an electrode layer disposed thereon and a patterned electrode layer above the electrode layer, and the electrode layer and the patterned electrode layer are electrically insulated from each other. The liquid crystal layer is located between the first substrate and the second substrate.

The present invention provides a method of aligning a display panel, which first provides a display panel as described above. Next, an alignment voltage is applied to the patterned electrode layer of the second substrate, and the electrode layer of the second substrate is placed in a floating state so that the liquid crystal of the liquid crystal layer has a pretilt angle.

The present invention provides a method of operating a display panel that first provides a display panel as described above. Next, a common voltage is applied to the electrode layer of the second substrate, and the patterned electrode layer of the second substrate is placed in a floating state.

The invention provides a color filter substrate comprising a substrate; a color filter layer on the substrate; an electrode layer on the color filter layer; and a patterned electrode layer on the electrode layer, wherein the patterned electrode layer and the electrode The layers are electrically insulated from one another.

Based on the above, since the present invention provides an electrode layer and an electrode pattern layer on the second substrate of the display panel, and the electrode layer and the electrode pattern layer are mutually connected Electrical insulation. When the aging process of the PSA technique is performed, the alignment voltage is applied to the patterned electrode layer at the same time and the electrode layer is placed in a floating state, so that the effect of aligning the liquid crystal can be achieved. When the operation procedure of the display panel is performed, the common display voltage is applied to the electrode layer, and the patterned electrode layer is placed in a floating state to perform normal display operation on the liquid crystal. The panel design and the matching alignment method and operation method can not only make the liquid crystal panel achieve the same alignment effect as the conventional PSA technology display panel, but also affect the normal display operation, and can also improve the penetration of the display panel. Rate and avoid the problem that the display slits formed in the pixel electrodes may have uneven widths due to the inconsistent width in the display panel conventionally using the PSA count.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention. Referring to FIG. 1 , the display panel of the present embodiment includes a first substrate 100 , a second substrate 110 , and a liquid crystal layer 150 between the first substrate 100 and the second substrate 110 .

The material of the first substrate 100 may be glass, quartz, organic polymer or metal or the like. The pixel substrate array 102 is disposed on the first substrate 100. The pixel array layer 102 is formed by a plurality of pixel structures U1. The layout of each pixel structure U1 is as shown in FIG. 3 . Shown. In more detail, please refer to FIG. 1 , FIG. 2A and FIG. 3 simultaneously, the pixel array layer 102 Each pixel structure U1 includes a scan line SL and a data line DL, an active device T, a storage capacitor electrode line 202, an upper electrode pattern 204, and a pixel electrode P.

The scan line SL and the data line DL are located on the first substrate 100. The scanning line SL and the data line DL extend in different directions. Further, the scanning line SL and the data line DL are located on different film layers with an insulating layer interposed therebetween. The scan line SL and the data line DL are mainly used to transmit a driving signal for driving the pixel structure.

The active device T is electrically connected to the scan line SL and the data line DL. Here, the active element T is, for example, a thin film transistor comprising a gate G, a channel layer CH, a source S and a drain D. The gate G is electrically connected to the scan line SL, the source S is electrically connected to the data line DL, and the channel layer CH is located above the gate and below the source S and the drain D. The active device T of the present embodiment is described by taking a bottom gate type thin film transistor as an example, but the present invention is not limited thereto. In other embodiments, the active device T can also be a top gate type thin film transistor.

The storage capacitor electrode line 202 is located on the first substrate 100. The storage capacitor electrode line 202 extends in a direction parallel to the scanning line SL. In the present embodiment, the storage capacitor electrode line 202 can be formed simultaneously with the scan line SL, and thus the storage capacitor electrode line 202 and the scan line SL belong to the same film layer. According to an embodiment of the invention, the capacitive electrode lines 202 in each pixel structure are electrically connected to a common voltage.

The upper electrode pattern 204 is located above the storage capacitor electrode line 202. In more detail, the upper electrode pattern 204 and the capacitor electrode line 202 are both heavy The stack is disposed with an insulating layer (not shown) therebetween for electrically isolating the upper electrode pattern 204 from the storage capacitor electrode line 202. In the present embodiment, the upper electrode pattern 204 is formed simultaneously when the data line DL is formed, and thus the upper electrode pattern 204 and the data line DL belong to the same film layer.

According to an embodiment of the present invention, in this pixel structure U1, a mask line 205 is further included. The shielding line 205 is disposed in parallel with the data line DL and is located at an intermediate position of the pixel structure U1. In the present embodiment, the shielding line 205 is formed simultaneously with the data line DL and the upper electrode pattern 204, and thus the shielding line 205 can be directly connected to the upper electrode pattern 204. However, the present invention is not limited thereto, and in another embodiment, the shielding line 205 may not be connected to the upper electrode pattern 204. It is worth mentioning that the shielding line 205 mainly functions to prevent the display phenomenon caused by the tilting of the liquid crystal molecules located above the shielding line 205 from being seen by the human eye. Therefore, designing the shielding line 205 can make the liquid crystal display panel have better display quality, but the present invention does not limit the use of the shielding line. In other words, in other embodiments, the fabrication of the masking line 205 can also be omitted.

The pixel electrode P is electrically connected to the active device T. In this embodiment, the pixel electrode P is electrically connected to the drain D of the active device T. In more detail, where the pixel electrode P overlaps with the drain D of the active device T, the contact window C1 is further provided to electrically connect the pixel electrode P and the drain D. In addition, the pixel electrode P covers the capacitor electrode line 202 and the upper electrode pattern 204, and an insulating layer (not shown) is interposed between the pixel electrode P and the upper electrode pattern 204. In addition, a contact window C2 is formed between the pixel electrode P and the upper electrode pattern 204 to electrically connect the pixel electrode P and the upper electrode pattern 204. connection. In other words, the pixel electrode P can be brought to a common potential with the upper electrode pattern 204 by the contact window C2. In addition, the charge of the pixel electrode P can be stored therein by the electrical coupling relationship between the upper electrode pattern 204 and the capacitor electrode line 202, so that the storage capacitor of the pixel structure U1 can be constructed. It is worth mentioning that an alignment pattern (orientation protrusion or alignment slit) is not provided on the pixel electrode P of the pixel structure U1.

Referring to FIG. 1 again, the material of the second substrate 110 may be glass, quartz or an organic polymer or the like. The second substrate 110 includes an electrode layer 112 and a patterned electrode layer 116. The electrode layer 112 and the patterned electrode layer 116 are electrically insulated from each other. In this embodiment, the electrode layer 112 is a transparent conductive layer, and the material thereof includes a metal oxide such as indium tin oxide or indium zinc oxide. The electrode layer 112 is entirely covered on the second substrate 110. In addition, the patterned electrode layer 116 is also a transparent conductive material, which may be a metal oxide such as indium tin oxide or indium zinc oxide. Since the patterned electrode layer 116 is a patterned film layer, it is not completely covered on the second substrate 110. In the present embodiment, an insulating layer 114 is further disposed between the electrode layer 112 and the patterned electrode layer 116 for electrically insulating the electrode layer 112 from the patterned electrode layer 116.

According to a preferred embodiment of the present invention, the second substrate 110 can also be divided into a plurality of unit regions U2, as shown in FIG. 2B, wherein each of the unit regions U2 corresponds to the pixel array layer 102 on the first substrate 100. One pixel structure U1 is set. In more detail, the second substrate 110 has a light transmitting region 302 and a light blocking region 304, and the light shielding region 304 surrounds the light transmitting region 302, and thus each of the light transmitting regions 302 may be referred to as a unit region U2.

In the present embodiment, the pattern of the patterned electrode layer 116 on the second substrate is designed corresponding to one unit region U2. 4 is a top plan view of a patterned electrode layer 116 in a cell region U2 in accordance with an embodiment of the present invention, and FIG. 5 is a top view of electrode layer 112 in a cell region U2 in accordance with an embodiment of the present invention. Referring to FIG. 4 and FIG. 5 simultaneously, the electrode layer 112 illustrated in FIG. 5 is a complete and unpatterned electrode layer, and the patterned electrode layer 116 illustrated in FIG. 4 has a plurality of slit patterns formed therein. In more detail, the patterned electrode layer 116 has a main slit 310 and a plurality of branch slits 312 connected to the main slit 310. Moreover, the branch slit 312 is an autonomous slit 310 extending in four directions. In other words, the branch slit 312 extends from the main slit 310 to the periphery of the unit region U2.

Further, in the present embodiment, the main slit 310 includes a horizontally extending slit 310a and a vertically extending slit 310b. Here, the horizontally extending slit 310a in the patterned electrode layer 116 is disposed to overlap the capacitive electrode line 202 (shown in FIG. 3) in the pixel structure U1 on the first substrate 100. In addition, the vertically extending slit 310b in the patterned electrode layer 116 is disposed to overlap the masking line 205 (shown in FIG. 3) in the pixel structure U1 on the first substrate 100. Therefore, the horizontally extending slit 310a and the vertically extending slit 310b are substantially in a cross shape in the unit area U2.

Referring back to FIG. 1 , the liquid crystal layer 150 between the first substrate 100 and the second substrate 110 includes liquid crystal molecules. Since the display panel of the present embodiment is a display panel using PSA technology, a monomer compound is included in the liquid crystal layer 150 in addition to liquid crystal molecules. In other words, when the display panel has not been subjected to the aging process of the monomer compound, the liquid crystal layer 150 includes There are liquid crystal molecules as well as monomeric compounds. When the display panel is subjected to a curing process of the monomer compound, the monomer compound undergoes polymerization to form a polymer film on the surface of the pixel array layer 102 and the patterned electrode layer 116, so when the display panel is subjected to a monomer After the aging process of the compound, the liquid crystal layer 150 is mainly liquid crystal molecules.

In the above embodiment, the second substrate 110 mainly includes an electrode layer 112 and a patterned electrode layer 116. According to another embodiment of the present invention, the second substrate 110 may further include a color filter layer 120. As shown in FIG. 6, the color filter layer 120 includes red, green, and blue filter patterns (not shown). Shown), it is disposed in the light transmitting area 302 shown in FIG. 2B. In addition, the color filter layer 120 may further include a light shielding pattern layer (not shown), which may also be referred to as a black matrix, which is disposed between the red, green, and blue filter patterns, that is, disposed in FIG. 2B. In the shaded area 304 shown.

As described above, in the embodiment of FIG. 6, the second substrate 110 and the film layer formed thereon constitute a so-called color filter substrate 160, which includes the substrate 110, the color filter layer 120, the electrode layer 112, and The electrode layer 116 is patterned. The color filter layer 120 is located on the substrate 110. The electrode layer 112 is located on the color filter layer 120, and the patterned electrode layer 116 is located on the electrode layer 112. The patterned electrode layer 116 and the electrode layer 112 are electrically insulated from each other. In the preferred embodiment, the insulating layer 114 is disposed between the patterned electrode layer 116 and the electrode layer 112 to electrically insulate the patterned electrode layer 116 from the electrode layer 112 from each other.

In the embodiment of FIG. 6 , the color filter layer 120 is disposed between the second substrate 110 and the electrode layer 112 . However, the invention is not limited thereto. root According to other embodiments of the present invention, the above color filter layer may also be disposed in the pixel array layer 102 of the first substrate 100, so that the pixel array layer 102 constitutes a so-called color filter structure on the array (color Filter on array, COA).

FIG. 7 is a schematic diagram of a method of aligning a display panel according to an embodiment of the invention. The embodiment of FIG. 7 is exemplified by the display panel of the embodiment of FIG. 1. However, the alignment method of the present invention is not limited to the display panel shown in FIG. 1, and can be applied to other embodiments. The display panel is, for example, the display panel of the embodiment shown in FIG. 6. Referring to FIG. 7, the alignment method of the display panel of the present embodiment includes applying an alignment voltage Va to the patterned electrode layer 116 on the second substrate 110, and placing the electrode layer 112 on the second substrate 110 in a floating state. The liquid crystal molecules in the liquid crystal layer 150 have a pretilt angle.

In more detail, when the curing process of the PSA technique is performed, the alignment voltage Va of the patterned electrode layer 116 on the second substrate 110 is simultaneously applied, and the electrode layer 112 on the second substrate 110 is floated. Set the status. In this embodiment, when the alignment voltage Va is applied to the patterned electrode layer 116 on the second substrate 110 and the electrode layer 112 on the second substrate 110 is in a floating state, the first substrate 100 is further included. The pixel electrode in the pixel array layer 102 is grounded. At this time, the liquid crystal molecules in the liquid crystal layer 150 generate a predetermined alignment effect due to the action of the alignment voltage Va of the patterned electrode layer 116, and at the same time, the monomer compounds in the liquid crystal layer 150 are simultaneously polymerized to form a polymer film. . Therefore, after completing the curing process of the PSA technology, the liquid crystal molecules in the liquid crystal layer 150 can be reached. To the intended alignment effect.

FIG. 8A is a schematic diagram of a method of aligning a display panel according to an embodiment of the invention. The embodiment of FIG. 8A is illustrated by taking the display panel of the embodiment of FIG. 1 as an example, but the alignment method of the present invention is not limited to the display panel shown in FIG. 1 , and can be applied to other embodiments. The display panel is, for example, the display panel of the embodiment shown in FIG. 6. Referring to FIG. 8A, the method for operating the display panel of the present embodiment includes applying a common voltage Vc to the electrode layer 112 on the second substrate 110, and placing the patterned electrode layer 116 on the second substrate 110 in a floating state. At this time, each pixel structure in the pixel array layer 102 on the first substrate 100 will cause a specific twisting behavior of the liquid crystal layer above each pixel structure according to the action of the driving signal thereof to make the display panel specific. The image is displayed.

In the display panel of the present embodiment, although the patterned electrode layer 116 is provided on the electrode layer 112, it mainly applies a voltage to the electrode layer 112 when performing a display operation. Therefore, the liquid crystal molecules in the liquid crystal layer 150 generate a specific twisting behavior according to the electric field between the electrode layer 116 and the pixel array layer 102. In other words, the patterned electrode layer 116 does not affect the normal display operation of the display panel. In addition, since no alignment pattern is formed in the pixel electrodes in the pixel array layer 102, the display panel has better transmittance than the display panel using the PSA technology (for example, the display panel can be increased by 9%). Light transmittance). Moreover, since no alignment pattern is formed in the pixel electrodes in the pixel array layer 102, it can be avoided that the alignment slit formed in the pixel electrode may have an inconsistent width in the display panel using the PSA technology. Causes uneven display.

FIG. 8B is a schematic diagram of a method of aligning a display panel according to an embodiment of the invention. The embodiment of FIG. 8B is exemplified by the display panel of the embodiment of FIG. 1. However, the alignment method of the present invention is not limited to the display panel shown in FIG. 1, and can be applied to other embodiments. The display panel in the display panel is, for example, the display panel of the embodiment shown in FIG. 6. Referring to FIG. 8B, the method for operating the display panel of the present embodiment includes simultaneously applying a common voltage Vc to the electrode layer 112 and the patterned electrode layer 116 on the second substrate 110. At this time, each pixel structure in the pixel array layer 102 on the first substrate 100 will cause a specific twisting behavior of the liquid crystal layer above each pixel structure according to the action of the driving signal thereof to make the display panel specific. The image is displayed.

Similarly, although the patterned electrode layer 116 is provided on the electrode layer 112, when the display operation is performed, the voltage is simultaneously applied to the electrode layer 112 and the patterned electrode layer 116. Therefore, the liquid crystal molecules in the liquid crystal layer 150 are subjected to a specific twisting behavior according to the electric field between the electrode layer 116/electrode layer 112 and the pixel array layer 102. In other words, the patterned electrode layer 116 does not affect the normal display operation of the display panel. In addition, since no alignment pattern is formed in the pixel electrodes in the pixel array layer 102, the display panel has better light transmittance than the conventional display panel using the PSA technology. Moreover, since no alignment pattern is formed in the pixel electrodes in the pixel array layer 102, it can be avoided that the alignment slit formed in the pixel electrode may have an inconsistent width in the display panel using the PSA technology. Causes uneven display.

Although the invention has been disclosed above by way of example, it is not intended to be limiting The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. Prevail.

100‧‧‧First substrate

102‧‧‧ pixel array

110‧‧‧second substrate

112‧‧‧electrode layer

114‧‧‧Insulation

116‧‧‧ patterned electrode layer

120‧‧‧Color filter layer

150‧‧‧Display media

160‧‧‧Color filter substrate

SL‧‧‧ scan line

DL‧‧‧ data line

T‧‧‧ active components

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

CH‧‧‧ channel layer

P‧‧‧ pixel electrodes

C1, C2‧‧‧ contact window

U1‧‧‧ pixel structure

U2‧‧‧ unit area

202‧‧‧Capacitive electrode line

204‧‧‧Upper electrode pattern

205‧‧ ‧ shading line

302‧‧‧Light transmission area

304‧‧‧ shading area

310‧‧‧Main slit

310a‧‧‧ horizontal extension slit

310b‧‧‧Vertically extending slit

312‧‧‧ branch slit

Va‧‧‧ Alignment voltage

Vc‧‧‧Common voltage

1 is a schematic cross-sectional view of a display panel in accordance with an embodiment of the present invention.

2A is a top plan view of the pixel array layer of FIG. 1.

2B is a top plan view of the second substrate of FIG. 1.

3 is a top plan view of a pixel structure in a pixel array layer in accordance with an embodiment of the present invention.

4 is a top plan view of a patterned electrode layer in a cell region in accordance with an embodiment of the present invention.

Figure 5 is a top plan view of an electrode layer in a cell region in accordance with an embodiment of the present invention.

6 is a cross-sectional view of a display panel in accordance with another embodiment of the present invention.

FIG. 7 is a schematic diagram of a method of aligning a display panel according to an embodiment of the invention.

8A and 8B are schematic diagrams showing a method of operating a display panel according to an embodiment of the present invention.

100‧‧‧First substrate

102‧‧‧ pixel array

110‧‧‧second substrate

112‧‧‧electrode layer

114‧‧‧Insulation

116‧‧‧ patterned electrode layer

150‧‧‧Display media

Claims (20)

  1. A display panel includes: a first substrate, the first substrate includes a plurality of pixel structures; and a second substrate disposed opposite the first substrate, wherein the second substrate includes an electrode layer and is disposed One of the electrode layers is patterned with an electrode layer that completely covers the second substrate, and the electrode layer and the patterned electrode layer are electrically insulated from each other; and a liquid crystal layer is located on the first substrate Between the second substrates.
  2. The display panel of claim 1, wherein the second substrate further comprises an insulating layer between the electrode layer and the patterned electrode layer.
  3. The display panel of claim 1, wherein the patterned electrode layer of the second substrate has a unit region corresponding to each pixel structure of the first substrate, and the patterning in each unit region The electrode layer has a main slit and a plurality of branch slits connected to the main slit.
  4. The display panel of claim 3, wherein the branch slits extend from the main slit in four directions.
  5. The display panel of claim 3, wherein the main slit comprises a horizontally extending slit and a vertically extending slit.
  6. The display panel of claim 5, wherein each pixel structure of the first substrate comprises: a scan line and a data line; an active component electrically connected to the scan line and the data line a pixel electrode electrically connected to the active component; a capacitor electrode line located below the pixel electrode; and an upper electrode pattern between the capacitor electrode line and the pixel electrode.
  7. The display panel of claim 6, wherein the horizontally extending slit of the main slit is disposed to overlap the capacitive electrode line.
  8. The display panel of claim 6, wherein the pixel structure further comprises a shielding line, and the shielding line is disposed to overlap the vertical extending slit of the main slit.
  9. The display panel of claim 6, wherein the pixel electrode is not provided with an alignment pattern.
  10. The display panel of claim 1, further comprising a color filter layer disposed on the first substrate or the second substrate.
  11. The display panel of claim 10, wherein the color filter layer is located below the electrode layer of the second substrate.
  12. A method for aligning a display panel, comprising: providing a display panel as described in claim 1; applying an alignment voltage to the patterned electrode layer of the second substrate, and causing the second substrate The electrode layer is in a floating state such that the liquid crystal of the liquid crystal layer has a pretilt angle.
  13. The method of aligning a display panel according to claim 12, wherein each pixel structure on the first substrate has a pixel electrode, and when the patterned electrode layer of the second substrate is applied When the voltage is aligned and the electrode layer of the second substrate is in a floating state, the pixel electrodes of the first substrate are further grounded.
  14. A method of operating a display panel, comprising: providing a display panel as described in claim 1; applying a common voltage to the electrode layer of the second substrate, and patterning the second substrate The electrode layer is in a floating state.
  15. The method of operating the display panel of claim 14, wherein the applying the common voltage to the electrode layer of the second substrate further comprises simultaneously applying the patterned electrode layer to the second substrate. The common voltage.
  16. A color filter substrate comprising: a substrate; a color filter layer on the substrate; an electrode layer on the color filter layer and covering the substrate in a comprehensive manner; and a patterned electrode layer at the electrode On the layer, wherein the patterned electrode layer and the electrode layer are electrically insulated from each other.
  17. The color filter substrate of claim 16, further comprising an insulating layer between the electrode layer and the patterned electrode layer.
  18. The color filter substrate of claim 16, wherein the substrate has a plurality of unit regions, and the patterned electrode layer in each unit region has a main slit and is connected to the main slit Branch slits.
  19. The color filter substrate of claim 18, wherein the branch slits extend from the main slit in four directions.
  20. The color filter substrate of claim 18, wherein the main slit comprises a horizontally extending slit and a vertically extending slit.
TW98144311A 2009-12-22 2009-12-22 Display panel and alignment method and operation method thereof and color filter substrate TWI418888B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200532284A (en) * 2004-03-19 2005-10-01 Toppoly Optoelectronics Corp Transmissive liquid crystal display
TW200641494A (en) * 2005-05-18 2006-12-01 Au Optronics Corp Pixel structure and active device array substrate
CN101097925A (en) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 Thin film transistor substrate of horizontal electric field applying type and fabricating method thereof
TW200846784A (en) * 2007-05-25 2008-12-01 Au Optronics Corp Liquid crystal panel, thin film transistors array substrate and curing line structure thereof in use of phase separation alignment process
TW200919002A (en) * 2007-10-18 2009-05-01 Au Optronics Corp Pixel structure and manufacturing method of liquid crystal display panel having the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200532284A (en) * 2004-03-19 2005-10-01 Toppoly Optoelectronics Corp Transmissive liquid crystal display
TW200641494A (en) * 2005-05-18 2006-12-01 Au Optronics Corp Pixel structure and active device array substrate
CN101097925A (en) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 Thin film transistor substrate of horizontal electric field applying type and fabricating method thereof
TW200846784A (en) * 2007-05-25 2008-12-01 Au Optronics Corp Liquid crystal panel, thin film transistors array substrate and curing line structure thereof in use of phase separation alignment process
TW200919002A (en) * 2007-10-18 2009-05-01 Au Optronics Corp Pixel structure and manufacturing method of liquid crystal display panel having the same

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