TWI414944B - Memory device, host device, memory system, memory device control method, host device control method, and memory system control method - Google Patents

Abstract

A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.

Description

Memory device, host device, memory system, control method of memory device, control method of host device, and control method of memory system

The present invention relates to a memory device including a semiconductor memory unit, a host device, a memory system, a method of controlling a memory device, a method of controlling a host device, and a method of controlling a memory system, and more particularly, a voltage that can change a data transmission signal Memory device, etc.

In recent years, the development of flash memory cards for semiconductor memory devices such as non-volatile semiconductor memory media has been widely used as an external memory device for information devices such as digital cameras of host devices. As the amount of data processed by the host device increases, the capacity of the flash memory is increased and the density is increased.

The NAND-type flash memory system is characterized by a large capacity, and in recent years, it is particularly useful for flash memory that is often used for archival memory applications.

The NAND type flash memory system is injected into the floating gate or the doped layer composed of the laminated film via the channel insulating film, in other words, the charge injected into the charge accumulation layer, and the amount of charge is used as the bit bit information utilization. And read as a 2-value or multi-value information. The NAND-type flash memory system is different from the memory of the DRAM-destroying read-out type, and is not accompanied by data corruption and can read data.

In semiconductor memory devices, the speed of writing and reading speed is required to be increased, and the speed of the bus bar transmission speed of the transmission bus is also required to be increased. Therefore, for example, it is prescribed to increase the transmission clock frequency of the memory card bus from the 25 MHz of the normal mode to the specification of the high-speed mode of 50 MHz, thereby realizing higher-speed data transmission.

On the other hand, Japanese Laid-Open Patent Publication No. 2007-11788 discloses a data transmission in a high speed, which is transmitted and received in synchronization with a rising edge and a falling edge of a clock signal supplied from a host device, in the same manner as the high speed mode. The clock frequency provides a memory card that can further obtain 2 times the data transmission speed in the ultra-high speed mode.

However, if the transmission clock frequency is increased, the unnecessary electromagnetic wave is shielded, that is, the countermeasure against EMI (Electro Magnetic Susceptibility) constitutes a problem. Moreover, if the transmission clock frequency is increased, there is also a problem that the power consumption of the memory card increases.

In order to solve such problems, it is effective to reduce the signal voltage of the transmission/reception signal between the memory card and the host device. However, when switching the signal voltage of the transmission/reception signal, a voltage higher than the assumption is applied, which may damage the I/O cell of the memory card or the host device.

According to an aspect of the invention, there is provided a memory device which is connectable to a host device and which has the following. a non-volatile memory portion; the first I/O cell can be connected to the host device via the command signal line, the response signal line, the clock signal line, or the data signal line, respectively, to be from the first voltage and lower than the first voltage a signal voltage transmission/reception command signal, a response signal, a clock signal, and a data signal selected by the second voltage; a first regulator that outputs the first voltage and the second voltage; and a memory controller Receiving, from the host device, a command signal for switching the signal voltage from the first voltage to the second voltage, transmitting the signal voltage to the host device by using the response signal, and outputting the voltage of the first regulator from the first The voltage is switched to the second voltage. After a certain period of time, the second voltage is applied to the response signal line and the data signal line at the ground level after detecting that the voltage is applied to the clock signal line other than the ground level. The signal voltage of the second voltage starts to be transmitted/received.

<First embodiment>

Hereinafter, a memory card 100, a host device 200, and a memory system 1 having a memory card 100 and a host device 200, which are memory devices of the first embodiment of the present invention, will be described with reference to the drawings.

1 is a schematic view showing the configuration of a memory system 1 composed of a memory card 100 and a host device 200; and FIG. 2 is a block diagram showing the configuration of a power supply circuit portion of the memory system 1.

As shown in FIG. 1, the memory card 100 is connectable to the host device 200 and functions as an SD memory card (registered trademark) of an external memory device connected to the host device 200 of the host device 200. As the host device 200, an information processing device including a personal computer or a digital camera that processes various kinds of data such as image data or music data can be cited. The host device 200 has an I/O cell 209 for performing command signals, response signals, clock signals, and data signals, that is, transmission/reception of transmission signals, with the connected memory card 100, and a host control unit. 251, which is a control for transmitting/receiving a transmission signal.

Further, the memory card 100 includes a memory unit 150 which is composed of a non-volatile memory, and a memory controller 151 which controls the transmission and reception of the memory unit 150 and the transmission signal, and the output of the data. The I/O cell 121 and the connector 152 (including pin 1 to pin 9) are used. The memory controller 151 is connected to the memory unit 150 via, for example, a busbar of an 8-bit busbar width.

If the memory card 100 is mounted on the host device 200, the connector 152 is electrically connected to the host device 200. The distribution of the signal line to the pin 1 to the pin 9 included in the connector 152 is defined by the specification of the SD memory card (registered trademark).

That is, the data DAT0, DAT1, DAT2, and DAT3 for transmitting/receiving the data signals are assigned to the pins 7, the pins 8, the pins 9, and the pins 1, respectively. Moreover, the pin 1 is also assigned to the card detection signal CD. The command signal CMD and the response signal RES of the memory card 100 for the command signal, that is, the response signal RES are assigned to the pin 2. The clock signal CLK is assigned to the pin 5. The power supply voltage VDD is assigned to the pin 4, the ground voltage VSS1 is assigned to the pin 3, and the ground voltage VSS2 is assigned to the pin 6.

Further, in the memory card 100 of the present embodiment, the memory portion 150 is a non-volatile semiconductor memory composed of a NAND type flash memory. The data transmitted from the host device 200 is stored in the memory unit 150.

Further, as shown in FIG. 2, the bus line for transmitting/receiving signals and the like between the memory card 100 and the host device 200 includes the CLK line 111 (hereinafter also referred to as "clock signal line") and the CMD/RES line 112 (hereinafter also referred to as "CMD line"), DAT[3:0] line 113 and VDD line (hereinafter also referred to as "power line"), and DAT1 line, DAT2 line, CD/DAT3 line, VSS1 line, and VSS2 line (not shown) . In addition, the following is an example of a DAT0 line (hereinafter also referred to as "data line") as a data signal line. Moreover, the CMD/RES line is also referred to as a command signal line or a response signal (RES) line. That is, the command signal line and the response signal line are the same one signal line.

The operation mode (hereinafter also referred to as "transmission mode") at the time of data transmission of the memory card 100 as an SD memory card (registered trademark) is defined by the SD mode and the SPI mode. Further, the transmission mode of the SD mode is defined by two types of the 1-bit mode using the data DAT0 and the 4-bit mode using the data DAT0 to DAT3. In addition, the transmission mode of the memory card 100 is based on the transmission clock frequency and the like, and in addition to the normal speed mode (NSM) which specifies the normal transmission speed and the high speed mode (HSM) which is twice the NSM, the HSP is further specified twice. Extremely high speed mode (UHSM).

Then, as shown in FIG. 2, the memory card 100 of the memory system 1 has a regulator (VR2) 116 as a first regulator; the host device 200 of the memory system 1 has a regulator (VR1) as a second regulator. 204. Therefore, in the memory system 1, in addition to the voltage mode corresponding to the memory system 1, that is, the signal voltage of the standard 3.3V (hereinafter referred to as "3.3V mode"), the memory system 1 corresponds to the power supply voltage maintenance standard. 3.3V, and the signal voltage of the data transmission is set to a mode of 1.8V of lower voltage (hereinafter referred to as "1.8V mode").

That is, the memory card 100 has a multi-drive type first I/O cell 121 that can be connected to the host device 200 from a first voltage (3.3V) and a second voltage lower than the first voltage (1.8V). Any one of the selected signal voltages, the transmit/receive command signal, the response signal, the clock signal, and the data signal; and the first adjuster 116 that outputs the first voltage and the second voltage; the host device 200 has: The card 100 has the second I/O cell 209 and the second regulator 204 of the multi-drive type of the same specification.

In FIG. 2, a power switch (PSW) 201 is a switch that turns on/off a power supply voltage (VDD) applied to the memory card 100. The band gap reference (BGR) 115 and 203 are reference voltage generating circuits that utilize the potential difference of the band gap. Although the noise filters 114 and 201 are unnecessary components, they are effective for preventing noise from the power supply line (VDD) to generate a more stable reference voltage. Then, the first regulator (VR2) 116 and the second regulator (VR1) 204 are 1.8V voltage regulators from a 3.3V power supply voltage, and 1.8V is generated based on the reference voltage of BGR115 or 203, respectively. The voltage.

The third regulator (VR3) 122, which is a voltage generating circuit used as the core of the internal logic circuit, generates a voltage supplied to the random logic unit 123. The random logic unit 123 has circuits such as the memory controller 151, the ROM, and the RAM shown in FIG. 1. The host device 200 also has a voltage generating circuit for internal logic, but is not shown. The comparator (VDCLK) 120, which is the first voltage comparison circuit, detects whether the voltage of the CLK line is 1.8V. Further, the comparator (VDCMD/RES) 208 as the second voltage comparison circuit detects whether or not the voltage of the CMD/RES line is 1.8V. In contrast, the comparator 119 as the third voltage comparison circuit or the comparator 207 as the fourth voltage comparison circuit detects 1.8V from the first regulator (VR2) 116 or the second regulator (VR1) 204, respectively. Whether the voltage is generated correctly.

Further, here, the second voltage of 1.8 V means that the second voltage is in the range of 1.65 V to 1.95 V. Moreover, the comparator that detects the first voltage or the second voltage is a voltage comparator having a third threshold voltage between the first voltage and the second voltage, and the voltage at the measurement line is higher than the third In the case of the limit voltage, the first voltage is determined, and when the voltage of the measurement line is lower than the third threshold voltage, the second voltage is determined.

When the signals of the boosting resistors 224 and 225 in the bus bar line are tri-stated, the voltage of each line is maintained at 3.3 V or 1.8 V. Further, the capacitors 118 and 206 accumulate charges for stabilizing a specific voltage.

Next, the switching operation of the signal voltage of the memory system 1 will be described with reference to FIGS. 3A, 3B, and 4. 3A and 3B are flowcharts for explaining the switching operation of the signal voltage of the memory system 1. FIG. 4 is a timing chart of the signal line group (bus bar) when the signal voltage of the memory system 1 is switched.

The host device 200 performs a switching processing operation in consideration of compatibility with a memory card that supports only a 3.3V mode memory card. That is, if the host device 200 applies a signal voltage of 1.8 V from the beginning of the connected memory card, only the input I/O cell supporting the 3.3 V mode memory card recognizes the applied 1.8 V as the intermediate voltage. Therefore, the input I/O cell of the memory card may have a large tunneling current.

Therefore, the host device 200 transmits a signal of a signal voltage of 3.3 V to the memory card in advance, and the memory card is detected by the handshake processing described later, and is detected as a memory card supporting the 1.8V mode, and then switched to the 1.8V mode. The program.

Hereinafter, the switching operation of the signal voltage of the memory system 1 will be described with reference to the flowcharts of FIGS. 3A and 3B. 3A and 3B show the operation flow of the host device 200, and the right side shows the operation flow of the memory card 100.

<Step S10> The memory card is connected to the host device

The memory card 100 is connected to the host device 200. That is, the I/O cells 121 of the memory card 100 and the I/O cells 209 of the host device 200 are composed of command/response signal lines, clock signal lines, and data signal lines by the lines 111 to 113 constituting the bus interface. Wait for the connection.

<Step S11> CMD8

When the host device 200 supporting the 1.8V mode is supported, the host device 200 inquires whether or not the connected memory card 100 is the memory card 100 supporting the 1.8V mode. That is, the command CMD8 is initially issued from the host device 200 (FIG. 4: T1). The argument of CMD8 is set to a bit that requires transfer to the 1.8V mode. Therefore, the command signal CMD8 transmitted from the host device 200 to the memory card 100 also switches the signal voltage from the first voltage (3.3V) to the first. Two voltage (1.8V) command signals.

<Step S12> Support 1.8V?

The memory card 100 determines whether the memory card 100 corresponds to the 1.8V mode in the case where the command signal CMD8 is received from the host device.

<Step S13> Non-support RES1.8V/Support RES1.8V

When the memory card 100 does not support the 1.8V mode (step S12: NO), the memory card 100 replies to the host device 200 with a response signal indicating that the 1.8V mode is not supported.

On the other hand, when the memory card 100 supports the 1.8V mode (step S12: YES), the memory card 100 replies to the host device 200 with a response signal indicating that the mode is switched to the 1.8V mode (FIG. 4: T2).

<Step S14> Support 1.8V?

When the host device 200 receives a response signal indicating that the 1.8V mode is not supported from the memory card 100 (No), the initialization process in the 3.3V mode is started in S33.

On the other hand, when the host device 200 receives the response signal indicating that the 1.8V mode is supported from the memory card 100 (Yes), the host device 200 performs a process of transmitting the next transmission signal based on the content of the received signal, that is, the handshake is performed. deal with.

<Step S15> CMD/RES drive is 0V

The memory card 100 sets the CMD line to the L level (ground level: 0V) after transmitting the response signal (Fig. 4: T3).

<Step S16> CLK is stopped and driven to 0V, and the drive is DAT0V.

The host device 200 sets the DAT line to the L level (ground level: 0V) (Fig. 4: T4), and stops the clock oscillation, and the CLK line is also set to the L level (ground level: 0V) (Fig. 4: T5). In addition, on the DAT line and the CLK line, any line can be set to the L level first.

Here, the CMD line, the CLK line, and the DAT line are set to the L level (0 V), that is, the drive is the L level (0 V), and a voltage that is unstable is applied to prevent the respective lines from being tri-stated. During the voltage switching period, if an unstable voltage is applied to the I/O cell 121 or the like, there is a risk that a tunneling current flows to the I/O cell 121 or the like. Therefore, the host device 200 or the memory card 100 fixes the voltage of the signal line to the L level (0 V) in advance.

<Step S17, Step S18> Switching VR1 and VR2 from 3.3V to 1.8V

The memory card 100 is switched to adjuster VR2 to generate 1.8V. Moreover, the host device 200 switches to the regulator VR1 to generate 1.8V.

<Step S19, Step S20> Timer Adjustment

The host device 200 waits until a specific time elapses (FIG. 4: T5 to T6). Therefore, for example, a timer of 100 microseconds is adjusted.

This is because it has to wait for the capacitors 206 or 118 connected to the regulator VR1 and the regulator VR2, respectively, to discharge from the state of charging 3.3V to the state of charging 1.8V. Of course, it is also possible to have a circuit for actively discharging the capacitor 206 or 118. However, since the discharge time is sufficiently short in a human sense, the memory system 1 is not provided with a discharge circuit. Further, in the above description, although the standby time is set to be 100 microseconds, the standby time varies depending on the specifications of the capacitor 206 or 118, and is approximately 10 to 500 microseconds.

<Step S21> Driving CLK to 1.8V-DC

The host device 200 is set to a clock signal line of the ground level after the elapse of 100 microseconds in the above-described example for a predetermined period of time (Fig. 4: T6). Here, the host device 200 is usually connected to a clock signal line that transmits a clock signal, and applies a 1.8V DC signal. Then, the host device 200 communicates to the memory card 100 that a signal voltage of 1.8 V can be supplied from the adjuster VR2. <Step S22> CLK is 1.8V?

When the memory card 100 applies a voltage to the clock signal line, it is confirmed by the comparator 120 as the first voltage comparison circuit whether or not the signal voltage is 1.8V. When the voltage of 1.8 V is not applied to the clock signal line (No), the memory card 100 does not perform the subsequent voltage switching process, and in step S32, the memory card 100 stops operating.

<Step S23> Driving CMD/RES to 1.8V-DC

In the case where it is confirmed in step S22 that the signal voltage of the clock signal line is 1.8 V (Yes), the memory card 100 drives the CMD/RES line (response signal line) of the ground level to 1.8 V (Fig. 4: T7). Here, the memory card 100 is usually connected to a response signal line that transmits an RES signal, and a 1.8V DC signal is applied.

<Step S24> Timer adjustment

The host device adjusts the timer after setting the signal voltage of the clock signal line to 1.8V.

<Step S25> The CMD line is 1.8V?

When a voltage is applied to the CMD/RES line, the host device 200 detects whether the signal voltage of the CMD/RES signal line is 1.8 V by the comparator (VDCMD/RES) 208 as the second voltage comparison circuit.

<Step S26, Step S27>

The host device 200 is in a case where a voltage of 1.8 V is not applied to the clock signal line even after a specific time elapses, for example, 100 microseconds (NO), the power switch (PSW) 201 is turned off in step S27, and the memory card 100 is stopped. action.

As described above, the memory system 1 of the present embodiment is in the middle of the handshake processing of the voltage switching process, and even if the memory card 100 or the host device 200 does not perform a specific action after a certain time has elapsed, It is not possible to switch to 1.8V, for example, output error code or perform initialization processing of 3.3V mode. An example of this is shown in FIG.

Fig. 5 is a timing chart showing a case where the memory card 100 does not drive the CMD/RES line (response signal line) to 1.8 V in step S23. The host device 200 applies a voltage of 1.8 V to the clock signal line, and waits for a response from the memory card 100, that is, waits for the response signal line to become 1.8 V from 0 V (ground level). However, the host device 200 is in a case where the response signal line does not become 1.8 V even after a certain time (for example, 100 microseconds) elapses, the power switch 201 is turned off at T12, and the power supply voltage (VDD) applied to the memory card 100 is stopped. . Further, the host device 200 sets the voltage of the CLK signal line to 0V.

Not only in the case shown in FIG. 5, when an error occurs in the middle of the handshake processing of the voltage switching process, the host device 200 sets the voltage of the CLK signal line to 0 V, and stops the supply of power to the memory card 100.

<Step S28> CLK oscillation

In step S24, when it is confirmed that the signal voltage of the CMD/RES signal line is 1.8 V (Yes), the host device 200 transmits the oscillated clock signal to the clock signal line, in other words, the oscillation clock signal (FIG. 4: T8).

<Step S29, Step S30> Driving DAT to 1.8V / Making DAT Three-State

The host device 200 is tri-stated after driving the DAT signal line to a voltage of 1.8 V (FIG. 4: T9 to T10) in a short time after the start of the oscillation of the clock. Since the DAT signal line is boosted at 1.8V, the voltage level of 1.8V is maintained.

<Step S31, Step S32> CLK oscillation? / Make CMD/RES tristate

When the memory card 100 receives the oscillated clock signal from the host device 200 (Yes), the CMD/RES line is brought into a three-state state (FIG. 4: T11) in step S29. Since the CMD/RES line is boosted at 1.8V, the voltage level of 1.8V is maintained.

In the case where the oscillation clock signal is not applied to the clock signal line (No), the memory card 100 is stopped in step S35.

<Step S33>

Both the memory card 100 and the host device 200 perform initialization processing in the 3.3V mode, and perform subsequent transmission/reception of signals with a signal voltage of 3.3V.

<Step S34>

Both the memory card 100 and the host device 200 perform the transfer processing to the 1.8V mode, and transmit and receive the subsequent signals with a signal voltage of 1.8V.

<Step S35>

When the signal voltage shifting procedure to the 1.8V mode fails and the memory card 100 is stopped, the host device 200 temporarily reduces the power supply, and then transmits the signal voltage of 3.3V to the memory card 100 again, without switching to the 1.8V mode. Processing is performed in the initialization process in the 3.3V mode.

As described above, the memory system 1 is a memory card 100 and the host device 200 mutually confirm the signal voltages used by the handshake processing so that the I/O cells or the like are not damaged. Further, in the memory system 1, the memory card 100 and the host device 200 mutually confirm the output voltages of the respective regulators 116 or 204, and the reliability of the voltage applied to the signal lines can be improved. Further, the memory system 1 can be safely switched from the first voltage (3.3 V) to the second voltage (1.8 V) by defining the order of the handshake processing using the clock signal line and the command signal line.

Further, even in the memory system 1, if the switching to the 1.8V mode is frequently performed, there is no possibility of damaging the I/O cells 121 or 209 or the like. Therefore, in the memory system 1, it is preferable to perform the process of switching the signal voltage to 1.8 V only at the initial stage before the normal initialization process is started. That is, in the memory system 1, after switching to the 1.8V mode, the voltage mode is not changed even if a reset command is issued.

In other words, even if the memory card 100 and the host device 200 issue a reset command, all signals are transmitted/received at the second voltage of 1.8 V, and the state continues until the end of the operation of the memory system 1 in which the power supply voltage becomes 0V. .

In the memory system 1, since the voltage mode should not be frequently switched, the stability and reliability can be maintained even if the signal voltage is not changed by resetting.

Next, the protection diodes of the memory card 100 and the host device 200 will be described with reference to FIG. 6 is a partial structural view showing a part of the structure of the I/O cells 121 and 209 of the memory card 100 and the host device 200.

For the I/O cells 209 and 121 of the host device 200 and the memory card 100, respectively, any voltage of 3.3 V or 1.8 V of the output of the regulator 204 or 116 is switched and applied. Therefore, at the time of voltage switching, there may be a time when the regulator 204 and the output voltage of the regulator 116 are different. In the case where the output voltage of the regulator 204 and the regulator 116 are different, the current may flow in an unexpected path, possibly damaging the I/O cells 121 or 209, and the like.

The host device 200 and the memory card 100 protect the power lines from which the diodes 232 and 136 are connected to a voltage of 3.3V. Therefore, even if the host device 200 and the memory card 100 are in the 1.8V mode, the protection diodes 137 or 233 are not destroyed by the applied voltage exceeding 1.8V.

That is, the memory card 100 has a non-volatile memory portion 150 connectable to the host device 200; has a power supply line VDD114 that supplies a first voltage (3.3V); and a first adjuster 116 that is VDD114, which outputs power of any voltage selected from a first voltage (3.3V) and a second voltage lower than the first voltage (1.8V); the I/O cell 121 receives power from the first regulator 116 The signal can be transmitted/received with the host device 200; and the protection diode 136 is connected to the input end of the I/O cell 121 and the power terminal connected to the power line of the 3.3V to protect the I/O. The cell 121 is exempt from overvoltage; it can transmit/receive with the host device 200 with a signal of any voltage selected from a first voltage (3.3 V) or a second voltage (1.8 V).

In the memory system 1, since either of the host device 200 and the memory card 100 has an adjuster 116 or 204 that can output two kinds of voltages, if the regulator output is connected to the protection diode, the protection diode may be damage. When the signal voltage is set to 1.8 V, the power supply voltage itself is generally set to 1.8 V. However, in the memory system 1, since the compatibility is considered, the power supply voltage is set to 3.3 V. Therefore, in the memory system 1, the protective diode 136 described above is very effective in order to prevent damage of the protective diode.

Further, as described above, the host device 200 and the memory card 100 perform the switching process of the voltage mode only at the stage of connection start. Therefore, the host device 200 does not perform voltage switching processing by transmitting a switch command. 7A and 7B are explanatory views showing examples of parameters of a switching command for changing a transmission mode transmitted by the host device 200.

Further, in the present embodiment, a memory system 1 having an SD memory card (registered trademark) or the like is described as an example of a memory device, but a memory system having the same bus bar structure can also be applied. The memory system having other memory cards, memory devices, internal memory, and the like can exhibit the same effects as those of the memory system 1 and the like.

As described above, the memory device and the like of the present invention are as follows.

1. Memory device, host device, memory system, control method of memory device, control method of host device, and control method of memory system.

2. The memory device according to the above 1, wherein the memory device includes a memory controller that transmits the response signal for switching the signal voltage from the first voltage to the second voltage. In this case, the memory controller maintains the response signal line at 0V.

3. The memory device according to the above 1 or 2, wherein the host device includes a host control unit, and when receiving the response signal to switch the signal voltage from the first voltage to the second voltage, the The host control unit stops the clock signal and holds the clock signal line and the data signal line at 0V.

4. The memory device according to any one of the above 1 to 3, wherein the voltage detected by the first voltage comparison circuit and the second voltage comparison circuit is a voltage of a direct current.

5. The memory device according to any one of the above 1 to 4, wherein the memory controller and the host control unit start voltages output by the first regulator and the second regulator After switching from the aforementioned first voltage to the aforementioned second voltage, it stands by for a specific time.

6. The memory device according to any one of 1 to 5, further comprising: a third voltage comparison circuit and a fourth voltage comparison circuit, wherein the first regulator and the second regulator are detected The output voltage is the aforementioned second voltage.

7. The memory device according to any one of 1 to 6, wherein the first I/O cell and the second I/O cell line are provided to protect respective I/O cells from overvoltage. Protect the diode.

The memory device according to any one of the above 1 to 7, wherein the memory controller and the host control unit switch the signal voltage from the first voltage to the second voltage, and the second The voltage transmits/receives the aforementioned signals until the power supply is interrupted.

9. The memory device according to any one of the above 1 to 8, wherein the memory portion is a NAND flash memory.

Further, the memory device of the present invention has the memory system of the memory device of the above 2 to 8, the control method of the memory device of the above 2 to 8, and the control method of the memory system.

Further, the memory device, the host device, the memory system, the control method of the memory device, the control method of the host device, and the control method of the memory system of the present embodiment are described below.

A memory device, characterized in that it is connectable to a host device; the memory device has a non-volatile memory portion; and a first I/O cell, which can be connected to the host device, respectively Transmitting/receiving a command signal, a response signal, or any signal voltage selected from a first voltage and a second voltage lower than the first voltage via a command signal line, a response signal line, a clock signal line, or a data signal line, a clock signal and a data signal; a first regulator capable of outputting the first voltage and the second voltage; and a memory controller receiving, from the host device, the signal voltage from the first voltage When switching to the command signal of the second voltage, switching the signal voltage to the host device by using the response signal, and switching the voltage output by the first regulator from the first voltage to the first The second voltage is applied to the response signal line of the ground level when the detected clock signal line is the second voltage, and the foregoing voltage is detected. In the case of the oscillation signal, the second voltage signal to the start of transmission / reception.

2. The memory device according to 1, wherein the first voltage comparison circuit detects that a signal voltage of the clock signal line is the second voltage.

3. A host device, characterized in that it is a memory device connectable with a non-volatile memory portion; the host device has: a second I/O cell, which can be associated with the memory device, respectively Transmitting/receiving a command signal, a response signal, or any signal voltage selected from a first voltage and a second voltage lower than the first voltage via a command signal line, a response signal line, a clock signal line, or a data signal line, a clock signal and a data signal; a second regulator that outputs the first voltage and the second voltage; and a host control unit that is configured to switch the signal voltage from the first voltage to the second voltage And transmitting, by using the foregoing command signal, the switching of the signal voltage, and when receiving the response signal indicating that the signal voltage can be switched, switching the voltage output by the second regulator from the first voltage to the second Voltage, applying the second voltage to a clock signal line at a ground level, and oscillating the clock signal when the detected response signal line is the second voltage To the start of the second voltage signal transmission / reception.

4. A host device, characterized in that it is a memory device connectable with a non-volatile memory portion; the host device has: a second I/O cell, which can be associated with the memory device, respectively Transmitting/receiving a command signal, a response signal, or any signal voltage selected from a first voltage and a second voltage lower than the first voltage via a command signal line, a response signal line, a clock signal line, or a data signal line, a clock signal and a data signal; a second regulator that outputs the first voltage and the second voltage; and a host control unit that is configured to switch the signal voltage from the first voltage to the second voltage And transmitting, by using the foregoing command signal, the switching of the signal voltage, and the situation that the switchable response signal indicating the signal voltage is not receivable is not received within a certain period of time, or is temporarily cut off when accepting the non-switchable response signal The power of the memory device is again transmitted/received by the first voltage.

5. The host device according to the above 3 or 4, further comprising a second voltage comparison circuit that detects a signal voltage of the response signal line as the second voltage.

A memory system, comprising: a memory device having: a first I/O cell that is connectable to the host device via a command signal line, a response signal line, a clock signal line, or a data signal a line, transmitting/receiving a command signal, a response signal, a clock signal, and a data signal by any signal voltage selected from a first voltage and a second voltage lower than the first voltage; and a first regulator capable of outputting The first voltage and the second voltage; and the memory controller is configured to receive the signal voltage from the first voltage to the second voltage, and receive the data from the memory device to a second I/O cell for transmitting/receiving any one of the signal voltages selected by the first voltage and the second voltage, and a switching request of a host device capable of outputting the first voltage and the second regulator of the second voltage In the case of the aforementioned command signal of the signal voltage, using the aforementioned response signal and switching the signal voltage to the host device by the first voltage, the foregoing The voltage outputted by the regulator is switched from the first voltage to the second voltage, and when the clock signal line is detected as the second voltage, the second voltage is applied to the response signal line at the ground level. When detecting that the response signal line is the second voltage, detecting the oscillation of the clock signal from the host device, starting transmission/reception with the signal voltage of the second voltage; and the host device having: a second I/O cell, which is capable of transmitting/receiving with any of the signal voltages selected from the first voltage and the second voltage; and a second regulator capable of outputting the first a voltage and the second voltage; and a host control unit configured to transmit the command signal required to switch the signal voltage to the memory device when the signal voltage is switched from the first voltage to the second voltage And outputting from the memory device by using the foregoing response signal and receiving the signal voltage by using the first voltage, and outputting the second regulator The pressure switch from the second voltage to the first voltage, the second voltage is applied to the contact position registration clock signal line, the signal line in response to the detection of the case where the second voltage, the oscillation clock signal.

7. The memory system according to the above 6, wherein the memory device further includes: a first voltage comparison circuit that detects a signal voltage of the clock signal line as the second voltage; and the host device further has The second voltage comparison circuit detects that the signal voltage of the response signal line is the aforementioned second voltage.

A method of controlling a memory device, characterized in that it is a control method of a memory device connectable to a host device; the memory device has a non-volatile memory portion; a first I/O cell, The signal device, the signal line, the response signal line, the clock signal line or the data signal line, respectively, may be connected to any one of the signal voltages selected from the first voltage and the second voltage lower than the first voltage. Transmitting/receiving a command signal, a response signal, a clock signal, and a data signal; a first regulator capable of outputting the first voltage and the second voltage; and a memory controller; having the following steps: an instruction receiving step Receiving, from the host device, the command signal required to switch the signal voltage from the first voltage to the second voltage; and the response signal transmitting step, using the response signal, to switchably transmit the signal voltage to the host a first adjuster switching step of switching a voltage output by the first regulator from the first voltage to the second power a clock signal line voltage detecting step, wherein the clock signal line is detected as the second voltage; and the response signal line voltage applying step is performed by applying the second voltage to the grounding level response signal line; the clock signal is detected by oscillation a step of detecting an oscillation of the aforementioned clock signal; and a transmitting/receiving step of starting transmission/reception with a signal voltage of the aforementioned second voltage.

9. The method of controlling a memory device according to the above 8, characterized in that the first voltage comparison circuit is configured to detect that the signal voltage of the clock signal line is the second voltage.

A control method for a host device, characterized in that it is a control method of a host device to which a memory device having a non-volatile memory portion can be connected; the host device has: a second I/O cell, And transmitting, by the memory device, the signal signal, the response signal line, the clock signal line or the data signal line, respectively, by any one of the signal voltages selected from the first voltage and the second voltage lower than the first voltage. Receiving a command signal, a response signal, a clock signal and a data signal; a second regulator capable of outputting the first voltage and the second voltage; and a host control unit; having the following steps: a command signal transmission step, which is And switching the signal voltage by using the foregoing command signal when the signal voltage is switched from the first voltage to the second voltage; and the response signal receiving step is to receive the foregoing response signal indicating that the signal voltage is switchable; a regulator voltage switching step of switching a voltage output by the second regulator from the first voltage to the second voltage a clock signal line voltage applying step of applying the second voltage to a clock signal line of a ground level; a response signal line voltage detecting step of detecting a response signal line for the second voltage; and a clock signal oscillation step, It oscillates the aforementioned clock signal; and a transmitting/receiving step of starting transmission/reception with the signal voltage of the aforementioned second voltage.

11. The method of controlling a host device according to claim 10, further comprising a second voltage comparison circuit that detects a signal voltage of said response signal line as said second voltage.

12. A method of controlling a memory system, characterized in that it has a host device and a control method of a memory system connectable to the memory device of the host device;

The non-volatile memory portion can be connected to the host device via the command signal line, the response signal line, the clock signal line or the data signal line, respectively, from the first voltage and the second lower than the first voltage a signal signal, a first I/O cell for transmitting/receiving a command signal, a response signal, a clock signal, and a data signal, and a first regulator for outputting the first voltage and the second voltage, and a memory The memory device of the body controller, and the second I/O cell capable of transmitting/receiving the signal with any of the signal voltages selectable from the first voltage and the second voltage with the memory device a second regulator that outputs the first voltage and the second voltage, and a host device of the host control unit switches the signal voltage from the first voltage to the second voltage, and has the following steps: a command signal a transmitting step of transmitting the command signal for switching the signal voltage to the memory device; and a response signal transmitting step for the memory Transmitting the foregoing response signal, and switching the signal voltage to the host device by using the first voltage; and adjusting a voltage switching step of the memory device and the host device to use the first regulator and the foregoing The voltage outputted by the second regulator is switched from the first voltage to the second voltage; and the clock signal line voltage applying step is performed by applying the second voltage to the clock signal line of the host device at the ground level; the clock signal line a voltage detecting step of detecting, by the memory device, the clock signal line as the second voltage; and in response to the signal line voltage applying step, applying the second voltage to the response signal line of the memory device at a ground level Responding to the signal line voltage detecting step, wherein the host device detects that the response signal line is the second voltage; the clock signal oscillating step is performed by the host device oscillating the clock signal; and the clock signal oscillation detecting step is The memory device detects an oscillation of the clock signal; and a transmitting/receiving step, which is the aforementioned Memory device and the host device body to the voltage of the second voltage signal transmit / receive.

13. The method of controlling a memory system according to the above 12, wherein the memory device includes: a first voltage comparison circuit that detects a signal voltage of the clock signal line as the second voltage; and the host device has The second voltage comparison circuit detects that the signal voltage of the response signal line is the aforementioned second voltage.

14. A memory device, characterized in that it is connectable to a host device; has: a non-volatile memory portion; a memory controller; a power supply that supplies a first voltage; and a regulator that is Outputting, from the power source, power of any voltage selected from the first voltage and a second voltage lower than the first voltage; the I/O cell receiving power supply from the regulator, and the host device Transmitting/receiving signals of any voltage selected from the first voltage or the second voltage via the command signal line, the response signal line, the clock signal line, and the data signal line, respectively; and protecting the diodes, which are connected The input terminal of the aforementioned I/O cell and the foregoing power supply terminal are used to protect the aforementioned I/O cell from overvoltage.

A host device, characterized in that it is connectable to a memory device having a non-volatile memory portion; having: a host control unit; a power supply for supplying a first voltage; and a regulator And outputting, from the power source, power of any voltage selected from the first voltage and a second voltage lower than the first voltage; and the I/O cell receives power supply from the regulator, and is compatible with the memory The device transmits/receives with the memory device by using a signal of any voltage selected from the first voltage or the second voltage via a command signal line, a response signal line, a clock signal line or a data signal line; and protection The diode is connected between the input end of the I/O cell and the power supply terminal to protect the I/O cell from overvoltage.

<Second embodiment>

Hereinafter, a memory card 400, a host device 500, and a memory system 301 having a memory card 400 and a host device 500, which are the memory devices of the second embodiment of the present invention, will be described with reference to the drawings. The memory system 301 and the like of the present embodiment are similar to those of the memory system 1 and the like of the first embodiment, and the same reference numerals will be given to the same components, and description thereof will be omitted.

Next, the switching operation of the signal voltage of the memory system 301 will be described with reference to FIGS. 8A, 8B, 9, and 10. 8A and 8B are flowcharts for explaining the switching operation of the signal voltage of the memory system 301; and FIG. 9 and FIG. 10 are signal line groups (bus bars) when the signal voltage of the memory system 301 is switched. Timing diagram.

Hereinafter, the switching operation of the signal voltage of the memory system 301 will be described with reference to the flowcharts of FIGS. 8A and 8B. In addition, the left side of FIGS. 8A and 8B shows the operation flow of the host device 500, and the right side shows the operation flow of the memory card 400.

<Step S40>~<Step S44>

Since it is the same as step S10 to step S14 of the memory system 1 and the like, the description thereof is omitted.

<Step S45> The CMD/RES drive is 0V, and the DAT drive is 0V. The memory card 400 is set to transmit the response signal, and the CMD line is set to the L level (ground level: 0V) (Fig. 9: T3), and the DAT is The line is set to the L level (ground level: 0V) (Figure 9: T4). In addition, on the CMD/RES line and the DAT line, any line can be set to the L level first.

<Step S46> CLK is stopped and driven to 0V

The host device 500 stops the clock oscillation, and the CLK line is also set to the L level (ground level: 0 V) (Fig. 9: T5).

<Step S47>~<Step S50>

Since it is the same as step S17 to step S20 of the memory system 1 and the like, the description thereof is omitted.

<Step S51> CLK oscillation

After the predetermined period (for example, 100 microseconds), the host device 500 transmits the oscillating clock signal to the clock signal line, in other words, the oscillation clock signal (FIG. 9: T6). Then, the host device 500 communicates to the memory card 400 a signal voltage that can be supplied from the regulator VR2 to 1.8V.

<Step S52> CLK oscillation?

The memory card 400 is confirmed on the clock signal line, and whether or not a clock signal having a specific voltage of H level is applied.

<Step S53>

Since it is the same as step S23 of the memory system 1 and the like, the description thereof is omitted.

<Step S54> Make CMD/RES tristate

The memory card 400 is driven to a voltage of 1.8 V (Fig. 9: T7 to T8) in a short time, and is in a three-state state (Fig. 9: T8). Since the CMD/RES line is boosted at 1.8V, the voltage level of 1.8V is maintained.

<Step S55, Step S56> Driving DAT to 1.8V/Making DAT into Tristate

The memory card 400 is tri-stated only after driving the DAT signal line to a voltage of 1.8 V (FIG. 9: T9 to T10) in a short time. Since the DAT signal line is boosted at 1.8V, the voltage level of 1.8V is maintained.

<Step S57> Clock Counter Adjustment

The host device 500 adjusts the clock counter after the oscillation clock signal, and sets the calculation number n to zero.

<Step S58, Step S59>

The host device 500 is on standby to a minimum count of up to 16 clocks. The standby time is set to a value of 16 clocks or more.

<Step S60> The DAT line is 1.8V?

The host device 500 detects that the DAT signal line is not grounded, that is, a specific voltage is applied. Here, the specific voltage is 1.8V.

When the host device 500 is not applied to the DAT signal line (NO), the power switch (PSW) 201 is turned off in step S61, and the operation of the memory card 400 is stopped. When the voltage is applied to the DAT signal line (Yes), the host device 500 performs transmission/reception of the signal after step S63 with a signal voltage of 1.8V.

In addition, the host device 500 detects not only the DAT signal line but also the non-ground level of the DAT signal line and the CMD signal line, that is, a specific voltage is applied, thereby enabling safer voltage switching processing. . Here, the specific voltage is 1.8V.

<Step S62>

Both the memory card 400 and the host device 500 perform initialization processing in the 3.3V mode, and transmit/receive subsequent signals with a signal voltage of 3.3V.

<Step S63>

Both the memory card 400 and the host device 500 complete the transfer processing to the 1.8V mode, and transmit/receive the subsequent signals with a signal voltage of 1.8V.

When the signal voltage transfer procedure to the 1.8V mode fails and the memory card 400 is stopped, the host device 500 temporarily reduces the power supply, and then transmits the signal voltage of 3.3V to the memory card 400 again, and does not switch to the 1.8V mode. Processing is performed in the initialization process in the 3.3V mode.

As described above, the memory card 400 of the memory system 301 detects the voltage of the oscillation clock signal output from the host device 500. Therefore, a circuit for applying a DC voltage necessary for the clock signal line in the memory system 1 is not required. Further, the memory card 400 sets the DAT line to a three-state state.

The memory system 301 of this embodiment has a simpler structure and can exhibit the same effects as the memory system 1 of the first embodiment.

<Third embodiment>

Hereinafter, a memory card 700, a host device 800, and a memory system 601 having a memory card 700 and a host device 800, which are the memory devices of the third embodiment of the present invention, will be described. The memory system 601 and the like of the present embodiment are similar to the memory system 301 of the second embodiment, and the like, and the same reference numerals will be given to the same components, and the description will be omitted.

In the memory system 601 or the like, there are no comparators 119, 120, 207, 208 (refer to FIG. 2) for confirming that the voltage is a desired voltage, for example, 1.8V.

Therefore, the memory card 700 is in step S52 of FIG. 8A, and only the clock signal line is not grounded, that is, only the oscillation of the clock is confirmed. Moreover, the host device 800 is in step S55 of FIG. 8B, and only confirms that some voltage is applied to the CMD line, that is, only whether the CMD line is the ground level is confirmed.

The memory system 601 of the present embodiment has a simpler structure and can exhibit the same effects as those of the memory system 1 of the first embodiment.

The present invention has been described with reference to the preferred embodiments of the invention, and it is understood that the invention is not limited to the scope of the invention and the scope of the invention as defined by the appended claims The artist can make various changes and modifications.

The above application is based on the Japanese Patent Application No. 2008-72429, filed on March 19, 2008, and the Japanese Patent Application No. 2008-99740, filed on Jan. The content is attached to the specification, patent application, and drawings of the present application.

1. . . Memory system

1~9. . . Pin

100. . . Memory card

111. . . CLK line

112. . . CMD/RES line

113. . . DAT[3:0] line

114,201. . . Noise Filter

115,203. . . Energy gap reference (BGR)

116. . . First regulator (VR2)

118,206. . . Capacitor

119,207. . . Comparators

120. . . Comparator (VDCLK)

121. . . First I/O cell

122. . . Third adjuster (VR3)

123. . . Random logic

136,137,232,233. . . Protective diode

150. . . Memory department

151. . . Memory controller

152. . . Connector

200. . . Host device

201. . . Power switch (PSW)

204. . . Second adjuster (VR1)

208. . . Comparator (VDCMD/RES)

209. . . Second I/O cell

224,225. . . Lifting resistance

251. . . Host control unit

CLK. . . Clock signal

CMD. . . Command signal

CMD8. . . Command, command signal

DAT[3:0]. . . data

RES. . . Response signal

VDD. . . Power supply voltage, power cord

Fig. 1 is a schematic view showing the configuration of a memory system composed of a memory card and a host device of an embodiment.

Fig. 2 is a block diagram showing the structure of a power supply circuit portion of a memory system of an implementation type.

Fig. 3A is a flow chart for explaining the switching operation of the signal voltage of the memory system of the embodiment.

Fig. 3B is a flow chart for explaining the switching operation of the signal voltage of the memory system of the embodiment.

Fig. 4 is a timing chart of the bus bar at the time of switching operation of the signal voltage of the memory system of the embodiment.

Fig. 5 is a timing chart of the bus bar at the time of switching operation of the signal voltage of the memory system of the embodiment.

Fig. 6 is a partial structural view showing a part of the structure of an I/O cell of the memory card and the host device of the embodiment.

Fig. 7A is an explanatory diagram showing an example of a parameter of a switching command transmitted by a host device of an embodiment.

Fig. 7B is an explanatory diagram showing an example of parameters of a switching command transmitted by the host device of the embodiment.

Fig. 8A is a flow chart for explaining a switching operation of a signal voltage of the memory system of the second embodiment.

Fig. 8B is a flow chart for explaining the switching operation of the signal voltage of the memory system of the embodiment.

Fig. 9 is a timing chart of the bus bar at the time of switching operation of the signal voltage of the memory system of the second embodiment.

Fig. 10 is a timing chart of the bus bar at the time of switching operation of the signal voltage of the memory system of the second embodiment.

CLK. . . Clock signal

CMD8. . . Command signal

CMD/RES. . . Command signal/response signal

DAT[3:0]. . . data

Claims (32)

A memory device, which is connectable to a host device, and includes: a non-volatile memory portion; a first I/O cell that can communicate with the host device via a command signal line and a response signal, respectively a line, a clock signal line or a data signal line, transmitting/receiving a command signal, a response signal, a clock signal and a data signal from any one of a signal voltage selected from a first voltage and a second voltage lower than the first voltage; a regulator that outputs the first voltage and the second voltage; and a memory controller that receives the aforementioned request from the host device to switch the signal voltage from the first voltage to the second voltage In the case of the command signal, the switching of the signal voltage is transmitted to the host device by using the response signal; and the voltage output by the first regulator is switched from the first voltage to the second voltage; after a certain period of time, Detecting the aforementioned response signal line and the aforementioned data signal at the ground level in the case where a voltage other than the ground level is applied to the clock signal line The line applies the aforementioned second voltage; the transmission/reception starts with the signal voltage of the aforementioned second voltage. The memory device of claim 1, further comprising a first voltage comparison circuit that determines whether the aforementioned signal voltage of the clock signal line is the second voltage; The memory controller is configured to apply the second voltage to the response signal line and the data signal line at the ground level when the first voltage comparison circuit determines that the second voltage is the first voltage comparison circuit. When it is determined that the voltage is not the second voltage, at least the data signal line continues the grounding level. The memory device of claim 1, further comprising a second voltage comparison circuit for determining whether the voltage output by the first regulator is the second voltage; the memory controller is coupled to the second voltage comparison circuit When the second voltage is determined, the second voltage is applied to the response signal line and the data signal line at the ground level, and when the second voltage comparison circuit determines that the second voltage is not the second voltage, at least The aforementioned data signal line continues to be grounded. A host device that can be connected to a memory device including a non-volatile memory portion, and includes: a second I/O cell that can communicate with the memory device via the command signal line and the response signal line, respectively a clock signal line or a data signal line for transmitting/receiving a command signal, a response signal, a clock signal, and a data signal from any one of a signal voltage selected from a first voltage and a second voltage lower than the first voltage; And outputting the first voltage and the second voltage; and a control unit, configured to switch the signal voltage from the first voltage to the second voltage Transmitting the signal voltage by using the foregoing command signal; and receiving the response signal indicating that the signal voltage can be switched, switching the voltage output by the second regulator from the first voltage to the second voltage; After a certain period of time, the clock signal of the second voltage is supplied to the clock signal line of the ground level; and when the data signal line is not the ground level, the signal voltage of the second voltage is started. Transmit/receive. The host device of claim 4, further comprising a third voltage comparison circuit that determines whether the signal voltage of the response signal line is the second voltage; and the control unit determines that the second voltage comparison circuit is the second In the case of a voltage, transmission/reception is started. When the third voltage comparison circuit determines that the second voltage is not the second voltage, the power supply of the memory device is temporarily turned off, and transmission/reception is started again by the first voltage. A host device that can be connected to a memory device including a non-volatile memory portion, and includes: a second I/O cell that can communicate with the memory device via the command signal line and the response signal line, respectively a clock signal line or a data signal line for transmitting/receiving a command signal, a response signal, a clock signal, and a data signal from any one of a signal voltage selected from a first voltage and a second voltage lower than the first voltage; a second regulator that outputs the first voltage and the second voltage; and a control unit that transmits the signal signal from the first voltage to the second voltage Switching the signal voltage; not receiving the response signal indicating that the signal voltage can be switched over for a certain period of time, or temporarily cutting off the power of the memory device when receiving the non-switchable response signal And start transmitting/receiving again by the aforementioned first voltage. The host device of claim 6, further comprising a third voltage comparison circuit that determines whether the signal voltage of the response signal line is the second voltage; and the control unit determines that the third voltage comparison circuit is the foregoing In the case of two voltages, transmission/reception is started. When the third voltage comparison circuit determines that the second voltage is not the second voltage, the power of the memory device is temporarily turned off, and transmission/reception is started again by the first voltage. . A memory system, comprising: a host device, comprising: a second I/O cell that is transmittable/receivable with a memory device at any one of a signal voltage selected from a first voltage and a second voltage; a regulator that outputs the first voltage and the second voltage; and a host control unit that is configured to transmit the signal voltage from the first voltage In the case of switching to the second voltage, the command signal for switching the signal voltage is transmitted to the non-volatile memory portion, and may be respectively connected to the host device via the command signal line, the response signal line, the clock signal line or the data. The signal line transmits/receives the first I/O cell of the command signal, the response signal, the clock signal, and the data signal by any of the foregoing signal voltages selected from the first voltage and the second voltage lower than the first voltage. And the memory device of the first regulator capable of outputting the first voltage and the second voltage; and switching from the memory device by using the response signal and receiving the signal voltage by using the first voltage; The voltage outputted by the second regulator is switched from the first voltage to the second voltage; after a certain period of time, the clock signal of the second level is supplied to the clock signal line of the ground level; When the data signal line is not in the foregoing ground level, the signal voltage of the second voltage is started to be transmitted/received; and the memory The device includes: the non-volatile memory portion; the first I/O cell and the host device respectively via the command signal line, the response signal line, the clock signal line or the data signal line Transmitting/receiving the command signal, the response signal, the clock signal, and the data signal from any of the foregoing signal voltages selected from the first voltage and the second voltage lower than the first voltage; the first adjustment And outputting the first voltage and the second voltage; and a memory controller that receives the command signal requesting switching of the signal voltage from the host device when the signal voltage is switched from the first voltage to the second voltage; using the foregoing response signal, and The first voltage converts the signal voltage to the host device; the voltage output by the first regulator is switched from the first voltage to the second voltage; after a certain time, the clock signal is detected When a voltage other than the grounding level is applied to the line, the second voltage is applied to the response signal line and the data signal line at the ground level; and the transmission/reception is started by the signal voltage of the second voltage. The memory system of claim 8, wherein the memory device further comprises: a first voltage comparison circuit that determines whether the signal voltage of the clock signal line is the second voltage; or a second voltage comparison circuit Determining whether the voltage output by the first regulator is the second voltage; and the memory controller is connected to the first voltage comparison circuit and the second voltage comparison circuit to determine the second voltage Applying the second voltage to the response signal line and the data signal line, wherein at least one of the first voltage comparison circuit or the second voltage comparison circuit determines that the second voltage is not the second voltage The signal line continues the grounding level; the host control unit starts transmitting/connecting with the signal voltage of the second voltage when determining that the data signal line is not the ground level Received. A method for controlling a memory device, which is a method for controlling a memory device that can be connected to a host device, and includes the following steps: a command receiving step, which includes a non-volatile memory portion, which can be respectively connected to the host device via the a command signal line, a response signal line, a clock signal line or a data signal line for transmitting/receiving a command signal, a response signal, a clock signal from any one of a signal voltage selected from a first voltage and a second voltage lower than the first voltage And the first I/O cell of the data signal, and the memory device of the first regulator capable of outputting the first voltage and the second voltage, receiving, from the host device, requesting to switch the signal voltage from the first voltage The foregoing command signal of the second voltage; the response signal transmitting step, wherein the switch signal is used to switchably transmit the signal voltage to the host device; and the first adjuster switching step is to use the first adjuster The output voltage is switched from the first voltage to the second voltage; the clock signal line voltage detecting step is performed after After a predetermined time, detecting a voltage other than the grounding level applied to the clock signal line; and responding, the data signal line voltage applying step, applying the second to the response signal line and the data signal line of the grounding level The voltage transmitting/receiving step is to start transmitting/receiving with the signal voltage of the second voltage in the case where the data signal line is not the aforementioned ground level. The method of controlling a memory device of claim 10, further comprising: said memory device for determining whether said signal voltage of said clock signal line is said first voltage of said second voltage, said first voltage comparison circuit When the second voltage is determined, the second voltage is applied to the response signal line and the data signal line of the ground level to start the transmitting/receiving step, and the first voltage comparison circuit determines that the current is not In the case of the aforementioned second voltage, the aforementioned grounding level is continued by at least the aforementioned data signal line so as not to start the aforementioned transmitting/receiving step. The control method of the memory device of claim 10, further comprising: determining the memory device of the second voltage comparison circuit for determining whether the voltage output by the first regulator of the memory device is the second voltage is When the second voltage comparison circuit determines that the second voltage is the second voltage, the second voltage is applied by the response signal line and the data signal line of the ground level to start the transmitting/receiving step, and the second When the voltage comparison circuit determines that the second voltage is not the second voltage, the grounding level is continued by at least the data signal line to prevent the transmission/reception step from being started. A control method of a host device, which is a control method of a host device that can be connected to a memory device including a non-volatile memory portion, and includes the following steps: a command signal transmission step including a memory device Passing the command signal line, the response signal line, the clock signal line, or the data signal line, respectively, from the first voltage and the second voltage lower than the first voltage Selecting any of the signal voltages to transmit/receive the command signal, the response signal, the clock signal, and the second I/O cell of the data signal; and the foregoing host device that can output the first voltage and the second regulator of the second voltage The switching of the signal voltage is performed by using the command signal when the signal voltage is switched from the first voltage to the second voltage; and the response signal receiving step is to receive the switchable signal indicating that the signal voltage is switchable; adjusting a voltage switching step of switching a voltage output by the second regulator from the first voltage to the second voltage; and a data signal line voltage detecting step of detecting that the data signal line is applied with a ground level a voltage; a transmitting/receiving step of starting transmission/reception with a signal voltage of the aforementioned second voltage. The control method of the host device of claim 13, further comprising: determining, by the third voltage comparison circuit, the host device that determines whether the signal voltage of the response signal line is the second voltage comparison circuit of the second voltage is In the case of the second voltage, the transmission/reception step is started, and when the third voltage comparison circuit determines that the second voltage is not the second voltage, the transmission/reception step is not started. A method for controlling a memory system, comprising: a host device and a control method of a memory system connectable to the memory device of the host device, and comprising the following steps: a command signal transmitting step of arranging the signal voltage from The aforementioned When the voltage is switched to the second voltage, the method includes a command signal line, a response signal line, a clock signal line or a data signal line, respectively, from the memory device to be from the first voltage and lower than the first voltage. a second I/O cell for transmitting/receiving a command signal, a response signal, a clock signal, and a data signal, and a second regulator capable of outputting the first voltage and the second voltage The host device transmits the command signal for switching the signal voltage to the memory device, and the response signal transmission step includes a non-volatile memory portion that can communicate with the host device via the command signal line, The response signal line, the clock signal line or the data signal line transmits/receives the command signal, the response signal, the clock signal, and the foregoing by any of the signal voltages selected from the first voltage and the second voltage a first I/O cell of the data signal, and a first regulator capable of outputting the first voltage and the second voltage The memory device uses the foregoing response signal, and the switchable transmission of the signal voltage to the host device by using the first voltage; and a regulator voltage switching step, wherein the memory device and the host device use the first regulator And the voltage outputted by the second regulator is switched from the first voltage to the second voltage; the clock signal oscillating step is that the host device supplies the second voltage to the clock signal line of the ground level after a certain time Clock signal; clock signal line voltage detecting step, which is the aforementioned memory device After a predetermined time, detecting a voltage other than the grounding level applied to the clock signal line; and responding to the data signal line voltage applying step, wherein the memory device is applied to the response signal line and the data signal line of the grounding level The second voltage; the data signal line voltage detecting step, wherein the host device detects that the data signal line is not the grounding level; and the transmitting/receiving step is that the memory device and the host device are in the foregoing second voltage The signal voltage starts transmitting/receiving. The memory system control method of claim 15, further comprising detecting whether the signal voltage of the clock signal line is a first voltage comparison circuit of the second voltage, or detecting whether a voltage output by the first regulator is the foregoing The memory device of the second voltage comparison circuit of the second voltage is in the clock signal line voltage detecting step. When the first voltage comparison circuit determines that the second voltage is the second voltage, the first voltage comparison circuit shifts to the response and the data signal line. a voltage application step of not performing the response and the data signal line voltage application step when the first voltage comparison circuit or the second voltage comparison circuit determines that the second voltage is not the second voltage; the host device is in the foregoing In the data signal line voltage detecting step, when it is determined that the data signal is not the grounding level, the transmitting/receiving step is started, and in the data signal line voltage detecting step, determining that the data signal is the grounding level The aforementioned transmission/reception steps are not started. A memory device that is connectable to a host device and includes: a non-volatile memory portion; a power source that supplies a first voltage; and an adjuster that outputs the first voltage from the power source and a power lower than a voltage selected by a second voltage of the first voltage; an I/O cell receiving power from the regulator, and being coupled to the host device via a command signal line, a response signal line, and a clock The signal line and the data signal line transmit/receive the command signal, the response signal, the clock signal and the data signal with the signal of any voltage selected from the first voltage or the second voltage; and protect the diode, It is connected between the input end of the aforementioned I/O cell and the aforementioned power supply terminal to protect the aforementioned I/O cell from overvoltage. A host device connectable to a memory device including a non-volatile memory portion, and includes: a power source that supplies a first voltage; and an adjuster that outputs the first voltage from the power source And an electric power lower than a voltage selected by the second voltage of the first voltage; the I/O cell receives the power supply from the regulator, and can communicate with the memory device via the command signal line and the response signal line, respectively. a clock signal line or a data signal line, transmitting or receiving a command signal, a response signal, a clock signal, and a data signal with the signal of any voltage selected from the first voltage or the second voltage; The pole body is connected between the input end of the aforementioned I/O cell and the power source end to protect the I/O cell from overvoltage. A memory device that is connectable to a host device and includes: a first I/O cell that is selectable by a signal selected from a first voltage and a second voltage lower than the first voltage The voltage is performed: receiving the command signal via the command/response signal line, receiving the clock signal via the clock signal line, transmitting the response signal via the command/response signal line, and transmitting/receiving the data signal via the data signal line; the first adjuster is And outputting the first voltage and the second voltage; and the memory device controller receiving, from the host device, the request signal for switching the signal voltage from the first voltage to the second voltage And, if the signal voltage is switchable to the host device by using the foregoing response signal, and the signal voltage is switchable, the host device sets the clock signal line to a ground level, and then starts the foregoing a process of switching the voltage of the regulator output from the first voltage to the second voltage, and detecting the clock signal line A case where the applied voltage other than the ground level, the second voltage is applied to the instruction by setting the contact position registration / reply signal line, the second voltage begins by transmitting / receiving. The memory device of claim 19, further comprising a first voltage comparison circuit for determining whether said signal voltage of said clock signal line is said second voltage; The memory device controller applies the second voltage to the command/response signal line set to the ground level and the data signal line when the first voltage comparison circuit determines that the second voltage is When the first voltage comparison circuit determines that the second voltage is not the second voltage, at least the data signal line continues the ground level. The memory device of claim 19, further comprising a second voltage comparison circuit for determining whether the voltage output by the first regulator is the second voltage; and the memory device controller is for comparing the second voltage When the circuit determines that the second voltage is the second voltage, the second voltage is applied to the command/response signal line set to the ground level and the data signal line set to the ground level, and the second voltage comparison circuit determines In the case where the second voltage is not the aforementioned voltage, at least the aforementioned data signal line continues the aforementioned ground level. The memory device of claim 19, comprising: a non-volatile memory portion. The memory device of claim 19, comprising a protection diode between the input end of the first I/O cell and the power supply line supplying the first voltage. A host device that is connectable to a memory device and includes: a second I/O cell that is selectable by a signal selected from a first voltage and a second voltage lower than the first voltage The voltage is performed: the command signal is transmitted via the command/response signal line, the clock signal is transmitted via the clock signal line, the response signal is received via the aforementioned command/response signal line, and the response signal is received. a signal line transmitting/receiving a data signal; a second regulator for outputting the first voltage and the second voltage; and a host control unit for switching the signal voltage from the first voltage to the second voltage In the case of the above command signal, the switching of the signal voltage is performed; when the memory device can switch the signal voltage, the clock signal line is set to the ground level, and the second regulator is started. a process of switching the output voltage from the first voltage to the second voltage; after the clock signal line is set to the ground level and after a certain period of time, supplying the clock signal of the second voltage to the clock signal line; The signal line is transmitted/received by the aforementioned signal voltage of the second voltage when the non-ground level is detected. The host device of claim 24, wherein: the host control unit starts transmitting/accepting by using the first voltage when receiving the response signal indicating that the switch is not switchable, and receiving the response signal indicating that the switchable signal is received. When an error is detected during the voltage switching, the power of the device is temporarily cut off, the device is initialized by the first voltage, and transmission/reception is started by the first voltage. The host device of claim 24, further comprising a third voltage comparison circuit for determining whether the signal voltage of the command/response signal line is the aforementioned second voltage; When the third voltage comparison circuit determines that the second voltage is determined, the host control unit starts transmission/reception by the second voltage, and when the third voltage comparison circuit determines that the second voltage is not the second voltage, The power supply of the device is temporarily cut off, and the device is initialized by the first voltage, and the signal is transmitted/received by the first voltage. The host device of claim 24, wherein the memory device comprises a non-volatile memory portion. The host device of claim 24, comprising a protection diode between the input end of the second I/O cell and the power supply line supplying the first voltage. A memory system comprising a host device and a memory device, wherein the memory device is connectable to the host device; wherein the memory device comprises: a first I/O cell, which is Performing any one of the signal voltages selected from the second voltage of the first voltage: receiving the command signal via the command/response signal line, receiving the clock signal via the clock signal line, transmitting the response signal via the command/response signal line, and Transmitting/receiving a data signal via a data signal line; and a first regulator that outputs the first voltage and the second voltage; the host device includes: a second I/O cell, which is Performing any one of the signal voltages selected by the first voltage and the second voltage: transmitting the command signal via the command/response signal line, and transmitting the foregoing via the clock signal line a clock signal, the aforementioned response signal is received via the command/response signal line, and the data signal is transmitted/received via the data signal line; and a second regulator is configured to output the first voltage and the second voltage; When the signal voltage is switched from the first voltage to the second voltage, the host device transmits the command signal requesting the switching of the signal voltage to the memory device; the memory device is responded by the foregoing a signal, wherein the signal voltage is switchably transmitted to the host device by using the first voltage; and when the memory device can switch the signal voltage, the clock signal line is set to a ground level by the host device The memory device and the host device start a process of switching a voltage output by the first regulator and the second regulator from the first voltage to the second voltage; and the host device sets the clock signal line to When the grounding level is accurate and after a certain period of time, the aforementioned second voltage is supplied Transmitting the signal to the clock signal line set to the ground level; the memory device detecting the voltage other than the ground level to the clock signal line, applying the second voltage to the previous command set to the ground level And responding to the signal line and the data signal line; the host device starts transmitting/receiving by the second voltage after detecting the non-ground level of the data signal line. The memory system of claim 29, wherein the memory device further comprises: a first voltage comparison circuit that determines whether the signal voltage of the clock signal line is the second voltage; or a second voltage comparison circuit that determines whether the first regulator is the second voltage; and the memory The device applies the second voltage to the command/response signal line set to the ground level and the data signal line when the first voltage comparison circuit and the second voltage comparison circuit determine that the second voltage is When the first voltage comparison circuit or the second voltage comparison circuit determines that the second voltage is not the second voltage, at least the data signal line continues to be grounded; the host device determines that the data signal line is not grounded. In the case of a standard, transmission/reception is started by the aforementioned second voltage. The memory system of claim 29, wherein the memory device comprises a non-volatile memory portion. The memory system of claim 29, wherein between the input end of the first I/O cell and the power line supplying the first voltage, and between the input end of the second I/O cell and the power line , respectively, contain protective diodes.