TWI401806B - Semiconductor device and method for manufacturing the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same. In particular, the present invention relates to a semiconductor device comprising a nanocrystalline layer of germanium and a method of fabricating the same.

Memory can be divided into two categories based on the storage of data: volatile memory and non-volatile memory. The classification is based on whether the memory can renew the data when the power is interrupted or there is no power. The memory that cannot renew the data is a volatile memory, and the non-volatile memory that can renew the data. At present, volatile memory is dominated by DRAM. Its advantages are low operating voltage and fast operation. However, its shortcoming is that it cannot be renewed. Non-volatile memory is currently dominated by Flash Memory.

The non-volatile memory is represented by flash memory. The flash memory uses the floating gate to store the charge, which is used to distinguish the digital signals 0 and 1. In other words, the electrons are heated by the channel. Channel hot electron injection or tunneling (Fowler-Nordheim tunneling injection) into the floating gate for charge storage purposes. When the power is turned off or there is no power, the internal data is still stored, so the flash memory is a non-volatile memory.

Please refer to FIG. 1. FIG. 1 is a diagram showing the flash memory 1 in the prior art. schematic diagram. As shown in FIG. 1, the conventional flash memory 1 includes a substrate 11, a tunneling 13, a floating gate 15, a control oxide layer 17, and a gate. 19. The substrate 11 has a source 111 and a drain 113. On the substrate 11, a tunnel oxide layer 13, a floating gate 15, a control oxide layer 17, and a gate are sequentially formed from bottom to top. 19. The floating gate 15 is used as a charge storage layer, which usually uses poly-silicon as the material of the floating gate 15, and the advantage of the polysilicon as the floating gate 15 material is: Complementary metal oxide semiconductor (CMOS) manufacturing processes are compatible.

When the flash memory 1 is operated through the channel hot electron mode, a voltage is applied to the gate 19 to form an electric field perpendicular to the substrate 11, and a bias is applied to the drain 113 to form the source 111. The electric field to the drain 113 accelerates the electrons and becomes hot electrons. The hot electrons are attracted by the vertical electric field and are pulled toward the floating gate 15 via the tunneling layer 13. When the electrons are stored in the floating gate 15, the digital signal is recorded as zero. When the gate 19 is grounded and a high voltage is applied to the source 111, the electrons on the floating gate 15 are pulled from the floating gate 19 to the source 111. When the electrons leave the floating gate 15, the digital signal is recorded as 1.

The ideal memory must have the advantages of non-volatility, low operating voltage, fast operation speed, long memory time and small component size. However, in order to achieve low operating voltage, small component size and reduced memory writing and erasing. The requirement of time (ie, fast operation) must reduce the thickness of the tunneling oxide layer when preparing the flash memory. However, the thinner the thickness of the tunnel oxide layer, the more easily the defect of the leakage current path runs through the entire tunnel oxide layer, which will cause the charge stored in the floating gate to be lost from the defect, so To reduce the leakage current of the flash memory, the tunnel oxide layer must have a sufficient thickness, which will cause the flash memory to become bulky, the operating voltage is too large, and the writing/erasing time is long.

The present invention therefore provides a semiconductor component and a method of fabricating the same. The semiconductor device can be used as a memory, and in the case of reducing the thickness of the tunnel oxide layer, the generation of leakage current can be reduced, the appropriate operating voltage can be maintained, and the writing/erasing time can be reduced to solve the problems of the prior art. .

According to a specific embodiment, the semiconductor device of the present invention comprises: a substrate, a tunneling layer, a nanocrystalline layer, a controlled oxide layer, and a gate. Wherein, the substrate has a source and a drain, and the through layer is formed on the substrate and located between the source and the drain. In practice, the tunneling layer is a high dielectric layer, and the material of the tunneling layer can be made of hafnium oxide (HfO ₂ ), but not limited thereto.

The nano-grain layer is formed on the tunneling layer and functions as a floating gate. Specifically, the nano-grain layer includes a plurality of nano-grains. Further, a control oxide layer is formed on the nano-grain layer, and a gate is formed on the control oxide layer. In practice, the control oxide layer is also a high dielectric material, and the material for making the control oxide layer may be cerium oxide, but not limited thereto.

Another aspect of the invention is to provide a method for fabricating a semiconductor component. In particular, the semiconductor device fabricated according to the method of the present invention can reduce the generation of leakage current, maintain an appropriate operating voltage, and reduce the time of writing/erasing. In addition, it also has a thin tunneling oxide layer.

According to a specific embodiment, the method of the present invention comprises the steps of first forming a tunneling layer on a substrate, and the tunneling layer is between the source and the drain of the substrate. Subsequently, a nano-grain layer is formed on the tunneling layer, and then the heat-treated nano-grain layer is formed to precipitate a plurality of nano-grain crystal grains formed in the nano-grain layer. Next, a controlled oxide layer is formed on the nanocrystalline layer. Finally, a gate is formed on the control oxide layer to obtain the semiconductor element of the present invention.

In summary, since the semiconductor device of the present invention utilizes a nanocrystalline layer as a floating electrode and a high dielectric material is used in the tunneling layer, the minimum effective thickness of the through layer can be thinner than that in the prior art. Tunnel layer. Therefore, the semiconductor device fabricated by the method of the present invention has the advantages of reducing leakage current, low operating voltage, fast operation speed, and small component size.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

The present invention provides a semiconductor device and a method of fabricating the same, and can be used as a memory for the semiconductor device.

Referring to FIG. 2, FIG. 2 is a schematic diagram of a semiconductor device 2 according to an embodiment of the present invention. As shown in FIG. 2, the semiconductor device 2 of the present invention comprises a substrate 21, a tunneling layer 23, a nano-crystal layer 25, a control oxide layer 27, and a gate 29.

The substrate 21 has a source 211 and a drain 213. The tunneling layer 23 is formed on the substrate 21 by a thin film technique and is located between the source 211 and the drain 213. The tunneling layer 23 is a high dielectric layer, and the material of the tunneling layer 23 may be cerium oxide (HfO ₂ ), but is not limited thereto.

The nano-grain layer 25 is formed on the through-layer 23, and the nano-grain layer 25 includes a plurality of nano-grains. The control oxide layer 27 is formed on the nano-grain layer 25 by a thin film technique. In practice, the control oxide layer 27 can also be a high dielectric layer, and the material thereof can be cerium oxide (HfO ₂ ), but is not limited thereto. Finally, a gate 29 is formed on the control oxide layer 27.

Referring to FIG. 3, FIG. 3 is a flow chart showing a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in Figure 3, the method according to the invention comprises the following steps:

Step S50: preparing a substrate having a source and a drain.

Step S52: forming a tunneling layer above the substrate, and the tunneling layer is located between the source and the drain. As described above, the tunneling layer may be a high dielectric layer, and the material of the tunneling layer may be cerium oxide (HfO ₂ ), but not limited thereto.

Step S54: forming a nanocrystalline layer of germanium on the through layer. In practice, the nano-grain layer can be formed by a plasma-assisted chemical vapor deposition method, a low-pressure chemical vapor deposition method, a sputtering method, or an organometallic chemical vapor deposition method.

Step S56: heat-treating the nano-grain layer, so that a plurality of nano-grain grains are precipitated and formed in the nano-grain layer. In practice, the nanocrystalline layer may be subjected to a predetermined time (eg, but not limited to 30 seconds) in a nitrogen atmosphere and a temperature range (eg, but not limited to 700 ° C to 900 ° C). The heat treatment causes a plurality of nanocrystalline grains to precipitate and form in the nanocrystalline layer.

Step S58: forming a controlled oxide layer on the nanocrystalline layer. The control oxide layer may be a high dielectric layer, and the material for the control oxide layer may be cerium oxide, but not limited thereto. In practice, the control oxide layer can be used to prevent charge from flowing into the gate, effectively reducing leakage current. Finally, step S60 is performed: forming a gate to control the oxide layer.

In practical applications, in order to obtain a HfO ₂ dielectric layer nanocrystalline semiconductor device (TaN/HfO ₂ /HfGdO/HfO ₂ /Si, abbreviated as MHHHS), the method of the present invention may comprise the following steps.

First, an n-type (100) tantalum wafer is used as a substrate, and after RCA cleaning, it is placed in a Radio Frequency Sputtering System, and the sputtering machine is preliminarily equipped with two kinds of targets required for the process ( 99.9% of target and target). Next, 5 nm of cerium oxide was deposited as a tunneling layer by reactive sputtering under the condition of shielding the target. The sputtering environment was at room temperature, the pressure was 20 mtorr, and the process gases were O ₂ (2 sccm) and Ar (20 sccm). The power of the RF sputter is controlled at 150 W.

Next, a 10 nm niobium oxide layer was deposited using both tantalum and niobium metal coffins. The wafer was then placed in a rapid annealing system and annealed at 700 ° C for 30 seconds in a N ₂ atmosphere. Due to the driving force such as supersaturation of the metal concentration in the oxide film and surface tension, spherical nanocrystal grains are precipitated in the oxide layer. Then, a sputtering method was used to deposit 30 nm of cerium oxide as a control oxide layer. Finally, an aluminum electrode is plated on the back side of the nanocrystalline semiconductor device for subsequent electrical measurement.

The above-mentioned HfO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device (TaN/HfO ₂ /HfGdO/HfO ₂ /Si, MHHHS) and SiO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device (TaN/SiO ₂ /HfGdO /SiO ₂ /Si, MOHOS) and SiO ₂ dielectric layer 铪 nanocrystalline semiconductor components (Al / SiO ₂ / HfO ₂ / SiO ₂ / Si, HfO ₂ MOHOS) for electrical comparison. See Figure IV, Figure IV shows comparison based HfO ₂ dielectric layer, a hafnium crystal semiconductor element gadolinium nm SiO ₂ dielectric layer with a hafnium crystal gadolinium nm semiconductor element, and SiO ₂ nm hafnium oxide dielectric layer of a polycrystalline semiconductor element Charge retention characteristics at room temperature.

Note that in Figure 4, the horizontal axis represents the retention time in seconds; the vertical axis represents the flat band voltage expressed in V _FB in volts; P is the write; E is the wipe In addition, the flat band voltage difference value (V _FB shift) is the flat band voltage at the time of writing minus the flat band voltage at the time of erasing, and the larger the difference value of the flat band voltage, the more distinguishing the digital signal.

As shown in Figure 4, comparing the flat-band voltages of the three semiconductor components at the time of writing, it can be found that the HfO ₂ dielectric layer is at the time of writing (MHHHS/P), and the flat-band voltage V _FB value The largest of the three, the HfO ₂ dielectric layer has a better charge retention characteristic than the other two semiconductor elements. The flat-band voltage value is extrapolated to 10 years. It can be seen from Fig. 4 that the flat-band voltage difference value of the HfO ₂ dielectric layer semiconductor component can still be maintained at about 1V, which is sufficient to distinguish the digital signals 0 and 1.

For comparison of the above three semiconductor components under other temperature conditions, please refer to FIG. 5, which is a comparison of the charge storage characteristics of the three semiconductor components in FIG. 4 at 85 ° C. Note that in Figure 5, the horizontal axis represents the retention time in seconds; the vertical axis represents the flat band voltage expressed in V _FB in volts; P is the write; E is the wipe In addition, the flat band voltage difference value (V _FB shift) is the flat band voltage at the time of writing minus the flat band voltage at the time of erasing. The comparison results show that compared with the other two kinds of semiconductor components, the HfO ₂ dielectric layer MH nanocrystalline semiconductor device (MHHHS) has the most charge storage characteristics, and the reason is as described above, and will not be described here. . The flat-band voltage value is extrapolated to 10 years. As shown in Figure 5, the flat-band voltage difference value can still be maintained at about 0.6V, and the digital signals 0 and 1 can still be distinguished.

Referring to FIG. 6 , FIG. 6 illustrates the endurance characteristics of the HfO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device and the SiO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device. As shown in FIG. 6, the HfO ₂ dielectric layer and the nanocrystalline semiconductor device are compared with the SiO ₂ dielectric layer and the nanocrystalline semiconductor device. The results show that after repeated reading and writing for 10 ⁴ times, V _The difference in _FB values can be maintained at around 1V, which is sufficient to distinguish between digital signals 0 and 1, indicating that both have excellent tolerance.

The invention is characterized in that the nano-grain layer is used as a floating gate of a semiconductor element, and a heat discontinuous and high-density nano-grain is deposited in the nano-grain layer by heat treatment. The charge is passed through the tunneling oxide layer into the nano-grain layer and stored in the nano-grain, respectively. Since the nanocrystallites are zero-dimensional quantum dot structures, the energy is discontinuous in three-dimensional space, so the charge can be effectively confined to the nanocrystal grains to reduce the leakage current.

When the tunnel oxide layer produces defects, only the nanocrystals near the defect The stored charge is lost. Moreover, the nano-grain layer has more deep trap states near the Fermi level, which can avoid interference from other deep levels, and has more metal work function selection and modulation. And the nanocrystalline layer promotes uniform charge injection, which makes the control of the threshold voltage more precise. In addition, the thermal stability of base metals is excellent. Some steps in the back-end part of the component need to be carried out at extremely high temperatures. The thermal stability is good to avoid defects caused by high temperature.

In addition, the use of a high dielectric material such as HfO ₂ in the fabrication of the tunnel oxide layer and the control oxide layer material allows the semiconductor device of the present invention to have a smaller equivalent oxide thickness.

In summary, the semiconductor device of the present invention can be used as a memory, and the semiconductor device utilizes a nano-grain layer as a floating gate, and the material for forming the oxide layer is a high dielectric material, thereby reducing oxidation. The thickness of the material allows the tunneling dielectric layer to be made thinner, effectively reducing the generation of leakage current, thereby reducing operating voltage, increasing operating speed, reducing component dimensions, reducing leakage current, and increasing retention time.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

1‧‧‧flash memory

11, 21‧‧‧ substrate

111, 211‧‧‧ source

113, 213‧‧ ‧ bungee

13, 23‧‧‧ Tunneling

15‧‧‧Floating gate

17, 27‧‧‧Control oxide layer

19, 29‧‧ ‧ gate

2‧‧‧Semiconductor components

25‧‧‧铪釓 nano grain layer

S50~S60‧‧‧ Process steps

FIG. 1 is a schematic diagram of a flash memory in the prior art.

2 is a schematic view of a semiconductor device in accordance with an embodiment of the present invention.

3 is a flow chart showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

Figure 4 is a diagram showing the comparison of HfO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device and SiO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device, and SiO ₂ dielectric layer 铪 nanocrystalline semiconductor device at room temperature charge storage characteristic.

Figure 5 is a graph showing the charge retention characteristics of the three semiconductor elements in Figure 4 at 85 °C.

Figure 6 is a graph showing the endurance characteristics of a HfO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device and a SiO ₂ dielectric layer 铪釓 nanocrystalline semiconductor device.

S50~S60‧‧‧ Process steps

Claims (9)

A method for fabricating a semiconductor device, the method comprising the steps of: forming a pass-through layer on a substrate, wherein the pass-through layer is between a source and a drain of the substrate; forming a stack a nano-grain layer on the puncture layer; heat-treating the nano-grain layer to cause a plurality of nano-grains to precipitate in the nano-grain layer; forming a control oxide layer on the crucible And forming a gate on the control oxide layer to obtain the semiconductor device. The method of claim 1, wherein the through layer is a high dielectric layer. The method of claim 2, wherein the material of the threading layer is cerium oxide. The method of claim 1, wherein the control oxide layer is a high dielectric layer. The method of claim 4, wherein the material of the control oxide layer is cerium oxide. The method of claim 1, wherein the nano-grain layer is plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, sputtering, or organometallic chemical vapor deposition. Formed on the piercing layer. The method of claim 1, further comprising the step of: heating the nanocrystalline layer of the germanium to a temperature range under a nitrogen atmosphere and maintaining the temperature range for a predetermined time. The method of claim 7, wherein the temperature range comprises from 700 ° C to 900 ° C. The method of claim 7, wherein the predetermined time comprises 30 seconds.