TWI392942B - New type liquid crystal display panel and its driving method - Google Patents

Description

Novel liquid crystal display panel and driving method thereof

The invention relates to a novel liquid crystal display panel and a driving method thereof, and relates to a novel liquid crystal display panel and a driving method thereof, which implement a Frame inversion architecture by using a double gate driving circuit.

The liquid crystal display utilizes characteristics such as thinness, light weight, low power consumption, and no environmental burden, and the usage rate in each application field is considerably high. In general, liquid crystal displays generally use an active matrix driving circuit to control the operation of the display panel. With the rapid development of display technology, how to improve display quality and reduce cost is a major problem that the industry has been trying to overcome.

Since the liquid crystal molecular characteristics cannot fix the application of the electric field of the same polarity for too long, if the voltage is too long, even if the voltage is cancelled, the liquid crystal molecules can no longer rotate according to the change of the electric field due to the destruction of the characteristics to form the corresponding gray scale. . Therefore, at intervals, the polarity of the voltage applied to the liquid crystal molecules must be switched to avoid damage to the characteristics of the liquid crystal molecules.

When the picture is always moving, that is, the picture always shows the same gray level, for the liquid crystal display, the display voltage in the liquid crystal display is divided into two polarities, one is defined as positive polarity and the other is negative polarity. When the voltage of the display electrode is higher than the common voltage (Vcommon), it is called positive polarity. When the voltage of the display electrode is lower than the common voltage, it is called negative polarity. Whether it is positive or negative, there will be a set of gray levels of the same brightness. Therefore, when the absolute value of the pressure difference between the upper and lower layers of glass is fixed, whether the voltage of the display electrode is high or the voltage of the common electrode is high, the gray scale expressed is exactly the same.

However, in both cases, the steering of the liquid crystal molecules is completely reversed, and the characteristic damage caused when the liquid crystal molecules are always fixed in one direction can be avoided. In other words, when the display is still moving, you can still use positive and negative polarity. The alternation achieves the result that the display does not move while the liquid crystal molecules are not destroyed. So when the LCD screen you see is still, the voltage inside is constantly changing, and the liquid crystal molecules are constantly turning to this side, and the other time turning in the opposite direction.

The panel changes in various polarities, but the polarity is changed the next time the screen data is changed. For the same point, its polarity is constantly changing. Whether adjacent points have the same polarity can be determined according to different polarity switching methods.

Among them, the liquid crystal display commonly used in personal computers is now used, and the panel polarity conversion method used can be roughly divided into dot inversion, line inversion, column inversion, and frame inversion. Frame inversion. Each polarity change has its own advantages and disadvantages. The following is a description of the problems encountered with prior art techniques using frame inversion polarity transformation.

The schematic diagram of the general active matrix drive circuit is shown in the first figure, which is designed by point inversion. In the active matrix liquid crystal display panel 24, each pixel 10 has a thin film transistor (TFT) 12 as a switch, its gate is connected to the horizontal scanning line 14, and the drain is connected to the vertical data line 16, The source is connected to the liquid crystal electrode as shown in the first figure. The display panel activates one horizontal scan line 14 at a time to open all of the thin film transistors 12 on the line, and sends a data signal to the corresponding pixel 10 via the vertical data line 16. Then, the thin film transistor 12 is turned off until the signal is rewritten again, during which the charge is stored on the pixel capacitor 18. At this time, the next scan line is activated, and the data signal is input to the corresponding pixel via the data line; The data signal of the entire picture is written, and the signal is rewritten from the first line. Wherein, the plurality of data lines 16 are driven by the data driver 20, and the plurality of scanning lines 14 are driven by the scan driver 22, so that each pixel 10 in the active matrix display panel can be controlled to operate according to the input data signal. The image is displayed on the display panel.

The second figure shows a schematic diagram of a general active matrix driving circuit using RGB pixels. From the point of view of the first picture as RGB pixels, it can be represented by the second picture. Every scan The line is connected to 2400 pixel TFTs, and the pixels in each scan line are alternately arranged in a cycle of R, G, and B. The first picture and the second picture introduced above belong to one type of single gate structure. For a single gate structure, the polar performance of RGB pixels is presented in a frame inversion manner, that is, each point. The polarity is the same polarity as the up, down, left, and right points adjacent to itself. Taking frame inversion as an example, the polarity of each pixel is the same as the pixels above and below.

Please refer to the second and third figures at the same time. The third figure is the waveform diagram of the clock signal and the gate signal of the second figure. YDIO1 represents the first trigger signal, YCLK is the clock signal, YOE is the interval signal, G1~G256 is the gate signal, YDIO2 is the second trigger signal, and each signal has a delay time t between Separate to avoid mutual interference. It can be seen from the third figure that the prior art G1~G256 are sequentially scanned from top to bottom.

In order to improve the picture quality of a liquid crystal display panel, it is necessary to pay sufficient attention to the problem of the pressure difference between the upper and lower layers of the liquid crystal. "The pressure difference between the upper and lower plates is too large, which will affect the gray scale change of the liquid crystal display panel." For the common voltage of the upper board, whether the common voltage can return to the common voltage level before the end of the charge (charge); if it cannot return to the Vcommon voltage level, horizontal cross-talk will occur. For the lower ITO electrode voltage, it is during the holding period, the ITO electrode voltage is coupled by the data line data. If the ITO electrode voltage is coupled, the vertical direction will appear. Cross-talk.

Therefore, the present invention provides a novel liquid crystal display panel and a driving method thereof, which can effectively reduce the cross-talk in the vertical direction generated by the frame inversion polarity switching method in the prior art, thereby improving the liquid crystal display. The picture quality of the panel.

The main object of the present invention is to provide a novel liquid crystal display panel and a driving method thereof, which adopt a double gate driving circuit and a polarity inversion method of frame inversion, which can reduce the cross-talk problem in the prior art in the vertical direction.

The invention provides a novel liquid crystal display panel and a driving method thereof, which have a complex A series of pixel units and a plurality of parallel data lines. Each column of pixels in the plurality of columns of pixel units includes a first scan line and a second scan line, and a plurality of parallel data lines, all of the data lines are perpendicular to all the scan lines, and the data lines are in the same Contains a first data line. The first pixels are respectively connected to the first scan line and the first data line, and the second pixels are respectively connected to the second scan line and the first data line. According to the above configuration, when the new liquid crystal display panel starts scanning, all the first scanning lines are sequentially scanned from top to bottom, and then all the second scanning lines are sequentially scanned from top to bottom.

With the newly designed driving method of the present invention, the present invention can reduce the vertical direction caused by the use of frame inversion by utilizing the advantages of the double gate driving circuit by using the polarity switching method of the frame inversion in the architecture of the double gate driving circuit. Cross-talk, with a different approach to improve the picture quality of frame inversion.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

In order to explain in detail the active matrix type new liquid crystal display panel of the present invention, please refer to the fourth figure. First, a novel liquid crystal display panel of the present invention will be described, which comprises a plurality of columns of pixel units and a plurality of parallel data lines. Each column of pixel units includes a first scan line and a second scan line. In addition, each data line is perpendicular to the scan lines, and the data lines include a first data line. Each column of pixel units of the present invention is composed of two scanning lines, and each pixel includes a switch and a liquid crystal pixel capacitor. Each of the open relationships is a thin film transistor or a P-type field effect transistor, an N-type field effect transistor. The first scan line G1 and the second scan line G1-1 in the fifth figure are a group, the first scan line G2 and the second scan line G2-1 are a group; the thin film transistor in the first pixel 34 The drain of 36 is connected to the first data line S01, and the source is connected to the liquid crystal electrode. The gate of the thin film transistor 36 in the first pixel 34 is connected to the scanning line G1. The thin film transistor 40 of the second pixel 38 is connected to the first data line S01 and the source is connected to the liquid crystal electrode. The gate of the thin film transistor 40 in the second pixel 38 is connected to the scanning line G1-1. the first The pixel 34 and the second pixel 36 share the first data line S01, but are controlled by two different scanning lines of the first scanning line G1 and the second scanning line G1-1, respectively.

The drain of the thin film transistor 44 in the third pixel 42 is connected to the first data line S01, and the source is connected to the liquid crystal electrode. The gate of the thin film transistor 44 in the third pixel 42 is connected to the scanning line G2-1. The thin film transistor 48 of the fourth pixel 46 is connected to the first data line S01 and the source is connected to the liquid crystal electrode. The gate of the thin film transistor 48 in the fourth pixel 46 is connected to the scanning line G2. The third pixel 42 and the fourth pixel 46 share the first data line S01, but are controlled by two different scanning lines of the scanning line G2-1 and the scanning line G2, respectively.

The first scan lines G1, G2, G2, G2 and the second scan lines G1-1, G2-1, G3-1, G4-1 are connected to the gate wafer and control the scan line signals by the scan driver 80. For transmission, the first data line S01 is connected to the source chip, and the data driver 70 is used to control the transmission of the data line signal.

According to the above structure, the driving method of the present invention will be further described. Please refer to FIG. 5 at the same time, and the fifth figure is a waveform diagram of a part of the clock signal and the gate signal of the fourth figure. Wherein YDIO1 represents a first trigger signal, YCLK is a clock signal, G1~G3, G1-1~G3-1 are gate signals, and YDIO2 represents a second trigger signal, compared to the prior art, each of the present invention Interval signals are not used between the gate signals.

The driving method of the present invention is to scan the first scanning lines (G1, G2, G2, G4, and the like) sequentially from top to bottom when the new liquid crystal display panel starts scanning, and then the same The two scan lines (G1-1, G2-1, G3-1, G4-1, and so on) are scanned sequentially from top to bottom.

Therefore, the display panel starts one horizontal scanning line G1 at a time, turns all the thin film transistors on the first scanning line G1 into 36, and sends the data signal to the corresponding first pixel 34 via the vertical data line S01, and then The thin film transistor 36 is turned off until the next time the signal is rewritten, during which the charge is stored on the pixel capacitor in each of the thin film transistors; at this time, the next first scan line G2 is activated to be on the line. All thin film electro-crystals The body is opened 48, and the data signal is sent to the corresponding first pixel 46 via the vertical data line S01, and then the thin film transistor 48 is turned off until the signal is rewritten again, during which the charge is stored in each of the thin film transistors. On the pixel capacitor, the first scan line G3, the first scan line G4, and the like are connected, and the data signal is input to the corresponding pixel via the data line in the above manner, and the data signal of the entire screen is sequentially written.

Then, a signal is written to the second scan line G1-1, all the thin film transistors on the first scan line G1 are turned on 40, and the data signal is sent to the corresponding first pixel 38 via the vertical data line S01, and then turned off. The thin film transistor 40 until the next time the signal is rewritten, during which the charge is stored on the pixel capacitor in each of the thin film transistors; at this time, the next first scan line G2-1 is activated to the line All of the thin film transistors are turned on 44, and the data signal is sent to the corresponding first pixel 42 via the vertical data line S01, and then the thin film transistor 44 is turned off until the next time the signal is rewritten, during which the charge is stored in each On the pixel capacitor in the thin film transistor; successively turning on the first scan line G3-1, the first scan line G4-1, etc., inputting the data signal to the corresponding pixel via the data line according to the above manner, sequentially The data signal of the screen is written.

In the foregoing, the panel has been changed in various polarities, but the polarity is changed the next time the screen data is changed. in accordance with

According to the driving method of the eighth drawing, the polarity changing mode of the liquid crystal panel of the present invention will appear as shown in the sixth (a) or sixth (b). The polarity conversion method of the liquid crystal panel shown in the sixth (a) diagram or the sixth (b) diagram is frame inversion.

The double-gate driving circuit adopts the frame inversion polarity conversion mode to effectively reduce the degree to which the ITO electrode voltage is coupled. Please refer to the seventh diagram (prior art) and the eighth diagram (invention) together. In the prior art, the panel is a single-gate frame inversion architecture, assuming that the ITO electrode voltage of the single-gate frame inversion structure is coupled to a degree of approximately 3:1 (the seventh picture on the upper left R-pixel: the seventh picture is on the lower right R) Picture)). The panel of the present invention is in a double gate frame inversion architecture (the spatial configuration is still dot inversion), and the ITO electrode voltage of the dual gate frame inversion architecture is coupled to a degree of (3+4): (1+4)=7:5 (8th picture, upper left R pixel: eighth picture Right lower R pixel). Therefore, in the double gate structure, the polarity conversion method combined with the frame inversion can effectively reduce the vertical cross-talk problem caused by the difference in the degree of coupling of the ITO electrode voltage, thereby improving the picture quality of the panel.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, any changes or modifications of the shapes, structures, features and spirits described in the scope of the present invention should be included in the scope of the present invention.

S01‧‧‧First data line

S02‧‧‧First data line

S03‧‧‧First data line

S04‧‧‧First data line

G1‧‧‧ first scan line

G1-1‧‧‧Second scan line

G2‧‧‧ first scan line

G2-1‧‧‧Second scan line

G3‧‧‧ first scan line

G3-1‧‧‧Second scan line

G4‧‧‧ first scan line

G4-1‧‧‧Second scan line

10‧‧‧ pixels

12‧‧‧film transistor

14‧‧‧ scan line

16‧‧‧Information line

18‧‧‧pixel capacitor

20‧‧‧Data Drive

22‧‧‧ scan driver

24‧‧‧Active Matrix LCD Panel

32‧‧‧New LCD panel

34‧‧‧ first pixels

36‧‧‧Thin film transistor

38‧‧‧Second pixels

40‧‧‧film transistor

42‧‧‧ Third pixel

44‧‧‧film transistor

46‧‧‧4th pixel

48‧‧‧film transistor

50‧‧‧Data Drive

52‧‧‧ scan driver

The first figure is a schematic diagram of a prior art active matrix drive circuit.

The second figure shows a schematic diagram of a prior art active matrix drive circuit using RGB pixel capacitance.

The third figure is a waveform diagram of the clock signal and the gate signal of the prior art.

The fourth figure is a schematic diagram of a driving circuit of the novel liquid crystal display panel of the present invention.

The fifth figure is a waveform diagram of a part of the clock signal and the gate signal of the present invention.

The liquid crystal panel shown in the sixth (a) and sixth (b) diagrams is frame inversion polarity conversion.

The seventh graph is a schematic diagram of the extent to which the ITO electrode voltage is coupled under the hypothetical single gate inversion frame architecture of the prior art.

The eighth figure is a schematic diagram of the degree to which the ITO electrode voltage is coupled under the hypothetical double gate frame inversion architecture of the present invention.

32‧‧‧New LCD panel

34‧‧‧ first pixels

36‧‧‧Thin film transistor

38‧‧‧Second pixels

40‧‧‧film transistor

42‧‧‧ Third pixel

44‧‧‧film transistor

46‧‧‧4th pixel

48‧‧‧film transistor

50‧‧‧Data Drive

52‧‧‧ scan driver

Claims (20)

A novel liquid crystal display panel includes: a plurality of columns of pixel units, each column of pixel units including a first scan line and a second scan line, the first scan line is parallel to the second scan line, and the first scan The line is located above the second scan line; a plurality of parallel data lines are perpendicular to the scan lines, and the data lines include a first data line; a first pixel is respectively connected to the first data line a scan line and the first data line; a second pixel adjacent to the first pixel, the second pixel is respectively connected to the second scan line and the first data line; a third pixel is located a next column of the first pixel, the third pixel is respectively connected to the second scan line and the first data line; a fourth pixel is adjacent to the third pixel, and the fourth pixel is respectively connected The first scan line and the first data line; wherein the first pixel and the third pixel respectively connected to different scan lines are in the same row, respectively connected to the second pixel and the fourth pixel of different scan lines The pixels are on the same line; and when the new LCD panel starts scanning After the first scan line and the like based the scanned sequentially from top to bottom, and then such second scan line scanned sequentially from top to bottom. The novel liquid crystal display panel of claim 1, wherein the first data line is connected to the source wafer. The novel liquid crystal display panel of claim 1, wherein the first scan line and the second scan line are connected to a gate wafer. The novel liquid crystal display panel of claim 1, wherein the first pixel comprises a first switch and a first liquid crystal pixel capacitor, and the second pixel comprises a second switch and a second liquid crystal pixel capacitor, The third pixel includes a third switch and a third liquid crystal pixel capacitor, and the fourth pixel includes a fourth switch and a fourth liquid crystal pixel capacitor, respectively. The novel liquid crystal display panel of claim 4, wherein the open relationship is It is a thin film transistor. The novel liquid crystal display panel of claim 5, wherein the thin film electro-crystal system is a P-type field effect transistor or an N-type field effect transistor. The new liquid crystal display panel of claim 5, wherein the first switch further comprises a first gate, a first source and a first drain, and the first gate is connected to the first a scan line, the first source is connected to the first liquid crystal pixel capacitor, and the first drain is connected to the first data line. The new liquid crystal display panel of claim 5, wherein the second switch further comprises a second gate, a second source and a second drain, and the second gate is connected to the first a second scan line, the second source is connected to the second liquid crystal pixel capacitor, and the second drain is connected to the first data line. The new liquid crystal display panel of claim 5, wherein the third switch further comprises a third gate, a third source and a third drain, and the third gate is connected to the third a second scan line, the third source is connected to the third liquid crystal pixel capacitor, and the third drain is connected to the first data line. The new liquid crystal display panel of claim 5, wherein the fourth switch further comprises a fourth gate, a fourth source and a fourth drain, and the fourth gate is connected to the fourth a scan line, the second source is connected to the fourth liquid crystal pixel capacitor, and the second drain is connected to the first data line. A driving method for a novel liquid crystal display panel comprises the following steps: providing a novel liquid crystal display panel having a plurality of columns of pixel units and a plurality of parallel data lines, each column of pixels comprising a first scan a line and a second scan line, the first scan line is parallel to the second scan line, the first scan line is located above the second scan line, and the data lines and the scan lines are perpendicular to each other, and the lines The data line includes a first data line; the new liquid crystal display panel further includes a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein the first pixels are respectively connected The first scan line and the first data line, the second pixel and the The first pixels are adjacent to and connected to the second scan line and the first data line, and the third pixel is located in a column below the first pixel and is respectively connected to the second scan line and the first data line. The fourth pixel is adjacent to the third pixel and is respectively connected to the first scan line and the first data line, and the first pixel and the third pixel respectively connected to different scan lines are in the same row. Connected to different scan lines respectively, the second pixel and the fourth pixel are in the same row; and when the new liquid crystal display panel starts scanning, the first scan lines are sequentially scanned from top to bottom, and then the The second scan line is scanned sequentially from top to bottom. The driving method of the novel liquid crystal display panel according to claim 11, wherein the first data line is connected to a source wafer. The driving method of the novel liquid crystal display panel according to claim 11, wherein the first scan line and the second scan line are connected to a gate wafer. The driving method of the novel liquid crystal display panel of claim 11, wherein the first pixel comprises a first switch and a first liquid crystal pixel capacitor, and the second pixel comprises a second switch and a second liquid crystal The third capacitor includes a third switch and a third liquid crystal pixel capacitor, and the fourth pixel includes a fourth switch and a fourth liquid crystal pixel capacitor, respectively. The driving method of the novel liquid crystal display panel according to claim 14, wherein the open relationship is a thin film transistor. The driving method of the novel liquid crystal display panel according to claim 15, wherein the thin film electro-crystal system is a P-type field effect transistor or an N-type field effect transistor. The driving method of the novel liquid crystal display panel of claim 14, wherein the first switch further comprises a first gate, a first source and a first drain, and the first gate is Connecting the first scan line, the first source is connected to the first liquid crystal pixel capacitor, and the first drain is connected to the first data line. The driving method of the novel liquid crystal display panel of claim 14, wherein the second switch further comprises a second gate, a second source and a second drain, and the second switch The second gate is connected to the second scan line, the second source is connected to the second liquid crystal pixel capacitor, and the second drain is connected to the first data line. The driving method of the novel liquid crystal display panel of claim 16, wherein the third switch further comprises a third gate, a third source and a third drain, and the third gate Connecting the second scan line, the third source is connected to the third liquid crystal pixel capacitor, and the third drain is connected to the first data line. The driving method of the novel liquid crystal display panel of claim 14, wherein the fourth switch further comprises a fourth gate, a fourth source and a fourth drain, and the fourth gate The first scan line is connected, the fourth source is connected to the fourth liquid crystal pixel capacitor, and the fourth drain is connected to the first data line.